From 084c233d0cd83b17a88c103575078d1e3aef39ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Leopoldo=20Rodr=C3=ADguez?= Date: Tue, 29 Sep 2026 11:29:18 -0600 Subject: [PATCH] =?UTF-8?q?v6:=20auditor=C3=ADa=20completa,=20plan=20de=20?= =?UTF-8?q?correcci=C3=B3n,=20resumen=20de=20cambios,=20revisi=C3=B3n=20fi?= =?UTF-8?q?nal=20y=20pr=C3=B3ximos=20pasos=20para=20ordenar=20(28-29=20sep?= =?UTF-8?q?)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- ...heda_EinarBoard-v6_Cambios-Resumen_v1.0.md | 332 ++++ ...Drogheda_EinarBoard-v6_Final-Check_v1.0.md | 223 +++ ..._Drogheda_EinarBoard-v6_Full-Audit_v1.0.md | 6 + ...ogheda_EinarBoard-v6_Full-Audit_v1.0_EN.md | 1650 +++++++++++++++++ ...a_EinarBoard-v6_Plan-de-Correccion_v1.0.md | 1536 +++++++++++++++ ..._EinarBoard-v6_Ports-and-No-Respin_v1.0.md | 288 +++ ...arBoard-v6_Schematic-Change-Report_v1.0.md | 5 + .../Delegated-Decisions_2026-09-28.md | 30 + ...hematic-Change-Report_pass1_EN-original.md | 419 +++++ .../verify_apply.md | 150 ++ ...inarBoard-v6_Proximos-Pasos-Pedido_v1.0.md | 184 ++ .../hbox-watchdog-v6-schematic.pdf | Bin 762536 -> 762726 bytes 03-Architecture-Hardware/pinmap-v6.md | 8 +- 13 files changed, 4830 insertions(+), 1 deletion(-) create mode 100644 03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Cambios-Resumen_v1.0.md create mode 100644 03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Final-Check_v1.0.md create mode 100644 03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0_EN.md create mode 100644 03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Plan-de-Correccion_v1.0.md create mode 100644 03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Ports-and-No-Respin_v1.0.md create mode 100644 03-Architecture-Hardware/2026-09-28_v6-audit-attachments/Delegated-Decisions_2026-09-28.md create mode 100644 03-Architecture-Hardware/2026-09-28_v6-audit-attachments/Schematic-Change-Report_pass1_EN-original.md create mode 100644 03-Architecture-Hardware/2026-09-28_v6-audit-attachments/verify_apply.md create mode 100644 03-Architecture-Hardware/2026-09-29_Drogheda_EinarBoard-v6_Proximos-Pasos-Pedido_v1.0.md diff --git a/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Cambios-Resumen_v1.0.md b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Cambios-Resumen_v1.0.md new file mode 100644 index 0000000..012a14d --- /dev/null +++ b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Cambios-Resumen_v1.0.md @@ -0,0 +1,332 @@ +--- +title: "EinarBoard v6 — Cambios de esquemático: resumen de las 3 pasadas" +tags: [project-drogheda, hardware, hbox, v6, esquematico, cambios, verificacion] +project: Project Drogheda +author: Helgen Technologies +date: 2026-09-28 +version: 1.0 +status: FINAL — esquemático terminado y verificado; falta el layout (Michelle) +audience: Michelle (layout), Leo, ingenieros +--- + +# EinarBoard v6 — Cambios de esquemático: resumen de las 3 pasadas + +!!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide" + Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios. + +**Tarjeta:** `hbox-watchdog-v6` (repo **HBox_PCB**) · **Fecha:** 28-sep-2026 · +[Plan de corrección y estado](v6-plan-correccion.md) · [Auditoría completa (español)](v6-auditoria-completa.md) · +[original en inglés](v6-full-audit.md) + +!!! success "Esquemático terminado y verificado de forma independiente" + - **Esquemático final:** `d58a89ba5a5ac46419edf9d68672a8208d825a16387298d0167e21399cd41e7b` + - **ERC: 0 errores.** Hay 135 avisos cosméticos, todos explicados (antes eran 166). + - **299 piezas montadas**, todas con número LCSC. TP1–TP12 y JP1–JP6 no van en el BOM ni en el CPL. + - **El PCB no se tocó** (`6ddec80d…36bf`). Michelle hace *Actualizar PCB desde esquemático*: es el paso 0 de su + [lista de trabajo](v6-plan-correccion.md#5-lista-de-trabajo-de-michelle-layout). + +## 1. Resumen: tres pasadas + +Todo se editó **en el mismo archivo** (`hbox-watchdog-v6.*`), con copia de respaldo antes de cada paso. El método fue el +mismo en las tres pasadas: + +- Antes de guardar se escribe la lista de cambios esperados. +- Se edita con cortes acotados al nodo del archivo, con una guarda que impide que cambie o desaparezca un UUID existente. +- Se exporta el netlist y se compara contra lo esperado. **En todos los grupos lo esperado coincidió exactamente con lo obtenido.** + +| Pasada | Qué hizo | Resultado | Verificación | Esquemático (sha256) | +|---|---|---|---|---| +| **1 · Correcciones de la auditoría** | Todos los Blockers y Majors que tocan esquemático o proyecto, los Minors de la lista D19, las netclasses y reglas DRC (F-01) y la librería (H-04). 37 piezas nuevas, 3 quitadas (D20, D21 y el flag PF15), 17 puestas en DNP | Netlist: 37 agregadas / 3 quitadas / 125 cambios de campo / 22 cambios pin-red / 16 cambios de clase, todo esperado. ERC 0 errores (166 → 134 avisos) | Verificación independiente con scripts propios: **126 ítems, 173 PASS / 0 FAIL**, 15 notas | `ecee9fed…` → `d54e330d…` | +| **2 · Puertos y sin nueva versión** | Revisó 24 puertos de punta a punta contra hojas de datos y corrigió 7 (RS-485, RS-232, H4, CTS del SC16IS752, LEDs y Bob-Smith de J10, pad de descarga del módem, UART del módem). **H-03** hecho (huella MWSA0804S) y **B-13** hecho (K1 fuera, R148) | Netlist: 8 agregadas / 0 quitadas / 41 campos / 8 pin-red / 0 clases, todo esperado. ERC 0 errores (134) | Revisada por la pasada 3: **26 PASS / 1 FAIL** (la huella de los inductores) | `d54e330d…` → `f73f41a8…` | +| **3 · Revisión final independiente** | Revisó la pasada 2 con su propio diff y las hojas de datos de los fabricantes. **Corrigió la huella MWSA0804S** (se habían intercambiado dos cotas de Sunlord), **agregó C176** en U28 (N2) y **confirmó los pads de Y3** con la hoja de SCTF (N1, sin cambio) | Netlist: C176 agregado, nada más. ERC 0 errores (134). Conectividad derivada del esquemático = netlist de KiCad (353 redes, 0 diferencias) | — | `f73f41a8…` → **`2b394ef9…`** | +| **4 · Paquete LFP-HT (igual que V5.6)** | JP2 → `Drogheda:SolderJumper-3_P1.3mm_Bridged23_RoundedPad1.0x1.5mm` (F2 a GND) y R55 10 k → **5.6 k (C23189)**; JP3/JP4 ya coincidían con V5.6 (F1 = 0, F0 = 1). Layout: L-67. | Flotación **3.50 V** LFP (antes 4.00 V Li-ion); ventana de carga ≈ +8…+60 °C con NTC B3380. | Netlist: 0 cambios de pin o de red; lo esperado = lo obtenido. ERC 0 errores (135 avisos). | `d58a89ba…e7b` | + +**Total contra la auditoría:** **46 piezas nuevas**, 3 quitadas, 22 puestas en DNP (17 por A-01, 5 por B-13; además +R145/R146 entran nuevas como DNP). La polaridad del USB_BOOT del módem quedó como aviso: los documentos de SIMCom se +contradicen, así que hay un procedimiento alterno en banco (TP8–GND). + +??? note "Hashes y archivos" + | Archivo | Estado final (sha256) | + |---|---| + | `hbox-watchdog-v6.kicad_sch` | `d58a89ba5a5ac46419edf9d68672a8208d825a16387298d0167e21399cd41e7b` | + | `hbox-watchdog-v6.kicad_pro` | `d577aa43076f5f751c291041dbf3054cb93a87facfe9f339ef91b60e073bd6ce` (pasada 1; netclasses) | + | `hbox-watchdog-v6.kicad_dru` | `31ce0f4f23e8178b4b5e837b452e7bb8647d446ffd420559049eaaae78100831` (pasada 1) | + | `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` | `3f38f26e435c477a7701636d4d5e1c05b4c7bd523e8dd04f9f57128657736313` (H-04) | + | `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod` (nueva) | `74528135d4f69617df8570da58700bac3920827a78ec9104c3440be2c5975638` (land corregido) | + | `hbox-watchdog-v6.kicad_pcb` | `6ddec80d1c15f79e69dff6c1a850b28345a5d826389f79cee8c61998240b36bf` (**sin tocar**) | + | PDF `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf` | `3e073181…4362` | + + Respaldos en la Mac: `kicad/_to_delete/v6-apply-20260928/`, `kicad/_to_delete/v6-ports-20260928/` y + `kicad/_to_delete/v6-final-20260928/` (nada se borró). + + **Git (lo corre Leo; desde aquí no se hizo commit):** dentro del submódulo `kicad`, commit de + `hbox-watchdog-v6.kicad_sch`, `.kicad_pro`, `.kicad_dru`, `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` + y `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod`; push a Gitea `HBox_PCB`; luego actualizar el gitlink del proyecto + padre. Si KiCad está abierto en v6, cerrarlo **sin guardar** antes del *Update PCB*. + +--- + +## 2. Estado final de cada cambio, por bloque + +Todo lo de estas tablas está verificado: la pasada 1 por la verificación independiente (126 ítems) y las pasadas 2 y 3 +por la revisión final. **Pasada:** 1 = correcciones de la auditoría · 2 = puertos / sin nueva versión · 3 = revisión final. + +### Entrada de 24 V, ignición y ventilador + +| Hallazgo | Ref | Estado final | LCSC | Pasada | +|---|---|---|---|---| +| A-01 / V1-01 | F2 | Fusible Nano2 de 3 A (0154003.DR), mismo porta-fusible; P1.1 → F2 → `/VIN_FUSED` | C206912 | 1 | +| V1-01 | D10 | SMBJ33A en `/VIN_FUSED` (salida de F2); con P1 al revés funde F2 | C224019 | 1 | +| A-01 | D20, D21 | Eliminados; `/VIN_MODEM` unido a `/MAIN5V` | — | 1 | +| A-01 | Q10, DzG1, Rrp1, C10, C11, C22 | DNP: la rama `/24V` queda sin cargas | — | 1 | +| A-01 | U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21 | DNP: bloque del ventilador | — | 1 | +| A-01 | JP1 | Puente de soldadura **puenteado** → `/5V_FAN` = `/VEH5V` | — | 1 | +| F-02 | **D35** (nuevo) | SMBJ33A de `/IGN_IN` a GND, para ir en P1.3 | C224019 | 1 | +| F-02 | Rig1 | 22 k sin cambio; se mueve a P1.3 en el layout. `/IGN_IN` = {P1.3, Rig1.1, D35.1} | C88614 | 1 | +| D-05 | Rigb1 | 2.2 k → relación 0.0833 para leer la ignición por ADC | C4190 | 1 | + +### Cargador LTC4040, 5 V, 3V3 e inductores + +| Hallazgo | Ref | Estado final | LCSC | Pasada | +|---|---|---|---|---| +| A-03 | R50 | 1.43 k 1 % → 1.316–1.483 A de carga | C22840 | 1 | +| A-04 | R121 | 57.6 k 1 % → U25 en 5.18 / 5.32 / 5.46 V | C23082 | 1 | +| A-05 | **C161, C162** (nuevos) | 47 µF X7R 1210 en `/MAIN5V` (VSYS de U6) | C5440143 | 1 | +| A-09 | C78 | 220 µF 16 V polímero | C881921 | 1 | +| H-02 | R53 | 499 k 1 % (HKR RCT03499KFLF) | C177479 | 1 | +| H-02b | R56, R57, R58, R85, R87, Rgs1 | 100 k 1 % | C25803 | 1 | +| A-11 | R56 | Pull-up a `/3V3` → cargador **apagado** sin MCU | C25803 | 1 | +| A-13 | **R141** (nuevo), red `/PFO` | PFO del LTC4040 → PB10, con 100 k a `/3V3` | C25803 | 1 | +| F-51 | **U29 + C168** (nuevos) | TMP102 del cargador en **0x48** + 100 nF | C99269, C14663 | 1 | +| F-51 | **R137, R138, C169** (nuevos) | Toma del NTC: `/NTC` → 100 k → `/NTC_CELL` (PC5) → 120 k + 10 nF a GND | C25803, C25808, C1589 | 1 | +| A-08 | U17 | TLV1117LV33DCYR, misma huella | C15578 | 1 | +| H-03 | L2 (DNP), L6, L8, L20 | Huella `Drogheda-v6:IND-SMD_MWSA0804S` (tierra de Sunlord); piezas sin cambio | — | 2 y 3 | + +### Módem A7670SA + +| Hallazgo | Ref | Estado final | LCSC | Pasada | +|---|---|---|---|---| +| A-01 | U20.2, C127, C128 | En `/MAIN5V` | — | 1 | +| F-03 | **C163, C164, C165** (nuevos) | 2 × 22 µF 0805 + 220 µF polímero en U20.2 | C86817, C881921 | 1 | +| B-02 | C130, C131 | 220 µF 16 V polímero | C881921 | 1 | +| B-02 | R116 / C141 / C142 | 113 k / 6.8 nF / 56 pF (compensación para 3.8 V) | C22862, C1542, C1572 | 1 | +| B-02 | **C166, C167** (nuevos) | 22 µF 0805 en `/VBAT_MODEM` | C86817 | 1 | +| B-03 | D28 | PESD0402-240 bidireccional, huella 0402 | C1975527 | 1 | +| B-09 | R132, R133, R134 | 22 Ω | C23345 | 1 | +| B-09 | **C171** (nuevo) | 100 nF 0402 en J14.C1 (`/SIMB_VDD`) | C1525 | 1 | +| B-10 | **R142, R143** (nuevos) | 100 k: `/MODEM_STATUS` a GND y `/DIN_4G` a `/3V3` | C25803 | 1 | +| B-10 | R106 | 1 k | C14676 | 1 | +| B-15 | R107, R108 | DNP, valor «0R-NEVER-FIT» y nota | — | 1 | +| F-52 | **U31 + C174** (nuevos) | TMP102 del módem en **0x49** + 100 nF | C99269, C14663 | 1 | +| G-02 | **U30** (nuevo) | USBLC6-2SC6 en J9 | C7519 | 1 | +| B-13 | K1, Q6, D6, R40, R41 | DNP: el relé sale del circuito | — | 2 | +| B-13 | **R148** (nuevo) | 0 Ω de `/USART6_TX` (PC6) a `/DIN_4G`; nunca junto con K1 | C21189 | 2 | +| P-5 | **TP12** (nuevo) | Pad en `/1V8_MODEM` junto a TP8 (descarga forzada del módem) | — | 2 | + +### GNSS ZED-F9P + +| Hallazgo | Ref | Estado final | LCSC | Pasada | +|---|---|---|---|---| +| C-01 | **U28, R135, R136** (nuevos) | TPS2552 (75 mA) con EN̅ = ANT_OFF + 100 k a GND y FAULT̅ → `/GNSS_ANT_SHORT_N` + 10 k a `/3V3_GNSS`; salida `/ANT_BIAS`; U18.7 sin conectar | C46506, C25803, C25804 | 1 | +| N2 | **C176** (nuevo) | 100 nF en U28 pin 1 (IN) | C14663 | 3 | +| C-02 | U21 | TPS7A2033PDBVR (arranque suave), misma huella | C2862740 | 1 | +| D-01 | **U27 + C170** (nuevos) | 74LVC1G125 de `/DOUT_4G` a U18.26 (`/DOUT_4G_F9P`), VCC = `/3V3_GNSS` | C12518, C14663 | 1 | +| D-01 | Rdfu1 | 100 k | C25803 | 1 | +| C-07 | **TP10, TP11** (nuevos) | Pads en SAFEBOOT_N (U18.50) y RESET_N (U18.49) | — | 1 | +| D-09 | **R144** (nuevo) | 100 k de la base de Q5 a GND | C25803 | 1 | + +### MCU y cristales + +| Hallazgo | Ref | Estado final | LCSC | Pasada | +|---|---|---|---|---| +| D-02 | Y3 | 25 MHz 3225-4P CL 10 pF; símbolo `Crystal_GND24` (pad 1 HSE_IN, pad 3 HSE_OUT, pads 2/4 GND), confirmado con la hoja de SCTF (N1) | C2901684 | 1 y 3 | +| D-02 | C113, C114 | 12 pF C0G | C38523 | 1 | +| D-03 | Y4 | FC-135 CL 7 pF, misma huella | C48615 | 1 | +| D-03 | C115, C116 | 6.8 pF C0G | C1679 | 1 | +| D-12 | **TP9** (nuevo) | Pad en PA9 (`/USART1_TX`) | — | 1 | + +### Ethernet + +| Hallazgo | Ref | Estado final | LCSC | Pasada | +|---|---|---|---|---| +| E-01 | **R139** (nuevo), red `/ETH_PWR_EN` | EN de U12 → PD2, con 100 k a GND | C25803 | 1 | +| E-02 | **R140** (nuevo) | 4.7 k de `/ETH_RST` a GND | C23162 | 1 | +| E-03 | C95, C96 | 33 pF C0G (Y1 se queda) | C1663 | 1 | +| E-04 | C91 / C90 | 10 nF 0603 / 4.7 µF 0805 | C1589, C1779 | 1 | +| E-04 | **C172, C173** (nuevos) | 100 nF en AVDD del W5500 | C14663 | 1 | +| G-03 | J10 | Montado; huella `Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal` | C12074 | 1 | +| P-3 | J10.11 / J10.12 | LED amarillo corregido: 12 = ánodo (`/ETH_ACT_A`), 11 = cátodo (`/ETH_ACTLED`) | — | 2 | +| P-3 | J10.8 | A GND (retorno Bob-Smith; plano de Hanrun) | — | 2 | + +### Puertos serie (SC16IS752, RS-485, RS-232, H4) + +| Hallazgo | Ref | Estado final | LCSC | Pasada | +|---|---|---|---|---| +| H-02 | U10 | SC16IS752IPW,128 (I²C 0x4D) | C57156 | 1 | +| Puertos | U10.2, U10.16 | CTSA̅/CTSB̅ a GND | — | 2 | +| P-1 | U14 | THVD1410DR, misma huella SOIC-8 | C2671345 | 2 | +| P-1 | **U32 + C175** (nuevos) | 74LVC1G04: RTSA̅ → `/RS485_DE` (arranca en recepción) + 100 nF | C7827, C14663 | 2 | +| P-1 | **D39** (nuevo) | SM712 en A/B de P11 | C12067 | 2 | +| P-4 | **R145, R146** (nuevos, **DNP**) | 390 Ω, opción de polarización del bus | C23151 | 2 | +| H-01 | U15 | Huella angosta `SOIC-16_3.9x9.9mm` | — | 1 | +| P-2 | U15 | TRS3232EIDR (ESD IEC) | C308878 | 2 | +| P-2 | **R147** (nuevo) | 1 k de R1OUT (`/RS232_R1OUT`) a `/SER_RXB` (H4 sin contienda) | C21190 | 2 | +| G-03 | P11, P12 | Montados; huella `PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal` | C5160226 | 1 | + +### Conectores, ESD y limpieza + +| Hallazgo | Ref | Estado final | LCSC | Pasada | +|---|---|---|---|---| +| G-08 | **D36, D37, D38** (nuevos) | PESD5V0S1BA en `/NRST`, `/NTC_TEMP` y `/NTC2` | C2827694 | 1 | +| G-04 | **JP6** (nuevo) | Puente de soldadura abierto sobre P5, «CUTOFF_BYPASS» | — | 1 | +| H-08 | C22, Y2 | Textos de valor «10uF/50V» y «3.6864MHz» | — | 1 | +| J-04 | Banderas NC y trozos de cable | 23 banderas huérfanas y 4 sobre pines conectados eliminadas; un trozo de cable borrado y otro recortado (sin cambio de red) | — | 1 | +| J-05 | TP1–TP12, JP1–JP6 | Fuera del BOM y del CPL | — | 2 | + +### Reglas del proyecto y librería + +| Hallazgo | Archivo | Estado final | Pasada | +|---|---|---|---| +| F-01 | `.kicad_pro` | Netclasses por nombre exacto: HV24, PWR_HI, PWR_MODEM, PWR_MID, RF y Default (lista en la [sección F-01](v6-plan-correccion.md#f-01-el-drc-no-veia-ningun-espaciado-de-24-v) del plan) | 1 | +| F-01 | `.kicad_dru` | Las 5 reglas del verificador 2 (piso 0.15, HV24↔HV24 0.2, HV24 externa 0.3, HV24 interna 0.5, pads de U2/U20/U25 0.15) | 1 | +| H-04 | `SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` | `LCSC Part` borrado; la copia de U25 en el PCB se refresca en el layout | 1 | +| H-03 | `IND-SMD_MWSA0804S.kicad_mod` (nueva) | Pads 2.75 × 5.5 mm a ±3.375 mm (separación 4.0 mm), cuerpo 8.8 × 8.2 mm, courtyard 10.0 × 9.0 mm | 2 y 3 | +| C-01 | Símbolo TPS2552 | Dibujado y embebido en el esquemático (KiCad no lo trae) | 1 | + +--- + +## 3. Delta de layout para Michelle (las tres pasadas juntas) + +La lista con casillas, en orden, está en la +[sección 5 del plan de corrección](v6-plan-correccion.md#5-lista-de-trabajo-de-michelle-layout). Aquí está el resumen +de lo que cambia en el PCB. + +### 3.1 Actualizar el PCB + +*Herramientas → Actualizar PCB desde esquemático* con **«Eliminar huellas sin símbolo»** y **«Reemplazar huellas con las +del esquemático»** marcados. Revisar la lista del diálogo antes de aplicar: + +- solo se borran **D20** (D_SMA) y **D21** (SOD-128); PF15 era un flag virtual, sin huella; +- solo cambian de huella las referencias de la tabla 3.2. + +Después, **solo en U25**, *Actualizar huella desde librería* para quitar `LCSC Part` (H-04). **Nunca** la actualización global +desde librería (L-45). Luego rellenar zonas y correr el DRC con las reglas nuevas. + +### 3.2 Huellas que cambian + +| Ref | Antes | Ahora | Nota | +|---|---|---|---| +| U15 | `SOIC-16W_7.5x10.3mm` | `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm` | TRS3232EIDR; C85–C88 ≤ 3 mm, C89 ≤ 2 mm de U15.16 (L-51) | +| D28 | SOD-923 | `Diode_SMD:D_0402_1005Metric` | con el re-ruteo LTE de F-06 | +| Y3 | HC-49SD | `Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm` | pad 1 HSE_IN, pad 3 HSE_OUT, pads 2/4 GND; ≤ 3 mm de PH0/PH1 (máx. 5 mm), sin pistas internas debajo | +| C91 | 0805 | `C_0603_1608Metric` | ≤ 2 mm de U11.22 | +| JP1 | puente abierto | `Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm` | puenteado (net-tie) | +| L2 (DNP), L6, L8, L20 | `Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm` | `Drogheda-v6:IND-SMD_MWSA0804S` | pads 2.75 × 5.5 mm a ±3.375 mm, courtyard 10.0 × 9.0 mm (L-53 corregido por L-63) | +| U25 | con `LCSC Part` | misma huella, refrescada desde la librería | H-04 | + +No cambian: J10 (el apodo de librería se corrigió a `Connector_RJ:`, la misma geometría), P11/P12 (ya eran *Horizontal* +en el PCB), Y4, F2, U10, U14, U17 y U21. + +### 3.3 DNP + +- **Pasan a montadas:** J10, P11, P12. +- **Pasan a DNP:** U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21, Q10, DzG1, Rrp1, C10, C11, C22 (A-01) · + K1, Q6, D6, R40, R41 (B-13). +- **Nuevas en DNP:** R145, R146 (polarización RS-485). + +Las huellas DNP se quedan en la tarjeta. Borrar su cobre `/24V`, `/SW_FAN` y `/BST_FAN` (L-6). En K1 no hay cambio de +cobre, salvo las dos conexiones de R148 (L-54). + +### 3.4 Piezas nuevas (46) + +| Ref | Huella | Dónde va | +|---|---|---| +| D35 | D_SMB | **en P1.3**; Rig1 a ≤ 3 mm de cobre de P1.3 (F-02) | +| U28 | SOT-23-6 | junto a L21/C144/C145 en J12; `/ANT_BIAS` ≥ 1 mm de la línea RF con franja GND cosida (C-01, F-06) | +| R135, R136 | 0603 | en los pines 3 y 4 de U28 | +| C176 | 0603 | **≤ 2 mm de U28 pin 1**, misma capa, GND con vía ≤ 1 mm (L-64) | +| C161, C162 | 1210 | ≤ 2 mm de VSYS 1/24 de U6, GND sobre el cobre del EP (A-05/A-02) | +| C163, C164 | 0805 | ≤ 2–3 mm de U20.2, GND sobre el cobre del EP de U20 (F-03) | +| C165 | CP_Elec_6.3x7.7 | en U20.2 (F-03) | +| C166, C167 | 0805 | ≤ 3 mm de L20.2 (B-02) | +| U29 + C168 | SOT-563 + 0603 | **entre U6 y L6, ≤ 5 mm del EP de U6** (F-51) | +| R137, R138, C169 | 0603 | R138/C169 junto al pad 25 de U16 (PC5); R137 en cualquier punto de `/NTC` | +| R139 | 0603 | en U12 pin 2 (EN); pista nueva `/ETH_PWR_EN` al pad 54 de U16 (PD2) | +| R140 | 0603 | en U11.37 (`/ETH_RST`) | +| U27 + C170 | SOT-23-5 + 0603 | **en U18.26 (RXD2)**; VCC de `/3V3_GNSS` | +| U30 | SOT-23-6 | **≤ 3 mm de cobre de los pads de J9**, D± pasando por los pads, vía GND ≤ 1 mm (G-02) | +| R141 | 0603 | pull-up de `/PFO` cerca del pad 29 de U16 (PB10) | +| C171 | 0402 | en J14.C1 | +| R142, R143 | 0603 | en `/MODEM_STATUS` (PC9) y `/DIN_4G`, donde convenga | +| TP10, TP11 | pad 1.0 mm | cerca de U18 pines 50 (SAFEBOOT_N) y 49 (RESET_N), junto a un pad GND (C-07) | +| R144 | 0603 | en la base de Q5 | +| TP9 | pad 1.5 mm | PA9, en la fila de pads de depuración con TP3–TP7 (L-56) | +| C172, C173 | 0603 | en AVDD 4/8 y 11/21 del W5500 | +| U31 + C174 | SOT-563 + 0603 | **entre U19 y U20** (F-52) | +| JP6 | puente de 2 pads, abierto | sobre P5 (`/MAIN5V`–`/SYS5V`), serigrafía «CUTOFF BYPASS» (G-04) | +| D36, D37, D38 | SOD-323 | ≤ 3 mm de P6.1, P7.1, P8.1, a GND (G-08) | +| U32 + C175 | SOT-23-5 + 0603 | ≤ 5 mm de U14 pines 2/3; C175 ≤ 2 mm de U32.5 (L-49) | +| D39 | SOT-23 | ≤ 5 mm de cobre de P11.1/P11.2, A/B en flow-through, pin 3 a GND con 2 vías (L-50) | +| R145, R146 | 0603 (DNP) | junto a P11 (L-50) | +| R147 | 0603 | ≤ 3 mm de U15.12; H4.3 del lado de U10 (L-51) | +| R148 | 0603 | camino más corto U16.37 (PC6) → U23.7 (`/DIN_4G`) (L-54) | +| TP12 | pad 1.5 mm | a 2.54 mm de TP8, con un contacto GND a ≤ 10 mm (L-55, L-65) | + +### 3.5 Redes que cambian de ruteo + +- `/VIN_MODEM` desaparece: U20.2, C127 y C128 pasan a **`/MAIN5V`** (≥ 1.5–2 mm hasta U20; borrar la pista de 48 mm de `/VIN_MODEM`). +- `/VIN_FUSED` gana D10.1: P1.1 → F2 → {D10, Q23.D}; `/24V_IN` = P1.1, F2.1 y Q10.D solamente. +- `/IGN_IN` = {P1.3, Rig1.1, D35.1}; el tramo largo al MCU es `/IGN_SENSE`. +- `/ANT_BIAS` (U28.6 → L21.2, C144, C145); U18.7 queda sin conectar; `/GNSS_ANT_OFF` (U18.5 → U28.3, R135); + `/GNSS_ANT_SHORT_N` gana U28.4 y R136; `/3V3_GNSS` gana U28.1, U28.5 y C176. +- `/ETH_PWR_EN` (U12.2, U16.54, R139); U12.2 sale de `/SYS5V`. +- `/DOUT_4G_F9P` (U27.4 → U18.26); U18.26 sale de `/DOUT_4G`; U27.2 entra a `/DOUT_4G`. +- `/PFO` (antes `/PFO_TP`: U6.20, TP2, más U16.29 y R141). +- `/NTC_CELL` (U16.25, R137, R138, C169); `/NTC` gana R137. +- `/GNSS_SAFEBOOT_N` (U18.50, TP10); `/USART1_TX` (U16.42, TP9). +- R56.2 pasa de GND a `/3V3`; los pads de Y3 se re-asignan como en 3.2. +- **Puertos:** `/RS485_DE` nueva (U14.2, U14.3, U32.4) y `/SER_DEA` = {U10.1, U32.2}; D39 en `/RS485_A`/`/RS485_B`; + `/RS232_R1OUT` nueva (U15.12, R147.1) y `/SER_RXB` = {U10.24, H4.3, R147.2}; J10.8 → GND, J10.11 → `/ETH_ACTLED`, + J10.12 → `/ETH_ACT_A`; U10.2 y U10.16 → GND; R148 entre `/USART6_TX` y `/DIN_4G`; TP12 en `/1V8_MODEM`. + +### 3.6 Qué va a mostrar el DRC + +En una copia del PCB sin actualizar, con las reglas nuevas: **161 errores de separación**. **149** son proximidades del +relleno de zonas guardado (se van al rellenar) y **12** son cobre real: + +- `/IGN_IN` en In2 contra vía GND 0.250, `/FAN_PWM` 0.291, vía `/5V_FAN` 0.300, `/NTC2` 0.305 y vía `/VEH5V` 0.340 mm. + Todos son F-02 y desaparecen al mover Rig1 a P1.3. +- `/VIN_PROT` contra `/VEH5V`: 0.157 y 0.191 mm en (175.5, 113.8). +- `/USB_VBUS` contra Q23.1 (`/Q23_GATE`): 0.225 mm. +- `/SW_PWRIN` contra pista GND: 0.270 mm. +- `/24V` contra `/COMP_FAN`: 0.290 mm × 2. Es la rama DNP, pero el cobre existe. +- Clase RF: vía de `/RF_LTE` contra `/PWR_CTRL`, 0.150 mm. Se va con el re-ruteo de F-06. + +Ojo: KiCad lista **una sola** violación entre el tramo largo de `/IGN_IN` en In2 y `/VEH5V` (la vía a 0.340 mm), aunque las +pistas paralelas están a 0.221–0.240 mm. No leer el conteo del DRC como la lista completa; el movimiento de F-02 elimina ese +tramo de todos modos. Los avisos de `track_width` bajan de 183 a 121. Después del *Update PCB* aparecen elementos HV24 +nuevos en `/VIN_FUSED` junto a D10 y desaparecen los de `/VIN_MODEM`. Comprobar una vez con *Inspeccionar → Resolución de +separación* que las clases sobrevivieron al guardado. + +### 3.7 Pasos de layout nuevos (L-49…L-66) + +L-49 dirección RS-485 · L-50 protección RS-485 en P11 · L-51 RS-232/H4 · L-52 J10 · L-53/L-63 land MWSA0804S · +L-54 R148 (B-13) · L-55 TP12 · L-56 fila de pads de depuración · L-57 SC16IS752 · L-58 resistencias CC de USB-C · +L-59 serigrafía de puertos · L-60 atributos de huella TP/JP · L-61 fiduciales · L-62 revisión de P1 · L-64 C176 · +L-65 pads de descarga forzada · L-66 revisión de LEDs de J10. Texto completo y agrupado en la +[lista de Michelle](v6-plan-correccion.md#5-lista-de-trabajo-de-michelle-layout). + +--- + +## 4. Informes de cada pasada + +- **[Pasada 1 — Informe de cambios al esquemático](v6-cambios-esquematico.md)** (en español): cada cambio por hallazgo, + pruebas de netlist, ERC, reglas del proyecto, librería, topología de fusible y polaridad, delta de layout y notas de firmware. +- **[Pasada 2 — Puertos y sin nueva versión](v6-puertos-sin-nueva-version.md)** (inglés): veredicto puerto por puerto, hojas + de datos que decidieron los cambios, mapa I²C, cambios con prueba, L-49…L-62, notas de firmware por puerto y la tabla de + aceptados permanentemente. +- **[Pasada 3 — Revisión final](v6-revision-final.md)** (inglés): 27 revisiones de la pasada 2 (26 PASS, 1 FAIL + corregido), cierre de N1/N2, avisos, L-63…L-66 y notas de firmware. + +La verificación independiente de la pasada 1 (126 ítems revisados uno por uno: 173 PASS / 0 FAIL) no se reproduce aquí; +su resultado está en la sección 1. diff --git a/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Final-Check_v1.0.md b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Final-Check_v1.0.md new file mode 100644 index 0000000..3591d03 --- /dev/null +++ b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Final-Check_v1.0.md @@ -0,0 +1,223 @@ +--- +title: "EinarBoard v6 — Revisión final independiente (pasada 3, inglés)" +tags: [project-drogheda, hardware, hbox, v6, esquematico, final-check] +project: Project Drogheda +author: Helgen Technologies +date: 2026-09-28 +version: 1.0 +status: FINAL — pass 3 of 3 (independent check) +audience: Michelle (layout), Leo, ingenieros +--- + +# EinarBoard v6: final independent check of the ports pass, and closure of N1/N2 (v1.0) + +!!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide" + Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios. + +!!! info "Pass 3 of 3 — final independent check" + Spanish summary, final state per block and the combined layout delta: + **[EinarBoard v6 — Cambios de esquemático: resumen de las 3 pasadas](v6-cambios-resumen.md)**. + Checks [pass 2](v6-puertos-sin-nueva-version.md), closes N1/N2 from the verification of [pass 1](v6-cambios-esquematico.md) (Spanish) + and fixes the inductor land. Final schematic sha256 `2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933`. + + +**Date:** 2026-09-28 · **Board:** `kicad/hbox-watchdog-v6.*` (HBOX RTK, Helgen Technologies) · **Input:** sch `f73f41a8…27ee` (ports-pass output, verified on the Mac and in the staged copy) · **Baseline for the ports diff:** `apply/netlists/05-final.xml` · **Author:** Claude (final checker, independent of the apply and ports passes) · **Rules followed:** in-place edit with a backup first, span-scoped splices with a UUID multiset guard, expected changes written before editing, semantic netlist proof, `.kicad_pcb` not touched, no git, a unique staged path per commit plus sha256 on the Mac afterwards. + +## Resumen (ES) + +**Pase de puertos: 26 PASS, 1 FAIL.** Revisé el pase de puertos por mi cuenta: diff propio desde `05-final.xml`, conectividad derivada directamente del `.kicad_sch` (idéntica al netlist de kicad-cli: 353 redes, 0 diferencias) y hojas de datos de los fabricantes. Todos los cambios del esquemático son intencionales y correctos. Confirmé: + +- **THVD1410** con el mismo pinout que el SP3485, 3–5,5 V y fail-safe abierto/corto/inactivo. +- **U32 74LVC1G04** en SOT-23-5 (1 NC, 2 A, 3 GND, 4 Y, 5 VCC). Según NXP, RTS̅ del SC16IS752 queda en ALTO tras el reset, así que el transceptor está en recepción durante el reset, en DFU y sin firmware. EFCR = 0x10 coincide con la tabla 30 de NXP. +- **SM712** bien orientado (pines 1 y 2 a A/B, pin 3 a GND). +- **TRS3232E** con el mismo pinout y capacitores de 0,1 µF a 3,3 V. +- **R147 1 k** y los **CTS̅ a GND**, correctos según NXP. +- **LED ACT de J10 (11/12) y J10.8 a GND**: confirmados con el **plano de Hanrun** (amarillo con ánodo en 12 y cátodo en 11; P8 = «CHS GND», con la nota «Connect CHS GND to PCB Ground»). El pase de puertos no había podido leer ese plano. Los LED del W5500 son activos en bajo. +- **B-13**: un solo excitador en `/DIN_4G` (PC6 → R148), sin contienda. +- **TP1–TP12 y JP1–JP6** fuera del BOM y del CPL. +- **Los 8 números LCSC** existen, con stock y encapsulado correcto. + +**El FAIL es la huella H-03 `IND-SMD_MWSA0804S`.** El pase de puertos intercambió las cotas J y H de Sunlord. La figura 4-1 de la especificación MWSA50230000 define I = largo del pad (2,75), **J = separación entre pads (4,0)** y **H = alto del pad (5,5)**, y los electrodos están sobre la cota **B = 8,8 mm**. La huella tenía pads de 2,75 × 4,0 a ±4,125 mm (separación 5,5) y el cuerpo dibujado girado. **Lo corregí:** pads de 2,75 × 5,5 a ±3,375 mm (separación 4,0, extensión 9,5), cuerpo de 8,8 × 8,2 y courtyard de 10,0 × 9,0. El netlist no cambia (el nombre de la huella es el mismo). Esto sustituye las cifras de L-53. + +**N2 cerrado:** se añadió **C176** de 100 nF 0603 (C14663) entre `/3V3_GNSS` y GND, junto a U28 en la hoja, con la nota «≤ 2 mm from U28 pin 1». Lo esperado coincide exactamente con lo obtenido. + +**N1 cerrado sin cambio:** la hoja de datos de SCTF (serie 3X, SMD3225-4P) da **1 Xtal, 2 GND, 3 Xtal, 4 GND**, con la misma numeración de vista superior que la huella de KiCad. El mapeo `Crystal_GND24` es correcto. Además, gm_crit = 0,50 mA/V (el F411 admite 1 mA/V) y la CL efectiva queda entre 9 y 11 pF para un cristal de 10 pF. + +**ERC:** 0 errores, 134 warnings (igual que antes). Superposiciones 30 → 30 y cruces 9 → 9 (todos preexistentes). **SHA-256 final del esquemático:** `2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933`. Ningún puerto queda bloqueado por el esquemático. Hay dos avisos que no bloquean: RXA flota durante la transmisión RS-485 (se resuelve en firmware), y la polaridad de USB_BOOT del A7670 es contradictoria entre documentos de SIMCom (hay procedimiento alterno en banco). Se añaden L-63…L-66 a la lista de Michelle. + +## 0. Summary + +| Item | Result | +|---|---| +| Ports-pass verification | **26 PASS · 1 FAIL** (the H-03 land pattern; fixed here, §3) | +| Diff 05-final → ports output (my own code) | 8 added, 0 removed, 8 pin-net changes, 0 net-class changes; every change is on the intended list | +| Sch-derived connectivity vs kicad-cli netlist | identical (353 nets, 0 partition differences, 0 name mismatches), at start and at the end | +| N2 | **C176** 100 nF 0603 C14663, `/3V3_GNSS`–GND, beside U28; expected == actual | +| N1 | **No change**: SCTF datasheet confirms pads 1/3 = crystal, 2/4 = GND | +| Fixes | **F2**: `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod` land corrected to the Sunlord drawing (no netlist effect) | +| ERC (kicad-cli via KiCad MCP) | 0 errors, 134 warnings, before and after | +| Overlaps / wire crossings | 30 → 30 / 9 → 9 (all pre-existing; C176 involved in none) | +| BOM | 299 fitted real parts, all with LCSC numbers (298 + C176); TP1–TP12 and JP1–JP6 excluded; PF* virtual | +| **Final sch sha256** | **`2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933`** | +| Untouched | `.kicad_pcb` `6ddec80d…36bf`, `.kicad_pro` `d577aa43…6ce`, `.kicad_dru` `31ce0f4f…831` | + +## 1. Ports-pass verification table + +Method: I staged the Mac sch (sha256 `f73f41a8…27ee`, equal to the ports pass's claim and its container copy) and re-exported the netlist with the KiCad MCP (`netlists/00-start.xml`). I wrote my own semantic diff against `apply/netlists/05-final.xml` (`work/fdiff.py`, xml.etree only). I derived connectivity directly from the `.kicad_sch` with the apply-verifier's `schconn.py`/`derive_compare.py` after reading them. I used the manufacturers' datasheets through WebFetch and, for image-only PDFs, rendered them with pdf.js in the Mac's browser pane. The screenshots are in `final/evidence/`. The container and Mac shell proxies block ti.com, nxp.com and lcsc.com (403); I did not route around that. + +| # | Item | Intended | Found | Verdict | Evidence / citation | +|---|---|---|---|---|---| +| 1 | Completeness of the change set | only the ports/no-respin items | Diff 05-final → current: +C175, D39, R145, R146, R147, R148, TP12, U32; 0 removed; pin changes J10.8/11/12, U10.2/16, U14.2/3, U15.12; field changes on D6, J10, K1, L2/L6/L8/L20, Q6, R40, R41, TP1–TP8, U14, U15; 0 class changes. Nothing else | PASS | `work/diff_apply_to_start.json`; equals `ports/netlists/final.xml` (0 differences) | +| 2 | U14 → THVD1410DR pinout | = SP3485 (R, RE̅, DE, D, GND, A, B, VCC) | TI D pkg: 1 R, 2 RE̅ (2 MΩ PU), 3 DE (2 MΩ PD), 4 D, 5 GND, 6 A, 7 B, 8 VCC. Netlist: 1 `/SER_RXA`, 2+3 `/RS485_DE`, 4 `/SER_TXA`, 5 GND, 6 `/RS485_A`, 7 `/RS485_B`, 8 `/3V3` | PASS | TI THVD14x0 datasheet, pin functions table | +| 3 | U14 supply | 3.3 V | "3 V to 5.5 V"; U14.8 on `/3V3`; C84 100 nF on `/3V3` (TI: 100 nF per supply) | PASS | TI datasheet | +| 4 | U14 fail-safe / ESD claims | open, short, idle; IEC ESD | "failsafe-high when … open-circuit … short-circuit … idle bus"; IEC 61000-4-2 ±18 kV contact, ±25 kV air; HBM ±30 kV; EFT ±4 kV; bus abs max ±18 V; R = Z when RE̅ = H | PASS | TI datasheet §7, function tables | +| 5 | U32 74LVC1G04 package pinout | DBV: 1 NC, 2 A, 3 GND, 4 Y, 5 VCC | TI DBV table matches; KiCad `SOT-23-5` pads 1-2-3 on the left, 4-5 on the right (standard). Netlist: 2 `/SER_DEA` (U10.1 RTSA̅), 4 `/RS485_DE` (U14.2+3), 5 `/3V3` (+C175), 3 GND, 1 NC | PASS | TI SN74LVC1G04 datasheet; `SOT-23-5.kicad_mod` | +| 6 | Direction polarity, receive in reset/DFU/no firmware | DE = RE̅ = NOT(RTSA̅) | RTSA̅ HIGH → DE = 0, RE̅ = 0 → receiver on, driver off. RTSA̅ LOW → DE = 1, RE̅ = 1 → transmit | PASS | logic plus items 7 and 8 | +| 7 | SC16IS752 RTS̅ after reset | HIGH | NXP Table 5 "Output signals after reset": "RTS HIGH"; MCR and EFCR "all bits cleared"; MCR[1] = 0 → "force RTS output to inactive (HIGH)" | PASS | NXP SC16IS752/762 datasheet | +| 8 | Firmware note EFCR = 0x10 | RTSCON = 1, RTSINVER = 0 | EFCR bit 4 RTSCON "1: transmitter controls RTS pin"; bit 5 RTSINVER "0: RTS = 0 during transmission and RTS = 1 during reception"; §9.1 "asserts the RTS pin (logic 0) once the host writes data … de-asserts (logic 1) once the last bit … has been transmitted". 0x10 is right; bit 0 (9-bit mode) is not needed | PASS | NXP Table 30, §9.1/9.2 | +| 9 | D39 SM712 orientation | pins 1/2 to the lines, 3 to GND | Semtech: "pins 1 and 2 have a working voltage of 12 volts … connected to the differential data line pairs … pin 3 … 7 volts … connected to ground". Netlist: 1 `/RS485_A`, 2 `/RS485_B`, 3 GND. KiCad `SOT-23` pads 1/2 on one side, 3 opposite | PASS | Semtech SM712 datasheet Rev 6.0 (Mouser copy) | +| 10 | R145/R146 bias, DNP | 3V3 → A, B → GND, 390 Ω, DNP | R145 `/3V3`–`/RS485_A`, R146 `/RS485_B`–GND, both DNP; A > B idle = logic 1 (THVD1410: V_ID > V_TH+ → R = H). 3.3 × 60/(780 + 60) = 0.236 V with two 120 Ω terminations | PASS | netlist; TI receiver function table | +| 11 | U15 → TRS3232EIDR pinout | = MAX3232 | TI: 1 C1+, 2 V+, 3 C1−, 4 C2+, 5 C2−, 6 V−, 7 DOUT2, 8 RIN2, 9 ROUT2, 10 DIN2, 11 DIN1, 12 ROUT1, 13 RIN1, 14 DOUT1, 15 GND, 16 VCC; netlist matches pin for pin; narrow SOIC-16 land | PASS | TI TRS3232E datasheet | +| 12 | U15 charge-pump caps | 0.1 µF at 3.3 V | TI table at 3.3 V ± 0.3 V: C1 = 0.1 µF, C2–C4 = 0.1 µF, "C3 … VCC or GND". C85 C1±, C86 C2±, C87 V+ → GND, C88 V− → GND, C89 VCC, all 100 nF C14663. Unused DIN2 to GND ("connected to VCC or ground") | PASS | TI datasheet | +| 13 | R147 1 k on R1OUT (H4) | R1OUT → R147 → `/SER_RXB`; H4.3 on the U10 side | `/RS232_R1OUT` = {U15.12, R147.1}; `/SER_RXB` = {U10.24, H4.3, R147.2}. An external TTL driver sees ≤ 3.3 mA of contention; RC ≈ 10 ns | PASS | netlist | +| 14 | CTSA̅/CTSB̅ tied to GND | GND, auto-CTS off | NXP: CTS̅ LOW = ready; "only affects the transmit and receive operations when Auto-CTS function is enabled via EFR[7]". Tied LOW is the safe choice: it can never block TX, even if auto-CTS gets enabled | PASS | NXP Table 2 | +| 15 | J10 ACT LED pin 11/12 swap | yellow A = 12, K = 11 | **Hanrun HR911105A drawing, p.1 schematic:** "Yellow LED" with pin 12 on the anode and pin 11 on the cathode; "Green LED" with pin 9 on the anode and pin 10 on the cathode. Netlist: 12 `/ETH_ACT_A` (R97 330 Ω → `/3V3_ETH`), 11 `/ETH_ACTLED` (U11.27); 9 `/ETH_LNK_A` (R96), 10 `/ETH_LINKLED` (U11.25) | PASS | `evidence/hanrun_HR911105A_p1_schematic.jpg` (rendered from lcsc.com/datasheet/C12074.pdf) | +| 16 | J10.8 → GND | Bob-Smith return | Hanrun: "CHS GND P8", through 1000 pF 2 kV to the 4 × 75 Ω node; note "Connect CHS GND to PCB Ground". P7 = NC. P4/P5 = TX/RX centre taps (J10.4 `/3V3_ETH`, J10.5 `/ETH_RCT`) | PASS | same page | +| 17 | W5500 LED drive polarity | active-low, so the LEDs light | W5500 v1.1.0: LINKLED (25) "Low: Link is established"; ACTLED (27) "Low: Carrier sense from the active PMD"; VOL 0.4 V at IOL 8 mA. LED current ≈ (3.3 − 2.0)/330 ≈ 4 mA (HR911105A LEDs: Vf 1.8–2.8 V, 20 mA rated) | PASS | WIZnet W5500 datasheet v1.1.0; Hanrun p.2 | +| 18 | **H-03 footprint `IND-SMD_MWSA0804S` land** | Sunlord recommended land | **Wrong.** Sunlord MWSA-S spec (SPEC No. MWSA50230000) Fig. 4-1 (applies to MWSA0412S–MWSA1265S): **I = pad length along the axis, J = gap between pads, H = pad height across**; electrodes at the **B** ends (D = depth along B, E = height along A). Table 4-1 MWSA0804S: A 8.2±0.3, B 8.8±0.4, C 3.8±0.2, D 1.4±0.3, E 5.0±0.3, I 2.75, J 4.0, H 5.5. The ports pass read J as pad width and H as the gap (and took A as the electrode axis), which gave 2.75 × **4.0** pads with a **5.5** gap at ±4.125 mm. Correct: 2.75 × **5.5** pads with a **4.0** gap at **±3.375 mm** | **FAIL → fixed (F2)** | `evidence/sunlord_MWSA-S_fig4-1_land.jpg`, `…fig4-1_body.jpg`; Table 4-1 row read from the PDF text layer | +| 19 | H-03 body vs courtyard | body fits the courtyard | The old courtyard (11.5 × 9.7) did enclose the body at maximum tolerance in either orientation, but the F.Fab outline was rotated (8.2 on the pad axis instead of 8.8). Fixed with item 18: body 8.8 × 8.2, courtyard 10.0 × 9.0 (max of pads 9.5 / body 9.2 on x, body 8.5 on y, plus 0.25) | PASS (after F2) | §3 | +| 20 | B-13 topology | PC6 USART6_TX → R148 → `/DIN_4G` → U23 (B → A) → modem RXD | `/USART6_TX` = {U16.37, R148.1, K1.10 (DNP)}; `/DIN_4G` = {R148.2, R143.2 100 k PU, U23.7 1B, K1.5/6 (DNP), R108.1 (DNP, never-fit)}; U23.5 DIR = GND → "B data to A" (1B input, 1A output); `/DIN_4G_M` = {U23.2, U19.10 **RXD**, R108.2 (DNP)}; U23 VCC(A) = `/1V8_MODEM`, VCC(B) = `/3V3` | PASS | netlist; evidence `ic_pins_U19.csv` (pin 10 RXD) | +| 21 | Drivers on `/DIN_4G` and neighbouring nets | no two outputs on one net | **Before (05-final):** `/DIN_4G` driven only through K1 COM, from either NC = F9P TXD2 (`/USART1_RX`) or NO = PC6, never both. **After:** `/DIN_4G` has one driver, PC6 via R148; `/USART1_RX` has one driver, F9P TXD2 (U18.27), with PA10 as input and Rdfu1 as PU; `/DIN_4G_M` has one driver, U23.1A; `/BYP_CTRL` (PB5) is now unloaded (R40 DNP); `/KCOIL` and `/Q6_BASE` are all DNP. Fitting K1 together with R148 would put F9P TXD2 against PC6 (both notes say "never") | PASS | §1.1 table | +| 22 | TP12 (1V8) | 1V8 pad beside TP8 for forced download | TP12 on `/1V8_MODEM` (U19.15 VDD_1V8/_EXTVDD). **SIMCom "A7670 Series Hardware Design V1.00"** (A7670C/E/SA): USB_BOOT pin 6 B-PD; "pull the USB_BOOT pin to 1.8V, then apply VBAT … to enter the download mode". **"A7670 & SIM7070 & A7672X Compatible Design V1.02":** A7670X pin 6 marked "●" = "cannot be pulled up before the module powered up"; "pull up the USB_BOOT pin to 1.8V for A7670". The v6 symbol names the pin `USB_BOOT●`. **Conflict:** "A7672X/A7670X Series Hardware Design V1.03" lists A7670SA and gives USB_BOOT B-PU with "pull the USB_BOOT pin to GND". TP12 matches two SIMCom documents; a GND fallback is recorded (A2, L-65) | PASS (with note A2) | SIMCom documents as cited | +| 23 | TP1–TP8 out of BOM/CPL | `in_bom no`, `in_pos_files no` | TP1–TP12 and JP1–JP6 all `in_bom no`, `in_pos_files no`, `on_board yes`; none appears in the kicad-cli BOM | PASS | sch flags; `bom_final_ungrouped.csv` | +| 24 | New/changed LCSC numbers | exist, package, stock | C2671345 THVD1410DR SOIC-8, 8 006 (Extended, **pre-order category**) · C7827 SN74LVC1G04DBVR SOT-23-5, 163 327 · C12067 SM712.TCT SOT-23, 49 238 · C308878 TRS3232EIDR SOIC-16 (narrow), 3 564 · C14663 100 nF 0603 X7R 50 V, Basic, 37.5 M · C23151 390 Ω 0603, Basic, 311 280 · C21190 1 kΩ 0603, Basic, 39.8 M · C21189 0 Ω 0603, Basic, 13.9 M. Inductors unchanged: C17700171 (470), C17700165 (646), C17700167 (1 675) | PASS | `get_jlcpcb_part` (all 11) | +| 25 | ERC | 0 errors | 0 errors / 134 warnings at start (same families as reported) | PASS | KiCad MCP `run_erc` | +| 26 | Sch ↔ netlist | derived = exported | 353 = 353 nets, 0 differences, 0 name mismatches (variant MR, −1, wire-interior on) | PASS | `derive_compare.py` | +| 27 | Overlaps / crossings | not worsened | 30 / 9. The two crossings on U10 (x = 551.18) and the four on U15 pre-date the ports pass (21 wires added, 0 removed, none of them among the crossings) | PASS | MCP checks; wire diff vs `ports/state/00-pre.kicad_sch` | + +### 1.1 Drivers per net, before and after (B-13) + +| Net | Before (05-final, K1 fitted) | After (current) | Outputs fighting? | +|---|---|---|---| +| `/DIN_4G` | K1 COM (5/6), R143 100 k PU, U23.7 input, R108 DNP | **R148 ← PC6** (single driver), R143 PU, U23.7 input; K1 and R108 DNP | No | +| `/USART6_TX` | U16.37 PC6, K1.10 (NO) | U16.37 PC6, R148.1; K1.10 DNP | No | +| `/USART1_RX` | U18.27 F9P TXD2, U16.43 PA10 input, Rdfu1 PU, K1.1 (NC) | U18.27, PA10, Rdfu1; K1.1 DNP | No | +| `/DIN_4G_M` | U23.2 (1A out), U19.10 RXD, R108 DNP | unchanged | No | +| `/BYP_CTRL` | PB5 → R40 → Q6 → K1 coil | PB5 only (R40 DNP): set it as output LOW or analog in firmware | — | + +When the MCU is in reset or DFU, PC6 is Hi-Z and R143 holds `/DIN_4G` HIGH (UART idle). With the modem off, 74LVC2T45 Ioff isolates the A side. + +### 1.2 Advisories (not failures; nothing to change in the schematic) + +- **A1. RXA floats during RS-485 transmit.** With RE̅ tied to DE, THVD1410 R = Z whenever DE = 1 (TI receiver table), and NXP documents no pull-up on RXA. TI's own typical application ties R straight to the UART RX, so this is not a datasheet violation and does not stop the port. The SP3485 behaved the same way. **Firmware:** after each frame, wait for LSR[6] (TEMT), reset the RX FIFO (FCR[1]), read LSR to clear any error flags raised during TX, and only then arm reception. An alternative is EFCR[1] RXDISABLE while transmitting. A 10 k pull-up on `/SER_RXA` would make this unnecessary, but it is an optional robustness item, not an error, so it was not added. +- **A2. USB_BOOT polarity conflict in SIMCom documents** (item 22). The bench procedure is to short TP8–TP12 at modem power-on; if the download port does not enumerate on J9, short TP8 to GND instead. L-65 keeps a GND point within reach. +- **A3. Cosmetic:** pre-existing text crowding at U14 value / R82 / JP5 and C85–C88 on U15 (already in the 30-overlap baseline). No electrical effect. +- **A4.** The ports report quotes the SM712 at 400 W (8/20 µs, the LCSC description); the Semtech Rev 6.0 sheet lists a higher peak pulse power class. Either value suits a cabinet-internal RS-485 run. + +## 2. N1 and N2 + +### N2: TPS2552 input decoupling (U28) +TI TPS255x: "Input voltage; connect a 0.1 µF or greater ceramic capacitor from IN to GND as close to the IC as possible." U28 DBV pin 1 = IN = `/3V3_GNSS`. The existing C170 (100 nF on `/3V3_GNSS`) sits elsewhere on the sheet (U27/F9P area), so it does not meet "close to U28". + +**Done:** **C176** = 100 nF 0603, LCSC **C14663** (Basic, 37.5 M in stock), pin 1 `/3V3_GNSS`, pin 2 GND. It sits at sheet (457.2, 182.88) rotated 90°, directly above U28, with the sheet note "N2: C176 = U28 IN decap, <=2 mm to U28.1" and a `Note` field that states the layout rule. C176 is the next reference after the highest used (C175); none of the gap numbers exists on the PCB either. + +### N1: Y3 pad assignment (SCTF SX3B25.000F1010F30, C2901684) +**Confirmed from the manufacturer datasheet**: SCTF "3X Series 3.2 × 2.5 mm SMD Crystal" (LCSC copy `2110101030_Shenzhen-SCTF-Elec-SX3B25-000F1010F30_C2901684.pdf`, rendered with pdf.js). The pin table reads **1 Xtal, 2 GND, 3 Xtal, 4 GND**. The top view numbers 1 bottom-left, 2 bottom-right, 3 top-right, 4 top-left, which matches KiCad `Crystal_SMD_3225-4Pin_3.2x2.5mm` (pad 1 at (−1.1, +0.85), 2 at (+1.1, +0.85), 3 at (+1.1, −0.85), 4 at (−1.1, −0.85)). The netlist has Y3.1 `/HSE_IN`, Y3.3 `/HSE_OUT`, Y3.2/Y3.4 GND. **No change.** + +Cross-checks from the same sheet: CL 6–20 pF (part code "10" = 10 pF), C0 ≤ 3 pF, ESR ≤ 30 Ω (20–54 MHz), drive level typ 10 / max 100 µW. From ST AN2867: gm_crit = 4 · 30 Ω · (2π · 25 MHz)² · (3 + 10 pF)² = **0.50 mA/V**, against the STM32F411 HSE Gm_crit_max of 1 mA/V (margin 2). C113/C114 = 12 pF give CL_eff = 6 pF + Cstray (3–5 pF) = **9–11 pF** for the 10 pF part. `evidence/sctf_3X_p1_specs.jpg`, `sctf_3X_p2_pinout.jpg`. + +## 3. Fixes, with proof + +### F1: N2 (schematic) +- **Expected, written before editing** (`out/F1-N2/expected_written_before_edit.json`): +C176 {100nF, `Capacitor_SMD:C_0603_1608Metric`, `Device:C`, LCSC C14663, fitted, in BOM/CPL, 1:`/3V3_GNSS`, 2:GND}; `/3V3_GNSS` gains C176.1; GND gains C176.2; nothing else. +- **Edit:** `tools/gF1_n2.py` uses the apply-pass editor (`apply/tools/ops.py`: splice-only, UUID multiset guard). The text diff is **152 lines added, 0 removed or changed**: 1 symbol, 2 wires, 2 labels, 1 text. The C176 field angles were set to 90 to match the sheet's other rotated passives (L6, RS1), patching only the block the script generated. +- **Actual:** netlist `00-start.xml` → `final.xml`: added 1 (C176, exactly the expected attributes and pins), removed 0, field changes 0, pin changes 0, class changes 0, membership changes as expected. **EXPECTED == ACTUAL.** Sch-derived connectivity also shows only the GND and `/3V3_GNSS` groups changed. +- Structural checks: orphan NC flags, NC on connected pins, dangling wire ends, dangling labels and unconnected pins without NC all stay at 0 → 0. + +### F2: H-03 land pattern (library file `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod`) +- **Error, with evidence:** item 18 (Sunlord MWSA50230000 Fig. 4-1 and Table 4-1). +- **New geometry:** pads 1/2 SMD round-rect **2.75 × 5.5 mm** at **x = ∓3.375 mm** (gap 4.0, outer extent 9.5); F.Fab body **8.8 (x) × 8.2 (y)**; F.CrtYd **10.0 × 9.0 mm**; silk lines at y = ±4.21 (≥ 1.4 mm from the pads); Reference/Value at y = ∓5.5. All 11 UUIDs of the old file are kept; the name is unchanged, so L2/L6/L8/L20 keep the same footprint link and **the netlist is unaffected**. +- **Coverage at the tolerance extremes:** the electrode spans x = 2.9…4.6 mm (B 8.4–9.2, D 1.1–1.7), inside the pad's 2.0…4.75 mm; E ≤ 5.3 mm fits inside H = 5.5 mm. The electrode is fully wetted, with a 0.35 mm toe and a 1.0 mm heel as Sunlord specifies. This land is also closer to the old SRU8028 land (outer ±4.9 mm) than the ports-pass version (±5.5 mm), so it disturbs placement less. +- Old file backed up; sha256 `dbf53557…a71f` → **`74528135d4f69617df8570da58700bac3920827a78ec9104c3440be2c5975638`**. The KiCad MCP cannot open project-local libraries; the file parses cleanly (sexpdata) in KiCad 9 writer format, and ERC (which checks footprint links) reports 0 errors. + +### Hashes and commits + +| Step | File | sha256 (Mac, checked after every commit) | Staged path used | +|---|---|---|---| +| start | `hbox-watchdog-v6.kicad_sch` | `f73f41a8…27ee` | — (backup `_to_delete/v6-final-20260928/00-pre/`) | +| F1 (first write) | sch | `889b3c32…1ef` | `/mnt/user-data/outputs/v6final-F1-N2-20260928a/` | +| F2 | `IND-SMD_MWSA0804S.kicad_mod` | `74528135…5638` | `/mnt/user-data/outputs/v6final-F2-H03-20260928b/` | +| F1 (fields horizontal, **final**) | sch | **`2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933`** | `/mnt/user-data/outputs/v6final-F1b-N2-20260928c/` | +| PDF | `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf` | `ae88d524…746b` (old `41241140…91b0` in `00-pre/`) | exported by the KiCad MCP | + +The only difference between the two F1 writes is C176's own UUID; C176 was never on the PCB. + +## 4. ERC + +| State | Errors | Warnings | Overlaps | Crossings | +|---|---|---|---|---| +| Start (`f73f41a8`) | 0 | 134 | 30 | 9 | +| After F1 + F2 (final) | 0 | 134 | 30 | 9 | + +## 5. Final state + +- **Schematic sha256: `2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933`** +- Total vs the apply-pass final (`05-final.xml`): +9 parts (C175, C176, D39, R145, R146, R147, R148, TP12, U32), 0 removed, 8 pin-net changes (J10.8/11/12, U10.2/16, U14.2/3, U15.12), 0 net-class changes. +- Final netlist: `final/netlists/final.xml` (sha256 `7b65595f…607c`; Mac copy `_to_delete/v6-final-20260928/netlists/final-b.xml`). + +## 6. Additions to Michelle's layout list (continuing from L-62) + +63\. **MWSA0804S land corrected (supersedes the figures in L-53).** L2/L6/L8/L20 now use pads of **2.75 × 5.5 mm at ±3.375 mm** (gap 4.0, outer extent 9.5), courtyard **10.0 × 9.0 mm**, with the body's 8.8 mm side along the pad axis. The land is smaller than the ports-pass version (11.5 × 9.7) and close to the old SRU8028 land, so neighbour spacing is easier than L-53 said. Keep L-11/L-21/L-22/L-23 distances measured to the new pads. If the ports-pass version of this footprint was already pulled into the board, refresh **only these four refs** from the library (L-45). + +64\. **C176 (N2):** 0603 **≤ 2 mm from U28 pin 1 (IN)**, on the same layer as U28. Its GND pad goes to the GND plane through a via ≤ 1 mm away, and U28 pin 2 uses the same GND region. Feed `/3V3_GNSS` to U28.1 through the C176 pad (the cap sits between the supply trace and the pin). + +65\. **TP8 / TP12 forced-download pads (A2):** TP12 (1V8) at 2.54 mm from TP8 (L-55), plus a **GND contact within 10 mm of TP8**, such as J9's shell tab (SH = GND) or another GND pad. Silk: "BOOT: TP8–1V8 (alt: TP8–GND)". + +66\. **J10 LED routing check:** after Update PCB, confirm pad 12 = `/ETH_ACT_A` (to R97) and pad 11 = `/ETH_ACTLED` (to U11.27), per the Hanrun drawing (yellow A = 12, K = 11). Pad 8 = GND per the Hanrun note "Connect CHS GND to PCB Ground" (L-52). + +## 7. Firmware notes added (FW 0.7.x `board_v6.h`) +1. RS-485 RX hygiene (A1): flush the RX FIFO and clear LSR after each transmitted frame (LSR[6] TEMT → FCR[1]), or use EFCR[1] RXDISABLE during TX. Keep EFR[6] (auto-RTS) and EFR[7] (auto-CTS) = 0 while EFCR RTSCON = 1. +2. PB5 (BYP_CTRL) is unconnected now (R40 DNP): configure it as output LOW or analog. +3. Modem forced download: try TP8–TP12 (1.8 V) first; if J9 does not enumerate the download port, use TP8–GND (A2). + +## 8. Anything that still blocks a port or the order +**Nothing in the schematic.** Remaining conditions: + +- **Layout:** L-49…L-66, especially L-63 (use the corrected MWSA land before routing the switchers) and L-64. +- **Library pass (optional):** `Drogheda-sym:TPS2552DBV` is still embedded-only (from the apply pass). +- **Order logistics:** pre-order THVD1410DR (C2671345, JLC pre-order category), U21 and J14; buy the P11/P12 mating plugs. +- **Bench, first board:** both J10 LEDs light with link up; RS-485 idles in receive during MCU reset and in DFU; RS-485 loopback with EFCR = 0x10 (checking the A1 FIFO handling); RS-232 and H4 checks; J9 download mode (TP8–TP12, then TP8–GND if needed); L6/L8/L20 solder joints inspected on the new land. + +## 9. Files +- This report: `/home/claude/v6audit/final/2026-09-28_Drogheda_EinarBoard-v6_Final-Check_v1.0.md` +- Final netlist: `final/netlists/final.xml`; start: `netlists/00-start.xml`; intermediate: `netlists/01-N2.xml` +- Final schematic copy: `final/hbox-watchdog-v6.kicad_sch.final`; footprint: `final/IND-SMD_MWSA0804S.kicad_mod.final`; PDF: `final/hbox-watchdog-v6-schematic.pdf`; BOM: `final/bom_final_ungrouped.csv` +- Proof: `final/out/F1-N2/` (expected written before the edit, edit log, output), `final/out/F2-H03/`, `final/work/diff_*.json`, `final/work/fdiff.py` +- Scripts: `final/tools/gF1_n2.py` +- Datasheet evidence: `final/evidence/` (Hanrun p.1/p.2, Sunlord Fig. 4-1 body and land, SCTF p.1/p.2, sheet crop of U28/C176) +- Mac backups: `kicad/_to_delete/v6-final-20260928/` (`00-pre/` sch and old PDF, `01-N2/` post and post-b, `02-H03-land/` pre and post footprint, `netlists/`, BOM, new PDF) +- Git (for Leo; nothing was run here): in the `kicad` submodule commit `hbox-watchdog-v6.kicad_sch` and `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod`, then bump the parent gitlink with `git -c diff.ignoreSubmodules=none commit …`. If KiCad is open on v6, close it without saving before Update PCB. + +## 10. F3: LFP-HT backup-pack straps (mirror of V5.6) + +**Resumen (ES):** v6 quedó con los mismos estrapes del cargador que V5.6 para el paquete LFP-HT 26650: JP2 puenteado 2-3 +(F2 a GND) y R55 = 5.6 k (C23189). Flotación **3.50 V** (antes 4.00 V Li-ion). Netlist: 0 cambios de pin o de red. +ERC 0 errores (135 avisos). Esquemático `d58a89ba…e7b`. + +**Reason.** On 28-Sep Leo chose a high-temperature LiFePO4 26650 pack for V5.6, and v6 uses the same pack family. v6 was still +strapped Li-ion (JP2 F2 high, R55 10 k): an LFP pack would have floated at **4.00 V instead of about 3.50 V** (overcharge hazard). + +| Ref | V5.6 (reference) | v6 before | v6 after | +|---|---|---|---| +| JP2 (F2) | `Jumper:SolderJumper_3_Bridged23`, fp `Drogheda:SolderJumper-3_P1.3mm_Bridged23_RoundedPad1.0x1.5mm`, value `F2:LFP (2-3)` | Bridged12, `F2:Li-ion` | **= V5.6**, Note "LFP-HT (F2 low), same as V5.6" | +| R55 (RNTB) | 5.6k/1 % 0603, C23189, `/VEH5V`–`/NTC` | 10k/1 %, C25804 | **5.6k/1 %, C23189** | +| JP3 (F1), JP4 (F0) | F1 = 0, F0 = 1 | same | unchanged | + +- **Netlist confirmation:** U6.12 F2 = `/F2_SEL` = {JP2.2}; U6.13 F1 = {JP3.2}; U6.14 F0 = {JP4.2}; U6.17 NTC = {R55.2, P3.3, R137.1}; R55.1 on `/VEH5V` (the RBIAS of the ADI datasheet). +- **Float voltage** (ADI LTC4040 datasheet, pin-function table): F2 = 0 selects LiFePO4; (F1, F0) = (0, 1) → **3.50 V**. +- **Charge window** with R55 = 5.6 k and a 10 k B3380 NTC: hot pause **+60 °C**, cold ≈ **+8 °C** on v6 (the F-51 tap R137/R138 shifts the cold trip about 2 °C). +- **Proof:** expected changes written before the edit; netlist diff: 0 added, 0 removed, 0 pin-net, 0 membership and 0 class changes; only JP2 value/footprint/lib/Note and R55 value/LCSC/Note changed (plus JP2's footprint-filter text, which follows the symbol swap exactly as on V5.6). +- **ERC:** 0 errors, 135 warnings (+1: the embedded Bridged23 symbol is not in the KiCad library, as on V5.6). +- **Hashes:** sch `2b394ef9…2f5933` → **`d58a89ba5a5ac46419edf9d68672a8208d825a16387298d0167e21399cd41e7b`**; PDF `3e073181…4362`; PCB `6ddec80d…` untouched. +- **Layout L-67 (safety):** after Update PCB confirm JP2 is the Bridged23 footprint with copper on pads 2-3 and no 1-2 bridge left; silk "F2: LFP". +- **Firmware / bench:** measure `/F2_SEL` = 0 V, `/F1_SEL` = 0 V, `/F0_SEL` = MAIN5V on the first board before connecting a pack; rescale the PC5 NTC conversion (RBIAS 5.6 k, β 3380); raise the `CHRG_EN` hot cut in step with +60 °C; LFP-appropriate SoC thresholds or coulomb counting. diff --git a/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md index 73332c7..51b158c 100644 --- a/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md +++ b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md @@ -11,6 +11,12 @@ author: Helgen Technologies !!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide" Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios. +!!! info "Estado al 28-sep (noche)" + Las correcciones de esquemático de esta auditoría **ya están aplicadas y verificadas** de forma independiente + (esquemático final `d58a89ba…`, ERC 0 errores; incluye los estrapes del paquete LFP-HT, igual que V5.6); falta el layout. Estado por hallazgo, decisiones y lista de trabajo: + [Plan de corrección y estado](v6-plan-correccion.md) · qué cambió en cada pasada: + [Cambios de esquemático — resumen de 3 pasadas](v6-cambios-resumen.md). + Responsable: Leo (Helgen Technologies) · Fecha: 2026-09-28 · Versión: 1.0 · Autor: Helgen Technologies (elaborado con asistencia de Claude) · Alcance: auditoría de solo lectura de `03-Architecture-Hardware/kicad/hbox-watchdog-v6.*`; no se modificó ningún archivo de KiCad · Brief: `2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_Agent-Brief_v1.0.md` · Documento compañero: [Pin map MCU v6](v6-pinmap.md) · Lo que se aplicó de esta auditoría: [Informe de cambios al esquemático v6](v6-cambios-esquematico.md) **Snapshot del diseño (KiCad 10.0.4, versión de archivo de tarjeta 20260206).** Tarjeta: 4 capas, 140.0 × 100.0 mm, 312 huellas, 1999 segmentos de pista, 210 vías, 205/205 nets multi-pad ruteadas. Esquemático: una hoja plana, 328 símbolos en la netlist. Hashes de los archivos en el anexo de trazabilidad. diff --git a/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0_EN.md b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0_EN.md new file mode 100644 index 0000000..e445e13 --- /dev/null +++ b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0_EN.md @@ -0,0 +1,1650 @@ +--- +title: "EinarBoard v6 — Auditoría completa (original en inglés, 28-sep-2026)" +tags: [project-drogheda, hardware, hbox, v6, pcb, audit, jlcpcb] +project: Project Drogheda +author: Helgen Technologies +date: 2026-09-28 +version: 1.0 +status: ACTIVE — do NOT order until the release checklist is closed +audience: Leo, Michelle (layout), engineers +--- + +# EinarBoard v6 — Full pre-fab audit (v1.0) + +!!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide" + Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios. + +!!! info "Update 28-Sep-2026: schematic fixes applied and independently verified" + The schematic-level fixes from this report have since been applied in `hbox-watchdog-v6.*` and independently + verified in three passes: audit fixes (173 PASS / 0 FAIL), ports and no new version, and a final check (the one FAIL, + the inductor land, was fixed). Final schematic sha256 `d58a89ba…e7b` (after a fourth pass that aligned the charger straps with the V5.6 LFP-HT pack), ERC 0 errors; the `.kicad_pcb` is untouched + until Michelle runs *Update PCB from Schematic*. Status, final state per block and the layout delta: + **[EinarBoard v6 — Cambios de esquemático: resumen de las 3 pasadas](v6-cambios-resumen.md)**. + Spanish translation of this report: [Auditoría completa v6](v6-auditoria-completa.md). + +!!! info "Correction plan, decisions and status: Spanish page" + This is the audit report as written on 28-Sep-2026 (read-only, before any correction). + The decisions taken afterwards on Leo's delegation (D1–D18), the status of every Blocker and Major, + Michelle's layout work list and the release checklist are on + **[EinarBoard v6 — Plan de corrección y estado](v6-plan-correccion.md)**, and the schematic + edits are summarised in [the 3-pass summary](v6-cambios-resumen.md). + Where the decisions differ from this report: **G-01 is a Blocker** (the V5.5 backplate is reused), + **F-51 is implemented in full** (sensor ≤ 10 mm of U6 is binding), **PD2 = `ETH_PWR_EN`** with the board ID + detected in firmware only (D-08 not applied), E-03 keeps Y1 with C95/C96 → 33 pF, and the schematic changes + were applied **in place** in `hbox-watchdog-v6.*` (not on a `-audit` copy; the `.kicad_pcb` is Michelle's). + Cost figures are not published on this site. + +**Owner:** Leo (Helgen Technologies) · **Date:** 2026-09-28 · **Version:** 1.0 · **Author:** Claude for Leo (four block auditors, two independent verifiers, one editor) · **Scope:** read-only audit of `03-Architecture-Hardware/kicad/hbox-watchdog-v6.*`; no KiCad file was modified · **Brief:** `2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_Agent-Brief_v1.0.md` · **Companion:** `pinmap-v6.md` + +**Design snapshot (KiCad 10.0.4, board file version 20260206).** Hashes identical at the start and end of evidence collection (20:22–20:58 UTC). + +| File | sha256 | mtime (UTC) | +|---|---|---| +| `hbox-watchdog-v6.kicad_sch` | `ecee9fed851f02e74074340bf8361bced7c385b2502b19c368861b9851c2f04a` | 2026-09-25 20:27:58 | +| `hbox-watchdog-v6.kicad_pcb` | `6ddec80d1c15f79e69dff6c1a850b28345a5d826389f79cee8c61998240b36bf` | 2026-09-28 17:36:06 | +| `hbox-watchdog-v6.kicad_pro` | `25c57f3936b96a4e31cb5947668c172d318189258d6a5d2fa34d230df8958028` | 2026-09-28 20:16:16 | +| `hbox-watchdog-v6.kicad_dru` | `47538e6cfadc0c53421ff59dadabc0e7f0ad5f11d9e2250618728788080aca1a` | 2026-09-25 18:57:05 | + +Board: 4 layers, 140.0 × 100.0 mm, 312 footprints, 1999 track segments, 210 vias, 205/205 multi-pad nets routed. Schematic: one flat sheet, 328 netlist symbols. + +--- + +## Resumen ejecutivo (ES) + +1. **¿Listo para ordenar? NO.** Condiciones para ordenar: (a) cerrar los **10 Blockers** (valores y campos de BOM, dos piezas nuevas —TPS2552 con sus 2 resistencias y un SMBJ33A—, reglas de diseño y layout); (b) Leo confirma el patrón de agujeros de la placa base (**G-01** es Blocker si se reutilizan los standoffs de la V5.5); (c) DRC limpio con las reglas corregidas de **F-01** como puerta de salida; (d) los **19 Major** hechos o con razón escrita (escala del brief: «deben cambiar antes de pedir salvo razón escrita»). Ningún hallazgo cambia la arquitectura de la v6. +2. **Conteo tras fusiones** (81 hallazgos activos; 36 IDs absorbidos en su hallazgo primario; mapa completo en el Apéndice D): + + | Severidad | Número | + |---|---| + | Blocker | **10 + 1 condicional** (G-01) | + | Major | **19** (incluye V1-01, nuevo del verificador 1, y H-02b, separado de H-02) | + | Minor | **30** | + | Note | **21** | + +3. **Blockers**, una línea cada uno (orden de riesgo): + 1. **A-01** — La rama `/24V` sin fusible alimenta U20 y U2; **D21** (Schottky 30 V) ve 23.5 V inversos con el bus cargando a 28.8 V y 30.7 V a 36 V → fuga con riesgo de embalamiento térmico a 45–60 °C; un D21 en corto pone 24 V sin fusible en `MAIN5V`. Arreglo: U20 solo desde `MAIN5V` (sin D20/D21), ventilador desde `VEH5V` (bloque U2 DNP), **F2 3 A (C206912) delante de D10**. + 2. **F-02** — La ignición cruda `/IGN_IN` (9–36 V) corre **106.5 mm en In2 a 0.221 mm de `/VEH5V`**: la geometría del corto del 23-jul otra vez, en el mismo par de redes. Arreglo: Rig1 a ≤ 3 mm de cobre de P1.3 + SMBJ33A (C224019). + 3. **F-01** — Netclasses rotas (solo `/24V_IN` resuelve a HV24) y una regla de 0.15 mm que anula todas las demás: el «DRC 0 errores» no puede ver ningún espaciado de 24 V. Arreglo: tabla de netclasses + `.kicad_dru` corregido por verify_2 (incluye la regla HV24↔HV24). + 4. **H-04** — U25 lleva `LCSC Part` = C2071691 (AP64350, 40 V) además de `LCSC` = C524806; Fabrication Toolkit lee `LCSC Part` primero → se ensamblaría un buck de 40 V detrás de un clamp de 53 V. Arreglo: borrar el campo en la tarjeta y en la huella de librería. + 5. **C-01** — El bias de la antena GNSS no tiene limitador (u-blox exige ≥ 10 Ω); un coaxial en corto supera los 300 mA abs. máx. de VCC_RF y los 400 mA de L21. Arreglo: **TPS2552DBVR (C46506)**, 75 mA, ANT_OFF → EN̅, FAULT̅ → ANT_SHORT_N. + 6. **B-03** — La ESD de la antena LTE (D28 ESD9L5.0, unidireccional 5 V) conduce en cada semiciclo negativo (−0.6 V) y avalancha en GSM (14.1 V pico). Arreglo: **PESD0402-240 (C1975527)**, bidireccional 24 V, o DNP (la PGB1010402KR propuesta solo aguanta 12 VDC). + 7. **A-02** — Cobre y placement del LTC4040 repiten la lección F5: `/SW_BAT` 0.5 mm × 11.9 mm con cuellos de 0.25/0.30 mm, EP de U6 sin vías, L6 a 8.65 mm, C30/C31 a 7.2/6.2 mm, sensor más cercano a 71.4 mm. Arreglo: layout (pour ≥ 2 mm, 9 vías en el EP, re-agrupar). + 8. **A-03** — R50 = 825 Ω programa 2.42 A (2.28–2.57 A; la esquina alta supera los 2.5 A máx. del LTC4040). Arreglo: **1.43 kΩ (C22840)** → ≥ 1.316 A en todas las esquinas (1.5 k de la ECO da 1.254 A mínimo). + 9. **H-01** — U15 MAX3232**ESE** (SO-16 angosto) sobre huella SOIC-16W (filas a 9.3 mm): no se puede soldar. Es una **regresión de la v6** (la V5.5 se fabricó con la huella angosta). Arreglo: `SOIC-16_3.9x9.9mm` en esquemático y PCB, mantener C15846. + 10. **H-02** — Sin stock para ningún pedido: U10 (15 pzas) y R53 (6 pzas, mínimo JLC 20). R53 fija el voltaje del boost de respaldo. Arreglo: U10 → **C57156** (SC16IS752, idéntico en I²C), R53 → **C177479**. + 11. *(condicional)* **G-01** — Falta el agujero MH4 de la V5.5 en (193.2, 90.3) (L6 queda encima) y los agujeros de la abrazadera del disipador (MH11 + pareja). Blocker si la placa base de la V5.5 se reutiliza; si se re-taladra, pasa a documentación. +4. **Majors (19):** V1-01 polaridad inversa derrota a D10 (F2 primero) · A-04 R121 57.6 k (5.32 V) · F-12 vías de tierra/EP/módulos/costura (69 vías vs ≥ 400) · F-03 lazos calientes de U25/U20/U12 · B-02 bulk de VBAT_MODEM → polímero + compensación 113 k/6.8 nF/56 pF · D-01 U24 retro-alimenta al F9P apagado · E-01 3V3_ETH conmutable (PD2) · F-51 sin temperatura de cargador ni de celda en el MCU · A-05 presupuesto en batería + CSYS · A-07 cuellos del camino de 5 V en capas internas · F-06 líneas RF (LTE 22 mm en In1) · F-05 In1 no es plano (19 % vacío, 1572 mm de pistas) · C-04 Q1 del F9P a 9 mm de la antena LTE · G-02 J9 sin ESD · A-08 AMS1117 → TLV1117LV33 · A-09 C78 electrolítico 85 °C → polímero · C-02 rampa de VCC del F9P → TPS7A2033 · E-02 ETH_RST 4.7 k · H-02b stock a verificar el día del pedido. +5. **Qué puede esperar a v6.1:** los 30 Minor y los 21 Note (§5 parte 3), más lo que los hallazgos difieren explícitamente: K1 → enlace directo PC6 → DIN_4G (B-13), PoE (E-07), U12 → AP64350 (A-20a), P3 → JST-XH-5 si se rehace el arnés (G-07). Ningún Major está marcado como diferible; E-02 baja a Minor si se adopta E-01. +6. **Firmware (FW 0.7.x, `board_v6.h`), lo más importante:** (1) `board_v6.h` desde `pinmap-v6.md`; un binario V5.6 en v6 choca en PC3 contra RTK_STAT; (2) primeras líneas de `setup()`: PC10, PC8, PC11, PA1, PB5, **PA15**, PA6, PB0 en LOW; (3) secuencia de ventana: F9P asentado → BAT ≥ 3.4 V → W5500 apagado → `MODEM_PWR_EN` → PWRKEY → STATUS; **nunca PC10 alto con PA1 bajo** hasta tener D-01 en hardware; (4) en batería: **solo LTE** (`AT+CNMP=38`), `ETH_PWR_EN` = 0, K1 solo en la ventana TX; (5) `V5_PFI` 4.60 → **4.40 V**, VDDA desde VREFINT, ignición por ADC con umbrales; (6) `$PHID` (UID 96 bits) por el enlace del módem al conectar y cada 5 min; (7) inhibición térmica con `tcell` (PC5) y `tchg` (TMP102 0x48), campos nuevos al final de `$PHLG`. +7. **Costo:** *cost analysis kept in the repository copy.* + +--- +## 1. Method and evidence + +- **Evidence pack** (read-only, built 2026-09-28 20:22–21:00 UTC): on the Mac at `03-Architecture-Hardware/kicad/_to_delete/v6-audit-20260928/evidence/` (KiCad exports) with the parsed tree under `evidence/pack/`; container copy `/home/claude/v6audit/`. It holds kicad-cli netlists (v6, V5.6, V5.5 as-fabbed), ERC (166 items) and DRC (283 items) outputs, BOM, CPL, IPC-D-356, per-layer PDF/SVG plots, pad/track/via/zone tables parsed from the board file, 64-pin MCU table, per-IC pin tables, 24 V clearance sweep, schematic↔PCB sync report and the firmware pin/constant tables. Self-checks: parsed pads match KiCad's IPC-356 on 1191/1191 pads (worst Δ 1.77 µm, 0 net mismatches); counts match KiCad on every table. Index in Appendix C. +- **Attachments kept with this report** (tracked in the repo, unlike the gitignored evidence folder): `03-Architecture-Hardware/2026-09-28_v6-audit-attachments/`. It holds `erc_summary.md`, `drc_summary.md`, `ercdrc_classified.csv` (all 166 ERC + 283 DRC items with their classification), `bom_check.csv` (152 BOM lines: stock, package, rating), the two verification files `verify_1.md` / `verify_2.md`, and the four block findings files these IDs come from. +- **Audit:** four block auditors, each writing one findings file: power + temperature/fan (A-xx, F-51…F-53), modem/GNSS/Ethernet (B-, C-, E-xx), MCU pin map + connectors (D-, G-xx, plus `pinmap-v6.md`), layout/EMC + BOM + ERC/DRC (F-, H-, J-xx, plus `bom_check.csv` and `ercdrc_classified.csv`). +- **Verification:** two independent verifiers re-derived every item the auditors rated Blocker or Major (plus D-02) from primary sources with their own scripts: verify_1 = power and RF (24 items), verify_2 = layout, BOM, MCU and connectors (22 items). Outcome: 0 refuted; 13 confirmed with corrections; 6 severity changes; 1 new Major (V1-01). **Where auditor and verifier disagree, this report uses the verifier.** Where the two verifiers merged overlapping items differently, the merge is reconciled into one item and the choice is stated (§2 per item, Appendix D). Minor and Note items outside that list are marked *not independently verified*. +- **Tools:** KiCad 10.0.4 through the KiCad MCP server on Leo's Mac (kicad-cli ERC, DRC, netlist, BOM, CPL, IPC-356, courtyard check, zone query); Python `sexpdata` S-expression parsers (`scripts/kisexp.py`; no numeric regex on KiCad files); `shapely` for pad-edge distances, copper islands, plane voids and clearances; a 2-D finite-difference field solver and closed-form (Hammerstad–Jensen, Wadell CPWG) impedance checks; an averaged current-mode model of U20 for burst droop (verify_1 `vbat_sim.py`); JLC parts DB snapshot (`get_jlcpcb_part`, `search_jlcpcb_parts`) for stock, package and price; the Fabrication-Toolkit source (GitHub) for BOM field priority; manufacturer datasheets cited per finding (LTC4040 Rev B, TPS54360B, AP64350 DS41976 Rev 5-2, MP1584, AMS1117, PMEG3050EP, SIMCom A7672X/A7670X HD V1.03 and A7670 HD V1.00, u-blox ZED-F9P-04B DS UBX-21044850 R05 and IM UBX-18010802, AP2112, TPS7A20, TPS2552, W5500 v1.0.2, ST DS10314 Rev 7 / RM0383, Maxim MAX3232 19-0273 Rev 10, Sunlord MWSA, Nexperia 74LVC1G125, IPC-2221B, ISO 7637-2 / ISO 16750-2 levels via TI TIDUC41). +- **Conventions:** "edge" = pad copper to pad copper; "ctr" = pad centre. Stackup for impedance and inner-layer current: JLC04161H-7628 (L1–L2 prepreg 0.2104 mm, εr 4.4; outer 1 oz; inner 0.5 oz by default), because the board file carries the generic 3 × 0.48 mm stack. Island and void analysis uses the zone fills stored in the file; refill before fab and re-check. +- **Finding format:** ID · severity · block; *Absorbs* (merged IDs); *Status* (verified / verified-with-correction / not independently verified); Evidence; Consequence; Fix (value + LCSC, or layout instruction with numbers); Effort (schematic-only / layout / both / firmware-only). Original working-file IDs are kept. **V1-01** is the new Major raised by verify_1; **H-02b** is the part of H-02 that verify_2 re-rated Major. + +--- +## 2. Findings and pass/fail by block (brief §4-A … §4-J) + +### 4-A Power tree (24 V → 5 V → rails), lessons F4 / F5 / F7 + +#### (a) Findings + +##### A-01 · Blocker · Unfused `/24V` branch feeds U20 and U2; D21 (30 V Schottky) reverse-stressed toward thermal runaway +*Absorbs:* B-01, H-05, F-53, F-08, A-06 (U2 row). *Status:* verified-with-correction (verify_1: the Blocker rests on D21 and the unfused branch, not on U2; ISO 7637-2:2011 pulse 2a is +50 V, not +112 V; D32 also clamps `/24V` for fast transients). + +- **Evidence:** + - Netlist: `/24V_IN` = {P1.1, D10, F2.1, Q10.D}. Fused branch F2 (0154002.DR 2 A, C206910) → `/VIN_FUSED` → Q23 → `/VIN_PROT` = {D32 SMCJ33A, C149–C151, U25.2, R124}. **Unfused branch** Q10.S → `/24V` = {C10, C11, C22, Ren1, U2.7, D20.A, DzG1.K}. `/VIN_MODEM` = {D20.K, D21.K, C127, C128, U20.2}; D21.A = `/MAIN5V` (LTC4040 VSYS, after RS1 and Q7). + - Clamping (verify_1): for µs–ms transients `/24V` is clamped by D10 and by D32 through Q10 (65 mΩ) → F2 (≈ 0.05 Ω) → Q23 (65 mΩ), ≈ 0.2 Ω. Neither TVS conducts at 36 V DC (VBR 36.7–40.6 V). "Outside the D32 clamp" holds only for DC and for fusing. + - Ratings: D21 PMEG3050EP VR 30 V, IR 2.6 mA typ / 8 mA max at 30 V, 25 °C, datasheet thermal-runaway warning, Rth(j-a) 60–200 K/W. U2 MP1584 VIN 4.5–28 V, **30 V abs max**, EN abs max 6 V (EN = 24V·20k/120k = 6.0 V at 36 V). U20 AP64350 42 V DC / 45 V for 400 ms. D20/Dbk1 SS34 40 V. + - Stress: 28.8 V charging bus → D21 VR = **23.5 V** (78 % VRRM), U2 0.8 V over its operating max. 36 V / 60 min (ISO 16750-2) → D21 VR **30.7 V > 30 V**, U2 6 V over abs max. Pulse 2a (+50 V, 2 Ω) → D10 ∥ D32 clamp ≈ 42–45 V: U20 at its 45 V/400 ms limit, D21 ≈ 37–40 V reverse (avalanche for 50 µs). Suppressed load dump 58 V: everything on `/24V` over rating (A-19). + - D21 runaway (verify_1): IR ≈ 1.8 mA at 23.5 V/25 °C; stability needs PR < 0.12 W at 120 K/W (0.24 W at 60 K/W). 45 °C board → IR ≈ 7 mA, PR ≈ 0.17 W; 60 °C → ≈ 20 mA, 0.48 W. **Runaway is plausible at port-box temperatures.** + - Layout: the `/24V` 1.5 mm track runs on In1 at 0.15 mm from the In1 GND pour, and a `/24V` via sits 0.15 mm from the B.Cu `/3V3` pour (`clearance_24v.md`). + - Field weighting: on V5.x P1 = 24 V fed only U2 and no U2 failure is recorded, so U2 alone would rate Major. D21, U20/D20 on the unfused branch and the D21-short mode are new on v6. +- **Consequence:** a D21 that fails short puts `/24V` onto `/MAIN5V` with no fuse (LTC4040 VSYS 6 V abs max, U21, U17, F9P, MCU). A short of C10/C22/U2/U20/D22 draws vehicle-fuse current through 0.3–1.5 mm board copper (fire and harness risk). +- **Fix (single topology, verify_1 conflict (a)):** + 1. U20 from `/MAIN5V` only: delete D20 and the 48 mm `/VIN_MODEM` run; merge `/VIN_MODEM` into `/MAIN5V` in copper (no D21). + 2. Fan from `/VEH5V`: DNP U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21; bridge JP1 by changing its footprint to `Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm` (no BOM part; A-01's 0 Ω 0805 alternative has no LCSC in the findings). Fan stays dark on battery, as today (ECO D4). + 3. `/24V` then has no loads: DNP Q10, DzG1, Rrp1, C10, C11, C22. Q23 remains the single reverse-polarity FET. + 4. **F2 → 3 A 0154003.DR, LCSC C206912** (stock 2217), placed electrically **ahead of D10** (V1-01). 4 A C206914 (stock 778) only if sustained 9 V operation is required. + 5. Prerequisites: A-07 (widen `/VEH5V`, `/VIN_SW`, `/MAIN5V`), A-04 (R121 57.6 k), A-05 (CSYS), F-03 (U20 Cin 2 × 22 µF C86817 + 1 × 220 µF C881921 at U20.2). + + - Numbers with the fix (verify_1): U20 input at MAIN5V ≈ 5.25 V, η 0.9: LTE 23 dBm 0.54 A, GSM 2 A **1.61 A**, 2.8 A peak 2.25 A. RS1 path while charging at 1.43 k plus LTE TX: 0.35 + 0.54 + 1.19 = **2.08 A** (< 2.35–2.65 A limit); during a GSM burst the charger is throttled to 0.4–0.7 A (system load has priority, LTC4040 DS p.16). U25 ≤ 2.65 A + 0.3 A fan = **2.95 A** vs 3.5 A rating; overshoot inductor peak ≈ 3.8 A < 4.5 A switch limit. D34 ≈ 0.8 W (≈ 1.0 W as-is). On battery VIN(U20) rises 4.42 → 4.72 V and MAIN5V current at 2 A GSM falls to ≈ 2.0–2.13 A. F2 current 0.74 A at 24 V, 1.48 A at 12 V, 1.97 A at 9 V. PFI margin with 57.6 k: 5.176 V − ≈ 0.2 V droop = 4.98 V vs 4.54 V PFI max (0.44 V; 0.13 V as-is). + - Rejected: D20 → `/VIN_PROT` with a 60 V Schottky (PMEG6045ETPX C552943) keeps U20 at 0–3 V margin to the pulse-2a clamp and costs ≈ 0.15 V of battery headroom. The JSMSEMI clone C53114006 (H-05) has unknown leakage. + - Record for Leo: U20 then sits upstream of the P5 cutoff. The ECO §A intent ("the cutoff switches everything off") still holds functionally, because cutting SYS5V unpowers the MCU and R113 holds U20 EN low (µA shutdown current). +- **Effort:** both. + +##### A-02 · Blocker · LTC4040 (U6) copper, EP vias and placement repeat lesson F5 +*Absorbs:* F-13 (U6 EP part), the In1-under-U6 part of A-14. *Status:* verified (verify_1 re-measured edge-to-edge; caveat: the H0008 thermal-cycling causality is weak, because the ≈ 1.3 A is inferred from an OCV slope and 0.75 W at bench ambient needs θJA > 150 °C/W to reach OT. The Blocker stands on lesson F5, ECO D2 "Obligatorio" and the datasheet layout guidance). + +- **Evidence (verify_1):** + + | Item | v6 | Target (ECO D2) | + |---|---|---| + | `/SW_BAT` U6.21/22 → L6.1 | 6 F.Cu segments, **0.5 mm × 11.89 mm** + 0.25 mm and 0.30 mm necks (0.50 mm long) at the pins, 0 vias; ≈ 12.2 mΩ | ≥ 2 mm polygon | + | `/BAT_PLUS` P3 → L6.2 | 1.0 mm × 21.27 mm | ≥ 1.5 mm + vias | + | `/BAT_PLUS` L6.2 → U6.23 | 1.0 mm, then 0.5 mm × 10.49 mm, then 0.25 mm × 5.38 mm | Kelvin from L6.2/CBAT | + | U6 EP (2.65 × 3.65 mm) | **0 vias**; nearest GND via 3.04 mm edge at (191.6, 104.3) | ≥ 9 vias | + | L6.1 ↔ U6.21/22 | **8.65 mm** | ≤ 5 mm | + | C30 / C31 → U6.6 (VIN) | **7.20 / 6.18 mm** | ≤ 3 mm | + | C32 / C33 / C34 → U6.1 (VSYS) | 3.90 / 3.44 / 4.74 mm, behind 0.30 mm pin necks | ≤ 2 mm, pour | + | C35 (CBAT) → L6.2 | 20.2 mm edge | at L6.2 / BAT pin | + | GND clusters | U6 EP, C32, C30/C31, C35 on a 252 mm² F.Cu cluster with 5 vias; C33 on the 3611 mm² cluster | one solid EP island | + | In1 under U6 | split by 7 `/VFB_BST` segments + `/IGATE` + `/CHRG_*` | solid ≥ 5 mm around U6/L6 | + | Temperature sensor ≤ 10 mm | none; U3 SHT40 at **71.4 mm** | ≤ 10 mm (F-51) | + + - IPC-2221 external rise: `/SW_BAT` 0.5 mm → **+32 °C at 2.42 A**, **+80 °C at 3.6 A** backup battery current; `/BAT_PLUS` 1.0 mm → +25 °C at 3.6 A. The same current at 2.0 mm gives +8 °C. + - LTC4040 has over-temperature shutdown only, no charge-current thermal regulation (DS p.5 Note 2). IC loss ≈ 0.75 W at 2.42 A; as-built θJA ≈ 60–70 °C/W (the 43 °C/W datasheet figure assumes a via array). +- **Consequence:** R5 (≥ 1.3 A without thermal cycling) is not met by layout; in continuous backup the boost node and the VSYS necks run hot. This repeats V5.5 lesson F5 (ECO D2 / EMC 🔴 #1, #2). +- **Fix (layout, Michelle; §6 L-11 … L-16):** L6 pad 1 ≤ 5 mm from U6.21/22; C32/C33/C34 ≤ 2 mm from VSYS pins 1/24 with GND on the EP copper; C30/C31 ≤ 3 mm from pin 6; C35 (or an extra 22 µF 0805, C86817) at L6.2 next to BAT pin 23. `/SW_BAT` F.Cu polygon ≥ 2 mm wide, starting after the combined pin 21+22 fan-out (QFN 0.5 mm pitch), kept compact. `/BAT_PLUS` P3 → L6.2 ≥ 1.5 mm F.Cu or pour (≥ 4 vias per transition if routed inner). `/MAIN5V` pour from pins 1/24 over C32–C34 to the Q7 drain, ≥ 2 mm, no 0.3/0.5 mm necks. EP: **≥ 9 vias, 3 × 3 at 0.9 × 1.2 mm pitch, 0.3/0.6 mm** (fit checked by verify_2; A-02 proposed 3 × 4 = 12 at 0.9 mm), pad `zone_connect` solid. In1/In2 GND solid for ≥ 5 mm around U6/L6 (reroute `/VFB_BST`, `/IGATE`, see A-14). Place the F-51 TMP102 between U6 and L6. +- **Effort:** layout. + +##### A-03 · Blocker · R50 = 825 Ω programs 2.42 A; set 1.43 kΩ to hold ≥ 1.3 A at every corner +*Status:* verified (verify_1). Lesson F4; ECO §C; R5. + +- **Evidence:** RPROG = 2000 V / ICHG (hPROG 2500, VPROG 0.8 V), ±5 % (950/1000/1050 mA at 2 k), maximum charge current 2.5 A (LTC4040 DS p.3, 10, 18). + + | R50 (1 %) | ICHG min | nom | max | + |---|---|---|---| + | 825 Ω (as-is, C50214) | 2.280 A | 2.424 A | **2.571 A** (above the 2.5 A maximum) | + | **1.43 kΩ** | **1.316 A** | 1.399 A | 1.483 A | + | 1.47 kΩ | 1.280 A | 1.361 A | 1.443 A | + | 1.5 kΩ (ECO C, C22843) | 1.254 A | 1.333 A | 1.414 A | + + - H0008 (V5.5, same R50): ≈ 1.3 A average, 8.5 h to termination, pulsed charge. At 1.4 A the IC loss drops ≈ 3× ((2.42/1.4)²). Input side at 1.4 A: 1.4·4.0/(0.9·5.3) ≈ 1.17 A + 0.35 A logic = 1.52 A < RS1 limit, so the charger stops being input-limited. The Li-ion safety timer (4.25 h) counts in CV only. +- **Consequence:** at 825 Ω v6 repeats the H0008 behaviour, runs U25 at the RS1 limit (≈ 2.5 A) whenever charging, and exceeds the IC's 2.5 A maximum at the top corner. +- **Fix:** **R50 → 1.43 kΩ 1 % 0603, LCSC C22840** (Extended, stock 4965). 1.43 k is the largest E96 value with a worst-case minimum ≥ 1.3 A; it costs ≈ 10 % more I²R than 1.5 k. 1.5 kΩ (C22843, Basic) keeps V5.6 commonality but meets R5 only nominally. +- **Effort:** schematic-only. + +##### V1-01 · Major · Reverse polarity is defeated by the D10 position (new) +*Status:* raised by verify_1 ("Anything else" #1); not cross-checked by a second verifier. + +- **Evidence:** D10 (C224019, SMBJ33A) and D32 (C699039, SMCJ33A) are unidirectional parts drawn with a bidirectional A1/A2 symbol, pad 1 (cathode) on the + rail. D10 sits on `/24V_IN`, ahead of F2 and ahead of the Q10/Q23 reverse-polarity FETs. +- **Consequence:** a reversed P1 forward-biases D10 straight across the harness with no board fuse; the SMB part carries harness-fuse current until it fails, typically short. +- **Fix:** F2 electrically first: **P1 → F2 → D10 ∥ Q23** (D10 moves from `/24V_IN` to the F2 output). A reversed connection then blows the socketed Nano2 fuse. ISO 7637-2 pulse 1 (24 V: −600 V, 50 Ω, 1 ms, ≈ 12 A, I²t ≈ 0.07 A²s) is ≈ 7 % of a 3 A Nano2's I²t. A-01 listed this as optional; verify_1 makes it mandatory. Same F2 part as A-01 (C206912). +- **Effort:** both. + +##### A-04 · Major · U25 set-point 5.00 V (4.87–5.14 V) sits below the charge governor's start line; set R121 = 57.6 k +*Status:* verified (verify_1). Lesson F7; ECO §A/§C. + +- **Evidence:** Vout = Vref·(1 + R121/R122), TPS54360B Vref 0.792/0.800/0.808 V (−40…150 °C), 1 % resistors, R122 = 10.2 k. + + | R121 | min | nom | max | vs CHG_RAIL_ON 5.05 V | vs LTC4040 VIN max 5.5 V | + |---|---|---|---|---|---| + | 53.6 k (as-is) | **4.871** | **5.004** | 5.140 | nominal below the start line | ok | + | 56.2 k | 5.069 | 5.208 | 5.350 | low corner +0.02 V | ok | + | **57.6 k** | **5.176** | **5.318** | **5.463** | ≥ 0.13 V above | 37 mV margin | + | 57.6 k, 0.1 % | 5.256 | 5.318 | 5.380 | ok | 120 mV margin | + + - LTC4040 PFI (R51 270 k / R52 100 k, 1.17/1.19/1.21 V, +30 mV hysteresis): **falling 4.27 / 4.40 / 4.54 V, rising 4.38 / 4.51 / 4.66 V**. Firmware `V5_PFI` 4.60 V is stale (it came from the old 287 k). + - ADC reads 5V_SENSE (R7/R8 10 k/10 k) against VDDA = the 3V3 LDO (±1.5 %, lower on battery, A-08): thresholds carry ±2–3 % unless calibrated with VREFINT. +- **Consequence:** with FW 0.6.0 thresholds most v6 units never start charging (R5 fails); margins are thin under modem bursts once the modem moves to MAIN5V (A-01). +- **Fix:** **R121 → 57.6 k 1 % 0603, LCSC C23082** (Extended, stock 3673). Top corner 5.463 V is 37 mV under the 5.5 V VIN operating maximum; load-release overshoot is brief and far below abs max (verify_1). 0.1 % parts optional (no 0.1 % LCSC found in the DB). Firmware: `V5_PFI` = 4.40 V, VREFINT calibration. +- **Effort:** schematic-only (+ firmware constants). + +##### A-05 · Major · Battery-mode budget: 2.25–2.33 A on MAIN5V during a GSM burst; CSYS ≈ 57–69 µF effective +*Absorbs:* nothing (its fix 1 is E-01, fix 3 is in F-03, fix 4 is A-01). *Status:* verified-with-correction (verify_1: the 93–97 % is against the datasheet's guaranteed 2.5 A from ≥ 3.2 V; the hard limit is ILIM(BST) ≥ 5.5 A, which leaves ≈ 30–40 % switch headroom at 3.5 V; a 2.8 A GSM peak at a 3.2 V battery reaches ≈ 5.4 A, i.e. the limit). + +- **Evidence:** what stays alive on battery: BAT → L6 → U6 boost → `/MAIN5V` (VSYS 0.8·(1 + 499k/100k) = **4.60 / 4.79 / 4.99 V**); from MAIN5V: D21 → U20 → modem (ahead of P5; EN held low by R113 when the MCU is unpowered), and P5 → `/SYS5V` → D12 → U17 (3V3), U12 (3V3_ETH, EN tied to VIN = always on), F1 → Q1 → U21 → F9P, K1 coil. CSYS = C32/C33 47 µF 16 V X7R 1210 + C34 10 µF 50 V = 104 µF nominal, **≈ 57–69 µF effective** at 4.8 V, below the 75 µF transient guidance (DS p.21). Worst-case budget below (assumptions: logic 90/120 mA, F9P 100/85 mA, W5500 132 mA at 3.3 V via U12 η 0.85, K1 30 mA, modem 2.0 A GSM peak / 0.7 A LTE / 20 mA idle, U20 η 0.88, boost η 0.88, battery 3.5 V). +- **Consequence:** as-is, a cold modem registration or a GSM burst with everything else on sits at 91–97 % of the guaranteed boost rating with no allowance for > 2 A bursts or an aged pack. Hitting the limit droops VSYS: U17 drops out first (A-08), then VBAT_MODEM < 3.4 V, the V5.5 "modem dark on battery" symptom by another mechanism. R1/R3 need the fixes plus firmware sequencing. +- **Fix:** add **2 × 47 µF 16 V X7R 1210, LCSC C5440143**, at U6 VSYS pins 1/24 (≈ 113 µF effective). Plus: E-01 (gate 3V3_ETH), A-01 (no D21, +0.30 V at U20), A-07 (MAIN5V ≥ 1.5–2 mm to U20), F-03 (U20 Cin), and mandatory firmware sequencing (§8: LTE-only on battery, W5500 off, F9P settled before the modem, refuse modem cold start below VBAT ≈ 3.4 V). +- **Effort:** both. + +**Worst-case current budget (A-05, reproduced by verify_1).** On 24 V, as-is topology, charging with R50 825 Ω / with 1.43 k: + +| Rail | Cold start | Steady | Modem TX burst | +|---|---|---|---| +| /3V3 (U17 out) | 0.120 A | 0.090 A | 0.090 A | +| /3V3_GNSS | 0.100 A | 0.085 A | 0.085 A | +| /3V3_ETH | 0.132 A | 0.132 A | 0.132 A | +| /VBAT_MODEM | 2.0 A pk (0.3 A avg) | 0.024 A | 2.0 A pk | +| /VIN_MODEM @ 23.5 V (from /24V) | 0.37 A pk | 0.005 A | 0.37 A pk | +| /SYS5V | 0.35 A | 0.31 A | 0.31 A | +| /VEH5V (U25 out; charger held off 120 s at boot) | 0.36 A | **2.50 A (RS1-limited) / 1.48 A** | 2.50 / 1.48 A | +| P1 total @ 24 V | 0.50 A | 0.65 / 0.43 A | **1.02 / 0.80 A** | +| P1 total @ 9 V | — | 1.73 / 1.1 A | **2.8 / 2.2 A** | + +On battery, as-is topology (VSYS 4.79 V, VIN_MODEM ≈ 4.4 V after D21): + +| Rail | Cold start (all on, modem registering) | Steady (idle) | GSM TX burst | LTE TX | +|---|---|---|---|---| +| /VIN_MODEM | 1.96 A pk | 0.024 A | 1.96 A pk | 0.69 A | +| /SYS5V (logic + F9P + W5500 + K1) | 0.36 A | 0.32 A | 0.32 A | 0.32 A | +| **/MAIN5V = boost load** | **2.33 A (93 % of 2.5 A)** | 0.34 A | **2.28 A (91 %)** | 1.01 A (40 %) | +| same at VSYS low corner 4.60 V | **2.43 A (97 %)** | 0.34 A | 2.38 A (95 %) | 1.04 A | +| Battery current (3.5 V, η 0.88) | 3.62 A | 0.53 A | 3.55 A | 1.57 A | +| with fixes + FW sequencing (W5500 off, K1 off, F9P deferred, D21 bridged) | **1.95 A (78 %)** | 0.15 A | 1.95 A | 0.85 A | +| with fixes + LTE-only on battery | ≈ 1.2 A (48 %) | 0.15 A | — | 0.85 A | + +verify_1 reproduction: MAIN5V **2.25 A** during a 2 A GSM burst (modem 1.89 A at 4.42 V input, SYS5V ≈ 0.36 A); battery **3.42 A at 3.5 V**, 3.24 A at 3.7 V. Cold-start statement for the modem: B-16 (§4-B). + +##### A-07 · Major · 5 V power path runs the full LTC4040 input current through inner 0.5/0.8 mm tracks +*Absorbs:* J-02 copper on `/VEH5V`, `/VIN_SW`, `/MAIN5V` (J-02 residual stays Minor). *Status:* verified (verify_1; verify_2 adds that JLC04161H inner copper is 0.5 oz by default, which makes the inner runs worse: R ≈ 27 mΩ, 0.17 W over 13.6 mm). + +- **Evidence (widest-path bottlenecks):** `/VEH5V` L22.2 → RS1.1: **In1 0.5 mm × 13.6 mm** (+ In2 1.0 mm × 66.6 mm), 2.5 A while charging → IPC-2221 internal +168 °C (IPC-2152 ≈ half). `/VIN_SW` RS1.2 → Q7: **In2 0.8 mm × 23.6 mm**, +77 °C at 2.5 A. `/MAIN5V` Q7 → U6.24/C32: F.Cu 0.5 mm × 13.3/6.6 mm, +26/+32 °C; U6.1 → C32 0.30 mm neck (A-02). `/MAIN5V` Q7 → D21: 1.0 mm, 40 mm. RS1 Kelvin: CLN sense (U6.7) taps 1.66 mm down the 0.8 mm trace from RS1.2 (+1.0 mΩ) → effective input limit 2.14–2.41 A instead of 2.35–2.65 A (conservative, unintended). verify_2 J-02: under-capacity length `/MAIN5V` 111 mm, `/VEH5V` 102 mm, `/VIN_SW` 26 mm. +- **Consequence:** hot inner copper under U6/Q7 at charge current, extra drop, heat shared with the U6 area. A-01 adds more hours at the RS1 limit, so A-07 is a prerequisite of A-01. +- **Fix (layout):** `/VEH5V` L22.2 → RS1.1 on F.Cu ≥ 2 mm or a pour (move L22/C153/C154 toward RS1), or ≥ 2 mm inner with ≥ 4 vias per transition. `/VIN_SW` on F.Cu ≥ 2 mm, Q7 ≤ 5 mm from RS1/U6. `/MAIN5V` per A-02, and ≥ 1.5 mm all the way to U20. Route U6.7 (CLN) and U6.6 (VIN) sense from the inner edges of the RS1 pads (Kelvin). Either order 1 oz inner copper or widen inner runs by 1.65× (verify_2). +- **Effort:** layout. + +##### A-08 · Major · U17 AMS1117-3.3 drops out on battery and sets a 25–55 mW sleep floor +*Status:* verified (verify_1). + +- **Evidence:** LDO_IN on battery = VSYS 4.60–4.99 V − D12 (≈ 0.3 V) = **4.27–4.67 V**; AMS1117 dropout ≈ 1.0 V at 0.1 A (1.1 V typ / 1.3 V max at 0.8 A) → needs ≈ 4.3 V. Ground current 5 mA typ / 11 mA max → 27–60 mW referred to the battery (boost η 0.88), against the 20–50 mW duty-cycle floor (`drogheda-backup-lowpower`). VDDA = 3V3 via R104 10 Ω while firmware assumes 3.30 V → BAT_SENSE/5V_SENSE read up to +4 % high; the 3.40 V low-battery cut trips at ≈ 3.27 V real. Datasheet asks for 22 µF tantalum; /3V3 is all ceramic. +- **Consequence:** degraded 3V3 exactly on battery, wrong battery telemetry, and a sleep floor as large as the whole target. +- **Fix:** **U17 → TI TLV1117LV33DCYR, LCSC C15578** (SOT-223, same 1-GND / 2-OUT / 3-IN pinout, 1 A, 455 mV at 1 A, ≈ 100 µA Iq, ceramic-stable, VIN max 5.5 V vs LDO_IN max ≈ 5.21 V with 57.6 k; stock 26 999). Do **not** use C48937499 (same MPN listed, wrong die: 1.2 V dropout, 12 V). Firmware: VREFINT calibration. +- **Effort:** schematic-only. + +##### A-09 · Major · C78 is an 85 °C / 2000 h general-purpose electrolytic on the 5 V rail (≈ 1-year life in a port box) +*C130/C131 moved to B-02.* *Status:* verified (verify_1). + +- **Evidence:** C78 (VEH5V bulk) = C2827940 SamYoung MVG 16 V 220 µF, −40…+85 °C, 2000 h @ 85 °C, 130 mA ripple. 10 °C-rule life at 65 °C local (assumption): MVG ≈ 8 000 h (0.9 y 24/7). Others: C10 MVK 105 °C/1000 h (removed by A-01), C3/C103 Rubycon TZV 105 °C/2000 h, C151 Nichicon UUD 105 °C/5000 h ✅. +- **Consequence:** bulk capacitance and ESR drift within the first year, affecting U25 transient response. +- **Fix:** **C78 → Lelon OVZ221M1CTR-0608 220 µF 16 V polymer, LCSC C881921** (same 6.3 × 7.7 can, 105 °C/2000 h, stock 2442). Effect on the U25 loop is benign: fc ≈ 4.4 kHz with 276 µF against the 1.8 kHz compensation zero → PM ≈ 68° (verify_1). +- **Effort:** schematic-only. + +##### Minor (A) +- **A-10 · Minor · No over-voltage protection on VEH5V** (not independently verified). U6.16 OVSNS tied straight to `/VEH5V` (OVP unused). A TPS54360B high-side short puts `/VIN_PROT` (24–36 V) on VEH5V (LTC4040 VIN abs max 6 V steady / 7 V transient) and through Q7 onto MAIN5V → SYS5V. V5 used the isolated SD-15B, so v6 adds this failure mode. *Fix (pick one):* (a) LTC4040 OVP arrangement per the datasheet application (OVSNS via 6.2 kΩ + series N-FET ≥ 40 V; verify the topology against the datasheet figure before committing), or (b) a 1.5 kW 5 V TVS (SMCJ5.0A class) as a crowbar to open F2 (imperfect). No LCSC selected in the findings. *Effort:* both. +- **A-11 · Minor · CHGOFF (PA8) has a pull-down: charger runs at full current whenever the MCU is not driving the pin** (not independently verified). R56 100 k `/CHRG_EN` → GND; during reset, DFU, boot loops and unflashed boards the charger is enabled with no governor (2.42 A as-is). *Fix:* R56 100 k (C25803) re-netted to `/3V3` → default charge OFF; polarity unchanged. *Effort:* schematic + one track. +- **A-13 · Minor · PFO goes only to TP2: no hardware power-fail interrupt** — *absorbs D-10* (not independently verified; pin allocation per verify_1 (h)). `/PFO_TP` = {U6.20, TP2}; firmware detects backup by polling 5V_SENSE (V5_OFF 3.80 V) although the LTC4040 has switched at PFI 4.40 V; tens of ms late to shed loads. `/CLPROG_TP` = {U6.3, TP1} (V = 32·(VIN − CLN), 0.32 V/A with RS1 10 mΩ). *Fix:* PFO → **PB10** (pad 29, EXTI10) with **100 k C25803 pull-up to /3V3**. D-10's CLPROG → PC5 is dropped because PC5 goes to F-51; CLPROG stays on TP1. *Effort:* both (two tracks). +- **A-14 · Minor · BSTFB divider 21–24 mm from U6; IGATE 43 mm unguarded** — *absorbs F-10* (not independently verified; the In1-cut part is in A-02). R53.2 → U6.18 21.4 mm, R54.1 24.0 mm; `/VFB_BST` F.Cu 16.8 mm + In1 24.4 mm, 5 vias, 41.2 mm total (83 kΩ Thevenin node); `/IGATE` F.Cu 6.0 + In1 37.0 mm, Q7.4 ↔ U6.15 23.2 mm. Switch-node overlap (F-10): `/SW_PWRIN` over In1 `/MAIN5V` 2.41 mm², `/SW_5V` 2.91 mm², `/VFB_BST` 1.14 mm² (≈ 0.095 pF → ≈ 0.23 mA spikes at 24 V/10 ns); `/SW_BAT` over In1 `/SW_5V` 1.39 mm². *Consequence:* backup set-point noise (the mode R1/R3 rely on); µA-class IGATE drive exposed to humid-box leakage (Q7 body diode ≈ 1.2 W at 2.5 A if partially off). *Fix:* R53/R54 ≤ 3 mm from pins 18/10, top leg Kelvin-tapped at the CSYS pads, net on F.Cu; Q7 ≤ 5 mm from U6.15, IGATE ≤ 8 mm on F.Cu flanked by MAIN5V copper; In1 solid under all switch nodes (F-05). *Effort:* layout. +- *(D-09, absorbing A-12, is in §4-D; F-51/F-52 are in §4-F; F-01/F-02 (24 V clearance) are in §4-F.)* + +##### Notes (A) — not independently verified unless stated +| ID | Observation | Action | +|---|---|---| +| A-16 | U25 EN/UVLO divider R124 523 k / R125 84.5 k DNP → internal UVLO 4.1–4.3 V; between ≈ 4.3 V and 5.8 V input VEH5V is in dropout inside the PFI band (12 V vehicles under crank only). | Optional: populate R124/R125 (start ≈ 8.0 V, stop ≈ 5.5 V) if 12 V machines are in scope; LCSC to be picked in sourcing. | +| A-18 | U25 compensation = TPS54360B datasheet example (13 k / 6.8 nF / 39 pF) for 8.2 µH + 58 µF; v6 has 10 µH + ≈ 56 µF ceramic + bulk; fco ≈ 4–6 kHz, PM > 60° (estimate); ≈ 0.16 V dip for a 1.8 A step. | None required; optional R123 → 24 k after A-01/A-09; bench 0.3 → 2.5 A step. | +| A-19 | SMCJ33A/SMBJ33A survive 36 V/60 min and ISO 7637-2 fast pulses but not an ISO 16750-2 Test B suppressed load dump (58 V, 100–350 ms, ≈ 10 A); the TVS would fail short and F2 then opens (after A-01). | Confirm alternator load-dump suppression in the fleet (§10). Keep SMCJ33A; do not raise the TVS voltage (U25 65 V abs max). | +| A-20 | (a) U12 MP1584EN (C15051, −20…+85 °C): gate EN (E-01); optional swap to AP64350 C2071691 (re-layout). (b) F1 3 A PPTC now protects only the F9P LDO branch: harmless, not protective; keep. (c) P2 bench jack has no reverse protection (VEH5V −0.3 V abs max): state on silkscreen. (d) JP_CUT → G-04. (e) C22 value text 22 µF vs 10 µF part → H-08. (f) K1 G5V-1 rated −40…+70 °C. (g) R112 1 k VBAT_MODEM bleeder 3.8 mA / 14 mW: fine. | As listed. | + +*F-53 (fan block) is absorbed into A-01 and not counted as a Note:* U2 5V_FAN 4.99 V (4.76–5.23 V); FB divider R20/R21 0.67/1.48 mm from U2.4 (ECO E3 fixed); PA6 → Rg1 100 Ω → Q2 with Rgs1 100 k (default OFF), D2 flyback; 2-wire fan, no tach. A-01 moves the fan to VEH5V; firmware adds the NTC to `thermalCtlTemp()`. + +#### (b) Pass/fail — §4-A +| Check | Evidence (one line) | Result | +|---|---|---| +| U25 output formula / tolerance | 0.8·(1 + 53.6/10.2) = 5.004 V; Vref 0.792–0.808 → 4.87–5.14 V | ❌ set-point (A-04) | +| U25 RT / fsw / min on-time | 162 k → 600 kHz; tON at 36 V = 244 ns ≥ 135 ns | ✅ | +| U25 inductor L22 | 10 µH ≥ Lmin 7.2 µH (36 V); SRP1265A Isat 15.5 A vs peak 3.1–3.4 A | ✅ | +| U25 current capability | ≤ RS1 limit 2.14–2.41 A (+0.3 A fan with A-01) vs 3.5 A rating, 4.5 A min switch limit | ✅ | +| U25 Cout / ripple | 2 × 47 µF X7R 1210 (≈ 56 µF eff) + 220 µF; ΔI 0.69 A, ΔV ≈ 3 mV | ✅ value / ❌ C78 life (A-09) | +| U25 compensation | datasheet example; fco ≈ 4–6 kHz, PM > 60° (estimate) | ✅ (A-18 Note) | +| U25 BOOT cap C152 | 100 nF, 1.49 mm edge | ✅ | +| U25 Cin value | 2 × 2.2 µF/100 V X7R ≈ 3.4–3.8 µF eff ≥ TI 3 µF | ✅ value / ❌ loop (F-03) | +| U25 soft start / inrush | 1024 cycles / 600 kHz = 1.7 ms; ≈ 0.9 A into ≈ 280 µF | ✅ | +| U25 EN / UVLO | EN floats → on; internal UVLO 4.1–4.3 V | ✅ (A-16 Note) | +| Vehicle-voltage exposure of other parts | U2 30 V abs max, D21 30 V, U20 42 V on unfused `/24V` | ❌ A-01 | +| Reverse polarity | Q23/Q10 IRFR5305 −55 V/65 mΩ, gate clamps D33/DzG1 ✅; but D10 ahead of F2 conducts on reversal | ❌ V1-01 | +| DzG1 netlisted (V5 corruption) | DzG1.1 `/Q10_GATE`, .3 `/24V` | ✅ | +| TVS standoff / polarity | SMCJ33A/SMBJ33A VRWM 33 V ≥ 32 V; pad 1 = K on + rail | ✅ (A-19 Note) | +| F2 part / coverage | C206910 2 A assigned ✅; protects the U25 branch only | ❌ A-01 | +| 24 V-to-LV inner clearance < 0.5 mm | 6 inner spots, all `/IGN_IN` (worst 0.221 mm to `/VEH5V` on In2); `/24V` In1 at 0.15 mm to GND fill | ❌ F-01, F-02 | +| RS1 input limit | 10 mΩ 1 W (C105362): 2.35–2.65 A (2.14–2.41 A with the CLN tap) < U25 3.5 A | ✅ | +| R50 charge current | 825 Ω → 2.42 A (2.57 A max > 2.5 A IC max) | ❌ A-03 | +| LTC4040 PROG node | R50 1.26 mm from pin 2; `/PROG` 2.6 mm | ✅ | +| BSTFB (backup VSYS) | 499 k/100 k → 4.60/4.79/4.99 V within 3.5–5.0 V; keep 499 k | ✅ value / ⚠ placement (A-14) | +| PFI divider | 270 k/100 k: fall 4.27/4.40/4.54, rise 4.38/4.51/4.66 V | ✅ (FW `V5_PFI` stale) | +| RSTFB / RST | RSTFB tied to BSTFB (allowed), RST NC | ✅ | +| OVSNS | tied to VIN → OVP unused | ⚠ A-10 | +| NTC window RNTB | R55 10 k: hot pause 42.4 °C, resume 40.1 °C, cold −3.1 °C (B3380) | ⚠ chemistry D1 pending | +| Chemistry straps | JP2 1-2 (Li-ion), JP3 F1 = 0, JP4 F0 = 1 → 4.00 V | ✅ | +| Safety timer | Li-ion 4.25 h, counts in CV only | ✅ | +| CHRG / FAULT to MCU | R57/R58 100 k to 3V3 → PB3/PB4 | ✅ | +| CHGOFF default | R56 100 k pull-down → charger ON without MCU | ⚠ A-11 | +| BSTOFF | tied to GND → boost always armed | ✅ / Note | +| Q7 ideal-diode orientation | AO4406A S = VIN_SW, D = MAIN5V | ✅ | +| L6 value / rating | 2.2 µH, 8 A ≥ ILIMBST max 7.5 A | ✅ value / ❌ placement (A-02) | +| SW_BAT / BAT_PLUS copper, U6 EP vias | 0.5 mm + 0.25/0.30 mm necks; 1.0 mm; 0 EP vias | ❌ A-02 | +| CSYS | 104 µF nominal, ≈ 57–69 µF effective (< 75 µF) | ⚠ A-05 | +| CBAT C35 | 22 µF ≥ 10 µF; 20.2 mm from L6.2 | ✅ value / ⚠ placement (A-02) | +| 5 V path widths | `/VEH5V` In1 0.5 mm, `/VIN_SW` In2 0.8 mm at 2.5 A | ❌ A-07 | +| U20 FB | 75 k/20 k → 3.70/3.80/3.90 V within A7670 3.4–4.2 V | ✅ | +| U20 RT / min on-time | 200 k → 500 kHz; tON at 36 V = 211 ns ≥ 100 ns | ✅ | +| U20 UVLO on battery | falling ≈ 3.1–3.3 V vs VIN_MODEM ≥ 4.2 V (≈ 1 V margin; V5.5 had 0.1 V) | ✅ | +| U20 EN default | EN pull-up 1.5 µA (verify_1; not 5.5 µA) × R113 100 k = 0.15 V < 1.03 V → OFF | ✅ | +| U20 BST | C129 100 nF, 1.8 mm | ✅ | +| L20 | 4.7 µH (MWSA0804S-4R7), 5 A vs peak 2.2–2.7 A | ✅ (land: H-03) | +| U2 FB / placement | 4.99 V; divider at pin | ✅ (rating ❌ A-01; Cin moot with A-01) | +| U12 FB | 100 k/31.6 k → 3.18/3.33/3.48 V | ✅ (EN ❌ E-01, loop ❌ F-03) | +| U21 AP2112K dropout | 250 mV at 600 mA; F9P ≈ 0.1 A; SW_5V ≥ 4.5 V on battery | ✅ (ramp ❌ C-02) | +| U17 AMS1117 | LDO_IN ≈ 4.6 V on 24 V ✅; 4.27–4.67 V on battery | ❌ A-08 | +| Worst-case battery budget | 2.25–2.33 A on MAIN5V at a GSM burst (91–97 % of guaranteed 2.5 A) | ⚠ A-05 | +| DFU-only power | DFU_VBUS → D13 → LDO_IN; D12 blocks back-feed into SYS5V | ✅ | +| K1 flyback | D6 1N4148W across the coil | ✅ | +| Fan PWM default | Rgs1 100 k → Q2 OFF at reset | ✅ | +| Q5 base (F9P rail) default | no base pull-down; floats in reset | ⚠ D-09 | + +--- +### 4-B Modem A7670SA (U19), lessons F1 / F2 / F3, ECO A / B + +Cross-references: U20 input topology → **A-01** (absorbs B-01); U20 hot loop and Cin → **F-03** (absorbs B-06); modem ground vias → **F-12** (absorbs B-04); LTE feed on In1 → **F-06** (absorbs B-05); J9 ESD → **G-02** (absorbs B-07's ESD part); NC flags on PC6/PC7 → **J-04** (absorbs B-11); stackup and netclasses → **F-06 / F-01** (absorb B-12). + +#### (a) Findings + +##### B-03 · Blocker · LTE antenna ESD D28 is a unidirectional 5 V TVS on an RF line with no DC bias +*Status:* verified-with-correction (verify_1: the proposed PGB1010402KR is rated 12 VDC max operating, below the 14.1 V GSM peak; use PESD0402-240). + +- **Evidence:** D28 = C82326 onsemi ESD9L5.0ST5G, "Unidirectional, 0.9 pF, VRWM 5 V, VBR 5.4 V, VC 9.8 V", SOD-923; pin 1 (C) on `/RF_ANT_LTE`, pin 2 (A) on GND; in-line 1.8 mm from J13.1. A7670SA output (HD V1.03 Table 30; GSM supported per Table 1): GSM850/900 33 dBm ±2, DCS/PCS 30 dBm, LTE 23 dBm ±2.7. Peak voltage at 50 Ω, V = √(2·P·50): 23 dBm → **4.47 V**, 33 dBm → **14.1 V**; at VSWR 3:1 (×1.5) 6.7 / 21.2 V. SIMCom Fig. 33: "D1 is a Bidirectional ESD Protection device". +- **Consequence:** the diode forward-conducts at ≈ −0.6 V on every negative half-cycle, even in LTE, and avalanches at 5.4 V on GSM positive peaks: hard clipping, spurious emissions (homologation), lost TX power, PA stress, D28 heating and likely failure (possibly shorting the antenna port). +- **Fix:** **D28 → Littelfuse PESD0402-240, LCSC C1975527** (bidirectional, 24 V working, 0.25 pF → −j335 Ω shunt at 1.9 GHz, |Γ| ≈ 0.07; stock 9394), or DNP D28 (SIMCom marks it optional). Either way needs an **0402 land** in place of the SOD-923 (comes with the F-06 reroute). Keep D27 on the GNSS line (+3.2 V bias, no TX; a unidirectional 5 V part is correct there). +- **Effort:** both. + +##### B-02 · Major · VBAT_MODEM bulk is a general-purpose electrolytic; U20 compensation is the 5 V table row +*Absorbs:* A-09 (C130/C131), A-17. *Status:* verified, severity changed Blocker → Major (verify_1: works on day 1, fails cold or aged; BOM-only fix on the same land). + +- **Evidence:** C130, C131 = C2827940 SamYoung MVG 16 V 220 µF 6.3 × 7.7 (value field reads "220uF/10V"), −40…+85 °C, 2000 h @ 85 °C, 130 mA ripple: not polymer. Placement: C131 8.70 mm, C130 16.26 mm from U19.55–57; nearest cap to L20.2 is C130 at 10.1 mm. Low-ESR output capacitance is only C132 22 µF + C133 1 µF + C134 100 nF ≈ 14 µF effective (SIMCom asks ≥ 300 µF, HD V1.03 p.27). Compensation R116 14 k / C141 3.3 nF / C142 47 pF = the AP64350 **Table 1 VOUT = 5.0 V** row (designed for 2 × 22 µF ceramic). FB R110 75 k / R111 20 k → 3.80 V (3.67–3.94 V worst case) ✅. Life ≈ 8 000 h at 65 °C. + + | Condition (verify_1 averaged current-mode model) | 2 A GSM burst droop | 0.7 A LTE | + |---|---|---| + | Battery via D21 (4.42 V), MVG new (ESR 0.2 Ω pair) | **0.28 V** (VBAT 3.52 V) | 0.08 V | + | Same, cold / aged (0.6 Ω pair) | **0.52 V** (3.29 V < 3.4 V min) | 0.13 V | + | Battery, polymer + 113 k / 6.8 nF / 56 pF | 0.06 V | 0.02 V | + | Battery, polymer with the as-is 14 k | 0.18 V (PM ≈ 27°) | 0.06 V | + +- **Consequence:** within SIMCom's 300 mV limit on day 1 with LTE-only on battery; with cold or aged caps GSM bursts pull VBAT below 3.4 V → "modem dark" likely within about a year. Reliability failure → Major. +- **Fix (change caps and compensation together):** **C130, C131 → C881921** (Lelon OVZ 220 µF/16 V polymer, 105 °C/2000 h, 6.3 × 7.7, stock 2442); **R116 14 k → 113 k 1 % (C22862, stock 59 728)**; **C141 3.3 nF → 6.8 nF X7R 0402 (C1542)**; **C142 47 pF → 56 pF C0G 0402 (C1572)** (C141/C142 are 0402 today); **add 2 × 22 µF 0805 (C86817, stock 4144) at L20.2** ≤ 3 mm. Checks: R5 = 4.67e3·14 kHz·3.8 V·454 µF = 112.8 k; C5 = 3.8·454 µ/(2 A·113 k) = 7.6 nF; zero 207 Hz, fc 14 kHz, C6 pole 25 kHz → **PM ≈ 60°**. 113 k is valid only with the polymer bank (with MVG the ESR zero ≈ 1.8 kHz sits below fc). A-17's alternative (R116 = 10 k with polymer) gives PM ≈ 15° and is rejected (verify_1 conflict (c)). Move C131 ≤ 5 mm from U19.55–57 (B-08). Bench: 0.1 → 2 A step on VBAT_MODEM, droop ≤ 150 mV, no ringing. +- **Effort:** both (BOM values + 2 caps + C131 move). + +##### Minor (B) — not independently verified +- **B-08 · Minor · VBAT_MODEM feed: 0.5 mm neck into pins 55–57; 1 mm over 7 mm; no pour.** F.Cu 48.9 mm (0.25/0.5/1/1.5/2 mm) + In1 6.3 mm, 2 vias; final feed 0.5 mm × 2.5 mm into U19.55 then 0.5 mm × 2.0 mm to 56/57. L20.2 → U19.55 12.5 mΩ, drop at 2 A 25–29 mV (static, fine). verify_2 J-02: 12.5 mm under capacity. *Consequence:* violates SIMCom's VBAT width rule (≥ 3 mm V1.03), adds loop inductance between bulk and pins. *Fix:* F.Cu pour ≥ 3 mm from L20.2 → C130 → C131 → C132–C136 → U19.55/56/57, fanned to all three pads; C131 ≤ 5 mm from the pads. *Effort:* layout. +- **B-09 · Minor · SIM interface: 0 Ω instead of 22 Ω; ESD 22–25 mm from J14; VDD cap 13.5 mm away.** J14 (C2977286) + R131–R134 0 Ω populated, U22 + R127–R130 DNP ✅. D23/D24/D25 PESD5V0S1BA (C2827694) sit 1.3–5.7 mm from U19 but 21.7–24.8 mm from J14; C126 100 nF 13.5 mm from J14.C1; `/SIM_VDD` unclamped. *Fix:* **R132/R133/R134 → 22 Ω 0603 (C23345, Basic)**; add **100 nF 0402 (C1525) at J14.C1**; move D23–D25 next to J14 (an ESDA6V1W5-class array covering VDD is an option; no LCSC selected). Keep F.Cu clear under U22's die-pad zone if MFF2 is ever fitted. *Effort:* both. +- **B-10 · Minor · Undefined idle levels on the modem interface; RTCM-tap resistor too small** — *absorbs D-14.* U24 (VCCA = `/1V8_MODEM`) is Hi-Z whenever the modem is off, so `/MODEM_STATUS` (PC9) and `/DOUT_4G` float; `/DIN_4G` floats during the K1 transfer and with the F9P off. R106 = 100 Ω between U24 1B and PC7: a mis-configured PC7 output would see ≈ 33 mA (> 25 mA pin limit). *Fix:* **100 k (C25803) `/MODEM_STATUS` → GND**; **100 k (C25803) `/DIN_4G` → /3V3**; **R106 100 Ω → 1 kΩ (C14676)** (ECO §B value; 1 k × ≈ 5 pF = 5 ns, fine to 921 600 Bd). *Effort:* schematic-only (+ 2 small footprints). + +##### Notes (B) — not independently verified +| ID | Observation | Action | +|---|---|---| +| **B-16** | **Cold start on battery (brief §4-B explicit statement).** With VSYS 4.79 V: PMEG3050EP as-is, GSM 2 A → VIN(U20) 4.44 V, MAIN5V 2.28 A (OK, 9 % margin to 2.5 A); 2.8 A peak (HD V1.00) → 3.08 A, **over** the backup limit; D21 replaced by a link (A-01) → 4.70 V, 2.17 A (13 % margin); LTE 1.0 A with link → 1.27 A. U20 UVLO (3.5–3.7 V rising) is never approached (VIN ≥ 4.2 V). **Yes, v6 can bring the modem up from the LTC4040 boost alone**, provided (1) the modem is enabled only after the F9P rail has settled, (2) the modem is LTE-only on battery, (3) the W5500 is off (E-01), and (4) the VBAT bank is fixed (B-02). Otherwise LTE-burst droop, not UVLO, is the failure mode. R2 hardware path: EN low stops U20; VBAT decays through R112 1 kΩ, τ 0.46 s → 47 mV after the 2 s HARD_CYCLE. | Firmware sequencing (§8). Bench-check VBAT at MAIN5V = 4.6 V with a 2 A load (AP64350 max duty not stated in DS41976). | +| B-13 | K1 fail-safe premise is obsolete: the A7670SA has no NTRIP client, and an MCU reset also switches the modem off (R113) and releases K1. Coil 5 V × 30 mA = 150 mW while Mode B is held. | No hardware change for v6; firmware energises K1 only while the modem is on; consider a direct PC6 → DIN_4G link in v6.1. | +| B-14 | Everything the modem prints (AT replies, URCs, socket headers) reaches F9P UART2 RXD. No contention (single driver U24). | Firmware: F9P UART2 in-protocol RTCM3 only at 115 200; caster socket transparent (`AT+CIPMODE=1`) or MCU re-assembly → USART2 → F9P UART1. | +| B-15 | R107/R108 "bypass the shifter" DNP 0 Ω footprints cannot work: fitted without the shifter they put 1.8 V on F9P RXD2 (VIH 2.64 V) and 3.3 V on modem RXD (abs max 2.0 V). | Delete them or add a "never fit" note. | + +#### (b) Pass/fail — §4-B +| Check | Evidence (one line) | Result | +|---|---|---| +| A7670SA footprint / pin numbering | LGA-124 matches HD V1.03 (VBAT 55–57, RF_ANT 60, STATUS 66, VDD_1V8 15, UART 9/10, USIM 30–34) | ✅ | +| U20 source | `/VIN_MODEM` from unfused `/24V` via D20 and from MAIN5V via D21 (30 V) | ❌ A-01 | +| U20 EN default OFF | EN pull-up 1.5 µA × R113 100 k = 0.15 V < 1.03 V | ✅ | +| U20 output set-point | 75 k/20 k → 3.80 V; worst 3.67–3.94 V within 3.4–4.2 V | ✅ | +| U20 frequency / min on-time | R117 200 k → 500 kHz; tON at 40 V = 190 ns > 100 ns | ✅ | +| U20 compensation vs datasheet for 3.8 V | 5 V Table 1 row applied at 3.8 V; PM ≈ 27° with polymer and 14 k | ❌ B-02 | +| U20 input caps | C127 10 µF 50 V + C128 1 µF; ≈ 65 mV p-p ripple at 2 A; GND 6.86/8.48 mm, 0.25 mm neck | ❌ F-03 | +| L20 saturation | 4.7 µH MWSA0804S, ≥ 8.7 A family Isat vs 2.7 A peak | ✅ (land: H-03) | +| L20 / C129 / COMP / RT placement | L20 2.24 mm, BST 1.8 mm, COMP 0.72 mm, RT 1.44 mm | ✅ | +| SW_MODEM copper | 1.0 mm × 6.6 mm, 2.2 mΩ (was 0.25 mm × 23 mm on 25-Sep) | ✅ | +| Bulk ≥ 220 µF polymer within 10–20 mm | 2 × 220 µF MVG electrolytic at 8.70 / 16.26 mm | ❌ B-02 (type) | +| VBAT track width ≥ 0.25 mm / vendor ≥ 3 mm | 0.5 mm neck into pins 55–57, 1 mm over 7 mm | ⚠ B-08 | +| VBAT HF ceramics | C133–C136 1.7–2.7 mm, C132 4.1 mm from VBAT pads | ✅ | +| D22 polarity | SMAJ5.0A pad 1 = cathode on `/VBAT_MODEM` | ✅ | +| VBAT bleed for HARD_CYCLE | τ = 0.46 s → 47 mV after 2 s EN low | ✅ | +| PWRKEY / RESET drive | 2N7002 open-drain, 100 k gate pull-downs, no caps | ✅ | +| Level shifting to 1.8 V | U23 DIR = GND (3.3 → 1.8 V into modem RXD); U24 DIR = VCCA (TXD + STATUS up); unused 2B tied | ✅ | +| Back-powering of the modem | 74LVC2T45 Ioff with VCCA = 0; PWRKEY/RESET open-drain; only 1.8 V on `_M` nets | ✅ | +| STATUS readback | U24 2A→2B, VOH ≈ 3.3 V vs PC9 VIH 2.31 V; floats when modem off | ✅ / ⚠ B-10 | +| UART contention | `/DOUT_4G` single driver (U24); `/DIN_4G` via break-before-make K1 | ✅ | +| RTCM visibility (R106 tap) | GGA field 13 on USART2 (PA3) + raw RTCM3 on USART6 RX (PC7); R106 100 Ω too small | ✅ / ⚠ B-10 | +| USART allocation | USART6 PC6/PC7 AF8, USART2 PA2/PA3, USART1 RX PA10; PA9 free | ✅ | +| USB_BOOT | TP8 floating (not pulled low at power-up) | ✅ | +| SIM population / eSIM | J14 + R131–R134 fitted; U22 MFF2 + R127–R130 DNP; USIM1_DET NC | ✅ (details B-09) | +| LTE π-pad | R118 0 Ω + C146/C147 DNP at J13 | ✅ | +| LTE antenna ESD | unidirectional ESD9L5.0 on a 14.1 V-peak TX line | ❌ B-03 | +| LTE feed geometry | 22.14 mm on In1, 2 via transitions, 32–47 Ω, 1 fence via | ❌ F-06 | +| Modem ground vias | 1 GND via under U19; U20 EP 0 vias; J13 20–21 mm to a via | ❌ F-12 | +| J9 modem USB ESD | none | ❌ G-02 | +| Cold start on battery (R1) | possible with sequencing, LTE-only, W5500 off and B-02 (B-16) | ⚠ needs fixes + firmware | + +--- +### 4-C GNSS ZED-F9P (U18) + +Cross-references: F9P back-power through U24 → **D-01** (§4-D, absorbs C-06); F9P ground vias → **F-12** (absorbs C-03); GNSS RF line and bias-line coupling → **F-06** (absorbs C-05). + +#### (a) Findings + +##### C-01 · Blocker · GNSS antenna bias has no current limit and no supervisor; ANT_DETECT / ANT_SHORT_N are undriven +*Absorbs:* D-07. *Status:* verified (verify_1). + +- **Evidence:** `/VCC_RF_GNSS` = {U18.7, L21, C144, C145}; L21 = C162555 LQG18HN68NJ00D, 68 nH, 0.8 Ω, **400 mA**, SRF 1 GHz (u-blox recommends 120 nH). ZED-F9P-04B DS R05: pin 4 ANT_DETECT = **input** (active high), pin 5 ANT_OFF = output, pin 6 ANT_SHORT_N = **input** (active low); VCC_RF 50 mA operating, **300 mA abs max**. On v6 pins 4/6 connect only to PC1/PC2 (MCU inputs), so nothing drives them; U18.5 ANT_OFF is NC. u-blox IM UBX-18010802 R02 §8.6: "a 10 Ω current limiting resistor is **required** to prevent against short circuits destroying the BIAS-T inductor." +- **Consequence:** a crushed or wet coax (the H0005/H0014 field fault class) lets U21 (AP2112, current limit ≈ 0.6–0.8 A) push more than VCC_RF's 300 mA abs max and L21's 400 mA, collapses 3V3_GNSS into an F9P brown-out loop, and the PC1/PC2 "antenna telemetry" never reports it. Hardware-damage path. +- **Fix:** add **TPS2552DBVR, LCSC C46506** (SOT-23-6, stock 3002). Pinout 1 IN / 2 GND / 3 EN̅ / 4 FAULT̅ / 5 ILIM / 6 OUT. IN = `/3V3_GNSS`; OUT → new net `/ANT_BIAS` = L21.2 + C144 + C145; **ILIM tied to IN → 75 mA typ** (VIN 2.5–6.5 V; constant current into a short, ≈ 0.25 W at 3.3 V; FAULT̅ deglitch 7.5 ms); **EN̅ ← U18.5 ANT_OFF with 100 k (C25803) to GND** (antenna ON by default; ANT_OFF high → antenna off, matching the F9P's active-high ANT_OFF); **FAULT̅ → `/GNSS_ANT_SHORT_N`** (U18.6 + PC2) with **10 k (C25804) to /3V3_GNSS**; leave U18.7 VCC_RF NC. ANT_DETECT stays unimplemented (infer open antenna from C/N0). U21 load becomes 130 mA + 75 mA. The 10 Ω series fallback gives 3.2 V/10.8 Ω ≈ 0.30 A, right at VCC_RF's abs max: acceptable only as u-blox's stated minimum, and no LCSC is selected for it in the findings. +- **Effort:** both. + +##### C-02 · Major · U21 AP2112K has no soft-start: the ZED-F9P VCC ramp window (20–8000 µs/V) is met only by an unspecified margin +*Status:* verified, Major at the low end (verify_1). + +- **Evidence:** U21 = AP2112K-3.3 (C51118), EN tied to VIN (`/SW_5V`), starts when Q1 switches `/SW_5V` (no gate RC). AP2112 DS39724: tS = 20 µs at no load, 50 mA foldback short-circuit current, no soft-start. `/3V3_GNSS` ≈ 18 µF (2 × 10 µF X5R + 3 × 100 nF). Ramp: ≈ 400 µs/V at start → ≈ 28 µs/V near regulation, ≈ 80 µs/V average: inside 20–8000 µs/V (ZED-F9P DS Table 15), but the fast-end margin (≈ 1.4×) depends on the AP2112's unspecified current-limit maximum. The F9P is power-cycled every 10-min window (R1: ≈ 52 000 starts/year). +- **Consequence:** occasional failed F9P start (dark receiver until the next cycle) in exactly the duty-cycled mode R1 requires. +- **Fix:** **U21 → TPS7A2033PDBVR, LCSC C2862740** (same DBV pinout 1 IN / 2 GND / 3 EN / 4 NC / 5 OUT; t_STR 750–1150 µs → **239–367 µs/V**; current limit ≥ 360 mA > 20 µF·3.3 V/0.75 ms = 88 mA + load; VIN max 6.0 V vs SW_5V ≤ 5.46 V; COUT 0.47–200 µF; stock 28 370). Bench: scope `/3V3_GNSS` rise (target 100–1000 µs/V). +- **Effort:** schematic-only (drop-in). + +##### C-04 · Major · GNSS supply switch Q1 sits 9 mm from the LTE antenna feed; `/SW_5V` crosses the board on In1 +*Status:* verified (verify_1). + +- **Evidence:** Q1 AO3401A (`/SW_IN` → `/SW_5V`) at (197.28, 59.81) = **9.0 mm from J13**, Q5 7.1 mm (centres); F1 at (171.4, 44.3) in the LTE corner. `/SW_5V` Q1.3 → U21.1: **In1 181.32 mm** + F.Cu 19.7 mm, 2 vias (95 mΩ at 35 µm, 184 mΩ at 17.5 µm inner copper). The In1 section of RF_LTE passes 0.21 mm under `/SW_IN` and `/SYS5V`. +- **Consequence:** the F9P supply starts in the LTE transmitter's near field and travels ≈ 17–20 cm as a slot in the GND plane; LDO PSRR at LTE frequencies ≈ 0 dB, so TX envelope/IMD products ride into the receiver rail (desense, the brief's #1 risk), and In1 is cut end to end (F-05). +- **Fix (layout):** move Q1 + Q5 + R1 + R2 (F1 optional) into the GNSS island next to U21/C3/C40/C119; bring `/SYS5V` (or `/SW_IN`) to it instead; keep `/PWR_CTRL` as the long signal; route the remaining feed on F.Cu or In2 away from the RF lines. Target `/SW_5V` ≤ 15 mm and 0 mm on In1. +- **Effort:** layout. + +##### Minor (C) — not independently verified +- **C-07 · Minor · No test pad on SAFEBOOT_N.** U18.50 SAFEBOOT_N NC; V_USB/USB_DM/USB_DP NC; the only access is UART1 through the MCU bridge (P17 removed). *Consequence:* a failed F9P firmware update over the passthrough cannot be recovered (safeboot needs SAFEBOOT_N low at power-up). *Fix:* 1 mm test pads on U18.50 (SAFEBOOT_N) and U18.49 (RESET_N) next to a GND pad; no resistor. *Effort:* both. + +##### Notes (C) — not independently verified +| ID | Observation | Action | +|---|---|---| +| C-08 | Identity: no `$GPTXT H00xx` source on v6 (the ArduSimple NTRIP Master is gone; A7670SA and F9P emit no unit ID). FW 0.6.0-eth builds `$PHID,<96-bit UID>,,,,` (L718–724) but sends it only on the Ethernet TCP mirror. Lesson F9. | FW 0.7.x sends `$PHID` on the modem uplink at every connect and every 5 min; backend `retranslator` maps UID → H-number before v6 ships. | +| C-09 | V_BCKP (U18.36) on the always-on `/3V3` → hot start after each 10-min off (45 µA) ✅; its decoupler Cu4 (100 nF) is 4.06 mm from pin 36. | Optional: move Cu4 ≤ 2 mm. | + +#### (b) Pass/fail — §4-C +| Check | Evidence (one line) | Result | +|---|---|---| +| VCC ramp window 20–8000 µs/V | AP2112 no soft-start: ≈ 28 µs/V near regulation, margin unspecified | ⚠ C-02 | +| RTK_STAT | U18.20 → PC3 (output → MCU input) | ✅ | +| TIMEPULSE | U18.53 → PA7 (TIM3_CH2 / EXTI7) | ✅ | +| RESET_N | PC12 + R105 10 k to /3V3_GNSS (open-drain drive in firmware) | ✅ | +| SAFEBOOT_N | NC, no pad | ⚠ C-07 | +| V_BCKP | on always-on /3V3, 45 µA; Cu4 at 4.06 mm | ✅ (C-09 Note) | +| Antenna bias current limit / short detect | none; ANT_DETECT/ANT_SHORT_N undriven F9P inputs | ❌ C-01 | +| DC block / bias-T | C143 0.56 mm from J12; L21 68 nH still −j455 Ω at L1 despite 1 GHz SRF | ✅ | +| GNSS ESD D27 | unidirectional 5 V, cathode on line, bias 3.2 V < VRWM | ✅ | +| 50 Ω trace geometry on the real stackup | 0.5 mm / 0.15 mm gap → 38–41 Ω on JLC04161H-7628; `/VCC_RF_GNSS` 0.274 mm alongside over 3.3 mm | ❌ F-06 | +| RF_GNSS over a solid plane | 0 In1 slot crossings | ✅ | +| F9P decoupling | C121/C122 1.7 mm, C120/C124 2.4–2.5 mm, U21 4.4 mm from VCC pins | ✅ | +| UART / I²C / SPI to MCU | UART1 ↔ USART2 PA2/PA3; UART2 RX ← modem, TX → PA10 / K1 NC; D_SEL open = UART | ✅ | +| u-center passthrough via J11 (P17 removed) | only through the MCU USB-CDC bridge to USART2 (firmware must follow CDC line coding) | ✅ (firmware item) | +| F9P back-powering while off | U24 drives 3.3 V into unpowered RXD2 | ❌ D-01 | +| Supply switch distance from LTE feed | Q1 9.0 mm from J13; `/SW_5V` 181 mm on In1 | ❌ C-04 | +| GNSS island vs switchers ≥ 25 mm | nearest SW copper `/ETH_SW` 27.5 mm, L8 35.3 mm | ✅ | +| Island separation | J13 ↔ J12 150.3 mm; U19 ↔ U18 108.9 mm | ✅ | +| F9P ground vias | 0 vias under U18; 946 mm² cluster with 5 vias | ❌ F-12 | +| Identity without `$GPTXT` (lesson F9) | no H00xx source on v6; `$PHID` on Ethernet only | ⚠ C-08 (firmware) | +| MCU UID path for identity | 96-bit UID at 0x1FFF7A10 used by 0.6.0-eth | ✅ | + +--- +### 4-D MCU pin map vs firmware 0.6.0 (U16 STM32F411RET6) + +The full 64-pin table is in §4 of this report (condensed) and in `pinmap-v6.md` (complete, with AF/ADC/EXTI, V5 macro and proposed v6 macro per pin). Cross-references: ETH_RST pull-down → **E-02** (absorbs D-04); raw ignition on In2 → **F-02** (absorbs D-06); antenna pins PC1/PC2 → **C-01** (absorbs D-07); PFO → **A-13** (absorbs D-10); NC flags on connected pins → **J-04** (absorbs D-11); MODEM_STATUS pull → **B-10** (absorbs D-14); Y2 value text → **H-08** (absorbs D-16). + +#### (a) Findings + +##### D-01 · Major · U24 back-powers the unpowered ZED-F9P through RXD2 +*Absorbs:* C-06. *Status:* verified-with-correction (verify_2: use the Nexperia gate C12518, not the clone; the 10 k series-R alternative is not enough). + +- **Evidence:** U24 74LVC2T45: VCC(A) = `/1V8_MODEM`, **VCC(B) = `/3V3` (always on)**, DIR = VCC(A) (A→B). `/DOUT_4G` = {U24.7 (1B), R106.1, R107.2 (DNP), U18.26 RXD2}; `/3V3_GNSS` = U21 output + U18.33/34 only (switched by PA1 → Q5 → Q1). ZED-F9P-04B DS R05 Table 14: input −0.5 … VCC + 0.5 V for VCC ≤ 3.1 V, so at VCC = 0 a 3.3 V push-pull high exceeds it by 2.8 V. The 74LVC2T45's Ioff protects only the modem side (U23), not U24's B output into a dead load. Smaller paths into the same receiver: Rdfu1 22 k → /3V3 on `/USART1_RX` (U18.27) ≈ 0.12 mA; PA10 internal pull-up 7–14 kΩ (≈ 0.5 mA if left enabled); PC7 pull-up via R106 (≈ 70 µA); PA2/PC12 if driven high. Same mechanism as the FW 0.5.5/0.5.6 lesson (idle-high UART held the V5.5 rails up through ESD diodes). +- **Consequence:** whenever the modem is up and PA1 is low, the F9P rail sits pre-biased (≈ 2–2.7 V, auditor estimate): no clean ramp, F9P power-cycle recovery silently fails, RXD2 ESD structure stressed. Firmware can avoid it only by never having the modem on with the F9P off (rules out F9P-only recovery with the modem registered). Major, not Blocker, because that sequencing avoids it (verify_2). +- **Fix:** add **U27 = Nexperia 74LVC1G125GV,125, LCSC C12518** (SOT-753: 1 OE̅, 2 A, 3 GND, 4 Y, 5 VCC; datasheet Rev 17.1 "IOFF … partial power-down", ±2 µA), **VCC = `/3V3_GNSS`**, OE̅ = GND, **100 nF C14663** at VCC; A = `/DOUT_4G`, Y = new net `/DOUT_4G_F9P` → U18.26. PC7/R106 stay on `/DOUT_4G` (moving U24's VCCB to `/3V3_GNSS` would kill MODEM_STATUS and the RTCM tap with the F9P off, R2). Do not use the TECH PUBLIC clone C3040595. **Rdfu1 22 k → 100 k (C25803)** (≤ 27 µA into U18.27). Rejected: 10 k in series at U18.26 (≈ 0.28 mA, the same order as the leakage that held the V5.5 modem rail at ≈ 1 V). Bench: `/3V3_GNSS` < 0.3 V with PA1 low and the modem on. +- **Effort:** both (1 IC + 1 cap + short reroute at U18.26). + +##### Minor (D) +- **D-02 · Minor · HSE crystal 8.3/11.3 mm from the MCU; HC-49S CL 20 pF crystal at the ST start-up gm limit** — *absorbs F-11 (Y3 part).* *Status:* verified (verify_2). Y3 = C14872 (CL 20 pF, **−20…+70 °C**) pad edge → PH0/PH1 **8.32 / 11.30 mm**; C113/C114 15 pF (C1644) → CL_eff 12.5–17.5 pF; gm_crit 1.21–2.37 mA/V at ESR 40 Ω vs Gm_crit_max 1 mA/V (DS10314 Table 37): passes at typical ESR; V5.5 as-fabbed has the same parts at 11.9–13.7 mm and starts in the field. In1 `/USART6_RX` crosses both HSE lines under Y3; `/BAT_PLUS` on all four layers beside it (F-11). ROM DFU and the USB clock depend on HSE. *Fix:* **Y3 → C2901684** (SCTF 3225-4P, 25 MHz, CL 10 pF, ESR 30 Ω, −40…+85 °C, stock 11 076; footprint `Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm`) + **C113/C114 → 12 pF C0G (C38523)** → CL_eff 9.5 pF, gm_crit **0.46 mA/V** (2.2× margin); ≤ 3 mm from PH0/PH1, no inner track under the crystal or its lines. Verifier conflict: verify_2 prefers **C9006** (YXC 3225, CL 12 pF, Basic, 528 k stock) with the existing 15 pF C1644 (≈ 0.77 mA/V at ESR 40 Ω) **after confirming its ESR**; verify_1 (f) left Y3 to the MCU auditor, who chose C2901684. This report picks C2901684 because its ESR is stated in the listing and its margin is larger; C9006 is the Basic-part alternative once its ESR is confirmed. *Effort:* both. +- **D-03 · Minor · LSE crystal load and gm do not suit the F411 low-drive LSE** (not independently verified). Y4 = C32346 FC-135 (CL 12.5 pF, ESR 70 kΩ max); C115/C116 12 pF → CL_eff ≈ 9 pF (+44 ppm ≈ 3.8 s/day); gm_crit 2.16 µA/V at max ESR (≈ 1.1 typ) vs Gm_crit_max 0.56 µA/V low-drive / 1.50 high-drive (DS10314 Table 38); pads 5.54/7.91 mm centre (3.92/6.32 mm pad edge, F-11). *Consequence:* LSE may fail to start in the default low-drive mode; an RTC wake from STOP falls back to LSI (±5–10 %). *Fix:* **Y4 → C48615** (FC-135, CL 7 pF, stock 101 k) + **C115/C116 → 6.8 pF C0G (C1679)** → CL_eff ≈ 6.9 pF, gm_crit 0.76 µA/V max ESR; ≤ 3 mm from PC14/PC15; firmware sets `LSEMOD` (high-drive) before `LSEON`, LSI fallback. *Effort:* both. +- **D-05 · Minor · IGN_SENSE read digitally cannot detect a 12 V ignition; ADC saturates at 28.6 V** (not independently verified). Ratio 2.870 k/(22 k + 2.870 k) = 0.1154: 12 V → 1.385 V (1.30 V with the INPUT_PULLDOWN of `board_v5.h`), 24 V → 2.77 V, 28 V → 3.23 V; VIH 2.31 V → a digital HIGH is guaranteed only above **20.0 V**; ADC full scale at 28.6 V. *Fix:* firmware reads PA5 on the ADC with thresholds (for the as-is ratio: ON > 0.60 V ≈ 5.2 V in, OFF < 0.35 V), no internal pull; hardware **Rigb1 3.3 k → 2.2 k (C4190, Basic)** → ratio 0.0833: 12 V → 1.00 V, 24 V → 2.00 V, 36 V → 3.00 V, linear to 39.6 V; new `$PHLG` field `vign`. *Effort:* firmware (+ schematic value). +- **D-08 · Minor · No hardware board ID: a V5.6 binary on v6 drives PC3 against the F9P's RTK_STAT output** (not independently verified). V5.6 drives PC3 push-pull as MODEM_EN; v6 PC3 = U18.20 RTK_STAT (push-pull output); PC1/PC2 are F9P inputs on v6. *Fix:* **10 k (C25804) strap → GND** on a spare pin; firmware reads it with INPUT_PULLUP at boot (v6 build requires 0, V5.6 build requires 1, else outputs off and `BOARD MISMATCH`). **Open conflict:** D-08 proposed PD2, which verify_1 (h) assigns to E-01 (`ETH_PWR_EN`); the only spare left is PA9, which D-12 wants as a debug TX pad. Leo to choose (§10). *Effort:* schematic + 1 short trace. +- **D-09 · Minor · PWR_CTRL has no default-off pull at Q5's base** — *absorbs A-12* (not independently verified). `/PWR_CTRL` = {U16.15, R1.1}; `/BASE_LS` = {R1.2, Q5.1}; PA1 floats in reset/DFU; worst-case leakage ±1 µA × hFE ≈ 100 → up to 100 µA through R2 10 k → ≈ 1 V gate drive on Q1 AO3401A (VGS(th) −0.5…−1.3 V). V5.5 identical and fielded (typical leakage nA). *Fix:* **100 k (C25803) `/BASE_LS` → GND** next to Q5 (A-12's 47 k had no LCSC; 100 k C25803 is already in the BOM). *Effort:* both. +- **D-12 · Minor · No UART TX pad for a TX-only log / ROM USART bootloader; SWD pads scattered** (not independently verified). PA9 (USART1_TX, pad 42) NC; ROM USART1 bootloader runs on HSI but needs PA9; SWD = TP3 (109.0, 69.7), TP4 (112.5, 76.2), TP5 (110.0, 74.7), GND TP6 17.6 mm from TP3, 3V3 TP7; no SWO (PB3 = CHRG_STAT). *Fix:* **TP9** (`TestPoint_Pad_D1.5mm`, no BOM part) on PA9 next to TP3–TP5; optional DNP 1×5 2.54 mm footprint (3V3, SWDIO, SWCLK, NRST, GND) or a Tag-Connect TC2030-NL land (no BOM cost). *Effort:* layout (+ schematic pad). + +##### Notes (D) — not independently verified +| ID | Observation | Action | +|---|---|---| +| D-13 | EXTI3 shared by PC3 RTK_STAT and PB3 CHRG_STAT; EXTI9 by PB9 ACC_INT1 and PC9 MODEM_STATUS; PA6 fan (TIM3_CH1) and PA7 PPS (TIM3_CH2) share TIM3. | EXTI9 → PB9 (motion wake); poll PC9 and PB3; fan stays GPIO ON/OFF so TIM3 is free for PPS capture. | +| D-15 | Nearest 100 nF per VDD pin (centre): VDD19 3.29 mm, VDD32 3.65, VDD48 2.10, VDD64 3.90 (shared with VBAT pin 1), VDDA 3.13, VCAP1 3.19. | Tighten to ≤ 2 mm in the layout pass if convenient. | + +#### (b) Pass/fail — §4-D +| Check | Evidence (one line) | Result | +|---|---|---| +| U16 symbol vs ST LQFP64 | 64/64 pin numbers and names match ST open-pin-data | ✅ | +| Pin-map coverage | 64/64 rows (`pinmap-v6.md`, §4) | ✅ | +| Firmware pins unconnected on v6 | `PIN_USART1_TX` PA9 NC (Mode-B TX moves to PC6 USART6_TX); TMP102 0x48 and PCF P7 modem-reset absent | ⚠ firmware delta (§8) | +| v6 nets with no firmware counterpart | PA7, PC1–PC4, PC6–PC12, PB9 | ⚠ firmware delta (§8) | +| ADC nets on ADC pads | PA0/IN0, PA4/IN4, PA5/IN5, PB1/IN9, PC4/IN14; spare PC5/IN15 | ✅ | +| AF conflicts | USART2 AF7, USART6 AF8, USART1_RX AF7, SPI2 AF5, I2C1 AF4, OTG AF10, SWD AF0: no overlap | ✅ | +| 5 V on a non-FT pin | none; TC pins carry PA0 ≤ 2.10 V and PB5 (output) | ✅ | +| 1.8 V modem signals reaching the MCU | none (U23/U24, Q20/Q21) | ✅ | +| PWM (fan) timer | PA6 TIM3_CH1 shares TIM3 with PPS capture on PA7; fan is ON/OFF | ✅ (D-13 Note) | +| EXTI allocation | EXTI3 and EXTI9 each shared by two pins | ⚠ D-13 | +| Modem control defaults in reset | R113/R114/R115 100 k pull-downs on PC10/PC8/PC11 | ✅ | +| F9P rail default in reset | Q5 base floats | ⚠ D-09 | +| Charger default in reset | R56 pull-down → charger ON | ⚠ A-11 | +| BOOT0 / BOOT1 DFU trap | R98 10 k PD + SW2; PB2 only R99 10 k PD; ETH_INT on PC0 | ✅ | +| NRST routing (SW1, P6, C104) | C104 100 nF at 3.26 mm; SW1 pad pairs correct; P6 RESET-EXT; TP5 | ✅ (P6 ESD: G-08) | +| SWD access | TP3/TP4/TP5 pads, no header, GND TP 17.6 mm away, no SWO | ⚠ D-12 | +| DFU ESD at J11 | D14/D15/D16 at 3.19/6.74/6.83 mm; CC 5.1 k × 2; VBUS diode-OR D12/D13 | ✅ (stubs: F-14) | +| VCAP1 / VDDA | C111 4.7 µF at 3.19 mm; R104 10 Ω + 1 µF + 100 nF | ✅ | +| CHRG_STAT / FAULT inputs | R57/R58 100 k → /3V3 on PB3/PB4 | ✅ | +| PFO input | `/PFO_TP` goes to TP2 only | ⚠ A-13 | +| IGN_SENSE divider (Rig 22 k) and junction | Rig1.2/Rig2.1/Rigb1.1/C9/D5/U16.21 on one net, sch and PCB (6 pads, 1 group); V5.6 junction loss not present | ✅ | +| IGN clamp orientation | D5 K → /3V3, A → /IGN_SENSE | ✅ | +| IGN digital threshold for 12 V vehicles | HIGH guaranteed only above 20.0 V | ⚠ D-05 | +| I²C address map | 0x18 SC7A20, 0x20 PCF8574, 0x44 SHT40, 0x4D SC16IS752: no clash (TMP102 0x48 would also fit) | ✅ | +| NC flags on connected pins hide an error? | U16.37/38, U10.13/14 nets real in netlist + IPC-356, routed | ✅ (cosmetic: J-04) | +| HSE ≤ 5 mm | 8.32 / 11.30 mm pad edge | ❌ D-02 (Minor) | +| LSE ≤ 5 mm | 3.92 / 6.32 mm pad edge (5.54 / 7.91 mm centre) | ⚠ D-03 | +| F9P back-feed from MCU-side logic | U24 → U18.26 with the F9P off | ❌ D-01 | +| ETH_RST pull-down | none; 100 k would not work | ❌ E-02 | +| Hardware board ID | none; mis-flash drives PC3 against RTK_STAT | ⚠ D-08 | + +--- +### 4-E Ethernet W5500 (U11), lesson F8 + +Cross-references: J10/P11/P12 DNP and footprint parity → **G-03** (absorbs E-05); J9 (modem USB) ESD → **G-02**; U12 hot loop and FB node → **F-03** (absorbs F-09). + +#### (a) Findings + +##### E-01 · Major · 3V3_ETH is not switchable: the W5500 is powered on battery and during MCU reset (lesson F8 repeated) +*Absorbs:* A-05 fix 1. *Status:* verified (verify_1). + +- **Evidence:** U12 (MP1584EN) pin 2 EN = `/SYS5V` = pin 7 VIN → on whenever SYS5V exists (vehicle and battery). W5500 DS v1.0.2: 128 mA (100M link), 75 mA (10M), 13 mA power-down. J10 is DNP on the PCB but U11/U12 are populated, so the draw exists even without a jack. MP1584 EN: internal 1 µA pull-up to ≈ 3 V, rising threshold 1.5 V, abs max 6 V. W5500 VIH max 5.5 V (5 V-tolerant I/O), so MCU-driven SPI/RST lines do not back-power a gated 3V3_ETH. +- **Consequence:** a permanent ≈ 0.05–0.6 W battery load; even the 13 mA power-down current costs ≈ 57 mW from the battery, more than the whole 20–50 mW sleep floor. Hardware gating is required for R1's energy target. +- **Fix:** new net **`/ETH_PWR_EN`: U12.2 (EN) → U16 pad 54 PD2**, with **100 k (C25803) to GND** → EN at 0.1 V (OFF) in reset/DFU/battery; PD2 at 3.3 V turns it on. PD2 allocation per verify_1 conflict (h). +- **Effort:** both (1 resistor, 1 track). + +##### E-02 · Major (Minor once E-01 is in) · `/ETH_RST` has no pull-down; the 100 k proposed in the lessons review could never work +*Absorbs:* D-04. *Status:* verified-with-correction (verify_1: the W5500 RSTn has its own internal pull-up, so 100 k fails even without PA15; D-04's "PD2 + 100 k" also fails). + +- **Evidence:** `/ETH_RST` = {U11.37, U16.50 PA15}. PA15 resets to JTDI with pull-up (RM0383: GPIOA_PUPDR reset 0x6400 0000), R_PU 30–50 kΩ (DS10314). W5500 RSTn internal pull-up **62–112 kΩ** (DS v1.0.2 §5.3); VIL 0.8 V; Schmitt VT− 0.95–1.09 V. 100 k pull-down: 3.3·100/(100 + 30k∥62k = 20.2 k) = **2.75 V** (reads HIGH); with PA15 floating 1.56–2.04 V (undefined or high). **4.7 k:** worst case 3.3·4.7/(4.7 + 20.2) = **0.62 V** (typ 0.49 V) → reliably LOW; drive current 0.70 mA when firmware holds it high. +- **Consequence:** the W5500 leaves reset during every MCU reset/DFU/bootloader and draws up to 128 mA; on battery that is the lesson-F8 drain. A V5.6 built with R112 = 100 k keeps the same bug. +- **Fix:** **add 4.7 kΩ 0603 (C23162, Basic) from `/ETH_RST` to GND at U11.37.** Tell V5.6: R112 100 k → 4.7 k. D-04's move to PD2 with 100 k is rejected (1.56–2.04 V, and PD2 is needed for E-01). Firmware still drives PA15 low as the first line of `setup()`. +- **Effort:** schematic-only (+ 1 small footprint). + +##### Minor (E) +- **E-03 · Minor · W5500 crystal Y1 10.8/13.7 mm from XO/XI; CL mismatch pulls +78…+156 ppm** — *absorbs H-07, F-11 (Y1 part).* *Status:* verified, severity changed Major → Minor (verify_1: V5.5 as-fabbed and V5.6 have the identical Y1 C14872 and C95/C96 18 pF C1647 and Ethernet works; J10 is DNP on the v6 prototypes). Y1 = C14872 HC-49S, **CL 20 pF**, ±20 ppm, −20…+70 °C; W5500 specifies CL 18 pF, ±30 ppm (100BASE-TX ±50 ppm). Pad edge → U11.31 XO 10.79 mm, → U11.30 XI 13.74 mm; `/ETH_XI` 22.98 mm, `/ETH_XO` 22.03 mm; C96 6.4 mm from Y1. CL ≈ (C1+Cp)(C2+Cp)/(C1+C2+2Cp) + Cshunt with Cp ≈ 5.5 pF → **≈ 12.8 pF** → pulling ≈ **+78…+156 ppm**. 63 × 25 MHz = 1575.000 MHz, 420 kHz from GPS L1 (a +100 ppm pull moves it to ≈ 1575.16 MHz, closer to L1 centre; EMC note shared with Y3). *Fix (verify_1 conflict (f)):* preferred **Y1 → C9006** (YXC 3225, 25 MHz, CL 12 pF, ±10 ppm, −40…+85 °C, Basic, stock 528 k) and **keep C95/C96 = 18 pF (C1647)** → CL ≈ 12 pF; place ≤ 3 mm from U11.30/31, caps adjacent, 2 GND vias, no inner track under it (F-11). Alternative keeping the HC-49 part: **C95/C96 → 33 pF C0G (C1663, Basic)** → CL ≈ 19.3–20.3 pF. Verify with a frequency counter (target ±10 ppm). *Effort:* both. +- **E-04 · Minor · W5500 TOCAP and 1V2O capacitor values do not follow the datasheet** (not independently verified). C90 on `/ETH_TOCAP` (U11.20) = 10 µF (DS: 4.7 µF; schematic note "VERIFY value vs ref"); C91 on `/ETH_1V2` (U11.22) = 4.7 µF (DS: **10 nF**, 470× larger); C90 4.4 mm, C91 5.5 mm from their pins; AVDD pins 4/8/11/21 rely on C94 10 µF (7.1 mm) / C102 22 µF (5.8 mm). *Consequence:* internal 1.2 V regulator outside its specified load capacitance (start-up/stability risk). *Fix:* **C91 → 10 nF 0603 X7R (C1589)**; **C90 → 4.7 µF 0805 (C1779**, the part now on C91); both ≤ 2 mm from their pins; add **100 nF (C14663)** at the AVDD 4/8 and 11/21 pairs. *Effort:* both. +- **E-06 · Minor · Ethernet pairs not coupled and split across layers; no line-side ESD; J10 pin 8 NC** (not independently verified). TXP F.Cu 3.9 + In1 11.7 mm (1 via) vs TXN F.Cu 21.5 mm → coupled 0.3 mm; RXP F 5.0 + In1 11.2 vs RXN F 5.8 + In1 14.9 → coupled 1.2 mm; skew 5.9/4.4 mm (≈ 30–40 ps, irrelevant at 100BASE-TX). Terminations, EXRES1 12.4 k 1 % (5.0 mm from pin 10), VBG open, RSVD23 → GND, PMODE high: ✅. *Consequence:* common-mode emission from unbalanced pairs; lower ESD robustness on cabled installs. *Fix:* each pair coupled on F.Cu only (100 Ω diff), ≤ 1 via pair, In1 unbroken; optional low-capacitance array between magjack and U11 (SRV05-4 class; no LCSC selected); tie J10.8 per the HR911105A drawing (function not confirmed). *Effort:* layout. + +##### Notes (E) — not independently verified +| ID | Observation | Action | +|---|---|---| +| E-07 | No PoE PD/controller; J10.7/J10.8 NC; firmware prints "SIN PoE". Consistent with the recorded decision (external splitter). | None for v6; PoE is a v6.1 feature (PD controller + isolated DC-DC). Record the decision in the schematic block note. | + +#### (b) Pass/fail — §4-E +| Check | Evidence (one line) | Result | +|---|---|---| +| SPI2 wiring | PB12 CS (GPIO), PB13 SCK, PB14 MISO, PB15 MOSI (AF5) | ✅ | +| INT | U11.36 → PC0 (EXTI0), BOOT1 trap avoided | ✅ | +| RST pull-down | none on `/ETH_RST`; 100 k would read 2.75 V | ❌ E-02 | +| 3V3_ETH switchable | U12 EN tied to VIN (`/SYS5V`): always on, battery included | ❌ E-01 | +| Straps / analog | PMODE all high (R84); EXRES1 12.4 k 1 % at 5.0 mm; VBG open; RSVD23 GND; 38–42 open | ✅ | +| TOCAP / 1V2O | 10 µF / 4.7 µF vs DS 4.7 µF / 10 nF | ❌ E-04 | +| Termination | TX 49.9 Ω to 3V3_ETH + TCT; RX 49.9 Ω to RCT + 6.8 nF | ✅ | +| Magnetics / HR911105A | J10 C12074 set; PCB DNP vs schematic populated; LED pins still "VERIFY" | ⚠ G-03 | +| Magjack keepout | MAGJACK_NO_POUR rule area on all layers | ✅ | +| Line-side ESD on J10 | none (optional) | ⚠ E-06 | +| ESD on J9 (USBLC6-2SC6) | none | ❌ G-02 | +| No PoE (state it) | none in hardware, documented | ✅ (E-07) | +| 25 MHz crystal ≤ 5 mm | 10.79 / 13.74 mm; CL 20 pF with 18 pF caps | ❌ E-03 (Minor) | +| Pair routing | TX coupled 0.3 mm, RX 1.2 mm, split across layers | ⚠ E-06 | +| U12 buck loop / FB | Cin 6.40 mm from VIN, D11 11.92 mm, FB top 25.9 mm, FB node under SW | ❌ F-03 | + +--- +### 4-F Thermal and EMC (ECO §E, Copper Plan), lessons F5 / F6, 23-Jul short incident + +Cross-references: U6 copper and EP vias → **A-02**; BSTFB/IGATE and switch-node overlap → **A-14** (absorbs F-10); crystals → **E-03** (Y1) and **D-02** (Y3) (absorb F-11); U2 fan buck → **A-01** (absorbs F-08, F-53); J9 ESD → **G-02** (absorbs F-14's J9 part). + +#### (a) Findings + +##### F-02 · Blocker · Raw ignition `/IGN_IN` crosses the board on In2 at 0.221 mm from `/VEH5V`: the 23-Jul inner-layer geometry repeated +*Absorbs:* D-06, F-16. *Status:* verified (verify_2: Blocker; D-06's Major under-rated a repeat of a paid-for lesson with a damage path). + +- **Evidence:** `/IGN_IN` = {P1.3, Rig1.1}; P1.3 at (177.5, 135.0), Rig1.1 at (123.55, 50.675), 100 mm apart. Routing: 4.08 mm F.Cu + **106.47 mm In2**, 0.5 mm wide, 1 via at (127.6, 50.75). With the corrected HV24 rule it is the **only** inner-layer violation set: + + | Layer | Other net | Gap | At | + |---|---|---|---| + | In2 | `/VEH5V` 1.0 mm track | **0.221 mm** | (147.34, 67.49) | + | In2 | GND via | 0.250 mm | (154.4, 83.15) | + | In2 | `/FAN_PWM` track | 0.291 mm | (152.63, 73.49) | + | In2 | `/5V_FAN` via | 0.300 mm | (157.5, 104.5) | + | In1 | `/NTC2` track (IGN via) | 0.305 mm | (127.32, 50.47) | + | In2 | `/VEH5V` via | 0.340 mm | (147.4, 67.4) | + + Plus zone fills at 0.1505 mm on all four layers (re-pour under F-01). 23-Jul incident (`drogheda-einarboard-short-incident`): `/24V_IN` on In2 at 0.202–0.25 mm from MAIN5V/VEH5V and **`VEH5V ↔ IGN_IN` at 0.2 mm on In2**; v6 is within 0.02 mm of that geometry on the same net pair. `/IGN_IN` has no TVS (D10 covers `/24V_IN` only); D5 BAT54 clamps positive only; a negative ISO 7637-2 pulse through 22 k gives ≈ −27 mA into PA5 vs −5 mA I_INJ (DS10314 Table 12). F-16 (absorbed): `/24V_IN` runs 27.11 mm of 1.5 mm track on In1 at exactly **0.500 mm** from `/SW_5V`, cutting a 25 mm In1 slot. + +- **Consequence:** one inner-layer defect puts 9–36 V (and load-dump pulses) onto `/VEH5V` (LTC4040 VIN, 6 V class, and the whole 5 V system) or the fan gate/5 V fan rail. This is the failure that scrapped the 23-Jul board; inner layers can be neither inspected nor reworked. +- **Fix:** move **Rig1 (22 k 0603, C88614) to ≤ 3 mm of copper from P1.3**, with `/IGN_IN` ≤ 3 mm long on F.Cu. The 106 mm run becomes `/IGN_SENSE`, limited to (36 − 5 V)/22 k = 1.4 mA (2.5 mA at 58 V) into any bridged 5 V net; C9 at the MCU keeps τ = (22 k ∥ 2.87 k)·100 nF = 0.25 ms. Keep Rig2/Rigb1/C9/D5 at the MCU. **Add SMBJ33A (C224019**, Littelfuse DO-214AA, stock 9624; VR 33 V, VC 53.3 V at 11.3 A) **from `/IGN_IN` to GND at P1.3**: it also clamps negative ISO 7637 pulses at ≈ −1 V, removing the PA5 injection (D-06's BAT54S C19726 becomes optional). Rig1 at 58 V dissipates 0.13 W for 400 ms: an 0603 thick-film part (75 V working, 2.5× short-time overload) is acceptable with the TVS; 1206 optional. The In1 IGN via next to `/NTC2` disappears with the reroute. F-16: move `/24V_IN` to F.Cu along the south edge, or keep ≥ 1.0 mm from any LV net with nothing crossing it. Conflict ≤ 3 mm (F-02) vs ≤ 5 mm (D-06) resolved to ≤ 3 mm of copper (verify_2). +- **Effort:** both (one resistor moved, one TVS added, one net rerouted). + +##### F-01 · Blocker · Netclasses are broken and one custom rule overrides every clearance: "DRC 0 errors" cannot see any 24 V spacing +*Absorbs:* J-01, F-15, B-12 (netclass part). *Status:* verified-with-correction (verify_2: the proposed `.kicad_dru` misses HV24↔HV24 pairs, which would add 4 false errors; corrected rule set below). + +- **Evidence:** + - `.kicad_pro` HV24 patterns = `/24V_IN`, `24V`, `IGN_IN`, `Q10_GATE`; patterns are anchored matches against the full name, so the three un-prefixed ones match nothing. Netlist `class` attribute: **HV24 = {`/24V_IN`} only**; PWR_HI 6 nets; PWR_MID 6 (incl. `/3V3_ETH`); Default 338, including `/24V`, `/IGN_IN`, `/Q10_GATE`, `/VIN_PROT`, `/VIN_FUSED`, `/VIN_MODEM`, `/Q23_GATE`, `/SW_PWRIN`, `/BOOT_PWRIN`, `/SW_MODEM`, `/BST_MODEM`, `/BST_FAN`, `/VBAT_MODEM`, `/RF_LTE`, `/RF_GNSS`. Dead patterns also include the un-prefixed PWR_* duplicates, `/3V3_MODEM`, `/SW3_NODE`. **RF and PWR_MODEM classes are missing** (lost on GUI saves, `drogheda-v6-resync-protocol` §5). + - Rule "Minimum clearance 1" = 0.15 mm, condition `A.NetClass != 'HV24' && B.NetClass != 'HV24'`, no layer or type clause. Netclass values become implicit rules and custom rules are appended after them; the **last matching rule wins** (KiCad developer statement). So it replaces Default/PWR 0.2 mm, the zones' 0.3 mm and any future RF class. + - Proof in the stored fills: gap to every non-HV24 net **0.1505 mm**, to `/24V_IN` 0.5005 mm, although all 5 zones carry `(connect_pads (clearance 0.3))`; DRC reports 0 clearance items. + - Deleting the rule with Default at 0.2 mm would fail 471 item pairs (209 net pairs) at 0.15–0.20 mm, so the floor must stay 0.15 mm, stated explicitly. + - Spacing basis (IPC-2221B Table 6-1, 51–100 V row, since the rail peaks at the 53.3 V clamp and 58 V suppressed load dump): B1 internal 0.10 mm, B4 external coated 0.13 mm, A6 0.13 mm. The **0.5 mm inner** value is a defect/CAF margin from the 23-Jul loss; **0.3 mm outer** under mask (2.3× IPC) fits the SO-8 pin rows. + - F-15 (absorbed), outer layer with corrected classes: 15 spots < 0.3 mm (38 < 0.5 mm): `/SW_MODEM` U20.8–GND 0.150; `/VIN_MODEM`–GND 0.150 / U20.9 0.200 / U20.2 pad–GND track 0.195; **`/VIN_PROT` 1.5 mm – `/VEH5V` 0.8 mm track 0.162 mm at (176.24, 116.28)** and – untented `/VEH5V` via 0.193; `/SW_MODEM`–GND 0.170; `/Q23_GATE` and `/VIN_PROT` – `/USB_VBUS` 0.225; `/BST_MODEM`–GND 0.225 / 0.275; `/VIN_MODEM` – U20.3/U20.4 0.250; `/SW_PWRIN`–GND 0.270; `/24V` – `/COMP_FAN` 0.290. Full list `work/FHJ/hv24_violations_corrected_rule.csv`. +- **Consequence:** DRC cannot flag a repeat of the 23-Jul geometry. F-02 is exactly that, and it passed DRC with 0 errors. +- **Fix (project settings + rules, then copper):** + - Netclass table (exact names, one pattern per line): + + | Class | Nets | Clearance | Track | Via | + |---|---|---|---|---| + | HV24 | `/24V_IN` `/VIN_FUSED` `/VIN_PROT` `/24V` `/VIN_MODEM` `/IGN_IN` `/Q10_GATE` `/Q23_GATE` `/SW_PWRIN` `/BOOT_PWRIN` `/SW_FAN` `/BST_FAN` `/SW_MODEM` `/BST_MODEM` | **0.3** (class value; layer rules below) | 1.0 | 0.8/0.4 | + | PWR_HI | `/BAT_PLUS` `/SW_BAT` `/MAIN5V` `/VEH5V` `/SYS5V` `/VIN_SW` | 0.15 | 1.5 | 0.8/0.4 | + | PWR_MID | `/SW_5V` `/SW_IN` `/5V_FAN` `/FAN_RET` | 0.15 | 0.6 | 0.8/0.4 | + | PWR_MODEM | `/VBAT_MODEM` | 0.15 | 1.5 | 0.8/0.4 | + | RF | `/RF_GNSS` `/RF_ANT_GNSS` `/RF_LTE` `/RF_ANT_LTE` | CPWG gap (F-06) | CPWG width (F-06) | none | + | Default | everything else (incl. `/3V3_ETH`, `/EN_FAN`, `/EN_PWRIN`) | **0.15** | 0.2 | 0.6/0.3 | + + If A-01 is adopted, remove `/SW_FAN`, `/BST_FAN` (U2 deleted) and `/VIN_MODEM` (merged into MAIN5V) from HV24 (verify_2). Delete the un-prefixed duplicates. + + - `.kicad_dru` (replaces "Minimum clearance 1", "HV24 clearance", "HV24 exception"; order matters, later rules win): + ``` + (rule "Floor 0.15 (non-HV24, non-RF)" + (condition "A.NetClass != 'HV24' && B.NetClass != 'HV24' && A.NetClass != 'RF' && B.NetClass != 'RF'") + (constraint clearance (min 0.15mm))) + (rule "HV24 to HV24" + (condition "A.NetClass == 'HV24' && B.NetClass == 'HV24'") + (constraint clearance (min 0.2mm))) + (rule "HV24 outer" + (layer outer) + (condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'") + (constraint clearance (min 0.3mm))) + (rule "HV24 inner" + (layer inner) + (condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'") + (constraint clearance (min 0.5mm))) + (rule "HV24 IC land patterns" + (layer outer) + (condition "A.Type == 'Pad' && B.Type == 'Pad' && ((A.memberOfFootprint('U2') && B.memberOfFootprint('U2')) || (A.memberOfFootprint('U20') && B.memberOfFootprint('U20')) || (A.memberOfFootprint('U25') && B.memberOfFootprint('U25')))") + (constraint clearance (min 0.15mm))) + ``` + Without the "HV24 to HV24" rule, 4 false errors appear: `/BST_MODEM` C129.1 ↔ `/SW_MODEM` 0.180 mm, `/BST_FAN` Cbst1.1 ↔ `/SW_FAN` 0.285, `/Q23_GATE` D33.1 ↔ `/VIN_PROT` 0.388, `/SW_FAN` ↔ `/VIN_MODEM` 0.400. + + - Then: refill all zones, run DRC (gate). Expected: the 6 inner spots of F-02 and the 15 outer spots of F-15; the F.Cu pour recedes to 0.3/0.5 mm around ≈ 178 HV24 items (re-check `isolated_copper` and the U25/U20 GND islands). Fix the outer spots: `/VIN_PROT` vs `/VEH5V` ≥ 0.5 mm near R124/U25 (24 → 5 V); remove the U20 GND neck (F-03); `/USB_VBUS` away from Q23; `/COMP_FAN` ≥ 1 mm from `/24V` (moot with A-01); tent all vias except test vias. Check with Inspect → Clearance Resolution on one `/24V` ↔ GND-zone pair and one GND-zone ↔ Default pair; re-check that the classes survive every GUI save. +- **Effort:** both (rules now; the copper they flag is F-02 / F-15). + +##### F-12 · Major · Ground vias: 69 on the board (V5.5: 165); 1 under the modem, 0 under the F9P, 0 in every regulator EP; east pour stitched by 5 vias +*Absorbs:* F-13, F-04, B-04, C-03, A-06 (EP/via part). The U6 EP belongs to A-02. *Merge note:* verify_1 made F-12 the umbrella; verify_2 used F-13 as primary of the same family (M-C); both agree on content and severity. *Status:* verified (both verifiers; B-04 re-rated Blocker → Major; F-12's via target corrected to ≥ 400; F-13's board-wide pad setting corrected). + +- **Evidence:** + - GND vias per 20 × 20 mm cell (rows from y 40.32): `[0,5,4,3,0,1,0] [2,3,4,4,4,0,2] [2,1,2,3,0,1,3] [0,2,2,2,0,2,4] [4,5,0,2,2,0,0]` → **10 of 35 cells empty**; 2 GND vias within 3 mm of the 480 mm edge; max distance to a GND via 27.8 mm at (197.7, 42.3) next to J13. + - East F.Cu GND (U19, U20, U25, U2, J13, D34): 3611 mm² pad/track-joined cluster (verify_1) / 3766 mm² pour piece (verify_2), reaching In1/In2 through **5 vias** at (145.7, 129.9), (148.1, 135.3), (152.6, 62.5), (153.5, 77.0), (198.8, 78.1); pour-point-to-via median 10.4 mm, p90 19.8 mm, max 29.5 mm. + - U19 A7670SA: 39 GND pads (20 × 2.1 mm centre pads on a 3.8 mm grid, 1.7 mm gaps), **1 GND via** under the courtyard at (184.6, 81.775), 4 in a 5 mm ring; pads on thermal spokes (18–24 % perimeter contact). U18 ZED-F9P: 56 GND pads (48 × 1.1 mm on a 2.1 mm grid + 8 ring pads), **0 vias** under the body, 946 mm² cluster with 5 vias. J13 GND pads 20.3/21.3 mm from a via; D28 GND 19.1 mm; J12.3 has a GND via 0.73 mm away (verify_1 correction), J12.2 3.7 mm. + - EPs: 0 vias in U6, U25, U20, U2, U12; zones default to thermal relief (gap 0.5 / spoke 0.5 mm); solid overrides only on U6.25, U2.9, U12.9, U11.9, U11.29, JP1–JP5; contact U25 EP 18 %, U20 EP 13 %, D34 anode 18 %. +- **Consequence:** the modem's return currents (23 dBm LTE, 2 A GSM bursts) and the whole east pour reach the planes through 5 vias 30–70 mm apart: the pour behaves as a resonant patch at 1–2.7 GHz (LTE self-desense of the F9P, the brief's #1 risk; ESD returns through the pour); U19 (≈ 1–2 W at max TX) and the regulators lose their heat path (spokes + no vias roughly double θ). Major, not Blocker (both verifiers): no R1–R5 violated outright, no V5.5 field precedent for an on-board modem, no damage path, manufacturable. Zero BOM cost: do it with the Blockers. +- **Fix (layout; §6 L-24 … L-29):** EP arrays of 0.3/0.6 mm vias: U6 9 (A-02); **U25, U20: 2 × 3 = 6 at 1.0 mm, or 2 × 4 = 8 at 0.8 mm with 0.3/0.5 mm vias** (3 × 3 at 1.0 mm does not fit the 2.5 mm EP side); U12 (and U2 if kept) 2 × 3. Pad-level `zone_connect` solid on EPs, all U18/U19 GND pads, D34/Dbk1/D11 anodes and buck Cin/Cout GND pads — **not** a board-wide `thru_hole_only`, which would make 23 × 0402 and 142 × 0603 GND pads solid (tombstoning). U19: one tented via in each 1.7 mm gap between centre GND pads (0.55 mm clearance per side) + perimeter ring, **≥ 30, target 40**, never in pads. U18: vias at the diagonal interstitial centres of the 2.1 mm grid (0.41 mm to pad corners), **≥ 24**, no microvias needed. 2 vias ≤ 1 mm from each U.FL GND pad (J12, J13) and at D28. Every F.Cu GND island ≥ 20 mm² gets ≥ 2 vias; no F.Cu GND pour point > 5 mm from a GND via; edge fence ≤ 5 mm pitch within 1.5 mm of the edge clearance (≈ 96 vias); **board total ≥ 400 GND vias** (≈ 96 edge + ≈ 316 area at 1 per 25 mm² of the 7890 mm² F.Cu GND). Tented, or JLC "epoxy filled & capped" under U18/U19. **Acceptance:** 0 empty 20 mm cells; every GND pad of U19/U18/U20/U25/J12/J13 in an F.Cu cluster with ≥ 1 plane via ≤ 2 mm. +- **Effort:** layout. + +##### F-03 · Major · Switcher hot loops: U25 input caps on a different GND island from its EP/diode (≈ 311 mm² loop); U20 returns through a 0.25 mm neck; U12 Cin 6.4 mm, diode 11.9 mm +*Absorbs:* A-06 (loop part), B-06, F-07, F-09 (U2 = F-08 → A-01). *Merge note:* verify_2 made F-03 primary (M-D); verify_1 kept A-06 and used B-06 as primary for U20. One item here, because both merges share F-07 and A-06. *Status:* verified (verify_1 and verify_2; F-09 corrected: Cin is 6.40 mm from VIN pin 7, not 1.77 mm, which was measured to EN). + +- **Evidence:** + - **U25 TPS54360B (non-synchronous, 24–36 V):** C150.1 → U25.2 2.88 mm ✅, C149.1 6.36 mm, C151.1 6.42 mm; C149/C150/C151 GND on the ≈ 252–270 mm² U6 island (nearest via 9.4–11.4 mm); U25.7/EP and D34.2 on the east piece (nearest on-piece via 29.5–30.4 mm from the EP, 37.9 mm from D34.2); D34 → SW 4.28 mm; L22.1 → SW 13.75 mm edge; `/SW_PWRIN` 45.8 mm². Input loop ≈ **311 mm²** (≈ 51 mm² if C150.2 joined the EP island; Copper Plan target ≤ 1 cm²). EP 0 vias, 4 × 0.5 mm spokes. D34 loss 0.78·2.5 A·0.5 V ≈ 0.98 W. Estimated 15–25 nH × 3 A/5 ns → ≈ 9–15 V ringing on VIN over the 53.3 V clamp vs 65 V abs max (not simulated). + - **U20 AP64350:** C128.1 → U20.2 0.72 mm, C127.1 2.38 mm ✅; GND C128.2 → U20.7 **6.86 mm**, C127.2 **8.48 mm**, via a **0.25 mm GND track squeezed between U20.1 and U20.2** (gaps 0.225/0.195 mm); EP 0 vias (nearest 3.45 mm). Cin C127 10 µF 50 V X5R + C128 1 µF ≈ 9.5 µF at 5 V → 2 A·D(1−D)/(f·C) ≈ **65 mV p-p**, input RMS 0.78 A. FB: R110/R111 junction ≈ 2 mm from SW copper, `/FB_MODEM` 13.9 mm, VBAT tap via a 5.6 mm In1 detour. + - **U12 MP1584EN (3V3_ETH):** C101.1 → U12.7 **6.40 mm**; D11 → U12.1 11.92 mm; L8 15.10 mm; R87 (FB top) 25.9 mm → `/ETH_FB` 35 mm long, 1.84 mm² directly under `/ETH_SW` on In1; C101.2 and D11.2 on different F.Cu pieces (224 / 178 mm²). The same R5 🟠 item was 8.5 mm on V5.5. +- **Consequence:** SW-node/VIN ringing and conducted/radiated EMI into the GNSS/LTE receivers; U25 VIN overshoot eats the margin to 65 V during a clamped transient; EP/diode thermals; FB noise on U12 (3V3_ETH jitter) and U20. ECO §E.4 (Cin loops < 3 mm) not met. +- **Fix (layout; §6 L-20 … L-23), common rules:** Cin (VIN and GND pads) ≤ 2 mm from the IC VIN and GND/EP pins; Cin GND, catch-diode anode (D34/D11) and EP on **one solid F.Cu area**, no GND neck < 1 mm; ≥ 2 vias ≤ 1 mm from each Cin GND pad; catch diode ≤ 3 mm from SW; inductor ≤ 5 mm from SW; SW copper ≤ 25 mm²; FB divider ≤ 3 mm from the FB pin with nothing on In1 under the SW copper; acceptance input loop ≤ 1 cm². Per regulator: **U25** C149/C150 ≤ 2 mm from pins 2/7 on the EP/D34 copper, L22 ≤ 5 mm from pin 8, `/SW_PWRIN` off In1 signal tracks, 4 GND vias around the Cin/D34 node. **U20** delete the 0.25 mm GND neck; R110/R111 ≤ 2 mm from U20.5 on the side away from pin 8; VBAT sense by a dedicated trace from C131 (delete the In1 detour); **add 2 × 22 µF 16 V 0805 (C86817) ≤ 3 mm + 1 × 220 µF 16 V polymer (C881921) at U20.2** (verify_1 conflict (d): ripple 65 → 17 mV p-p; the 220 µF because at PFI hand-over the modem load sits on CSYS ≈ 60 µF; 16 V parts are valid only with A-01's 5 V input). **U12** R87/R88 ≤ 3 mm from U12.4, top resistor Kelvin-fed from C102/C94, FB ≤ 5 mm on F.Cu, nothing under `/ETH_SW`; D11 ≤ 2 mm from pin 1 with its anode on C101's GND copper; L8 ≤ 5 mm. +- **Effort:** both (layout + 3 caps at U20). + +##### F-51 · Major · No charger-die or cell temperature reaches the MCU; the firmware thermal inhibit has no source on v6 (R4) +*Status:* verified (verify_1). + +- **Evidence (every temperature source on v6):** + + | Sensor | Ref / net | MCU input | Distance to U6 | Notes | + |---|---|---|---|---| + | Board air + RH | U3 SHT40 (0x44) | I²C1 | **71.4 mm** | 52 mm from U19 | + | MCU die | U16 internal | ADC1_IN16 | 77 mm | | + | External probe 1 | P7 → `/NTC_TEMP` (R42 10 k) | PB1 / ADC1_IN9 | ≈ 100 mm | jack only | + | External probe 2 | P8 → `/NTC2` (R126 10 k) | PC4 / ADC1_IN14 | ≈ 83.5 mm | jack only | + | Pack NTC | P3.3 → `/NTC` → **U6.17 only** (R55 10 k from VEH5V) | **none** | — | LTC4040 hot pause 42.4 °C (B3380) | + | Modem die | A7670SA internal | AT over USART6 | — | firmware only (F-52) | + | TMP102 | **absent** (V5.x U4 and V5.6 TMP102 deleted in v6 T10) | — | — | — | + + Free pins: PC5 (only free ADC, ADC1_IN15), PB10, PA9, PD2. I²C: TMP102 at 0x48 does not clash (U10 A0 = A1 = GND → 0x4D). + +- **Consequence:** `CHG_CELL_HOT/COOL` (45/40 °C) have no cell sensor unless an installer tapes P7 to the pack; no charger-die visibility, so A-02-type cycling is invisible in telemetry. R4 is not met in firmware (the cell is still protected in hardware by the LTC4040 NTC pause). +- **Fix:** (1) **TMP102AIDRLR, LCSC C99269** (SOT-563, stock 34 854) between U6 and L6, ≤ 5 mm from the U6 EP, I²C1 **0x48** (ADD0 → GND), **100 nF C14663**. (2) Pack NTC to the MCU: tap `/NTC` into **PC5** through **100 k (C25803) top / 120 k bottom (**C25808**, 0603 1 %, Basic; assigned at publication) + 10 nF (C1589, the 10 nF 0603 X7R of E-04)**; PC5 ≤ 0.545·5.46 V = 2.98 V; the 220 k load shifts the LTC4040 hot threshold ≈ 0.7 °C (B3380, verify_1). `tcell` is valid only with VEH5V present (VEH5V = 0 on battery), which is when charging is possible. (3) Firmware: `tchg`, `tcell` appended to `$PHLG`; governor inhibits on `tcell` (Li-ion 45 °C / LFP 55–60 °C) and sheds on `tchg` > 85 °C. Rating Major: R4 is still reachable with the P7 probe on the pack plus the NTC pause; **Leo can promote it to Blocker if "sensor ≤ 10 mm of U6" is binding for R4** (verify_1). +- **Effort:** both (2 parts + 3 passives, placed in the A-02 re-cluster). + +##### F-06 · Major · RF feeds: LTE routed 22 mm on In1 under the modem power tracks with 2 via transitions; GNSS bias line 0.27 mm beside the RF line; neither line is 50 Ω on the real stackup +*Absorbs:* B-05, C-05, B-12 (stackup part). *Status:* verified-with-correction (verify_1 and verify_2: GNSS coupling re-measured; impedances re-derived; fence pitch set to ≤ 3 mm). + +- **Evidence:** + - LTE: `/RF_LTE` U19.60 → 4.01 mm F.Cu → **In1 22.14 mm** (0.5 mm) with vias at (174.25, 58.25) and (194.27, 53.72) → R118 → `/RF_ANT_LTE` 5.62 mm F.Cu → D28 → J13; ≈ 31.5–31.8 mm total. Copper within ±0.25 mm of the In1 run: `/VBAT_MODEM` F.Cu 1.15 mm², `/SYS5V` 0.71, `/SW_IN` 0.40, `/MODEM_LED_K/A` 0.56/0.10, `/DIN_4G` In2 0.71. F.Cu GND above covers ≈ 45–55 %; 1 GND via within 3.5 mm of the whole path. In1 section ≈ 30–47 Ω (FD 32.5 / 47.1 Ω). + - GNSS: `/RF_GNSS` 22.7 mm F.Cu, 0.5 mm / 0.15 mm gap; `/VCC_RF_GNSS` alongside with minimum edge gap **0.274 mm**, 3.25 mm of run at ≤ 0.3 mm, 13.4 mm at ≤ 0.5 mm, 17.9 mm within 1 mm (verify_2; FHJ's "16.7 mm at 0.27" overstated it); 2 GND vias within 3.5 mm; D27 on a 2.8 mm stub beyond C143 (≈ 1–1.2 pF, RL ≈ 11 dB, ≈ 0.4 dB). + - Impedance (JLC04161H-7628, L1–L2 0.2104 mm, εr 4.4): 0.5 mm microstrip **42.1 Ω**; CPWG 0.5/0.15 as built 41.0 Ω (FD 38.4 bare / 35.2 masked); CPWG 0.30/0.20 56.6 Ω bare closed-form, **FD 53.3 Ω bare / 48.4 Ω masked**; 0.35/0.20 52.1 Ω bare. On the file's generic stack (0.48 mm, εr 4.5) 0.5 mm is 66.6 Ω. The board file carries the generic stackup (copper finish "None"); RF and PWR_MODEM netclasses are missing. +- **Consequence:** LTE mismatch plus two unshielded via transitions, with the PA supply crossing the RF line (PA noise and burst ripple couple into the antenna feed) and radiated desense of the adjacent F9P; on GNSS a coupled section between the antenna input and a bias line decoupled only at L21. The G3 desense bench test is likely to fail. +- **Fix (layout + stackup; §6 L-1, L-30 … L-33):** set the real stackup in Board Setup (JLC04161H-7628: 0.035 / 0.2104 / 0.035 / 1.065 / 0.035 / 0.2104 / 0.035 mm, εr 4.4 prepreg / 4.6 core) and order impedance control. Both RF runs on **F.Cu only as CPWG over solid In1, starting at w 0.30 mm / gap 0.20 mm**, finalised in JLC's calculator; RF netclass (width = CPWG width, clearance = gap, no autoroute). LTE: reroute U19.60 → R118/C146/C147 → D28 → J13 on F.Cu (rotate J13 or move it toward U19's RF pad side); nothing above or below; `/VBAT_MODEM` ≥ 3 mm away. Via fence both sides at **≤ 3 mm pitch** (λg/20 = 3.1 mm at 2.69 GHz), ≤ 1 mm from the gap edge; 2 vias per U.FL GND pad. GNSS: bias feed (`/ANT_BIAS` after C-01) ≥ 1 mm from the RF line with a stitched GND strip between (or on In2 after 100 pF + 100 nF decoupling at U18 pin 7); L21 taps the line stub-free at J12; D27 on the J12 pad. Optional (C-05): C143 → 47 pF C0G 0402 (no LCSC selected). Fence-pitch conflict (FHJ ≤ 2.5 mm, BCE ≤ 3.3 mm) resolved to ≤ 3 mm (verify_2). +- **Effort:** both (stackup setting + layout). + +##### F-05 · Major · In1, the "solid GND reference", is 19 % void and carries 1572 mm of tracks from 49 nets +*Status:* verified, fix scope corrected (verify_2). + +- **Evidence:** In1 GND fill 11 370.5 mm² in 8 islands: **18.8 % void** vs 14 000 mm² (17.4 % vs the 139 × 99 mm usable area); **1571.9 mm of tracks from 49 nets** (largest users `/SW_5V` 181 mm, `/DOUT_4G` 95, `/KCOIL` 85, `/MAIN5V` 73, `/CHRG_FAULT` 72, `/CHRG_STAT` 69, `/USART6_TX` 68, `/BOOT0` 61, … `/24V_IN` 27, `/RF_LTE` 22). F.Cu nets over In1 voids: USB_DP/DM 10.4/9.7 mm (directly over `/24V_IN` and `/SW_5V`); I2C_SDA 25.2 mm (14.2 mm directly over `/SER_TXB`); ETH_XO 8.3 mm (6.95 mm over `/ETH_RST`); NRST 21.1 mm (7.2 mm over `/USART6_RX`); DFU_DM 13.2 mm; SIMB_CLK 9.1 mm (5.8 mm over `/SW_5V`); DOUT_4G_M 13.1 mm; RF_GNSS/RF_ANT_* 0 mm ✅. In2 GND (1 island) carries 1009 mm from 25 nets; B.Cu is the `/3V3` pour. +- **Consequence:** return currents detour around slots (emissions, susceptibility); broadside crosstalk with no plane between (I2C_SDA over SER_TXB, ETH_XO over ETH_RST); the Copper Plan's "unbroken In1" rule for the RF receiver is broken by design. +- **Fix (layout):** a full "In1 = plane" re-layout is ideal. **Minimum (verify_2):** clear In1 under the USB pairs, the crystals and their lines, all switch nodes, VBAT_MODEM/the RF area, SIM, and the three broadside parallels above. Priority moves: `/RF_LTE` (F-06), `/24V_IN` (F-02), `/SW_5V` (C-04), `/MAIN5V`, `/KCOIL`, `/USART6_TX/RX`, `/DOUT_4G`, `/CHRG_*`, `/SER_TXB/RXB`, `/ETH_*`, `/VFB_BST`, `/IGATE` → In2/B.Cu (or F.Cu where short). **Acceptance: ≤ 3 In1 islands and no critical net over a void longer than 1 mm.** +- **Effort:** layout (large). + +##### Minor (F) — not independently verified +- **F-52 · Minor · No on-board sensor near the modem (ECO D3 dropped).** Nearest board sensor to U19 is U3 at 52.1 mm; the only modem-temperature path is AT over USART6 (`AT+CPMUTEMP` exists on SIMCom A76xx; availability on the A7670SA firmware not verified; works only while the modem is up). *Fix:* firmware-only (`tmodem` in `$PHLG`), or a **second TMP102 (C99269) at 0x49** (ADD0 → 3V3) between U19 and U20. *Effort:* firmware-only, or both. +- **F-14 · Minor · DFU ESD (D14/D15/D16) hangs on stubs; D15 is 10.9 mm of copper from J11** (J9 part → G-02). DFU_DP/DM have no series resistors. Pad-edge / copper path J11 → ESD / on the path?: D14 2.53 / 3.3 mm / no (T-stub); D15 6.07 / **10.9 mm** / no; D16 2.62 / 3.0 mm / no; ESD GND → via 2.6 / 1.8 / 4.9 mm. *Consequence:* ≈ 1 nH/mm stub raises the clamp voltage on the fast IEC 61000-4-2 edge. *Fix:* route J11 D+/D− through the D14/D15 pads, D15 ≤ 3 mm of copper from J11, each ESD GND pad with its own via ≤ 1 mm; optional: one USBLC6-2SC6 (C7519) at J11 instead of three PESD5V0S1BA. *Effort:* layout. +- **F-17 · Minor · USB pairs split across layers and crossing slots.** `/USB_DP` F.Cu 49.9 + In1 9.6 mm; `/USB_DM` F.Cu 50.0 + In1 8.0 + In2 1.7 mm; they cross In1 `/24V_IN` (2.5 mm gap) at (157.75, 121.75), `/SW_5V` 2.47 mm, `/5V_FAN`, `/IGATE`, `/CHRG_FAULT/STAT`; `/DFU_DM` runs 5.98 mm over In1 `/ETH_ACTLED`. *Consequence:* A7670SA USB is high speed; FOTA/recovery through J9 may fail at HS. *Fix:* both pairs on F.Cu only over solid In1, coupled (≈ 0.2/0.15 mm on JLC7628 for 90 Ω, verify in the calculator), ≤ 1 via pair, no slot crossings. *Merge note:* verify_1 folded F-17 into B-07; verify_2 kept it separate as the routing (not ESD) part. Kept separate here so the Minor routing item does not inherit a Major rating. *Effort:* layout. +- **F-18 · Minor · Silkscreen: 304 of 312 reference texts are 0.5 mm / 0.1 mm (JLC minimum 1.0 mm / 0.15 mm).** The DRU text rule is 0.5/0.1 so DRC stays silent; 14 DRC silk items (11 silk_overlap incl. D27, U23, U24, Q10/JP5, Q23; 2 silk_over_copper Rigb1, C10; 1 silk_edge P1). *Fix:* refs ≥ 0.8 mm / 0.15 mm (1.0/0.15 where it fits); DRU text rule `(min 0.8mm)` / `(min 0.15mm)`; clear the 14 items; check D27/D28/Q10 polarity marks in the 3D view. See G-05 for label content. *Effort:* layout. + +##### Notes (F) — not independently verified +| ID | Observation | Action | +|---|---|---| +| F-19 | JLC 4-layer standard: passes (min track 0.20 mm, spacing 0.15 mm, vias 0.30/0.80 mm, copper-to-edge 0.625 mm); J9/J11 (GCT USB4085) at the limits: PTH ring 0.15 mm, hole-to-hole 0.45 mm, PTH hole → track 0.30 mm (V5.5 fabbed fine). | Order notes: ENIG (LGA U18/U19); JLC04161H-7628 with impedance control; X-ray on U18/U19; tent vias. | +| F-20 | Courtyard overlaps: all 15 MCP hits are bounding-box artefacts (polygon intersection 0.000 mm²); KiCad `courtyards_overlap` reports 0; only MH5–MH8 lack courtyards. | None. Watch the MWSA0804S bodies (8.2 × 8.8 mm on an 8.0 × 8.0 courtyard basis, H-03). | +| F-21 | One dangling `/SW_5V` track end at (86.35, 121.88): overlaps U21.3 by 0.085 mm², connected per KiCad. | Extend 0.3 mm to the pad centre (cosmetic). | + +#### (b) Pass/fail — §4-F +| Check | Evidence (one line) | Result | +|---|---|---| +| Fan driver / FB divider location | R20/R21 0.67/1.48 mm from U2.4 (ECO E3 fixed); moot if A-01 removes U2 | ✅ | +| Fan tach | 2-wire, `ENABLE_FAN_TACH 0` (decision) | ✅ (Note) | +| Fan default OFF | Rgs1 100 k on Q2 gate | ✅ | +| Temperature sensor near U6 | none; U3 at 71.4 mm | ❌ F-51 | +| Temperature sensor near modem | none on board (U3 52.1 mm); AT path only | ⚠ F-52 | +| Board ambient sensor | U3 SHT40 at (122.4, 77.3), I²C 0x44 | ✅ | +| Pack NTC reaches the MCU | `/NTC` → U6.17 only (the brief's "P12 NTC" is P3 on v6; P12 is now the RS-232 terminal) | ❌ F-51 | +| Real cell source for `CHG_CELL_HOT` 45 °C | none on board | ❌ F-51 | +| Crystals ≤ 5 mm | Y1 10.79/13.74 mm (E-03), Y3 8.32/11.30 mm (D-02), Y4 3.92/6.32 mm (D-03), Y2 5.51/4.64 mm (no finding) | ❌ Minor items | +| Crystal ↔ inductor ≥ 10 mm | nearest Y1–L8 13.6 mm | ✅ | +| Via stitching under the modem / F9P | 1 / 0 vias under the bodies | ❌ F-12 | +| Board stitching / edge fence | 69 GND vias, 10 empty 20 mm cells, 2 edge vias | ❌ F-12 | +| Thermal vias in regulator EPs | 0 in U6/U25/U20/U2/U12 | ❌ A-02, F-12 | +| DFU ESD at J11 | 2.5–6.1 mm pad edge (V5.5: 41 mm) | ✅ (stubs: F-14) | +| Return paths across splits | In1 19 % void, 1572 mm of tracks; USB, crystal, SIM, I²C lines over slots | ❌ F-05 | +| 24 V on inner layers next to LV | `/IGN_IN` In2 0.221 mm from `/VEH5V`; `/24V_IN` In1 0.500 mm from `/SW_5V` | ❌ F-02 | +| Netclasses resolve / DRC can see 24 V spacing | 1 of 14 HV nets in HV24; 0.15 mm override rule; RF/PWR_MODEM missing | ❌ F-01 | +| Outer-layer 24 V spacing ≥ 0.3 mm | 15 spots < 0.3 mm (worst 0.150; `/VIN_PROT`–`/VEH5V` 0.162) | ❌ F-01 (F-15) | +| `/24V_IN` clearance | ≥ 0.500 mm to everything on all 4 layers | ✅ | +| Switch nodes only on outer layer | `/SW_PWRIN`, `/SW_FAN`, `/SW_MODEM`, `/SW_BAT`, `/ETH_SW` F.Cu-only | ✅ | +| Buck hot loops (ECO E.4) | U25 GND split (≈ 311 mm² loop), U20 0.25 mm neck, U12 6.40 mm / 11.92 mm | ❌ F-03 | +| U20 VIN cap, BST, L20 placement | C128 0.72 mm, C129 1.8 mm, L20 2.24 mm | ✅ | +| U25 BST cap, FB/COMP/RT | C152 1.49 mm; R122 1.0, R121 2.9 mm; FB net 4.1 mm | ✅ | +| RF lines 50 Ω, fenced, on the real stackup | LTE 22 mm on In1, 30–47 Ω, 1 fence via; GNSS 38–42 Ω, bias line 0.274 mm | ❌ F-06 | +| RF_GNSS over a solid plane | 0 In1 slot crossings | ✅ | +| GNSS island ↔ switchers ≥ 25 mm | `/ETH_SW` 27.5 mm, L8 35.3 mm, `/SW_FAN` 54.1 mm | ✅ | +| Courtyard overlaps (real) | 0 of 15 (polygon intersection 0.000 mm²) | ✅ | +| Dangling track ends | 1, benign | ✅ (F-21) | +| Silkscreen size vs JLC | 304 refs at 0.5/0.1 mm | ❌ F-18 | +| JLC 4-layer manufacturability | passes; J9/J11 at PTH-ring and hole-spacing limits | ✅ / ⚠ (F-19) | +| DRC clean | 0 errors, but only because of F-01; 283 warnings classified in §4-J | ⚠ F-01 | + +--- +### 4-G Connectors and harness (`drogheda-einarboard-harness`, `drogheda-einarboard-j1-mirror`) + +#### (a) Findings + +##### G-01 · Blocker (conditional) · Mounting-hole pattern changed vs V5.5: MH4 now lands on L6; heatsink-clamp holes MH11 + partner missing +*Status:* verified-with-correction (verify_2: Blocker unless Leo confirms a re-drilled backplate; MH11 and its partner are also missing). + +- **Evidence:** outline identical to V5.5 (140.00 × 100.00 mm, x 60.19–200.19, y 40.32–140.32). V5.5 PCB holes: MH5 (65.2, 45.3), MH6 (65.2, 135.3), **MH4 (193.2, 90.3)**, MH7/9/10/11 (M2.5 shield/heatsink). v6 holes: MH5 (65.2, 45.3), MH6 (65.2, 135.3), MH7 (195.2, 45.3), MH8 (195.2, 135.3): a 130 × 90 mm corner pattern. At (193.2, 90.3) on v6 the **L6 courtyard contains the point** (0.0 mm); L6.2 `/BAT_PLUS` pad centre 2.44 mm away; R133 1.75 mm. Design brief v1.0: "Keep 140.000 × 100.000 mm — no enclosure rework"; memory `drogheda-v6-zed-f9p-integration`: "MH4/5/6 (enclosure) and MH11 (heatsink clamp) survive"; Phase-2 delta: "KEEP MH11 and add one partner near U19". **MH11 at (168.3, 84.6) is missing** (the point is now 0.6 mm from the U19 courtyard), and so is its partner: these are the modem heatsink-clamp holes for thermal gate T1. MH6: `/3V3` F.Cu track 3.55 mm from the hole centre (an M3 washer Ø7 mm needs ≥ 3.5 mm plus tolerance). +- **Consequence:** in an enclosure drilled for V5.5, v6 cannot be screwed down on the right side, and a metal standoff at (193.2, 90.3) would press on L6 / `/BAT_PLUS`. No modem heatsink clamp is possible. If the backplate is re-drilled per board, this becomes a documentation item. +- **Fix:** Leo confirms the backplate pattern (§10). If the V5.5 standoffs are reused: **restore MH4 at (193.2, 90.3)** (L6 must move anyway, A-02: ≤ 5 mm from U6); decide and place the heatsink-clamp pair near U19 (MH11 + partner). Otherwise publish the 130 × 90 mm corner pattern for the enclosure. Keep a ≥ 4.0 mm copper-free radius on F.Cu/B.Cu around every mounting hole (move the `/3V3` track at MH6 by ≥ 0.5 mm) or specify nylon washers. +- **Effort:** layout (+ enclosure drawing). + +##### G-02 · Major · Modem USB-C J9 has no ESD protection (lesson F8, ECO §E.5) +*Absorbs:* B-07 (ESD part), F-14 (J9 part). *Merge note:* verify_1 used B-07 as primary and folded F-17 in; verify_2 used G-02 and kept F-17 (pair routing) separate as a Minor. This report follows verify_2, because the routing item carries its own lower severity. *Status:* verified (verify_1 and verify_2). + +- **Evidence:** `/USB_DP` = {J9.A6, J9.B6, U19.27}, `/USB_DM` = {J9.A7, J9.B7, U19.28}, `/USB_VBUS` = {J9.A4/A9/B4/B9, U19.24}: no protection device (unchanged since the 25-Sep review). J9 is 64.6 mm (centre) from U19. J11 has D14/D15/D16. J9 is the modem's firmware-update / USB_BOOT recovery port (TP8). +- **Consequence:** a field-service ESD hit on J9 goes straight into the A7670SA USB PHY/VBUS; the modem is the unit's only link and J9 is its only recovery route. +- **Fix:** add **USBLC6-2SC6, LCSC C7519** (ST, SOT-23-6, 3.5 pF, stock 1415): pins 1/6 → `/USB_DM`, 3/4 → `/USB_DP`, 5 → `/USB_VBUS`, 2 → GND (same connection as V5.6 D19); **≤ 3 mm of copper from the J9 pads**, flow-through (D± routed through the device pads), GND via ≤ 1 mm (distance conflict ≤ 3 mm vs B-07's ≤ 5 mm resolved to ≤ 3 mm by verify_2). +- **Effort:** both. + +##### Minor (G) — not independently verified +- **G-03 · Minor · J10 / P11 / P12: DNP and footprint disagree between schematic and PCB** — *absorbs E-05, H-06.* Schematic: J10, P11, P12 populated; PCB: all three `dnp`. P11 (`/RS485_A,B,GND`) and P12 (`/RS232_TX,RX,GND`) schematic footprint `…MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical` **does not exist** in the KiCad library (MC = right-angle; vertical is MCV); the PCB uses `…_Horizontal`, which matches **C5160226 DEGSON 15EDGRC-3.5-03P, right-angle, 7 A** (V5.5 fabbed the same Horizontal footprint). J10: schematic nickname `Connector_RJ45` (not configured) vs PCB `Connector_RJ`; LED pins 9–12 still marked "VERIFY". U10/U14/U15 are populated on both sides. With J10 DNP, the populated W5500 block (U11, U12, Y1, C90–C103) has no connector. These are the 3 "real" ERC items (`footprint_link_issues`). *Consequence:* the schematic BOM orders three parts the CPL marks DNP; an Update-PCB with "replace footprints" would load the missing Vertical footprint and flip DNP back. *Fix:* schematic footprints → `Connector_Phoenix_MC:PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal` (P11, P12) and `Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal` (J10); set DNP identically on both sides per Leo's intent (if hand-fitted THT: DNP in the schematic too, listed on the hand-assembly sheet); if Ethernet is not fitted on v6, DNP U11/U12/Y1 and their passives as well; verify the J10 LED pins against the HR911105A drawing. *Effort:* schematic-only (+ Leo's decision). +- **G-04 · Minor · No solder-jumper bypass across the cut-off connector P5** (ECO §F JP_CUT; Review §4 #9). P5 CUTOFF-SW = {1 `/MAIN5V`, 2 `/SYS5V`}; nothing bridges them. Without a plug in P5, `/SYS5V` is dead. *Fix:* add **JP_CUT = `Jumper:SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm`** (no BOM part) across P5, open by default, silk "CUTOFF BYPASS"; `/SYS5V` load ≲ 0.8 A fits a 1.0 × 1.5 mm bridged pad pair. *Effort:* both. +- **G-05 · Minor · Silkscreen labels: stale modem-reset label, ECO names missing, P-renumber collisions.** "4G NTRIP RESET" at (187.0, 124.1): v6 has no modem-reset button (SW4G1 deleted); the label sits between D34 and L22. SW1 "NRST", SW2 "BOOT" (ECO asks "RESET MCU"); JP2 (chemistry) carries only its refdes, and "F2" is also the fuse refdes; P1 has one label "IGN 24V" at (178.5, 129) with no per-pin legend although v6 accepts 9–36 V; all labels 0.5 mm / 0.1 mm. **Renumber hazard:** a V5-labelled "P6 FAN" XH-2 plug fits v6 **P6 RESET-EXT** (the fan motor across NRST–GND holds the MCU in reset); V5 "P8 PANEL_LED" fits v6 **P8 NTC2**. *Fix:* delete "4G NTRIP RESET"; SW1 "RESET MCU", SW2 "BOOT0 (DFU)"; JP2 "CHEM 1-2 Li-ion / 2-3 LFP"; P1 legend "VIN 9-36V · GND · IGN · GND · NC"; a function name at every connector (FAN, RESET, NTC1, NTC2, LED, BATT, CUTOFF, 5V BENCH); text ≥ 0.8 mm / 0.15 mm (F-18); harness labels by function, not P-number. *Effort:* layout. +- **G-08 · Minor · External-cable inputs P6 (NRST) and P7/P8 (NTC ADC) have no ESD protection.** `/NRST` = {U16.7, C104, SW1, P6.1, TP5}: C104 3.26 mm from the MCU, 35.6 mm from P6, NRST routed 108.6 mm. `/NTC_TEMP` (PB1) and `/NTC2` (PC4) go to P7.1/P8.1 with 100 nF near the MCU (C24 6.63 mm, C157 3.11 mm); P7/P8 at 20.2/21.5 mm. IEC 8 kV/150 pF dumps 1.2 µC ≈ 12 V step on 100 nF before the MCU diodes conduct. *Fix:* **PESD5V0S1BA (C2827694, SOD-323**, already in the BOM as D14–D16) at P6.1, P7.1 and P8.1, each ≤ 3 mm from its connector to GND; optional 100 Ω series (C22775) on NRST between P6 and the net. *Effort:* both. + +##### Notes (G) — not independently verified +| ID | Observation | Action | +|---|---|---| +| G-06 | P2 bench input sits directly on U25's output (`/VEH5V`), no OR-ing. With P2 only: current flows L22 → SW → TPS54360B high-side body diode → `/VIN_PROT`; Q23 then conducts to `/24V_IN`, and via Q10's body diode to `/24V`: ≈ 4 V on P1.1 and `/24V` (U2 may try to run). Benign with both sources (both source-only). | Document in the bench procedure ("P1.1 reads ≈ 4 V on P2-only power"); or a series Schottky on P2 (no LCSC selected). With A-01, Q10/U2 are DNP. | +| G-07 | P3 = JST B3B-XH-A (C144394), 3 A per contact: 2.42 A charge (81 %) with 825 Ω, 1.4 A after A-03; backup peaks 3.0–3.4 A, 0.6–1 A average; ≈ 70 mV across two contacts at 3.4 A. | Keep XH-3 for compatibility with the existing 1S4P packs; if the pack harness is remade (LFP-HT, ECO D1) move to XH-5 (2 × BAT+, 2 × GND, NTC) or JST VH (v6.1). | + +#### (b) Pass/fail — §4-G +| Check | Evidence (one line) | Result | +|---|---|---| +| P1 / P2 power entry | P1 MKDS 5-pin (16 A) = VIN, GND, IGN, GND, NC; P2 = bench 5 V on `/VEH5V` | ✅ (G-06 Note) | +| Ignition GND return | P1.2 and P1.4 = GND, P1.5 NC (as V5.5) | ✅ | +| Ignition wire routing / protection | raw `/IGN_IN` 106 mm on In2, no TVS | ❌ F-02 | +| JP_CUT across the P5 cutoff | none | ❌ G-04 | +| Pin-1 marking / mirrored sockets (J1 errata class) | every connector a KiCad-library footprint with a distinct pad-1 shape and silk marker; J12/J13 symmetric; J14 stock KiCad JAE; no module sockets on v6 | ✅ | +| Harness pinouts vs V5.5 (by function) | P1, P2, P3=P4, P4=P6, P5=P11, P6=P10, P7=P12, P9=P8, P10=P14, P11=P15, P12=P16 identical | ✅ | +| Renumbered-plug collisions | V5 "P6 FAN" fits v6 P6 RESET-EXT; V5 "P8 PANEL_LED" fits P8 NTC2 | ⚠ G-05 | +| Silkscreen names (RESET MÓDEM / RESET MCU / F2) | stale "4G NTRIP RESET"; SW1 "NRST"; JP2 no legend | ❌ G-05 | +| J9 modem USB ESD | none | ❌ G-02 | +| J11 DFU ESD | D14/D15/D16 at 3.19/6.74/6.83 mm | ✅ (stubs: F-14) | +| P6/P7/P8 external-cable ESD | none | ⚠ G-08 | +| Sch/PCB parity J10/P11/P12 | DNP and footprint mismatch | ❌ G-03 | +| Mounting holes vs V5.5 enclosure | MH4 (193.2, 90.3) missing, L6 on it; MH11 + partner missing | ❌ G-01 (conditional) | +| Outline / case fit XY | 140.00 × 100.00 at V5.5 coordinates; J10 and J11 within 0.09 mm of V5.5 | ✅ | +| Connector current ratings | P1 16 A, P2 3 A at ≤ 2.5 A, P5 3 A at ≤ 0.8 A, P11/P12 7 A; P3 3 A at 81 % (as-is) | ✅ (P3: G-07) | + +--- +### 4-H BOM and JLC manufacturability + +Full line-by-line check: `findings/bom_check.csv` (152 BOM lines; LCSC, JLC DB part, package, Basic/Extended, stock at 20/100 boards, footprint vs package, unit price). Cross-references: C130/C131/C78 electrolytics → **B-02 / A-09**; D21 60 V clone (H-05) → **A-01**; J10/P11/P12 → **G-03** (absorbs H-06); Y1 load caps → **E-03** (absorbs H-07). + +#### (a) Findings + +##### H-04 · Blocker · U25's footprint carries `LCSC Part` = C2071691 (AP64350, 40 V) and the Fabrication Toolkit reads that field first +*Absorbs:* A-15. *Status:* verified, severity raised Major → Blocker (verify_2: the key order is proven in the toolkit source; the 25-Sep pre-fab audit prescribes that toolkit). + +- **Evidence:** 14 v6 footprints carry `LCSC Part`, all inherited from the easyeda `Drogheda-v6.pretty` footprints; **U25 is the only one whose value differs from `LCSC`** (C2071691 vs C524806). Source: `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` line 12, `(property "LCSC Part" "C2071691")` (U20 and U25 share this footprint). Fabrication-Toolkit `plugins/process.py::_get_mpn_from_footprint` tries `['LCSC Part #', 'LCSC Part', …]` before the fallback `['LCSC', …]` and returns the first non-empty field. The 25-Sep pre-fab audit says "Generate BOM/CPL from the board … (Fabrication Toolkit)", and the V5.5 `production/` folder is the toolkit's output folder. AP64350 and TPS54360B are pin-compatible (1 BST, 2 VIN, 3 EN, 4 RT/CLK, 5 FB, 6 COMP, 7 GND, 8 SW) with the same 0.8 V FB. +- **Consequence:** U25 would be assembled as the AP64350: boards pass the bench, then fail at the first transient above 40 V behind a 53 V clamp. Damage risk → Blocker. +- **Fix:** delete `LCSC Part` from U25 **on the board and in the library footprint** (or from all 10 `Drogheda-v6.pretty` footprints). Alternatively generate the BOM from the schematic with kicad-cli (`evidence/bom.csv` is correct), but delete the field regardless. +- **Effort:** schematic/board property only. + +##### H-01 · Blocker · U15 MAX3232ESE (narrow SO-16) sits on a wide SOIC-16W land: it cannot be soldered (v6 regression) +*Status:* verified-with-correction (verify_2: V5.5 was built on the correct narrow land; v6 regressed when its footprints were rebuilt from the schematic). + +- **Evidence:** JLC DB: C15846 = MAX3232ESE+T, "SOIC-16" (compare C7605 PCF8574T = "SOIC-16-300mil"). Maxim 19-0273 Rev 10 Ordering Information: "MAX3232ESE+ … 16 Narrow SO"; "MAX3232EWE+ … 16 Wide SO". v6 PCB U15 = `SOIC-16W_7.5x10.3mm`, pads 2.05 × 0.6 mm, pad-row centres x = 117.3 / 126.6 (**9.3 mm apart**); a narrow SO lead tip reaches ±3.0–3.1 mm while the inner pad edge is at ±3.625 mm → leads end 0.5–0.6 mm short of the pads. History: the V5.5/V5.6 schematics carry the same stale SOIC-16W field, but the V5 PCB uses `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm` (pads 1.95 × 0.6 at ±2.475 mm); v6 regressed at the 02-Sep fresh-layout re-sync. U15 is the only carried-over LCSC part whose footprint changed. +- **Consequence:** RS-232 (P12) dead on every v6 board; JLC either rejects the job or places a part that cannot be soldered. +- **Fix:** set **`Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`** in the v6 schematic **and** PCB, keep **C15846** (genuine Maxim, stock 4873), re-place C84–C88 against U15. Fix the stale field in the V5.x schematics too, so a future Update-PCB cannot break the working V5.5 land. C19268179 (TECH PUBLIC MAX3232ID) only as an alternate; the wide part C118514 (30 in stock) is not recommended. +- **Effort:** both (footprint + local re-route). + +##### H-02 · Blocker (order gate) · U10 and R53 cannot be bought for any order quantity +*Status:* verified-with-correction (verify_2: Blocker only for U10 + R53; the other stock items become Major H-02b). + +- **Evidence (JLC DB snapshot 2026-09-28):** U10 C729142 (SC16IS762IPW) **15 in stock**; R53 C131054 (YAGEO 499 k 1 %) **6 in stock**, first price break 20+, so JLC's 20-piece minimum cannot be met at any board quantity. R53 sets the LTC4040 boost set-point: unplaced, the backup rail does not regulate. +- **Consequence:** JLC leaves U10 (RS-485/RS-232 bridge) and R53 unplaced. +- **Fix:** **U10 → C57156 SC16IS752IPW,128** (same TSSOP-28, pinout and registers; U10 runs in I²C mode (pin 9 = 3V3), where 752 and 762 are identical; the value field already says 752; stock 2670). **R53 → C177479** HKR RCT03499KFLF (499 k, 1 %, 100 ppm, 0603, 100 mW, 75 V; stock 26 862). Both are exact drop-ins. Re-check stock on order day. +- **Effort:** schematic-only. + +##### H-02b · Major · Stock to re-check against the order quantity (split from H-02) +*Status:* verified (verify_2). + +- **Evidence:** C103211 (RALEC 100 k **5 %**) 702 in stock, 9 per board → 78 boards max (refs R20, R56–R58, R85, R87, Ren1, Rfreq1, Rgs1; R20/Ren1/Rfreq1 disappear if A-01 DNPs the U2 block). U19 A7670SA-LASC C18548276: 96. U18 ZED-F9P-04B C5120257: 104. J14 C2977286: 10 890 but in "Pre-ordered Products" (must be pre-ordered into the JLC account; pre-fab B4 still open). L2+L8 / L6 / U13 / P11+P12 stock is fine at 100 boards. +- **Consequence:** a 100-board order stalls on U18/U19/C103211; J14 fails without a pre-order. +- **Fix:** **C103211 → C25803** (UNI-ROYAL 100 k **1 %**, Basic, 10.8 M in stock; an upgrade: R87 sets 3V3_ETH, R20 the fan output). Pre-order/consign U18 and U19 for quantities ≳ 100; pre-order J14. Re-check all on order day. +- **Effort:** schematic-only + purchasing. + +##### Minor (H) +- **H-03 · Minor · Sunlord MWSA0804S inductors (L2, L6, L8, L20) sit on a Bourns SRU8028 land.** *Status:* verified, severity changed Major → Minor (verify_2: the same part/land pairing ran on L2/L6/L7/L8 of 15 assembled V5.5 boards; joint strength is ample). Land: pads 2.0 × 3.2 mm at ±3.9 mm (2.9–4.9 mm from centre). MWSA0804S (Sunlord spec Table 4-1): body 8.2 ± 0.3 × 8.8 ± 0.4 × 3.8 mm, electrodes D 1.4 × E 5.0 mm, recommended land I 2.75 / J 4.0 / H 5.5 mm (typ); wetted electrode area **55–64 %**; ≈ 3.8 mm² per joint, SAC ≈ 30 MPa → ≈ 100 N against ≈ 0.1 N/g. The Sunlord drawing letters could not be read in the sandbox (LCSC/Digikey PDFs blocked). The V5.5 "modem dark on battery" was root-caused to back-feed/UVLO, not inductor joints. *Fix:* change the footprint, not the part (SRU8028-class Bourns parts have lower Isat than MWSA0804S-2R2 for L6): build `Drogheda-v6:IND-SMD_MWSA0804S` from the LCSC drawing (auditor's reading: pads 2.75 × 4.0 mm, 5.5 mm inner gap → centres ±4.125 mm; courtyard 9.4 × 9.8 mm; confirm against the drawing) and assign it to L2/L6/L8/L20 (C17700171/65/67) while L6/L20 are re-placed anyway; re-check neighbours for the 0.4 mm body growth. *Effort:* both. +- **H-08 · Minor · Value-field / BOM mismatches** — *absorbs D-16* (not independently verified). C22 "22uF/50V" but C138687 is 10 µF 50 V X7R 1210 (moot if A-01 DNPs C22); **Y2 "1.8432MHz" but C2238 is 3.6864 MHz** (firmware `BOARD_SER_XTAL_HZ 3686400UL` already matches the fitted part); U10 "SC16IS752IPW" but C729142 is SC16IS762 (fixed by H-02); C103 "100uF/6.3V" but C88744 is 35 V (harmless); C130/C131/C78 "220uF/10V" but C2827940 is 16 V (parts replaced by B-02/A-09). *Fix:* correct the value fields (C22 → "10uF/50V" unless 22 µF was intended; Y2 → "3.6864MHz"). *Effort:* schematic-only. + +##### Notes (H) — not independently verified +| ID | Observation | Action | +|---|---|---| +| H-09 | Every fitted BOM line has an LCSC number except TP1–TP8 (copper pads) and PF1–PF21 (virtual). Schematic DNP: C146/C147, R107/R108, R124/R125, R127–R130, U22 (+ J10/P11/P12 on the PCB only, G-03). F2 = C206910 now assigned. The 10 "not found" and 22 "differs from library" symbols were checked pin → pad → net on 25 parts: **no hidden pin mismatch**. RS1 62.5 mW of 1 W. | None beyond H-01…H-08. | +| H-10 | Cost: cost analysis kept in the repository copy. Consolidations that remove 4 Extended parts: C14676 → C21190 (1 k 1 % Basic), C14675/C103211 → C25803, C304185 → C21189 (0 Ω Basic). | See the repository copy (§9 cost note, §10 #23). | + +#### (b) Pass/fail — §4-H +| Check | Evidence (one line) | Result | +|---|---|---| +| Every fitted BOM line has an LCSC number | all except TP1–TP8 (pads) | ✅ | +| LCSC parts exist in the JLC DB | 121/121 found | ✅ | +| Stock for any order quantity | U10 15, R53 6 (20-pc minimum) | ❌ H-02 | +| Stock for 100 boards | C103211 78 boards max; U19 96; U18 104; J14 pre-order | ⚠ H-02b | +| Package ↔ footprint | U15 narrow SO on SOIC-16W land (hard mismatch) | ❌ H-01 | +| Inductor land (L7-class SRU8028 vs MWSA0804S question) | 55–64 % electrode wetting; ran on 15 V5.5 boards | ⚠ H-03 | +| BOM field integrity (tool reads the intended LCSC) | U25 `LCSC Part` = AP64350 read first by Fabrication Toolkit | ❌ H-04 | +| DNP list explicit / consistent | schematic DNP list explicit; J10/P11/P12 DNP only on the PCB | ⚠ G-03 | +| No `TBD` | F2 now C206910; no TBD on fitted parts | ✅ | +| Polarity marks | polarized parts use footprints with pin-1/cathode marks; D27/D28/Q10 marks among the silk overlaps | ✅ / ⚠ F-18 | +| Voltage ratings on 24 V nets | ceramics ≥ 50 V (≥ 1.8× at 28.8 V); D21 30 V, U2 30 V abs max | ✅ / ❌ A-01 | +| Value fields match parts | C22, Y2, U10, C103, C130/C131/C78 | ⚠ H-08 | +| Stale library symbols hide pin errors | 25 parts checked pin → pad → net, 0 mismatches | ✅ | +| U19 / L22 fab attribute | both `smd` (pre-fab B2 closed) | ✅ | +| Unit BOM cost delta vs V5.6 | cost analysis kept in the repository copy | (H-10 Note) | + +--- +### 4-I Requirements traceability (ECO §0 R1–R5) + +The full traceability table is §3. Pass/fail summary on v6 **as drawn**: + +| Requirement | As drawn | Closed by | +|---|---|---| +| R1 — 10-min off/on on battery with report | ❌ needs changes + firmware | A-05, E-01, B-02, C-02, D-01, A-01, A-08, H-02 (R53) + FW sequencing | +| R2 — modem never left dark (MCU can power-cycle it) | ✅ hardware; firmware only | FW ladder (B-10 makes STATUS unambiguous) | +| R3 (brief) — report while on battery | ❌ needs changes + firmware | A-05, E-01, B-02, B-03, F-12, F-06 + FW | +| R3 (ECO) — charge from the 5 V source without brown-out loops | ⚠ no fold-back possible; charger does not start | A-04 (+ A-03) | +| R4 — temperature management (sensors + fan + charger inhibit) | ❌ no cell/charger temperature at the MCU | F-51 (+ F-52 option, A-01 fan) + FW | +| R5 (brief) — charge ≥ 1.3 A without thermal cycling | ❌ | A-03, A-02, A-04 (+ A-07) | +| R5 (ECO) — EMC list of the second batch (ECO §E) | ❌ items 1, 2, 4, 5 (J9 part) and 6 open; item 3 (fan FB divider) and item 5 (DFU ESD at J11) done | A-02 (1, 2), F-03 (4), G-02 (5), D-02 / D-03 / E-06 / F-12 (6) | + +--- + +### 4-J ERC / DRC + +Run with kicad-cli (KiCad 10.0.4) through the KiCad MCP on the unmodified v6 files. Summary tables in Appendix A (ERC) and Appendix B (DRC). Every item is classified in **`findings/ercdrc_classified.csv`** (449 rows: 166 ERC + 283 DRC; columns tool, type, severity, message, coordinates, refs, net, width, rule, layer, classification, justification). Classes: **real** (a design problem), **pre-existing-benign** (rule or library noise, no action beyond hygiene), **needs-fix-cosmetic** (fix for a clean gate, no electrical effect). + +| Tool | Result | real | pre-existing-benign | needs-fix-cosmetic | +|---|---|---|---|---| +| ERC | 0 errors, **166 warnings** | 3 (`footprint_link_issues`: P11, P12, J10 → G-03) | 126 (104 pin_to_pin, 22 lib_symbol_mismatch) | 37 (23 orphan NC flags, 10 lib_symbol_issues, 2 NC-on-connected markers, 2 wire stubs) | +| DRC | 0 errors, **283 warnings**, 0 unconnected | 59 per the CSV (`track_width` on 7 power nets) → **verified: 63 hits on 6 nets** (J-02) | 206 (124 track_width on low-current nets, 82 lib_footprint_mismatch) | 18 (11 silk_overlap, 4 lib_footprint_issues MountingHole, 2 silk_over_copper, 1 silk_edge) | + +**The DRC "0 errors" is produced by the rule set, not by the copper (J-01 → F-01).** With the corrected netclasses and `.kicad_dru`: 6 inner-layer errors (all `/IGN_IN`, F-02) + 15 outer-layer errors at the 0.3 mm rule (38 at 0.5 mm), plus ≈ 178 zone-fill proximities that disappear on refill. With Default = 0.2 mm and no floor rule: +471 pairs. Five DRC checks are ignored in the project (`footprint_type_mismatch`, `missing_courtyard`, `track_not_centered_on_via`, `footprint_filters_mismatch`, `tuning_profile`); J-05 found nothing hidden behind them. + +#### (a) Findings + +*J-01 is merged into F-01 (Blocker, §4-F).* + +##### Minor (J) +- **J-02 · Minor (residual) · `track_width` warnings: 6 nets really under-sized; the rest is an over-strict T15 rule.** *Status:* verified-with-correction (verify_2: 6 real nets carrying 63 DRC hits (`/BAT_PLUS` 123 mm under capacity incl. 69.9 mm of In2 1.0 mm, `/MAIN5V` 111 mm, `/VEH5V` 102 mm, `/SW_BAT` 12.9 mm, `/VIN_SW` 26 mm, `/VBAT_MODEM` 12.5 mm); `/VIN_MODEM` is only a 0.1 mm neck; JLC04161H inner copper 0.5 oz makes inner runs ≈ 40 % weaker than the file's 1 oz). The copper itself is owned by A-02 (`/SW_BAT`, `/BAT_PLUS`), A-07 (`/VEH5V`, `/VIN_SW`, `/MAIN5V`) and B-08 (`/VBAT_MODEM`). *Residual fix:* move `/3V3_ETH` to Default (54 benign hits, 0.15 A) and relax T15 for the benign fan/SW_5V/SW_IN/SYS5V/VIN_PROT/VIN_FUSED nets (keep the 0.8 mm rule on `/VIN_PROT`/`/VIN_FUSED` for pulse/fuse coordination), so the warning list becomes a clean gate. Order 1 oz inner copper or widen inner runs 1.65×. *Effort:* layout (rules). +- **J-03 · Minor · 104 ERC pin-to-pin warnings are pin-type noise** (not independently verified). All involve pins typed `unspecified` in easyeda-imported symbols (U19, U20, U23, U24, U26, D21, D22, D27, D28, J12, J13): 50 Unspecified–Passive, 46 Unspecified–Unspecified, 5 –Bidirectional, 2 –Power output, 1 –Input. Net-by-net check found no driver conflict (U23 DIR = GND, U24 DIR = VCCA, single drivers on every UART/status net, Q20/Q21 open drain). *Consequence:* 104 standing warnings hide the next real one. *Fix:* retype the pins in `Drogheda-v6.kicad_sym` (power_in/power_out/input/output/passive). *Effort:* schematic-only (library). +- **J-04 · Minor · ERC cosmetics: 23 orphan NC flags, NC flags on 4 connected pins, 2 wire stubs, 10 missing symbols, 22 lib-mismatched symbols** — *absorbs B-11, D-11* (not independently verified). Orphan NC flags at x = 453.898 mm (13) and 484.378 mm (10), left from the deleted SimpleRTK2B socket. NC flags on connected pins U16.37 (PC6 `/USART6_TX` → K1.10), U16.38 (PC7 `/USART6_RX` → R106.2), U10.13/14 (`/I2C_SCL`/`/I2C_SDA`): nets are real in the netlist and IPC-356 and routed (KiCad reports 2 markers). Wire stubs at P1.4 and R52.2 (uuid 2b755f7f…, 46f71e27…, 7c1dbfc0…). *Consequence:* the NC flags would suppress a future "unconnected pin" ERC if a label broke (the V5.6 junction incident shows how that happens); a tool honouring NC flags could drop the modem UART. *Fix:* delete the 27 flags and 3 stub segments by UUID; copy the 10 missing symbols into `Drogheda-sym` and re-link; leave the 22 mismatches (do not bulk-update); re-run ERC (D-11: the NC-on-connected count should drop by its 2 markers). *Effort:* schematic-only. + +##### Notes (J) — not independently verified +| ID | Observation | Action | +|---|---|---| +| J-05 | Ignored DRC checks hide nothing real today: `missing_courtyard` only MH5–MH8; `footprint_type_mismatch` JP1–5/TP1–8 (unspecified attribute, SMD pads); 178 track ends off-centre in vias (≤ 0.40 mm, all connected); no tuned nets; 82 lib_footprint_mismatch = KiCad 10 library revisions; 4 lib_footprint_issues = MountingHole nickname not in `fp-lib-table`. | Re-enable `footprint_type_mismatch` after setting TP1–8 to SMD + exclude-from-BOM. Do **not** run "Update footprints from library" (it would swap P11/P12 and reset pads). | + +#### (b) Pass/fail — §4-J +| Check | Evidence (one line) | Result | +|---|---|---| +| ERC run | kicad-cli, 166 items, full list reconstructed (22 + 10 + 30 exact + 104 pin-to-pin modelled, totals equal KiCad) | ✅ | +| ERC errors | 0 | ✅ | +| ERC real items | 3 footprint-link issues (P11, P12, J10) | ❌ G-03 | +| ERC pin-to-pin conflicts hide a driver clash? | net-by-net check: none | ✅ (J-03 hygiene) | +| NC flags hide a wiring error? | 4 flagged pins are connected and routed | ✅ (J-04 hygiene) | +| DRC run | kicad-cli on stored fills, 283 items, 0 unconnected | ✅ | +| DRC errors meaningful | 0 errors only because the 0.15 mm catch-all overrides all classes | ❌ F-01 | +| DRC unconnected | 0; 205/205 multi-pad nets routed (pack union-find agrees) | ✅ | +| `track_width` real vs benign | 63 hits on 6 real nets (A-02/A-07/B-08), 124 benign | ❌ copper (A-02, A-07, B-08) / ⚠ J-02 rules | +| Silk DRC items | 14 (11 overlap, 2 over copper, 1 edge) | ⚠ F-18 | +| Library footprint mismatch / issues | 82 revisions (benign), 4 MountingHole nickname | ⚠ J-05 | +| Ignored checks | 5 ignored; nothing real behind them | ✅ (J-05) | + +--- +## 3. §4-I Requirements traceability (R1–R5, ECO §0) + +**Wording note.** The ECO §0 table and the brief §4-I phrase two requirements differently: ECO R3 = "charge the battery from the 5 V source without brown-out loops" (brief R3 = "report while on battery"); ECO R5 = "EMC list of the second batch" (brief R5 = "charge at ≥ 1.3 A without thermal cycling"). The power auditor used the brief wording for R5, the other auditors and verify_2 the ECO wording. Both readings are traced below (R3 / R3′, R5 / R5′) so neither is lost. "As drawn" = v6 snapshot `ecee9fed…` / `6ddec80d…`. + +| Req. | Requirement | Status on v6 as drawn | IDs that close it | Residual risk after the fixes | +|---|---|---|---|---| +| **R1** | 10-min cycle on battery: everything off, wake, register the modem, report, off | **Needs changes + firmware.** Structure is right (independent `PWR_CTRL` PA1 / `MODEM_PWR_EN` PC10, STATUS PC9, U20 UVLO margin ≈ 1 V vs 0.1 V on V5.5). As drawn: boost at 91–97 % of its guaranteed 2.5 A during a GSM burst with all loads on; W5500 cannot be switched off; AMS1117 sets a 25–55 mW floor; U24 back-feeds the F9P whenever the modem is on and the F9P off; F9P ramp margin unspecified; VBAT bank ages out; R53 (boost set-point) unobtainable | A-05, E-01, E-02, A-01 (+0.30 V at U20), B-02, C-02, D-01, A-08, H-02; Minor D-03 (LSE wake), A-13 (PFO); firmware §8 (sequencing, LTE-only on battery) | GSM 2.8 A peaks exceed the backup limit → LTE-only on battery is mandatory (Leo: is 2G needed on battery?). Modem LTE average current is an assumption: run the ECO §I-1 battery cold start at VBAT 3.5 V with MAIN5V/VIN scope and a `/BAT_PLUS` current probe | +| **R2** | Modem never left dark: MCU can switch, reset and see the modem | **Satisfied by hardware; firmware only.** U20 EN on PC10 with R113 pull-down (full power removal, τ 0.46 s bleed), PWRKEY via Q20/PC8, RESET via Q21/PC11, STATUS via U24/PC9; the modem can be cycled alone | Firmware recovery ladder (§8); B-10 (STATUS pull-down) makes STATUS unambiguous; A-01 changes the U20 source, not the control | Every MCU reset power-cycles the modem (≈ 30 s re-registration, by design). A V5.6 binary on v6 leaves the modem uncontrolled (D-08; board-ID pin unresolved) | +| **R3** (brief) | Report while on battery | **Needs changes + firmware.** Budget fits with LTE-only (≈ 1.0–1.3 A on MAIN5V); GSM bursts at 2.2–2.4 A sit at the 2.5 A limit; link robustness limited by LTE ESD, ground vias, RF feed | A-05, E-01, B-02, B-03, F-12, F-06, C-04; A-13 (faster load shedding); firmware §8 | LTE-to-GNSS desense not measured: G3 bench (modem TX power vs F9P C/N0, before/after F-12/F-06) | +| **R3′** (ECO) | Charge from the 5 V source without brown-out loops (on v6 the source is U25, not the SD-15B) | **Fold-back impossible** (RS1 limit 2.14–2.41 A < U25 4.5 A minimum switch limit; the governor is a safety net) ✅, but U25 at 5.00 V nominal sits below `CHG_RAIL_ON` 5.05 V, so the charger never or randomly starts ❌ | A-04 (R121 57.6 k → 5.18–5.46 V), A-03 (charger no longer input-limited at 1.4 A); firmware `V5_PFI` 4.40 V + VREFINT | With A-01 the modem load moves onto MAIN5V: 0.44 V margin from U25 minimum minus a 1.6 A step droop to PFI max with 57.6 k (0.13 V as drawn) | +| **R4** | Temperature management at ~45 °C ports: sensors + fan + charger inhibit | **Needs changes.** No cell or charger-die temperature at the MCU (TMP102 deleted; pack NTC goes only to U6.17); fan block works (U2 out of rating, A-01); LTC4040 NTC pause at 42.4 °C unchanged (chemistry D1 pending) | F-51 (TMP102 0x48 + pack-NTC tap on PC5), F-52 (optional modem sensor), A-01 (fan from VEH5V), A-02 / F-12 (heat paths); firmware thermal inhibit | `tcell` exists only with VEH5V present; RNTB/JP2 waits for the chemistry decision; F-51 promotion to Blocker is Leo's call; no modem heatsink clamp holes (G-01) | +| **R5** (brief) | Charge at ≥ 1.3 A without thermal cycling | **Needs changes.** R50 825 Ω → 2.42 A (2.57 A corner > 2.5 A IC max); `/SW_BAT` 0.5 mm with 0.25/0.30 mm necks, 0 EP vias, L6 8.65 mm; U25 set-point below the governor start | A-03 (1.43 k → 1.316–1.483 A), A-02, A-04, A-07 | H0008 causality unproven (≈ 1.3 A inferred from the OCV slope); do the clamp-meter + IR checks and a thermal-camera run on U6/L6 at 1.4 A charge and 2.3 A backup | +| **R5′** (ECO) | EMC list of the second batch (ECO §E) | **Needs changes.** #1 `SW_BAT` pour ❌, #2 `BAT_PLUS` ❌, #3 fan FB divider at U2.4 ✅ (0.67/1.48 mm), #4 Cin loops < 3 mm ❌, #5 DFU ESD at J11 ✅ / J9 USBLC6 ❌, #6 crystals ≤ 5 mm ❌ (Y3 8.3/11.3, Y4 3.9/6.3, Y2 5.51/4.64 mm), Ethernet RX pair coupled ❌ (1.2 mm), empty 20 mm stitching cells ❌ (10; V5.5 had 8) | A-02 (#1, #2), F-03 (#4), G-02 (#5), D-02 / D-03 / E-06 / F-12 (#6) | Grades follow Leo's ECO marks (🔴 → Blocker, 🟠 → Major, 🟡 → Minor) except stitching, kept Major because v6 adds an LTE PA and a GNSS receiver (verify_2). Y2 (5.51 mm) has no finding | + +--- + +## 4. §4-D Pin map (condensed, 64/64 pins) + +Complete table (AF/ADC/EXTI, FT/TC, V5 macro vs v6, distances, draft `board_v6.h`): **`pinmap-v6.md`** (same folder). "Audit change" = pin-level effect of a finding if it is adopted; blank = no change. + +| Pin | Name | v6 net | Function on v6 | Proposed v6 macro | Audit change | +|---|---|---|---|---|---| +| 1 | VBAT | /3V3 | backup domain tied to 3V3 (no coin cell) | — | | +| 2 | PC13 | /LED_C13 | status LED, active LOW | `PIN_LED_C13` | | +| 3 | PC14 | /LSE_IN | 32.768 kHz LSE | `BOARD_LSE_HZ` | D-03: Y4 → C48615, C115 6.8 pF | +| 4 | PC15 | /LSE_OUT | LSE | — | D-03: C116 6.8 pF | +| 5 | PH0 | /HSE_IN | 25 MHz HSE (ROM DFU needs it) | `BOARD_HSE_HZ` | D-02: Y3 → C2901684, C113 12 pF | +| 6 | PH1 | /HSE_OUT | HSE | — | D-02: C114 12 pF | +| 7 | NRST | /NRST | MCU reset (SW1, P6, TP5, C104) | — | G-08: ESD at P6 | +| 8 | PC0 | /ETH_INT | W5500 INT, EXTI0 | `PIN_ETH_INT` | | +| 9 | PC1 | /GNSS_ANT_DETECT | F9P input, undriven | `PIN_GNSS_ANT_DET` (hi-Z) | C-01: stays undriven | +| 10 | PC2 | /GNSS_ANT_SHORT_N | F9P input | `PIN_GNSS_ANT_SHORT_N` | C-01: TPS2552 FAULT̅ → LOW = antenna short | +| 11 | PC3 | /GNSS_RTK_STAT | F9P RTK status, EXTI3 | `PIN_GNSS_RTK_STAT` | D-08: mis-flash hazard (V5.6 drives PC3) | +| 12 | VSSA | GND | analog ground | — | | +| 13 | VDDA | /VDDA | ADC reference (R104 10 Ω) | — | A-08/A-04: calibrate from VREFINT | +| 14 | PA0 | /BAT_SENSE | pack ÷ 2, ADC1_IN0 (TC) | `PIN_BAT_SENSE` | | +| 15 | PA1 | /PWR_CTRL | F9P rail enable (Q5 → Q1 → U21) | `PIN_GNSS_PWR` (+ alias `PIN_PWR_CTRL`) | D-09: 100 k base pull-down | +| 16 | PA2 | /GNSS_TX | USART2_TX → F9P RXD | `PIN_GNSS_TX` | hi-Z while F9P off | +| 17 | PA3 | /GNSS_RX | USART2_RX ← F9P TXD | `PIN_GNSS_RX` | | +| 18 | VSS | GND | ground | — | | +| 19 | VDD | /3V3 | supply | — | D-15: cap ≤ 2 mm | +| 20 | PA4 | /5V_SENSE | VEH5V ÷ 2, ADC1_IN4 | `PIN_5V_SENSE` | A-04: 5.32 V → 2.66 V | +| 21 | PA5 | /IGN_SENSE | ignition, ADC1_IN5 (read analog) | `PIN_IGN_SENSE` | F-02: Rig1 at P1.3 + SMBJ33A; D-05: Rigb1 2.2 k | +| 22 | PA6 | /FAN_PWM | fan low-side ON/OFF (TIM3_CH1) | `PIN_FAN` | A-01: fan supply = VEH5V | +| 23 | PA7 | /GNSS_TIMEPULSE | PPS, TIM3_CH2 / EXTI7 | `PIN_GNSS_PPS` | | +| 24 | PC4 | /NTC2 | probe 2, ADC1_IN14 | `PIN_NTC2` | | +| 25 | PC5 | NC (spare) | ADC1_IN15 | `PIN_NTC_CELL` | **F-51: pack-NTC tap** | +| 26 | PB0 | /EXT_LED | panel LED (P9) | `PIN_EXT_LED` | | +| 27 | PB1 | /NTC_TEMP | probe 1, ADC1_IN9 | `PIN_NTC` | | +| 28 | PB2 | /BOOT1_STRAP | BOOT1 = 0 (R99 10 k) | — (never reconfigure) | | +| 29 | PB10 | NC (spare) | EXTI10 | `PIN_PFO` | **A-13: PFO + 100 k pull-up** | +| 30 | VCAP1 | /VCAP1 | core regulator cap (C111) | — | | +| 31 | VSS | GND | ground | — | | +| 32 | VDD | /3V3 | supply | — | D-15 | +| 33 | PB12 | /ETH_CS | W5500 CS | `PIN_ETH_CS` | | +| 34 | PB13 | /ETH_SCK | SPI2 SCK (AF5) | `PIN_ETH_SCK` | | +| 35 | PB14 | /ETH_MISO | SPI2 MISO (AF5) | `PIN_ETH_MISO` | | +| 36 | PB15 | /ETH_MOSI | SPI2 MOSI (AF5) | `PIN_ETH_MOSI` | | +| 37 | PC6 | /USART6_TX | MCU → modem via K1 NO (Mode B), AF8 | `PIN_MODEM_TX` | J-04: delete NC flag | +| 38 | PC7 | /USART6_RX | modem → MCU via R106, AF8 | `PIN_MODEM_RX` | D-01 gate on U18.26; B-10: R106 1 k; J-04 | +| 39 | PC8 | /MODEM_PWRKEY | PWRKEY via Q20 (HIGH = pressed) | `PIN_MODEM_PWRKEY` | | +| 40 | PC9 | /MODEM_STATUS | STATUS via U24 | `PIN_MODEM_STATUS` | B-10: 100 k pull-down | +| 41 | PA8 | /CHRG_EN | charger disable (HIGH = off) | `PIN_CHRG_EN` | A-11: R56 → pull-up (default off) | +| 42 | PA9 | NC (spare) | USART1_TX (was RELAY TX on V5) | `PIN_DBG_TX` if a pad is added | D-12: TP9; only candidate left for D-08 | +| 43 | PA10 | /USART1_RX | F9P TXD2 tap, RX-only, no pull | `PIN_F9P_TX2_TAP` | D-01: Rdfu1 100 k | +| 44 | PA11 | /DFU_DM | USB FS D− (J11) | — | F-14: ESD in-line | +| 45 | PA12 | /DFU_DP | USB FS D+ (J11) | — | F-14 | +| 46 | PA13 | /SWDIO | SWD (TP3) | — | D-12 | +| 47 | VSS | GND | ground | — | | +| 48 | VDD | /3V3 | supply | — | | +| 49 | PA14 | /SWCLK | SWD (TP4) | — | D-12 | +| 50 | PA15 | /ETH_RST | W5500 reset (JTDI pull-up at reset) | `PIN_ETH_RST` | **E-02: 4.7 k (C23162) to GND** | +| 51 | PC10 | /MODEM_PWR_EN | U20 EN (R113 100 k PD) | `PIN_MODEM_PWR_EN` | A-01: U20 input source only | +| 52 | PC11 | /MODEM_RST | modem RESET via Q21 | `PIN_MODEM_RST` | | +| 53 | PC12 | /GNSS_RESET_N | F9P reset, open-drain only | `PIN_GNSS_RESET_N` | | +| 54 | PD2 | NC (spare) | EXTI2 | `PIN_ETH_PWR_EN` | **E-01: U12 EN + 100 k PD** (D-08 conflict) | +| 55 | PB3 | /CHRG_STAT | LOW = charging | `PIN_CHRG_STAT` | | +| 56 | PB4 | /CHRG_FAULT | LOW = fault / NTC pause | `PIN_CHRG_FAULT` | | +| 57 | PB5 | /BYP_CTRL | K1 Mode B (TC pin, output) | `PIN_BYP_CTRL` | | +| 58 | PB6 | /I2C_SCL | I2C1 SCL (AF4) | `PIN_I2C_SCL` | F-51: TMP102 at 0x48 | +| 59 | PB7 | /I2C_SDA | I2C1 SDA (AF4) | `PIN_I2C_SDA` | | +| 60 | BOOT0 | /BOOT0 | R98 10 k PD + SW2 | — | G-05: silk "BOOT0 (DFU)" | +| 61 | PB8 | /SER_IRQ | SC16IS752 IRQ, EXTI8 | `PIN_SER_IRQ` | | +| 62 | PB9 | /ACC_INT1 | SC7A20 INT1, EXTI9 | `PIN_ACC_INT1` | | +| 63 | VSS | GND | ground | — | | +| 64 | VDD | /3V3 | supply | — | D-15 | + +Count: 50 GPIO pads + 6 special (NRST, BOOT0, VBAT, VCAP1, VDDA, VSSA) + 4 VDD + 4 VSS = 64. Spares as drawn: PA9, PB10, PC5, PD2; after the adopted fixes only PA9 remains. + +--- +## 5. Ranked change list + +Ranking criterion within each severity: hardware-damage path first, then repeat of a paid-for lesson, then requirement R1–R5, then reliability/EMC, then process. Owner: **Sch** = schematic (Claude applies on the copy `hbox-watchdog-v6-audit.*`, Leo reviews); **Lay** = layout (Michelle); **FW** = firmware; **Leo** = decision or purchasing. Effort: S = schematic-only, L = layout, B = both, F = firmware-only. + +### Part 1 — Blockers (must change before ordering) + +| # | ID | Change | Owner | LCSC / numbers | Effort | Closes | +|---|---|---|---|---|---|---| +| 1 | A-01 | U20 fed from `/MAIN5V` only (delete D20 + 48 mm `/VIN_MODEM` run, D21 → copper); fan from `/VEH5V` (U2 block DNP, JP1 bridged); Q10/DzG1/Rrp1/C10/C11/C22 DNP; F2 → 3 A ahead of D10 | Sch + Lay | F2 **C206912** (4 A C206914 only for 9 V); JP1 bridged footprint | B | Damage path; R1/R3 (+0.30 V at U20); F1, F8 | +| 2 | F-02 | Rig1 ≤ 3 mm of copper from P1.3 (long run becomes `/IGN_SENSE`); SMBJ33A `/IGN_IN` → GND at P1.3; `/24V_IN` off In1 or ≥ 1.0 mm from LV | Sch + Lay | **C224019**; Rig1 C88614 moves | B | 23-Jul short lesson; damage | +| 3 | F-01 | Netclass table + corrected `.kicad_dru` (incl. HV24↔HV24); refill; DRC gate; fix the 15 outer spots (F-15) | Lay (rules drafted in §2 4-F) | floor 0.15 · HV24↔HV24 0.2 · HV24 outer 0.3 · HV24 inner 0.5 mm | L | 23-Jul short lesson | +| 4 | H-04 | Delete `LCSC Part` from U25 on the board and in `Drogheda-v6.pretty/SO-8_L4.9-…-EP.kicad_mod` | Sch | U25 stays **C524806** | S | Damage (40 V part behind 53 V clamp) | +| 5 | C-01 | TPS2552 current-limited antenna feed: ANT_OFF → EN̅ (100 k PD), FAULT̅ → ANT_SHORT_N (10 k to 3V3_GNSS), U18.7 NC | Sch + Lay | **C46506**, C25803, C25804 | B | Damage; field faults H0005/H0014 | +| 6 | B-03 | D28 → bidirectional 24 V ESD on an 0402 land, or DNP | Sch + Lay | **C1975527** | B | R3 (link); homologation | +| 7 | A-02 | U6 re-cluster: L6 ≤ 5 mm, C30/C31 ≤ 3 mm, C32–C34 ≤ 2 mm; `/SW_BAT` pour ≥ 2 mm; `/BAT_PLUS` ≥ 1.5 mm; EP ≥ 9 vias; In1/In2 solid ≥ 5 mm | Lay | 3 × 3 vias 0.3/0.6 mm at 0.9 × 1.2 mm | L | R5, R4, ECO §E #1 #2; F5 | +| 8 | A-03 | R50 825 Ω → 1.43 kΩ | Sch | **C22840** | S | R5, R3′; F4 | +| 9 | H-01 | U15 footprint → `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm` (sch + PCB), re-place C84–C88; fix the stale field in V5.x too | Sch + Lay | U15 stays **C15846** | B | Manufacturability | +| 10 | H-02 | U10 → SC16IS752; R53 → HKR 499 k | Sch | **C57156**, **C177479** | S | Order gate; R1 (R53 = boost set-point) | +| 11 | G-01 *(conditional)* | Restore MH4 at (193.2, 90.3); place MH11 + partner near U19; ≥ 4 mm copper-free radius | Leo (backplate) + Lay | coordinates | L | Enclosure fit; thermal gate T1 | + +### Part 2 — Majors (change before ordering unless Leo writes a reason) + +| # | ID | Change | Owner | LCSC / numbers | Effort | Closes | +|---|---|---|---|---|---|---| +| 1 | V1-01 | F2 electrically first: P1 → F2 → D10 ∥ Q23 (D10 moves to the F2 output) | Sch + Lay | F2 C206912 (A-01) | B | Damage on reversed P1 | +| 2 | D-01 | U27 74LVC1G125 on `/3V3_GNSS` between `/DOUT_4G` and U18.26 (+100 nF); Rdfu1 22 k → 100 k | Sch + Lay | **C12518**, C14663, C25803 | B | R1; 0.5.5/0.5.6 back-feed lesson | +| 3 | A-04 | R121 53.6 k → 57.6 k (5.18/5.32/5.46 V) | Sch | **C23082** | S | R3′, R5; F7 | +| 4 | B-02 | C130/C131 → polymer; R116 113 k, C141 6.8 nF, C142 56 pF; + 2 × 22 µF at L20.2; C131 ≤ 5 mm from U19 | Sch + Lay | **C881921** ×2, **C22862**, **C1542**, **C1572**, **C86817** ×2 | B | R1, R3; F1 | +| 5 | E-01 | `/ETH_PWR_EN`: U12.2 EN → PD2, 100 k to GND | Sch + Lay | C25803 | B | R1, R3; F8 | +| 6 | A-05 | CSYS + 2 × 47 µF 1210 at U6 VSYS pins 1/24 | Sch + Lay | **C5440143** ×2 | B | R1, R3; F1, F2 | +| 7 | F-51 | TMP102 between U6 and L6 (0x48); pack-NTC tap `/NTC` → PC5 (100 k / 120 k + 10 nF) | Sch + Lay | **C99269**, C14663, C25803, **C25808** (120 k), C1589 | B | R4; F5, F6 | +| 8 | F-12 | Ground vias: EP arrays (U25/U20 6, U12 6), U19 ≥ 30–40, U18 ≥ 24, U.FL 2 per pad, islands ≥ 2, edge fence ≤ 5 mm, board ≥ 400; pad-level solid on EPs/module GND | Lay | 0.3/0.6 mm vias; 0 empty 20 mm cells | L | R3, R4, ECO §E #6 | +| 9 | F-03 | Hot loops U25/U20/U12 (Cin ≤ 2 mm, one GND island, loop ≤ 1 cm², FB ≤ 3 mm); U20 + 2 × 22 µF + 220 µF | Lay + Sch | **C86817** ×2, **C881921** | B | ECO §E #4 | +| 10 | A-07 | `/VEH5V`, `/VIN_SW`, `/MAIN5V` ≥ 2 mm F.Cu or pour; Kelvin CLN/VIN sense at RS1; 1 oz inner or 1.65× width | Lay | ≥ 2 mm; ≥ 4 vias per transition | L | R5; prerequisite of A-01 | +| 11 | F-06 | Real stackup + impedance control; RF CPWG 0.30/0.20 on F.Cu over solid In1; LTE rerouted off In1; fence ≤ 3 mm; RF netclass; GNSS bias line ≥ 1 mm | Lay | JLC04161H-7628 | L | R3 (link, desense) | +| 12 | F-05 | Clear In1 under USB, crystals, switch nodes, VBAT/RF, SIM and the 3 broadside parallels; ≤ 3 In1 islands | Lay | no critical net over a void > 1 mm | L | ECO §E (return paths), Copper Plan | +| 13 | C-04 | Q1/Q5/R1/R2 into the GNSS island; `/SW_5V` ≤ 15 mm, 0 mm on In1 | Lay | — | L | R3 (desense) | +| 14 | G-02 | USBLC6-2SC6 at J9, ≤ 3 mm, flow-through | Sch + Lay | **C7519** | B | ECO §E #5; F8 | +| 15 | C-02 | U21 AP2112K → TPS7A2033P (soft-start 239–367 µs/V) | Sch | **C2862740** | S | R1 (52 000 starts/year) | +| 16 | A-08 | U17 AMS1117 → TLV1117LV33 (not C48937499) | Sch | **C15578** | S | R1 (sleep floor); F2 | +| 17 | E-02 | 4.7 k `/ETH_RST` → GND at U11.37 (Minor once E-01 is in) | Sch | **C23162** | S | R1; F8 | +| 18 | A-09 | C78 → polymer | Sch | **C881921** | S | Lifetime | +| 19 | H-02b | C103211 ×9 → C25803; pre-order U18, U19 (qty ≳ 100) and J14 | Sch + Leo | **C25803** | S | Order | + +### Part 3 — Minors (brief; can ride along or go to v6.1) + +| ID | Change | Owner | LCSC / numbers | Effort | +|---|---|---|---|---| +| A-10 | VEH5V over-voltage protection (LTC4040 OVP circuit or 5 V TVS crowbar) | Sch + Lay | no LCSC selected in the findings | B | +| A-11 | R56 re-netted to `/3V3` (charger OFF by default) | Sch + Lay | C25803 | B | +| A-13 | PFO → PB10 + 100 k pull-up (absorbs D-10) | Sch + Lay | C25803 | B | +| A-14 | R53/R54 ≤ 3 mm from U6.18/10, Q7 ≤ 5 mm, IGATE ≤ 8 mm on F.Cu (absorbs F-10) | Lay | — | L | +| B-08 | `/VBAT_MODEM` pour ≥ 3 mm into pins 55–57 | Lay | — | L | +| B-09 | R132–R134 → 22 Ω; 100 nF at J14.C1; SIM ESD next to J14 | Sch + Lay | C23345, C1525 | B | +| B-10 | 100 k `/MODEM_STATUS` → GND; 100 k `/DIN_4G` → 3V3; R106 → 1 k (absorbs D-14) | Sch | C25803 ×2, C14676 | S | +| C-07 | Test pads on U18.50 SAFEBOOT_N and U18.49 RESET_N | Sch + Lay | no part | B | +| D-02 | Y3 → 3225 CL 10 pF + 12 pF caps, ≤ 3 mm (absorbs F-11 Y3) | Sch + Lay | C2901684, C38523 (alt. C9006 + C1644) | B | +| D-03 | Y4 → FC-135 CL 7 pF + 6.8 pF caps, ≤ 3 mm | Sch + Lay | C48615, C1679 | B | +| D-05 | Rigb1 3.3 k → 2.2 k; firmware reads PA5 on the ADC | Sch + FW | C4190 | S/F | +| D-08 | Board-ID strap 10 k → GND (pin unresolved: PD2 taken by E-01) | Leo + Sch | C25804 | B | +| D-09 | 100 k `/BASE_LS` → GND (absorbs A-12) | Sch + Lay | C25803 | B | +| D-12 | TP9 on PA9; optional SWD footprint | Lay | no part | L | +| E-03 | Y1 → 3225 CL 12 pF, keep 18 pF, ≤ 3 mm (absorbs H-07, F-11 Y1) | Sch + Lay | C9006 (alt. C95/C96 → C1663) | B | +| E-04 | C91 → 10 nF, C90 → 4.7 µF, + 100 nF at AVDD pairs | Sch + Lay | C1589, C1779, C14663 | B | +| E-06 | Ethernet pairs coupled on F.Cu, 100 Ω diff | Lay | optional array: no LCSC | L | +| F-14 | J11 ESD in-line, D15 ≤ 3 mm, via ≤ 1 mm | Lay | — | L | +| F-17 | USB pairs F.Cu only, coupled, ≤ 1 via pair | Lay | — | L | +| F-18 | Silk refs ≥ 0.8/0.15 mm; DRU text rule; clear 14 silk items | Lay | — | L | +| F-52 | Modem temperature: `AT+CPMUTEMP` or TMP102 at 0x49 | FW or Sch + Lay | C99269 | F/B | +| G-03 | Sch footprints for P11/P12/J10 + DNP parity (absorbs E-05, H-06) | Sch + Leo | — | S | +| G-04 | JP_CUT solder jumper across P5 | Sch + Lay | no part | B | +| G-05 | Silk labels: delete "4G NTRIP RESET", RESET MCU, BOOT0 (DFU), JP2 CHEM, P1 legend, function names | Lay | — | L | +| G-08 | PESD5V0S1BA at P6.1, P7.1, P8.1 | Sch + Lay | C2827694 ×3 (opt. C22775) | B | +| H-03 | New `IND-SMD_MWSA0804S` footprint for L2/L6/L8/L20 | Lay (+ lib) | parts unchanged | B | +| H-08 | Value fields: C22, Y2 (3.6864 MHz), U10, C103, C130/C131/C78 (absorbs D-16) | Sch | — | S | +| J-02 | Residual: `/3V3_ETH` → Default; relax T15 on benign nets | Lay (rules) | — | L | +| J-03 | Retype `unspecified` pins in `Drogheda-v6.kicad_sym` | Sch (lib) | — | S | +| J-04 | Delete 27 NC flags + 3 wire stubs; re-link 10 missing symbols (absorbs B-11, D-11) | Sch | — | S | + +--- +## 6. Layout instruction list for Michelle + +Self-contained: every instruction carries its numbers; the finding ID is only for traceability. Work on the audit copy `hbox-watchdog-v6-audit.kicad_pcb` after the schematic changes of §7 have been synced (Update PCB **without** "replace footprints", see L-45). Units mm. Vias 0.3 mm drill / 0.6 mm pad unless stated. Coordinates are v6 board coordinates. Order: set rules and stackup first (L-1 … L-4), then the Blocker copper (L-5 … L-17), then Majors, then Minors, then the acceptance checks (L-48). + +**A. Board setup (before touching copper)** + +1\. **Stackup (F-06):** Board Setup → Physical Stackup = JLC04161H-7628: Cu 0.035 / prepreg 0.2104 (εr 4.4) / Cu 0.035 / core 1.065 (εr 4.6) / Cu 0.035 / prepreg 0.2104 (εr 4.4) / Cu 0.035; copper finish ENIG. Order note: impedance control; **1 oz inner copper** (or widen every inner power run 1.65×, L-19). + +2\. **Netclasses (F-01):** create/assign by exact net name (one pattern per line, leading `/`). HV24 (clearance 0.3, track 1.0, via 0.8/0.4): `/24V_IN` `/VIN_FUSED` `/VIN_PROT` `/24V` `/IGN_IN` `/Q10_GATE` `/Q23_GATE` `/SW_PWRIN` `/BOOT_PWRIN` `/SW_MODEM` `/BST_MODEM` (plus `/VIN_MODEM`, `/SW_FAN`, `/BST_FAN` only if A-01 is **not** adopted). PWR_HI (0.15 / 1.5 / 0.8/0.4): `/BAT_PLUS` `/SW_BAT` `/MAIN5V` `/VEH5V` `/SYS5V` `/VIN_SW`. PWR_MID (0.15 / 0.6 / 0.8/0.4): `/SW_5V` `/SW_IN` `/5V_FAN` `/FAN_RET`. PWR_MODEM (0.15 / 1.5 / 0.8/0.4): `/VBAT_MODEM`. RF (clearance = CPWG gap 0.20, width 0.30, no vias, excluded from autoroute): `/RF_GNSS` `/RF_ANT_GNSS` `/RF_LTE` `/RF_ANT_LTE`. Default (0.15 / 0.2 / 0.6/0.3): everything else, including `/3V3_ETH`. Delete all un-prefixed duplicate patterns and the dead `/3V3_MODEM`, `/SW3_NODE` patterns. + +3\. **Custom rules (F-01):** replace the rules "Minimum clearance 1", "HV24 clearance", "HV24 exception" with, in this order: floor 0.15 mm for non-HV24 non-RF pairs; HV24↔HV24 0.2 mm; HV24↔other 0.3 mm on outer layers; HV24↔other **0.5 mm on inner layers**; pad-to-pad 0.15 mm inside U2/U20/U25 footprints (exact text in §2 4-F, F-01). Set the text rule to min height 0.8 mm / min thickness 0.15 mm (F-18). Relax the T15 width warnings for the low-current nets (`/5V_FAN`, `/FAN_RET`, `/SW_FAN`, `/SW_5V`, `/SW_IN`, `/SYS5V`), keep ≥ 0.8 mm on `/VIN_PROT`/`/VIN_FUSED` (J-02). + +4\. **Check the rules resolve:** Inspect → Clearance Resolution on one `/24V`–GND-zone pair (expect 0.5 mm on In1) and one GND-zone–Default pair (expect 0.15 mm). After every GUI save of the project, re-check that the netclasses survived. + +**B. Vehicle input and 24 V (Blockers A-01, F-02, V1-01, F-01)** + +5\. **Fuse first (V1-01, A-01):** place F2 (now 3 A, C206912, same Nano2 holder) electrically first: P1.1 → F2 → then D10 (SMBJ33A) and Q23 in parallel on the F2 output. Nothing but F2 on the P1.1 copper. + +6\. **Remove the unfused branch (A-01):** Q10, DzG1, Rrp1, C10, C11, C22 and the U2 fan-buck block (U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21) become DNP: delete their `/24V`, `/SW_FAN`, `/BST_FAN` copper. JP1 becomes a bridged solder jumper (`SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`), so `/5V_FAN` = `/VEH5V`. + +7\. **Modem buck input (A-01):** delete D20 and the 48 mm `/VIN_MODEM` run from D20 (136.5, 113.8) to U20; remove D21 and join its two nets in copper (`/VIN_MODEM` becomes part of `/MAIN5V`). The `/MAIN5V` path from Q7/U6 to U20.2 is ≥ 1.5 mm wide all the way (A-05/A-07). + +8\. **Ignition (F-02):** move Rig1 (22 k, 0603) so that the copper from P1.3 to Rig1.1 is ≤ 3 mm, on F.Cu only. Add the new SMBJ33A (DO-214AA) from `/IGN_IN` to GND right at P1.3. The long run from Rig1.2 to the MCU is now `/IGN_SENSE` (Default class); keep Rig2, Rigb1, C9, D5 at the MCU. Remove the old In2 `/IGN_IN` run (106.5 mm) and the In1 via at (127.3, 50.5). + +9\. **`/24V_IN` off In1 (F-16):** reroute the 27 mm In1 run (167.5, 128.65) → (143.25, 121.75) to F.Cu along the south edge; if In1 must be used, keep ≥ 1.0 mm from every LV net with nothing crossing it. + +10\. **Outer-layer 24 V spots (F-15):** after refill + DRC (L-48), fix: `/VIN_PROT` 1.5 mm track vs `/VEH5V` 0.8 mm track at (176.24, 116.28) → **≥ 0.5 mm**, and tent the `/VEH5V` via there; `/USB_VBUS` away from Q23 (≥ 0.3 mm from `/Q23_GATE` and `/VIN_PROT`); remove the U20 GND neck (L-22); `/SW_PWRIN` and `/BST_MODEM` ≥ 0.3 mm from GND tracks. Tent every via except test vias. + +**C. LTC4040 charger/backup (Blocker A-02; A-07, A-14, F-51, A-05)** + +11\. **Re-cluster U6:** L6 pad 1 ≤ 5 mm (edge) from U6 pins 21/22; C30/C31 ≤ 3 mm from U6 pin 6; C32/C33/C34 and the two new 47 µF 1210 CSYS caps ≤ 2 mm from VSYS pins 1/24, GND pads on the EP copper; C35 (or the new 22 µF 0805) at L6.2 next to BAT pin 23. L6 may not sit on (193.2, 90.3) if MH4 is restored (L-40). + +12\. **`/SW_BAT`:** F.Cu polygon ≥ 2 mm wide from the combined pin 21+22 fan-out to L6.1, compact (switch node), no 0.25/0.30 mm necks beyond the pin fan-out. + +13\. **`/BAT_PLUS`:** P3 → L6.2 ≥ 1.5 mm F.Cu or pour; if any part runs inner, ≥ 4 vias per layer change and ≥ 1.5 × 1.65 = 2.5 mm on 0.5 oz inner copper. Take the BAT-pin sense (U6.23) as a Kelvin tap from L6.2/C35. + +14\. **`/MAIN5V`:** pour from U6 pins 1/24 over C32–C34 to the Q7 drain, ≥ 2 mm, no 0.3/0.5 mm necks. + +15\. **U6 EP:** 9 vias, 3 × 3 at 0.9 × 1.2 mm pitch, 0.3/0.6 mm, plugged/capped (JLC via-in-pad) or tented; pad `zone_connect` solid. + +16\. **Planes under U6:** In1 and In2 GND solid for ≥ 5 mm around U6 and L6: move the 7 `/VFB_BST` segments, `/IGATE`, `/CHRG_*` off In1 there. + +17\. **Temperature sensor (F-51):** place the new TMP102 (SOT-563) between U6 and L6, ≤ 5 mm from the U6 EP, 100 nF at its VDD, on I²C1. Route the pack-NTC tap: `/NTC` → 100 k → PC5 (U16 pad 25), with 120 k (C25808) and 10 nF (C1589) from the PC5 node to GND. + +18\. **BSTFB / IGATE (A-14):** R53/R54 ≤ 3 mm from U6 pins 18/10, top leg Kelvin-tapped at the CSYS pads, `/VFB_BST` on F.Cu; Q7 ≤ 5 mm from U6.15; `/IGATE` ≤ 8 mm on F.Cu, flanked by `/MAIN5V` copper. + +19\. **5 V path (A-07):** `/VEH5V` L22.2 → RS1.1 on F.Cu ≥ 2 mm (move L22/C153/C154 toward RS1), or ≥ 2 mm inner with ≥ 4 vias per transition; `/VIN_SW` RS1.2 → Q7 on F.Cu ≥ 2 mm, Q7 ≤ 5 mm from RS1/U6. Route U6.7 (CLN) and U6.6 (VIN) sense traces from the inner edges of the RS1 pads (Kelvin), not 1.66 mm down the trace as today. + +**D. Switchers (Major F-03)** + +20\. **Common rule for U25, U20, U12:** input caps (VIN and GND pads) ≤ 2 mm from the IC VIN and GND/EP pins; Cin GND, catch-diode anode and EP on **one solid F.Cu area**, no GND neck narrower than 1 mm; ≥ 2 vias ≤ 1 mm from each Cin GND pad; catch diode ≤ 3 mm from SW; inductor ≤ 5 mm from SW; SW copper ≤ 25 mm²; FB divider ≤ 3 mm from the FB pin; nothing on In1 under any SW copper. Acceptance: input loop area ≤ 1 cm² (U25 today ≈ 3.1 cm²). + +21\. **U25:** C149/C150 ≤ 2 mm from pins 2/7 on the EP/D34 copper (today C149/C150/C151 GND is on the U6 island); D34 cathode ≤ 2–3 mm from pin 8, anode on the Cin GND copper; L22 ≤ 5 mm from pin 8 (today 13.75 mm) with `/SW_PWRIN` ≤ 25 mm² (today 45.8 mm²) and not above In1 signal tracks; 4 GND vias around the Cin/D34 node within 2 mm; D34 GND pad solid. + +22\. **U20:** delete the 0.25 mm GND track between U20.1 and U20.2; C127/C128 GND pads face the EP, bonded by solid F.Cu; add the two new 22 µF 0805 caps ≤ 3 mm from U20.2 and the new 220 µF polymer (6.3 × 7.7) at U20.2; R110/R111 ≤ 2 mm from U20.5 on the side away from pin 8; VBAT sense by a dedicated trace from C131; delete the 5.6 mm In1 FB detour; keep `/VIN_MODEM` (now MAIN5V) ≥ 0.3 mm from the EN/RT/EP pads. + +23\. **U12:** C101 ≤ 2 mm from U12.7 (VIN; today 6.40 mm) with GND next to pin 5; D11 ≤ 2 mm from pin 1 with its anode on C101's GND copper (today 11.92 mm, different island); L8 ≤ 5 mm (today 15.10 mm); R87/R88 ≤ 3 mm from U12.4, R87 top fed by a Kelvin trace from C102/C94; `/ETH_FB` ≤ 5 mm on F.Cu with nothing under `/ETH_SW`; replace the 0.2 mm GND ties with pour. + +**E. Grounding and stitching (Major F-12)** + +24\. **EP via arrays:** U25 and U20 (EP 3.2 × 2.5): 2 × 3 = 6 vias at 1.0 mm pitch, or 2 × 4 = 8 at 0.8 mm with 0.3/0.5 vias (3 × 3 at 1.0 mm does not fit the 2.5 mm side); U12 (EP 2.29 × 3.0): 2 × 3; U6: see L-15. + +25\. **Pad connection:** set `zone_connect` solid **per pad** on: all EPs, all U18 and U19 GND pads, D34/D11 anodes, buck Cin/Cout GND pads. Leave the zone default thermal relief (≥ 2 spokes) for small passives (do **not** set the zones to "thermal reliefs for PTH only": that makes 23 × 0402 and 142 × 0603 GND pads solid and risks tombstoning). + +26\. **U19 A7670SA:** one tented via in each 1.7 mm gap between adjacent 2.1 mm centre GND pads (0.55 mm clearance per side) plus a via ring on the perimeter GND pads: **≥ 30, target 40**, never inside a pad. + +27\. **U18 ZED-F9P:** vias at the diagonal interstitial centres of the 2.1 mm GND pad grid (0.41 mm to pad corners): **≥ 24**; no microvias needed. Under U18/U19 use tented or JLC "epoxy filled & capped" vias. + +28\. **U.FL and ESD grounds:** 2 GND vias ≤ 1 mm from each GND pad of J12 and J13, and at D28. + +29\. **Stitching:** every F.Cu GND island ≥ 20 mm² gets ≥ 2 vias; no F.Cu GND pour point > 5 mm from a GND via (today median 10.4 mm, max 29.5 mm in the east pour); edge fence at ≤ 5 mm pitch within 1.5 mm of the 0.5 mm edge clearance (≈ 96 vias); **board total ≥ 400 GND vias** (today 69). Acceptance: 0 empty 20 × 20 mm cells (today 10 of 35). + +**F. RF, GNSS supply and planes (Majors F-06, C-04, F-05; Blocker B-03)** + +30\. **RF lines (F-06):** both RF runs on F.Cu only, CPWG over solid In1, start at **w 0.30 / gap 0.20 mm**, finalise with JLC's impedance calculator for 50 Ω on JLC04161H-7628. + +31\. **LTE (F-06, B-03):** reroute U19.60 → R118/C146/C147 → D28 → J13 entirely on F.Cu (rotate J13 or move it toward U19's RF pad side); remove the 22 mm In1 section and its two vias at (174.25, 58.25) and (194.27, 53.72). Nothing on any layer above or below the line; `/VBAT_MODEM` ≥ 3 mm away. Replace D28's SOD-923 land with an **0402** land in the same in-line spot (new part PESD0402-240, or leave DNP). + +32\. **Fences (F-06):** GND vias on both sides of RF_LTE/RF_ANT_LTE and RF_GNSS/RF_ANT_GNSS at **≤ 3 mm pitch**, ≤ 1 mm from the gap edge. + +33\. **GNSS bias (F-06, C-01):** place the new TPS2552 (SOT-23-6) near L21/J12; its output net `/ANT_BIAS` (was `/VCC_RF_GNSS`) runs ≥ 1 mm from the RF line with a stitched GND strip between (or on In2 after 100 pF + 100 nF decoupling); L21 taps the RF line stub-free at J12; move D27 onto the J12 pad (no stub). + +34\. **GNSS supply switch (C-04):** move Q1, Q5, R1, R2 (F1 optional) into the GNSS island next to U21/C3/C40/C119; bring `/SYS5V` (or `/SW_IN`) to them; `/PWR_CTRL` becomes the long signal; `/SW_5V` ≤ 15 mm and 0 mm on In1 (today 181 mm on In1). + +35\. **In1 plane (F-05):** at minimum clear In1 under: the USB pairs (J9 and J11), every crystal and its lines, all switch nodes, `/VBAT_MODEM` and the RF area, the SIM lines, and the three broadside parallels (I2C_SDA over `/SER_TXB` 14.2 mm, ETH_XO over `/ETH_RST` 6.95 mm, NRST over `/USART6_RX` 7.2 mm). Move In1 tracks to In2/B.Cu (or F.Cu where short), priority `/SW_5V`, `/MAIN5V`, `/KCOIL`, `/USART6_TX/RX`, `/DOUT_4G`, `/CHRG_*`, `/SER_TXB/RXB`, `/ETH_*`, `/VFB_BST`, `/IGATE`. Acceptance: ≤ 3 In1 islands, no critical net over a void longer than 1 mm. + +**G. Modem power (Major B-02, Minor B-08)** + +36\. **VBAT_MODEM:** F.Cu pour ≥ 3 mm from L20.2 → C130 → C131 → C132–C136 → U19 pins 55/56/57 (fan out to all three pads; no 0.5 mm neck); C131 (now polymer) ≤ 5 mm from the pads; the two new 22 µF 0805 caps ≤ 3 mm from L20.2. + +**H. New parts and footprint swaps** + +37\. **Footprint swaps:** U15 → `SOIC-16_3.9x9.9mm_P1.27mm` (narrow; re-place C84–C88 hard against it) (H-01); D28 → 0402 (L-31); Y1 and Y3 → 3225-4P crystal footprint (E-03, D-02); L2/L6/L8/L20 → new `IND-SMD_MWSA0804S` land (pads 2.75 × 4.0 mm, 5.5 mm inner gap, courtyard 9.4 × 9.8 mm, confirm against the Sunlord drawing) and re-check neighbours for the 0.4 mm body growth (H-03). U17 and U21 keep their footprints (drop-ins). + +38\. **New parts to place:** U27 74LVC1G125 (SOT-753) + 100 nF at U18.26, powered from `/3V3_GNSS` (D-01); USBLC6-2SC6 at J9 (L-41); 4.7 k at U11.37 (E-02); 100 k at U12.2 (E-01, new net `/ETH_PWR_EN` to U16 pad 54); 100 k at Q5 base (D-09); 100 k pull-up on `/PFO` routed U6.20 → PB10 (A-13); 100 k `/MODEM_STATUS` → GND and 100 k `/DIN_4G` → 3V3 (B-10); 100 nF 0402 at J14.C1 and D23–D25 moved next to J14 (B-09); PESD5V0S1BA at P6.1, P7.1, P8.1, each ≤ 3 mm from its connector (G-08); R56 re-netted to `/3V3` (A-11); JP_CUT open solder jumper across P5 `/MAIN5V`–`/SYS5V`, silk "CUTOFF BYPASS" (G-04); TP9 1.5 mm pad on PA9 next to TP3–TP5 (D-12); 1 mm test pads on U18.50 and U18.49 next to a GND pad (C-07). + +39\. **Crystals (E-03, D-02, D-03):** Y1 ≤ 3 mm from U11.30/31, Y3 ≤ 3 mm from U16 PH0/PH1, Y4 ≤ 3 mm from PC14/PC15; load caps adjacent to the crystal, 2 GND vias, no inner-layer track under any crystal or its lines (Y3 today has In1 `/USART6_RX` under both HSE lines and `/BAT_PLUS` on all 4 layers beside it). + +**I. Mechanics, connectors, silkscreen** + +40\. **Mounting holes (G-01, after Leo's answer):** if the V5.5 backplate is reused, restore MH4 (Ø3.2 NPTH) at **(193.2, 90.3)** and add the modem heatsink-clamp pair near U19 (V5.5 MH11 was at (168.3, 84.6), now 0.6 mm from the U19 courtyard, so its position must be re-chosen). Keep a ≥ 4.0 mm copper-free radius on F.Cu/B.Cu around every mounting hole (move the `/3V3` track at MH6 out by ≥ 0.5 mm) or specify nylon washers. + +41\. **J9 ESD (G-02):** USBLC6-2SC6 ≤ 3 mm of copper from the J9 pads, D± routed through its pads (pins 1/6 `/USB_DM`, 3/4 `/USB_DP`, 5 `/USB_VBUS`, 2 GND), GND via ≤ 1 mm. + +42\. **J11 ESD (F-14):** route DFU D+/D− through the D14/D15 pads (no T-stubs); D15 ≤ 3 mm of copper from J11 (today 10.9 mm); each ESD GND pad with its own via ≤ 1 mm. + +43\. **USB pairs (F-17):** J9 and J11 pairs on F.Cu only over solid In1, coupled (≈ 0.2/0.15 mm for 90 Ω on JLC7628, confirm in the calculator), ≤ 1 via pair, no slot crossings. + +44\. **Ethernet (E-04, E-06):** C90/C91 ≤ 2 mm from U11.20/22; 100 nF at the AVDD 4/8 and 11/21 pairs; each TX/RX pair coupled on F.Cu only (100 Ω diff), ≤ 1 via pair; J10.8 per the HR911105A drawing. + +45\. **Library hygiene (J-05):** do **not** run "Update footprints from library" (it would swap P11/P12 and reset pads); when syncing from the schematic, do not tick "replace footprints". + +46\. **Silkscreen (F-18, G-05):** all reference texts ≥ 0.8 mm height / 0.15 mm stroke (1.0/0.15 where space allows); delete "4G NTRIP RESET" at (187.0, 124.1); SW1 "RESET MCU", SW2 "BOOT0 (DFU)"; JP2 "CHEM 1-2 Li-ion / 2-3 LFP"; P1 pin legend "VIN 9-36V · GND · IGN · GND · NC"; a function name at every connector (FAN, RESET, NTC1, NTC2, LED, BATT, CUTOFF, 5V BENCH); P2 "bench only, no reverse protection" (A-20c); clear the 14 DRC silk items; check the D27/D28/Q10 polarity marks in the 3D view. + +47\. **Small cleanups:** extend the `/SW_5V` track end at (86.35, 121.88) 0.3 mm to the U21.3 pad centre (F-21); VDD decoupling caps ≤ 2 mm from their pins where convenient (D-15); Cu4 ≤ 2 mm from U18.36 (C-09). + +**J. Acceptance before generating fab files** + +48\. Refill all zones → DRC with the new rules: **0 clearance errors** (the 6 inner and 15 outer spots of F-01/F-02 must be gone), `track_width` warnings only on nets deliberately left at T15, 0 unconnected; then check: GND vias ≥ 400 and 0 empty 20 mm cells; every GND pad of U19/U18/U20/U25/J12/J13 in an F.Cu cluster with ≥ 1 plane via ≤ 2 mm; each buck input loop ≤ 1 cm²; ≤ 3 In1 islands; RF lines at the calculator's 50 Ω geometry with fences ≤ 3 mm; U6 EP 9 vias; `/SW_BAT` ≥ 2 mm; no HV24 net on an inner layer within 0.5 mm of LV copper. Generate BOM/CPL only after H-04's field deletion (or from the schematic with kicad-cli). + +--- +## 7. Schematic change list (for the "apply" phase, brief §7) + +To be applied only if Leo says "apply", on a copy `hbox-watchdog-v6-audit.*` following the V5.6 method: copy → backup per step under `kicad/_to_delete/v6-audit-/` → KiCad MCP edits by ref/UUID (UUIDs preserved) → ERC → netlist diff = only the intended pins → PDF → change report. "From" values are the current v6 fields (`evidence/components.csv`). New parts have no refdes yet except U27, JP_CUT and TP9 (named in the findings). + +### 7.1 Blockers + +| Finding | Ref | From | To | LCSC | Note | +|---|---|---|---|---|---| +| A-01 | D20 | SS34 (C8678), `/24V` → `/VIN_MODEM` | **remove** | — | delete the `/24V`→`/VIN_MODEM` path | +| A-01 | D21 | PMEG3050EP (C50603) | **remove; merge `/VIN_MODEM` into `/MAIN5V`** | — | U20.2, C127, C128 now on `/MAIN5V` | +| A-01 | U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21 | fan buck (U2 MP1584EN C15051 …) | **DNP** | — | fan now from `/VEH5V` | +| A-01 | JP1 | `SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm` | `Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm` | no part | `/5V_FAN` = `/VEH5V` | +| A-01 | Q10, DzG1, Rrp1, C10, C11, C22 | IRFR5305 (C2624), BZX84C15, 10 k, 47 µF/50 V, 100 nF, "22uF/50V" | **DNP** | — | `/24V` left without loads | +| A-01 + V1-01 | F2 | 2A/125V Nano2 (C206910) | **0154003.DR 3 A**, same holder; topology P1.1 → F2 → {D10, Q23} | **C206912** | 4 A C206914 only for sustained 9 V operation | +| V1-01 | D10 | SMBJ33A on `/24V_IN` (ahead of F2) | SMBJ33A on the F2 output (`/VIN_FUSED`) | C224019 (unchanged) | reversed P1 now blows F2 | +| A-03 | R50 | 825R/1% (C50214) | **1.43 kΩ 1 % 0603** | **C22840** | 1.316–1.483 A | +| B-03 | D28 | ESD9L5.0ST5G (C82326), SOD-923 | **PESD0402-240, 0402** (or DNP) | **C1975527** | bidirectional 24 V | +| C-01 | new U (antenna switch) | — | **TPS2552DBVR**: 1 IN = `/3V3_GNSS`, 2 GND, 3 EN̅ = U18.5 ANT_OFF, 4 FAULT̅ = `/GNSS_ANT_SHORT_N`, 5 ILIM = IN, 6 OUT = new `/ANT_BIAS` | **C46506** | 75 mA limit | +| C-01 | new R | — | 100 k, EN̅ → GND | C25803 | antenna ON by default | +| C-01 | new R | — | 10 k, `/GNSS_ANT_SHORT_N` → `/3V3_GNSS` | C25804 | FAULT̅ pull-up | +| C-01 | L21, C144, C145 / U18.7 | on `/VCC_RF_GNSS` with U18.7 | on `/ANT_BIAS`; **U18.7 VCC_RF → NC** | unchanged | | +| F-02 | new D (IGN TVS) | — | **SMBJ33A**, `/IGN_IN` → GND at P1.3 | **C224019** | optional BAT54S C19726 at the MCU | +| F-02 | Rig1 | 22 k 0603 (C88614) | unchanged value; placed at P1.3 (layout) | C88614 | net split: `/IGN_IN` = {P1.3, Rig1.1, TVS} | +| H-01 | U15 | footprint `Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm` | **`Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`** | C15846 (unchanged) | also fix the stale field in the V5.x schematics | +| H-02 | U10 | SC16IS762IPW (C729142) | **SC16IS752IPW,128** | **C57156** | I²C mode, drop-in | +| H-02 | R53 | 499k/1% (C131054) | **499 k 1 % 0603 HKR RCT03499KFLF** | **C177479** | drop-in | +| H-04 | U25 | fields `LCSC` = C524806 **and** `LCSC Part` = C2071691 | **delete `LCSC Part`** (board, schematic and `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod`) | C524806 | or strip `LCSC Part` from all 10 library footprints | +| G-01 | MH4 (+ heatsink pair) | absent | board-only mounting holes (layout) | — | only if the V5.5 backplate is reused | +| F-01 | project | netclass patterns and `.kicad_dru` | per §2 4-F (F-01) | — | project settings, not schematic symbols | + +### 7.2 Majors + +| Finding | Ref | From | To | LCSC | Note | +|---|---|---|---|---|---| +| A-04 | R121 | 53.6k/1% (C23074) | **57.6 kΩ 1 % 0603** | **C23082** | 5.18/5.32/5.46 V | +| A-05 | new C ×2 | — | **47 µF 16 V X7R 1210** on `/MAIN5V` at U6 pins 1/24 | **C5440143** | same part as C32/C33 | +| A-08 | U17 | AMS1117-3.3 (C6186) | **TLV1117LV33DCYR** (same SOT-223 pinout) | **C15578** | not C48937499 | +| A-09 | C78 | 220uF/10V MVG (C2827940) | **220 µF 16 V polymer** | **C881921** | same 6.3 × 7.7 land | +| B-02 | C130, C131 | 220uF/10V MVG (C2827940) | **220 µF 16 V polymer** | **C881921** ×2 | change together with R116/C141/C142 | +| B-02 | R116 | 14k (C22803) | **113 kΩ 1 % 0603** | **C22862** | | +| B-02 | C141 | 3.3 nF 0402 (C1536) | **6.8 nF X7R 0402** | **C1542** | | +| B-02 | C142 | 47 pF 0402 (C1567) | **56 pF C0G 0402** | **C1572** | | +| B-02 | new C ×2 | — | **22 µF 0805** on `/VBAT_MODEM` at L20.2 | **C86817** | | +| F-03 | new C ×2 | — | **22 µF 16 V 0805** at U20.2 (`/MAIN5V`) | **C86817** | 16 V valid only with A-01 | +| F-03 | new C | — | **220 µF 16 V polymer** at U20.2 | **C881921** | | +| F-51 | new U (TMP102) | — | **TMP102AIDRLR**, I²C1, ADD0 → GND (0x48), 100 nF at VDD | **C99269**, C14663 | placed between U6 and L6 | +| F-51 | new R/R/C | — | `/NTC` → 100 k → new net → PC5 (U16 pad 25); 120 k and 10 nF from that net to GND | C25803; **C25808** (120 k); C1589 | remove PC5 NC flag | +| C-02 | U21 | AP2112K-3.3 (C51118) | **TPS7A2033PDBVR** (same SOT-23-5 pinout) | **C2862740** | soft-start 239–367 µs/V | +| E-01 | U12.2 EN | tied to `/SYS5V` | new net **`/ETH_PWR_EN`** → U16 pad 54 (PD2); new 100 k to GND | C25803 | remove PD2 NC flag | +| E-02 | new R | — | **4.7 kΩ 0603**, `/ETH_RST` → GND at U11.37 | **C23162** | tell V5.6: R112 100 k → 4.7 k | +| D-01 | U27 (new) | — | **74LVC1G125GV,125**: 1 OE̅ = GND, 2 A = `/DOUT_4G`, 3 GND, 4 Y = new `/DOUT_4G_F9P` → U18.26, 5 VCC = `/3V3_GNSS`; 100 nF at VCC | **C12518**, C14663 | U18.26 leaves `/DOUT_4G` | +| D-01 | Rdfu1 | 22k (C88614) | **100 kΩ** | **C25803** | | +| G-02 | new U (J9 ESD) | — | **USBLC6-2SC6**: 1/6 `/USB_DM`, 3/4 `/USB_DP`, 5 `/USB_VBUS`, 2 GND | **C7519** | | +| H-02b | R56, R57, R58, R85, R87, Rgs1 (+ R20, Ren1, Rfreq1 if U2 stays) | 100k 5 % (C103211) | **100 kΩ 1 %** | **C25803** | stock 702 limits the order to 78 boards | +| V1-01, F-12, F-05, F-06, C-04, A-07 | — | layout-only | — | — | see §6 | + +### 7.3 Minors + +| Finding | Ref | From | To | LCSC | +|---|---|---|---|---| +| A-11 | R56 | 100 k to GND | 100 k to `/3V3` (default charge OFF) | C25803 | +| A-13 | new R + net | `/PFO_TP` = {U6.20, TP2} | `/PFO` → U16 pad 29 (PB10) + 100 k to `/3V3`; remove PB10 NC flag | C25803 | +| B-09 | R132, R133, R134 | 0R (C304185) | **22 Ω 0603** | C23345 | +| B-09 | new C | — | 100 nF 0402 at J14.C1 (`/SIM_VDD`) | C1525 | +| B-10 | new R ×2 | — | 100 k `/MODEM_STATUS` → GND; 100 k `/DIN_4G` → `/3V3` | C25803 ×2 | +| B-10 | R106 | 100R (C22775) | **1 kΩ** | C14676 | +| C-07 | new TP ×2 | — | test pads on U18.50 SAFEBOOT_N, U18.49 RESET_N | no part | +| D-02 | Y3 | 25 MHz HC-49SD (C14872) | **25 MHz 3225-4P CL 10 pF**, footprint `Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm` | C2901684 (alt. C9006) | +| D-02 | C113, C114 | 15 pF (C1644) | **12 pF C0G** (keep 15 pF C1644 if C9006) | C38523 | +| D-03 | Y4 | 32.768 kHz FC-135 CL 12.5 pF (C32346) | **FC-135 CL 7 pF** | C48615 | +| D-03 | C115, C116 | 12 pF (C38523) | **6.8 pF C0G** | C1679 | +| D-05 | Rigb1 | 3.3k (C22978) | **2.2 kΩ** | C4190 | +| D-08 | new R | — | 10 k strap → GND on the board-ID pin (**pin unresolved**, see §10) | C25804 | +| D-09 | new R | — | 100 k `/BASE_LS` → GND | C25803 | +| D-12 | TP9 (new) | PA9 NC flag | test pad on PA9 (remove NC flag) | no part | +| E-03 | Y1 | 25 MHz HC-49SD (C14872) | **25 MHz 3225 CL 12 pF**; keep C95/C96 18 pF (C1647) | C9006 (alt.: keep Y1, C95/C96 → 33 pF C1663) | +| E-04 | C91 | 4.7 µF (C1779) | **10 nF 0603 X7R** | C1589 | +| E-04 | C90 | 10 µF (C440198) | **4.7 µF 0805** | C1779 | +| E-04 | new C ×2 | — | 100 nF at W5500 AVDD 4/8 and 11/21 | C14663 ×2 | +| F-52 (option) | new U | — | TMP102 at 0x49 (ADD0 → 3V3) between U19 and U20 | C99269 | +| G-03 | P11, P12 | fp `…MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical` | `Connector_Phoenix_MC:PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal`; DNP per Leo | C5160226 | +| G-03 | J10 | fp nickname `Connector_RJ45:…` | `Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal`; DNP per Leo | C12074 | +| G-04 | JP_CUT (new) | — | `Jumper:SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm` across P5 (`/MAIN5V`–`/SYS5V`) | no part | +| G-08 | new D ×3 | — | PESD5V0S1BA at P6.1, P7.1, P8.1 → GND (opt. 100 Ω series on NRST, C22775) | C2827694 ×3 | +| H-03 | L2, L6, L8, L20 | fp `Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm` | new `Drogheda-v6:IND-SMD_MWSA0804S` | parts unchanged | +| H-08 | C22, Y2 | value text "22uF/50V", "1.8432MHz" | "10uF/50V" (unless 22 µF was intended), "3.6864MHz"; C103/C130/C131/C78 texts are harmless or replaced by B-02/A-09 | — | +| J-03 | library | `unspecified` pin types in `Drogheda-v6.kicad_sym` | power_in / power_out / input / output / passive | — | +| J-04 | 23 orphan NC flags, NC flags on U16.37/38 and U10.13/14, wire stubs uuid 2b755f7f…, 46f71e27…, 7c1dbfc0… | present | delete; copy the 10 missing symbols into `Drogheda-sym` and re-link | — | +| B-15 (Note) | R107, R108 | DNP 0 Ω bypass | delete or mark "never fit" | — | + +**Expected netlist diff** (acceptance for the apply phase): only the nets and pins named in §7.1–7.3 change; no UUID changes on untouched symbols; ERC shows no new errors, and the J-04 items disappear. + +--- +## 8. Firmware requirements (`board_v6.h`, FW 0.7.x) + +Sources: firmware sections of the four findings files and `pinmap-v6.md` §5 (draft header). Items tagged *(if fix)* apply only when the named hardware change is adopted. + +**8.1 Build and identity** + +1\. New `board_v6.h` from `pinmap-v6.md` §5. A binary must never cross between V5.6 and v6: a V5.6 build drives PC3 (RTK_STAT, an F9P push-pull output on v6) and PC1/PC2 (F9P inputs). File names carry the board (`drogheda-firmware-por-tarjeta`). *(if D-08)* read the board-ID strap with INPUT_PULLUP at boot; mismatch → outputs off, print `BOARD MISMATCH`. + +2\. `$PHID,<96-bit UID>,,,,` on the **modem uplink** at every connect and every 5 min, not only on Ethernet (C-08). Backend `retranslator` must map UID → H-number before v6 ships. + +3\. `$PHLG` stays append-only; new fields at the end: `tchg`, `tcell` (F-51), `tmodem` (F-52 / AT), `tntc2`, `rtcm_bps`, `modem_status`, `vign` (D-05), `iin` only if CLPROG ever gets a pin. + +**8.2 Boot defaults** + +4\. First lines of `setup()`, before any delay or USB init, drive LOW: PC10 `MODEM_PWR_EN`, PC8 `PWRKEY`, PC11 `MODEM_RST`, PA1 `GNSS_PWR`, PB5 `BYP_CTRL`, **PA15 `ETH_RST`** (JTDI pull-up at reset), PA6 fan, PB0 panel LED; *(if E-01)* PD2 `ETH_PWR_EN`. PA8 `CHRG_EN` belongs to the governor (HIGH = charge off until it decides). + +5\. Keep hi-Z/analog: PA9, and PB10/PC5/PD2 unless their fixes are adopted; PC1/PC2 (F9P inputs; PC2 becomes a real antenna-short input *(if C-01)*, no MCU pull); PC12 open-drain only, never push-HIGH. + +6\. F9P back-feed rule (0.5.5/0.5.6 lesson): while PA1 is LOW keep PA2 INPUT no-pull, PA10 no pull (its internal pull-up is 7–14 kΩ), PC7 no pull-up, PC12 released, PA7/PC3 no pull-up. **Never hold PC10 HIGH with PA1 LOW** and never run F9P-only power cycles with the modem up, until the D-01 gate (U27) is fitted. + +**8.3 Pins and peripherals** + +7\. Modem: USART6 PC6 TX (via K1 NO, Mode B) / PC7 RX (always connected, AT replies + RTCM3 byte counter), 115 200 Bd. PC8 PWRKEY (HIGH = pressed via Q20), PC11 RESET (HIGH = asserted via Q21), PC9 STATUS (INPUT_PULLDOWN, poll it), PC10 buck enable. + +8\. GNSS: USART2 PA2/PA3 = F9P UART1 (`GNSS = Serial2`); USART1 **RX-only** on PA10 (F9P TXD2 tap, no pull; remove the V5 `RELAY(PA10, PA9)` TX); PA7 PPS on TIM3_CH2 capture or EXTI7; PC3 RTK_STAT (poll ≥ 10 Hz, or EXTI3 if blink timing is wanted, then poll PB3); PC12 RESET_N open-drain (prefer UBX-CFG-RST). + +9\. EXTI9 → PB9 (SC7A20 INT1 at 0x18, LIS3DH-compatible registers, motion wake); poll PC9 and PB3 (D-13). Fan stays GPIO ON/OFF so TIM3 is free for PPS. + +10\. ADC: IN0 BAT_SENSE, IN4 5V_SENSE, IN5 IGN_SENSE (**read analog**; as-drawn ratio thresholds ON > 0.60 V ≈ 5.2 V, OFF < 0.35 V, no internal pull; ratio 0.0833 *(if D-05)*), IN9 NTC, IN14 NTC2, *(if F-51)* IN15 pack NTC on PC5 (ratio 120/220; Rntc = R55·Vntc/(VEH5V − Vntc) with VEH5V from PA4; valid only with VEH5V present). + +11\. Delete: TMP102 at 0x48/0x49 as the V5 cell sensor and the PCF8574 P7 modem-reset bodge (`PCF_MODEM_RST_BIT`, `ENABLE_MODEM_RST`); *(if F-51)* re-add a TMP102 at 0x48 as the **charger** sensor (`tchg`); *(if F-52)* 0x49 near the modem. + +12\. `BOARD_SER_XTAL_HZ 3686400UL` (Y2 is the 3.6864 MHz part despite the "1.8432MHz" text); U10 SC16IS762 → SC16IS752 is register-compatible (H-02). If H-01 were not fixed, report `rs232=absent`. + +13\. *(if A-13)* PB10 EXTI10 falling = PFO (backup entry at VEH5V < 4.40 V). *(if E-01)* PD2 `ETH_PWR_EN`. + +**8.4 Power constants and ADC** + +14\. `V5_PFI` 4.60 → **4.40 V** (falling; rising 4.51 V). With R121 = 57.6 k keep `CHG_RAIL_ON 5.05` / `CHG_RAIL_OFF 4.90`; if R121 stayed 53.6 k the governor could not be retuned safely (ON ≤ 4.80 V is not possible with PFI rising max 4.66 V and ADC error), so the hardware change is preferred (A-04). The v6 supply cannot fold (RS1 2.14–2.41 A < U25 4.5 A minimum limit): the governor is a safety net. + +15\. Compute VDDA every window from VREFINT (`VREFINT_CAL` at 0x1FFF7A2A); never assume 3.30 V, especially on battery (A-08). + +16\. Charger status decode (LTC4040 DS table p.14, per the power auditor): "pausa NTC" = CHRG low ∧ FAULT low; bad battery = CHRG high ∧ FAULT low. (The pin-map note on PB4 words it differently; the datasheet-cited decode governs.) + +17\. BSTOFF is hard-wired to GND, so firmware cannot switch the boost off: at `VBAT_BACKUP_MIN` go to STOP with every load off; the hardware floor is the LTC4040 BAT UVLO (2.45 V) plus the pack PCM. + +**8.5 Thermal** + +18\. `CHG_CELL_HOT/COOL` on `tcell` (Li-ion 45/40 °C; LFP 55–60 °C) *(if F-51)*; shed charge on `tchg` > 85 °C; include the NTC in `thermalCtlTemp()` (`drogheda-fan-policy`). Fan policy `vehiclePower && ignitionOn` unchanged; with A-01 the fan supply exists exactly when `vehiclePower`. + +19\. Modem temperature via `AT+CPMUTEMP` (confirm on the A7670SA firmware) when no TMP102 is fitted. + +**8.6 Backup entry and duty window (R1/R3)** + +20\. On backup entry (PFO EXTI or 5V_SENSE < `V5_OFF`): `ETH_PWR_EN` = 0 (or hold ETH_RST low), `BYP_CTRL` = 0 except inside the TX window, modem to **LTE-only** (`AT+CNMP=38`) to avoid 2 A GSM bursts (2.8 A peaks exceed the 2.5 A backup limit). + +21\. Window power-up: `PWR_CTRL` HIGH → F9P settled (≥ 1–4 s) → BAT_SENSE ≥ 3.4 V (refuse a modem cold start below ≈ 3.4 V) → W5500 off → `MODEM_PWR_EN` HIGH → wait ≥ 100 ms (2 ms soft-start + bank charge) → PWRKEY asserted 100–500 ms (≥ 50 ms) → wait STATUS HIGH (typ 7–11.2 s, timeout 20 s) or AT `RDY` → `BYP_CTRL` HIGH (Mode B) → AT sync at 115 200 → `AT+CNMP=38` on battery → attach / NTRIP / report → ≥ 2 `$PHLG` with `pwr=BATT` → power-down. + +22\. Window power-down: `AT+CPOF` (or PWRKEY ≥ 2.5 s) → STATUS LOW (≤ ≈ 2–3 s) → `MODEM_PWR_EN` LOW → hold ≥ 2 s → `BYP_CTRL` LOW → `PWR_CTRL` LOW → MCU STOP with the LSE RTC (`LSEMOD` high-drive before `LSEON`, LSI fallback, D-03). + +23\. Any MCU reset power-cycles the modem (R113) and the F9P (PA1 floats): recovery logic must assume a cold modem after every reset and re-run the full sequence. + +**8.7 Modem recovery and watch (R2)** + +24\. Ladder (vehicle or battery, modem only): AT timeout → RESET asserted ≈ 2.5 s → PWRKEY off/on → HARD_CYCLE (EN LOW ≥ 2 s; VBAT decays to 47 mV) → 3 strikes → log `MODEM_DARK`, retry next window. Never cycle `PWR_CTRL` for a link problem; no stack cycle on battery. + +25\. Replace the V5 `sag5` heuristic with STATUS + AT responses + RTCM byte count on PC7; VBAT via `AT+CBC`. + +26\. K1 energised only while the modem is on (150 mW coil). + +**8.8 F9P configuration and NTRIP transport** + +27\. BBR + flash: UART2 baud = modem baud (115 200), UART2 in-protocol RTCM3 only (UBX/NMEA/SPARTN off); UART2 out NMEA GGA only if the K1-NC path is still wanted; UART1 NMEA/UBX for the MCU; *(if C-01)* `CFG-HW-ANT_CFG_VOLTCTRL` / `SHORTDET` = 1. u-center passthrough follows the CDC line coding → USART2 baud. + +28\. Caster socket transparent (`AT+CIPMODE=1`); if multi-socket is needed for `$PHLG`, disable RTCM on UART2 and forward re-assembled RTCM from the MCU on USART2 TX → F9P UART1. RTCM age from GGA field 13 plus an RTCM3 frame walker on PC7. + +**8.9 Ethernet** + +29\. `ETH_PWR_EN` LOW on battery and at boot until needed *(if E-01)*; RSTn LOW ≥ 500 µs before release; SPI2 pins LOW or Hi-Z while 3V3_ETH is off. + +--- + +## 9. Verdict + +### Ready to order? **NO.** + +**What blocks the order (all must be closed):** + +1. The 10 Blockers: **A-01** (unfused 24 V branch, D21 30 V), **F-02** (raw ignition on In2 at 0.221 mm from VEH5V), **F-01** (netclasses/DRC blind to 24 V spacing), **H-04** (U25 `LCSC Part` = AP64350), **C-01** (unlimited GNSS antenna bias), **B-03** (unidirectional LTE ESD), **A-02** (LTC4040 copper/EP/placement), **A-03** (R50 825 Ω), **H-01** (U15 on the wrong land), **H-02** (U10/R53 unobtainable). +2. **G-01:** Leo's backplate answer. If the V5.5 standoffs are reused, MH4 at (193.2, 90.3) and the heatsink-clamp pair must be restored (Blocker); if the backplate is re-drilled, publish the 130 × 90 mm pattern (documentation). +3. **DRC gate:** refill + DRC with the F-01 rules shows 0 clearance errors (the 6 inner `/IGN_IN` spots and 15 outer spots gone). +4. BOM/CPL generated after the H-04 field deletion (or from the schematic with kicad-cli); stock re-checked on order day (H-02, H-02b); J14 pre-ordered; U18/U19 pre-ordered for quantities ≳ 100. + +**Conditions for YES:** items 1–4 done, plus the 19 Majors done or waived in writing (severity scale: "should change before ordering unless there's a written reason"). The Majors are BOM values, three new small ICs (TMP102, 74LVC1G125, USBLC6-2SC6), two drop-in regulator swaps (TPS7A2033, TLV1117LV) and layout work that falls in the same layout pass as the Blockers; four of them (A-04, A-05 CSYS, A-07 and the F-03 U20 input caps) are **prerequisites of A-01**, so A-01 cannot be taken alone. Firmware 0.7.x (§8) is required for R1/R3 but does not gate the fab order. + +**What can follow in v6.1:** the 30 Minors (they can also ride along where they touch the same area) and the 21 Notes; items the findings defer explicitly: K1 → direct PC6 → DIN_4G link (B-13), PoE (E-07), U12 → AP64350 (A-20a), P3 → JST-XH-5/VH if the pack harness is remade (G-07), modem TMP102 (F-52 option). + +**Impact on V5.6 (found in passing):** R112 on `ETH_RST` must be 4.7 k (C23162), not 100 k (E-02); the V5.x schematics still carry the stale SOIC-16W footprint field for U15, so fix it before any Update-PCB on V5.6 (H-01). + +**Bench validation before accepting the v6 boards** (from the findings): thermal camera on U6/L6 at 1.4 A charge and 2.3 A backup, 1 h each (A-02); battery-only cold start at VBAT 3.5 V with MAIN5V/VIN(U20) scope and a `/BAT_PLUS` current probe (A-05, ECO §I-1); 0.1 → 2 A load step on VBAT_MODEM, droop ≤ 150 mV (B-02); `/3V3_GNSS` rise 100–1000 µs/V (C-02); antenna short test (C-01); `/3V3_GNSS` < 0.3 V with PA1 LOW and the modem on (D-01); G3 desense: modem TX power vs F9P C/N0 (F-06/F-12); D34/U25 IR at full load (A-06 → F-03); frequency counter on Y1, target ±10 ppm (E-03); H0008 follow-ups: clamp meter on the pack lead and U6/L6 IR during charge (A-02/A-03). + +**Cost note:** cost analysis kept in the repository copy. + +--- + +## 10. Inputs needed from Leo + +| # | Question | Affects | Assumption used in this audit | +|---|---|---|---| +| 1 | Backplate / enclosure hole pattern: are the V5.5 standoffs (incl. (193.2, 90.3)) reused? Is the modem heatsink clamp (MH11 + partner, thermal gate T1) still planned? | G-01 (Blocker or documentation), L-40 | Unknown → G-01 kept as conditional Blocker | +| 2 | Decision on the modem supply topology: U20 from MAIN5V only (D20/D21 removed), fan from VEH5V (U2 DNP), F2 3 A ahead of D10 | A-01, V1-01, A-04/A-05/A-07/F-03 prerequisites | Adopted as the verified single topology | +| 3 | Fleet supply systems: 24 V only, or 12 V machines too? Alternator load-dump suppression present? Unsuppressed ISO 7637/16750 transients on the ignition wire (terminal tractors, RTGs)? | F2 3 A vs 4 A, A-16 (U25 UVLO), A-19, D-05, F-02 | 9–36 V (T9), 24 V systems present, transients possible | +| 4 | Is GSM/2G fallback required **on battery**, or is LTE-only acceptable? | A-05, B-16, firmware §8 | LTE-only on battery | +| 5 | Fab stackup and copper: JLC04161H-7628 with impedance control, ENIG, and 1 oz inner copper? | F-06, A-07, J-02, L-1 | JLC04161H-7628, 0.5 oz inner by default | +| 6 | Order quantity (20 vs 100) | H-02b (C103211, U18, U19 limits), setup cost per board | Both computed | +| 7 | BOM tool for the JLC order: Fabrication Toolkit (board fields) or kicad-cli (schematic fields)? | H-04 (Blocker in either case until the field is deleted) | Fabrication Toolkit (per the 25-Sep pre-fab audit) | +| 8 | J10 (Ethernet) and P11/P12 (RS-485/RS-232): JLC-assembled, hand-fitted THT, or not fitted on v6? Ethernet on the prototypes? | G-03, E-01, H-01 relevance, U11/U12/Y1 population | Populated | +| 9 | Allocation of PD2: `ETH_PWR_EN` (E-01, verify_1) or board-ID strap (D-08)? If E-01 keeps PD2, is PA9 given to the board ID (losing D-12's debug TX pad)? | E-01, D-08, D-12 | PD2 = ETH_PWR_EN; board-ID pin open | +| 10 | Is "temperature sensor ≤ 10 mm of U6" binding for R4? (would promote F-51 to Blocker) | F-51 | No (Major) | +| 11 | R50: 1.43 kΩ (≥ 1.3 A at every corner) or 1.5 kΩ (V5.6 commonality, 1.254 A minimum)? | A-03 | 1.43 kΩ | +| 12 | LTE antenna ESD: fit PESD0402-240 (C1975527) or leave D28 DNP? | B-03 | Either; needs the 0402 land | +| 13 | Pack details: capacity (Ah), PCM cut-off, NTC β (B3380 vs B3950), chemistry decision D1 (LFP-HT + JP2 2-3 + RNTB 5.6 k, or Li-ion) | A-02, A-03, F-51 thresholds, G-07 | ≈ 11.6–12 Ah Li-ion, RNTB 10 k | +| 14 | Fan part and current | A-01 (U25 load), J-02 | 5 V, 2-wire, 0.2–0.3 A | +| 15 | Must Ethernet work on battery? | E-01 | No (gated off on battery) | +| 16 | Enclosure internal temperature at 45 °C ambient | A-09, B-02 (electrolytic life), H-07/D-02 (−20…+70 °C crystals), U6/D34 thermals | 60–65 °C local near the regulators | +| 17 | H0008 bench data: clamp-meter charge current and U6/L6 temperature | A-02/A-03 causality | Not yet measured | +| 18 | GNSS antenna model: bias voltage range and current | C-01 (75 mA limit) | 3.0–3.3 V, ≤ 30 mA | +| 19 | Will technicians use J9 (modem USB) in the field? | G-02 | Yes, occasionally | +| 20 | Are field harness cables labelled by P-number (V5 names)? | G-05 (P6 FAN / P6 RESET-EXT collision) | Unknown | +| 21 | Low-power plan: STOP + RTC (LSE), or duty cycle with the MCU running? | D-03 severity | STOP + LSE | +| 22 | SWD header wanted on the fab board, or DFU plus pads only? | D-12 | Pads only | +| 23 | Unit prices of the ArduSimple simpleRTK2B and 4G NTRIP Master (500-unit order) | H-10 system-level cost delta | — | +| 24 | Record as a decision: U20 sits upstream of the P5 cutoff (ECO §A intent met functionally via R113) | A-01, G-04 | — | + +--- +## 11. Appendices + +### Appendix A — ERC summary (`evidence/erc_summary.md`) + +KiCad 10.0.4 ERC via kicad-cli: **166 violations = 0 errors + 166 warnings** (same total on the original file and a byte-identical copy). The MCP prints 30 items per run, so the full list was built by running one check group at a time on the copy: 22 + 10 + 30 items are KiCad's exact output; the 104 pin-to-pin markers are a model whose totals equal KiCad's (104 and 70 in two pin-map settings) and which reproduces 29 of 30 visible positions. + +| Category | Count | Source | Classification (`ercdrc_classified.csv`) | Owner finding | +|---|---|---|---|---| +| pin_to_pin | 104 | model (count = KiCad) | pre-existing-benign | J-03 | +| no_connect_dangling (orphan NC flags at x = 453.898 / 484.378 mm) | 23 | KiCad exact | needs-fix-cosmetic | J-04 | +| lib_symbol_mismatch | 22 | KiCad exact | pre-existing-benign | J-04 (leave) | +| lib_symbol_issues (Q_*MOS_G?S ×7, D_Zener_ANK ×2, PCF8574) | 10 | KiCad exact | needs-fix-cosmetic | J-04 | +| footprint_link_issues (P11, P12 Vertical footprint not in library; J10 `Connector_RJ45` nickname) | 3 | KiCad exact | **real** | G-03 | +| no_connect_connected (markers on R31.2 `/I2C_SDA` and K1.10 `/USART6_TX`; flags on U16.37/38, U10.13/14) | 2 | KiCad exact | needs-fix-cosmetic | J-04 | +| unconnected_wire_endpoint (P1.4, R52.2) | 2 | KiCad exact | needs-fix-cosmetic | J-04 | +| **Total** | **166** | | real 3 · benign 126 · cosmetic 37 | | + +Pin-to-pin markers by net: GND 55, `/3V3` 5, `/1V8_MODEM` 4, `/VBAT_MODEM` 4, `/VIN_MODEM` 2, `/DIN_4G_M` 2, `/DOUT_4G_M` 2, `/RF_ANT_LTE` 2, `/RF_ANT_GNSS` 2, and 1 each on 26 modem/U20/U23/U24/U26 nets. Message mix: Unspecified–Passive 50, Unspecified–Unspecified 46, Unspecified–Bidirectional 5, Unspecified–Power output 2, Unspecified–Input 1. Root cause: easyeda-imported symbols in `Drogheda-v6.kicad_sym` with all pins typed `unspecified`. + +### Appendix B — DRC summary (`evidence/drc_summary.md`) + +KiCad DRC (swig backend, KiCad 10, stored fills) on `hbox-watchdog-v6.kicad_pcb` (sha256 6ddec80d…): **283 violations — 0 errors, 283 warnings; 0 unconnected items.** Ignored in the project: missing courtyard, track not centred on via, tuning profile, footprint filters mismatch, footprint type mismatch. The Sep-25 stale report had 303 warnings (199 track_width). + +| Type | Count | Classification | Owner finding | +|---|---|---|---| +| track_width (custom T15 warning rules) | 183 | 59 real per CSV → **verified 63 hits on 6 real nets**; 124 benign | A-02, A-07, B-08 (copper); J-02 (rules) | +| lib_footprint_mismatch | 82 | pre-existing-benign (KiCad 10 library revisions) | J-05 | +| silk_overlap | 11 | needs-fix-cosmetic | F-18 | +| lib_footprint_issues (MountingHole nickname) | 4 | needs-fix-cosmetic | J-05 | +| silk_over_copper (Rigb1 on C9.2, C10 on C10.2) | 2 | needs-fix-cosmetic | F-18 | +| silk_edge_clearance (P1 outline) | 1 | needs-fix-cosmetic | F-18 | +| **Total** | **283** | real 59 (63 verified) · benign 206 · cosmetic 18 | | + +`track_width` per net (count; widths; verdict per J-02 as verified): `/3V3_ETH` 54 (0.25–0.5 mm) benign · `/MAIN5V` 21 (0.3/0.5) **real** · `/VEH5V` 15 (0.25–0.8, incl. In1) **real** · `/5V_FAN` 14 (0.5) benign · `/VIN_SW` 10 (0.25–0.8, incl. In2) **real** · `/SW_5V` 9 benign · `/VIN_MODEM` 9 (0.3/0.5) neck only (0.1 mm under capacity) · `/SW_FAN` 8 benign · `/VBAT_MODEM` 7 (0.25/0.5) **real** · `/FAN_RET` 7 benign · `/SW_IN` 7 benign · `/SYS5V` 6 benign · `/SW_BAT` 6 (0.25/0.3/0.5) **real** · `/VIN_PROT` 5 benign (keep 0.8 mm rule) · `/BAT_PLUS` 4 (0.25/0.5) **real** · `/VIN_FUSED` 1 benign. + +**Rule-set caveat (F-01):** these 0 errors come from a 0.15 mm catch-all rule that overrides every netclass. With the corrected rules: 6 inner-layer errors (`/IGN_IN`), 15 outer-layer errors at 0.3 mm, ≈ 178 zone proximities that re-pour on refill. + +### Appendix C — Evidence file index + +Mac: `03-Architecture-Hardware/kicad/_to_delete/v6-audit-20260928/evidence/` (KiCad exports) and `…/evidence/pack/` (tree below). Container: `/home/claude/v6audit/`. + +| Path | Content | +|---|---| +| `INDEX.md`, `evidence/MANIFEST.md`, `evidence/_verification.md` | map and gotchas; hashes and provenance; self-checks (IPC-356 vs parser, counts, 64-pin MCU) | +| `evidence/netlists/*.xml` | kicad-cli netlists: v6, V5.6 (ECO copy), V5.5 as-fabbed, v5 current (stale) | +| `evidence/components.csv`, `nets.json`, `ref_pins.json` | 328 symbols with fields; net → pins; ref → pin → net | +| `evidence/mcu_pins.csv`, `evidence/ic_pins_.csv` | U16 64/64 pins; per-IC pin tables (U19, U18, U11, U6, U25, U20, U2, U12, U17, U21, U23, U24, U10, U13, U14, U15, U26, U3, U22) | +| `evidence/erc_summary.md`, `erc_full.json/.txt`, `erc/kicad_run_*.txt` | ERC (Appendix A) | +| `evidence/drc_summary.md`, `drc_full.rpt/.json`, `drc_items.csv` | DRC (Appendix B) | +| `evidence/bom.csv`, `bom_ungrouped.csv`, `cpl.csv`, `v6-pcb.ipc356` | kicad-cli BOM (correct LCSC fields), position file, IPC-D-356 | +| `evidence/pcb_footprints.csv`, `pcb_pads.csv`, `pcb_tracks.csv`, `vias.csv`, `zones.csv`, `net_routing_summary.csv` | parsed board geometry (1999 segments, 210 vias, 5 zones), per-net routing and resolved netclass | +| `evidence/stackup.md`, `clearance_24v.md/.csv`, `outline_and_holes.md`, `sch_pcb_sync.md` | stackup/rules/netclass resolution; 24 V clearance sweep; outline and holes; schematic↔PCB sync | +| `evidence/diff_v56_v6.md`, `diff_v5_v56.md` | UUID-matched semantic diffs with focus table | +| `evidence/firmware_pins.md/.csv`, `firmware_constants.csv` | every `PIN_*` in V5/V4 firmware vs the v6 net on the same pin; 84 constants | +| `evidence/v6-sch.pdf`, `v6-pcb-layers.pdf`, `svg/*.svg`, `mcp/*.json` | schematic PDF; per-layer plots; verbatim MCP results (courtyards, zones, rules) | +| `findings/A_power.md`, `BCE_modem_gnss_eth.md`, `DG_mcu_connectors.md`, `FHJ_layout_bom_ercdrc.md` | block auditor findings | +| `findings/verify_1.md`, `verify_2.md` | independent verification (power/RF; layout/BOM/MCU) | +| `findings/pinmap-v6.md`, `bom_check.csv`, `ercdrc_classified.csv` | auditor pin map; 152-line BOM check; 449 classified ERC/DRC items | +| `work//`, `work/verifier1/`, `work/verifier2/` | auditor and verifier scripts, renders (`in1_full.png`, `rf_lte.png`, `rf_gnss.png`, `u20.png`, `u25.png`, `fcu_gnd_pieces.png`), `hv24_violations_corrected_rule.csv`, `critical_crossings.csv` | +| `scripts/` | shared parsers (`kisexp.py` sexpdata helpers, `parse_pcb.py`, `parse_netlist.py`, `clearance_24v.py`, …) | + +### Appendix D — ID → working-file map (all 117 IDs) + +"Final" = severity after verification and merges; "—" = absorbed into the primary named in "State". v1 = `verify_1.md`, v2 = `verify_2.md`. + +| ID | Working file | Auditor severity | Final | State | Report § | Verification | +|---|---|---|---|---|---|---| +| A-01 | `A_power.md` | Blocker | Blocker | primary | §2 4-A | verified-with-correction (v1) | +| A-02 | `A_power.md` | Blocker | Blocker | primary | §2 4-A | verified (v1) | +| A-03 | `A_power.md` | Blocker | Blocker | primary | §2 4-A | verified (v1) | +| A-04 | `A_power.md` | Major | Major | primary | §2 4-A | verified (v1) | +| A-05 | `A_power.md` | Major | Major | primary | §2 4-A | verified-with-correction (v1) | +| A-06 | `A_power.md` | Major | — | absorbed → F-03 (loops), F-12 (EP vias), A-01 (U2 row) | §2 4-F | verified (v1, v2) | +| A-07 | `A_power.md` | Major | Major | primary | §2 4-A | verified (v1) | +| A-08 | `A_power.md` | Major | Major | primary | §2 4-A | verified (v1) | +| A-09 | `A_power.md` | Major | Major | primary (C78); C130/C131 → B-02 | §2 4-A | verified (v1) | +| F-51 | `A_power.md` | Major | Major | primary | §2 4-F | verified (v1) | +| A-10 | `A_power.md` | Minor | Minor | primary | §2 4-A | not independently verified | +| A-11 | `A_power.md` | Minor | Minor | primary | §2 4-A | not independently verified | +| A-12 | `A_power.md` | Minor | — | absorbed → D-09 | §2 4-D | not independently verified | +| A-13 | `A_power.md` | Minor | Minor | primary (absorbs D-10) | §2 4-A | not independently verified; pin per v1 (h) | +| A-14 | `A_power.md` | Minor | Minor | primary (absorbs F-10; In1 part → A-02) | §2 4-A | not independently verified | +| A-15 | `A_power.md` | Minor | — | absorbed → H-04 | §2 4-H | verified via H-04 (v2) | +| F-52 | `A_power.md` | Minor | Minor | primary | §2 4-F | not independently verified | +| A-16 | `A_power.md` | Note | Note | primary | §2 4-A | not independently verified | +| A-17 | `A_power.md` | Note | — | absorbed → B-02 | §2 4-B | verified via B-02, conflict (c) (v1) | +| A-18 | `A_power.md` | Note | Note | primary | §2 4-A | not independently verified | +| A-19 | `A_power.md` | Note | Note | primary | §2 4-A | not independently verified | +| A-20 | `A_power.md` | Note | Note | primary | §2 4-A | not independently verified | +| F-53 | `A_power.md` | Note | — | absorbed → A-01 | §2 4-A | verified via A-01 merge (v1) | +| B-01 | `BCE_modem_gnss_eth.md` | Blocker | — | absorbed → A-01 | §2 4-A | verified (v1) | +| B-02 | `BCE_modem_gnss_eth.md` | Blocker | Major | primary (absorbs A-09 C130/C131, A-17) | §2 4-B | verified, severity Blocker → Major (v1) | +| B-03 | `BCE_modem_gnss_eth.md` | Blocker | Blocker | primary | §2 4-B | verified-with-correction (v1) | +| B-04 | `BCE_modem_gnss_eth.md` | Blocker | — | absorbed → F-12 | §2 4-F | verified, severity Blocker → Major (v1, v2) | +| C-01 | `BCE_modem_gnss_eth.md` | Blocker | Blocker | primary (absorbs D-07) | §2 4-C | verified (v1) | +| B-05 | `BCE_modem_gnss_eth.md` | Major | — | absorbed → F-06 | §2 4-F | verified (v1) | +| B-06 | `BCE_modem_gnss_eth.md` | Major | — | absorbed → F-03 | §2 4-F | verified (v1) | +| B-07 | `BCE_modem_gnss_eth.md` | Major | — | absorbed → G-02 (ESD); routing → F-17 | §2 4-G | verified (v1) | +| C-02 | `BCE_modem_gnss_eth.md` | Major | Major | primary | §2 4-C | verified (v1) | +| C-03 | `BCE_modem_gnss_eth.md` | Major | — | absorbed → F-12 | §2 4-F | verified-with-correction (v1) | +| C-04 | `BCE_modem_gnss_eth.md` | Major | Major | primary | §2 4-C | verified (v1) | +| E-01 | `BCE_modem_gnss_eth.md` | Major | Major | primary (absorbs A-05 fix 1) | §2 4-E | verified (v1) | +| E-02 | `BCE_modem_gnss_eth.md` | Major | Major | primary (absorbs D-04); Minor once E-01 is in | §2 4-E | verified-with-correction (v1) | +| E-03 | `BCE_modem_gnss_eth.md` | Major | Minor | primary (absorbs H-07, F-11 Y1) | §2 4-E | verified, severity Major → Minor (v1) | +| B-08 | `BCE_modem_gnss_eth.md` | Minor | Minor | primary | §2 4-B | not independently verified | +| B-09 | `BCE_modem_gnss_eth.md` | Minor | Minor | primary | §2 4-B | not independently verified | +| B-10 | `BCE_modem_gnss_eth.md` | Minor | Minor | primary (absorbs D-14) | §2 4-B | not independently verified | +| B-11 | `BCE_modem_gnss_eth.md` | Minor | — | absorbed → J-04 | §2 4-J | not independently verified | +| C-05 | `BCE_modem_gnss_eth.md` | Minor | — | absorbed → F-06 | §2 4-F | verified via F-06 (v2) | +| C-06 | `BCE_modem_gnss_eth.md` | Minor | — | absorbed → D-01 | §2 4-D | verified via D-01 (v2) | +| C-07 | `BCE_modem_gnss_eth.md` | Minor | Minor | primary | §2 4-C | not independently verified | +| E-04 | `BCE_modem_gnss_eth.md` | Minor | Minor | primary | §2 4-E | not independently verified | +| E-05 | `BCE_modem_gnss_eth.md` | Minor | — | absorbed → G-03 | §2 4-G | not independently verified | +| E-06 | `BCE_modem_gnss_eth.md` | Minor | Minor | primary | §2 4-E | not independently verified | +| B-12 | `BCE_modem_gnss_eth.md` | Note | — | absorbed → F-01 (netclasses), F-06 (stackup) | §2 4-F | verified via merges (v1, v2) | +| B-13 | `BCE_modem_gnss_eth.md` | Note | Note | primary | §2 4-B | not independently verified | +| B-14 | `BCE_modem_gnss_eth.md` | Note | Note | primary | §2 4-B | not independently verified | +| B-15 | `BCE_modem_gnss_eth.md` | Note | Note | primary | §2 4-B | not independently verified | +| B-16 | `BCE_modem_gnss_eth.md` | Note | Note | primary | §2 4-B | not independently verified | +| C-08 | `BCE_modem_gnss_eth.md` | Note | Note | primary | §2 4-C | not independently verified | +| C-09 | `BCE_modem_gnss_eth.md` | Note | Note | primary | §2 4-C | not independently verified | +| E-07 | `BCE_modem_gnss_eth.md` | Note | Note | primary | §2 4-E | not independently verified | +| D-01 | `DG_mcu_connectors.md` | Major | Major | primary (absorbs C-06) | §2 4-D | verified-with-correction (v2) | +| D-06 | `DG_mcu_connectors.md` | Major | — | absorbed → F-02 (Blocker) | §2 4-F | verified, severity Major → Blocker (v2) | +| G-01 | `DG_mcu_connectors.md` | Major | Blocker (conditional) | primary | §2 4-G | verified-with-correction (v2) | +| G-02 | `DG_mcu_connectors.md` | Major | Major | primary (absorbs B-07 ESD, F-14 J9) | §2 4-G | verified (v1, v2) | +| D-02 | `DG_mcu_connectors.md` | Minor | Minor | primary (absorbs F-11 Y3) | §2 4-D | verified (v2) | +| D-03 | `DG_mcu_connectors.md` | Minor | Minor | primary | §2 4-D | not independently verified | +| D-04 | `DG_mcu_connectors.md` | Minor | — | absorbed → E-02 (alternative rejected) | §2 4-E | verified via E-02 (v1) | +| D-05 | `DG_mcu_connectors.md` | Minor | Minor | primary | §2 4-D | not independently verified | +| D-07 | `DG_mcu_connectors.md` | Minor | — | absorbed → C-01 | §2 4-C | verified via C-01 (v1) | +| D-08 | `DG_mcu_connectors.md` | Minor | Minor | primary (pin unresolved) | §2 4-D | not independently verified | +| D-09 | `DG_mcu_connectors.md` | Minor | Minor | primary (absorbs A-12) | §2 4-D | not independently verified | +| D-10 | `DG_mcu_connectors.md` | Minor | — | absorbed → A-13 (CLPROG part dropped) | §2 4-A | not independently verified; pin per v1 (h) | +| D-11 | `DG_mcu_connectors.md` | Minor | — | absorbed → J-04 | §2 4-J | not independently verified | +| D-12 | `DG_mcu_connectors.md` | Minor | Minor | primary | §2 4-D | not independently verified | +| G-03 | `DG_mcu_connectors.md` | Minor | Minor | primary (absorbs E-05, H-06) | §2 4-G | not independently verified | +| G-04 | `DG_mcu_connectors.md` | Minor | Minor | primary | §2 4-G | not independently verified | +| G-05 | `DG_mcu_connectors.md` | Minor | Minor | primary | §2 4-G | not independently verified | +| G-08 | `DG_mcu_connectors.md` | Minor | Minor | primary | §2 4-G | not independently verified | +| D-13 | `DG_mcu_connectors.md` | Note | Note | primary | §2 4-D | not independently verified | +| D-14 | `DG_mcu_connectors.md` | Note | — | absorbed → B-10 | §2 4-B | not independently verified | +| D-15 | `DG_mcu_connectors.md` | Note | Note | primary | §2 4-D | not independently verified | +| D-16 | `DG_mcu_connectors.md` | Note | — | absorbed → H-08 | §2 4-H | not independently verified | +| G-06 | `DG_mcu_connectors.md` | Note | Note | primary | §2 4-G | not independently verified | +| G-07 | `DG_mcu_connectors.md` | Note | Note | primary | §2 4-G | not independently verified | +| F-01 | `FHJ_layout_bom_ercdrc.md` | Blocker | Blocker | primary (absorbs J-01, F-15, B-12 netclass) | §2 4-F | verified-with-correction (v2) | +| F-02 | `FHJ_layout_bom_ercdrc.md` | Blocker | Blocker | primary (absorbs D-06, F-16) | §2 4-F | verified (v2) | +| F-03 | `FHJ_layout_bom_ercdrc.md` | Major | Major | primary (absorbs A-06 loops, B-06, F-07, F-09) | §2 4-F | verified (v1, v2) | +| F-04 | `FHJ_layout_bom_ercdrc.md` | Major | — | absorbed → F-12 | §2 4-F | verified (v2) | +| F-05 | `FHJ_layout_bom_ercdrc.md` | Major | Major | primary | §2 4-F | verified, fix scope corrected (v2) | +| F-06 | `FHJ_layout_bom_ercdrc.md` | Major | Major | primary (absorbs B-05, C-05, B-12 stackup) | §2 4-F | verified-with-correction (v1, v2) | +| F-07 | `FHJ_layout_bom_ercdrc.md` | Major | — | absorbed → F-03 | §2 4-F | verified (v2) | +| F-08 | `FHJ_layout_bom_ercdrc.md` | Major | — | absorbed → A-01 (moot with U2 DNP) | §2 4-A | verified (v2) | +| F-09 | `FHJ_layout_bom_ercdrc.md` | Major | — | absorbed → F-03 | §2 4-F | verified-with-correction (v2) | +| F-10 | `FHJ_layout_bom_ercdrc.md` | Minor | — | absorbed → A-14 | §2 4-A | not independently verified | +| F-11 | `FHJ_layout_bom_ercdrc.md` | Minor | — | absorbed → E-03 (Y1), D-02 (Y3) | §2 4-E / 4-D | verified via E-03 (v1) / D-02 (v2) | +| F-12 | `FHJ_layout_bom_ercdrc.md` | Major | Major | primary (absorbs F-13, F-04, B-04, C-03, A-06 vias) | §2 4-F | verified, target corrected to ≥ 400 (v1, v2) | +| F-13 | `FHJ_layout_bom_ercdrc.md` | Major | — | absorbed → F-12 (U6 EP → A-02) | §2 4-F | verified-with-correction (v2) | +| F-14 | `FHJ_layout_bom_ercdrc.md` | Minor | Minor | primary (J9 part → G-02) | §2 4-F | not independently verified | +| F-15 | `FHJ_layout_bom_ercdrc.md` | Minor | — | absorbed → F-01 | §2 4-F | verified via F-01 (v2) | +| F-16 | `FHJ_layout_bom_ercdrc.md` | Minor | — | absorbed → F-02 | §2 4-F | verified via F-02 (v2) | +| F-17 | `FHJ_layout_bom_ercdrc.md` | Minor | Minor | primary | §2 4-F | not independently verified | +| F-18 | `FHJ_layout_bom_ercdrc.md` | Minor | Minor | primary | §2 4-F | not independently verified | +| F-19 | `FHJ_layout_bom_ercdrc.md` | Note | Note | primary | §2 4-F | not independently verified | +| F-20 | `FHJ_layout_bom_ercdrc.md` | Note | Note | primary | §2 4-F | not independently verified | +| F-21 | `FHJ_layout_bom_ercdrc.md` | Note | Note | primary | §2 4-F | not independently verified | +| H-01 | `FHJ_layout_bom_ercdrc.md` | Blocker | Blocker | primary | §2 4-H | verified-with-correction (v2) | +| H-02 | `FHJ_layout_bom_ercdrc.md` | Blocker | Blocker | primary (U10 + R53 only) | §2 4-H | verified-with-correction (v2) | +| H-03 | `FHJ_layout_bom_ercdrc.md` | Major | Minor | primary | §2 4-H | verified, severity Major → Minor (v2) | +| H-04 | `FHJ_layout_bom_ercdrc.md` | Major | Blocker | primary (absorbs A-15) | §2 4-H | verified, severity Major → Blocker (v2) | +| H-05 | `FHJ_layout_bom_ercdrc.md` | Note | — | absorbed → A-01 | §2 4-A | verified via A-01 (v1) | +| H-06 | `FHJ_layout_bom_ercdrc.md` | Minor | — | absorbed → G-03 | §2 4-G | not independently verified | +| H-07 | `FHJ_layout_bom_ercdrc.md` | Minor | — | absorbed → E-03 | §2 4-E | verified via E-03 (v1) | +| H-08 | `FHJ_layout_bom_ercdrc.md` | Minor | Minor | primary (absorbs D-16) | §2 4-H | not independently verified | +| H-09 | `FHJ_layout_bom_ercdrc.md` | Note | Note | primary | §2 4-H | not independently verified | +| H-10 | `FHJ_layout_bom_ercdrc.md` | Note | Note | primary | §2 4-H | not independently verified | +| J-01 | `FHJ_layout_bom_ercdrc.md` | Major | — | absorbed → F-01 | §2 4-F | verified (v2) | +| J-02 | `FHJ_layout_bom_ercdrc.md` | Major | Minor | primary, residual (copper → A-02/A-07/B-08) | §2 4-J | verified-with-correction (v2) | +| J-03 | `FHJ_layout_bom_ercdrc.md` | Minor | Minor | primary | §2 4-J | not independently verified | +| J-04 | `FHJ_layout_bom_ercdrc.md` | Minor | Minor | primary (absorbs B-11, D-11) | §2 4-J | not independently verified | +| J-05 | `FHJ_layout_bom_ercdrc.md` | Note | Note | primary | §2 4-J | not independently verified | +| V1-01 | `verify_1.md` ("Anything else" #1) | — (new) | Major | primary | §2 4-A | raised by verify_1, not cross-checked | +| H-02b | `verify_2.md` (H-02 split) | (part of H-02, Blocker) | Major | primary | §2 4-H | verified (v2) | diff --git a/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Plan-de-Correccion_v1.0.md b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Plan-de-Correccion_v1.0.md new file mode 100644 index 0000000..cc5d756 --- /dev/null +++ b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Plan-de-Correccion_v1.0.md @@ -0,0 +1,1536 @@ +--- +title: "EinarBoard v6 — Plan de corrección y estado (28-sep-2026)" +tags: [project-drogheda, hardware, hbox, v6, pcb, auditoria, jlcpcb, correccion, puertos] +project: Project Drogheda +author: Helgen Technologies +date: 2026-09-28 +version: 1.2 +status: ACTIVO — NO se ordena hasta cerrar la lista de liberación +audience: Leo, Michelle (layout), Jesús (banco), ingenieros +--- + +# EinarBoard v6 — Plan de corrección y estado (28-sep-2026) + +!!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide" + Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios. + +!!! tip "¿Qué sigue para ordenar?" + La versión corta, con el orden, quién hace qué y cuánto tarda: **[Próximos pasos para ordenar](v6-proximos-pasos.md)**. + +!!! danger "Veredicto: TODAVÍA NO se ordena — pero el esquemático ya está terminado" + **Esquemático: terminado y verificado de forma independiente.** El 28-sep se hicieron cuatro pasadas: + + 1. **Correcciones de la auditoría:** 126 cambios. La verificación independiente dio **173 PASS / 0 FAIL**. + 2. **Puertos y «sin nueva versión»:** todos los puertos funcionan como están dibujados. + 3. **Revisión final independiente:** **26 PASS / 1 FAIL**. El FAIL era la huella de los inductores y ya está corregida. + 4. **Paquete LFP-HT (igual que V5.6):** JP2 puenteado 2-3 y R55 = 5.6 k (C23189) → flotación **3.50 V** en vez de 4.00 V. + + Esquemático final `d58a89ba…e7b`, **ERC 0 errores**. **El PCB no se tocó.** + + **Lo que queda para poder ordenar:** + + 1. **Layout (Michelle):** la [lista de trabajo](#5-lista-de-trabajo-de-michelle-layout) L-1…L-67 de la sección 5. + 2. **Actualizar el PCB desde el esquemático y revisarlo** (paso 0 de la lista). + 3. **DRC limpio con las reglas nuevas.** Es la puerta de salida: 0 errores de separación. + 4. **Compras y pre-órdenes:** THVD1410DR, TPS7A2033PDBVR y J14; conectores hembra de P11/P12; stackup con control de impedancia (sección 7). + + El firmware 0.7.x es necesario para que la v6 funcione en batería, pero **no** detiene el pedido. + +**Tarjeta:** `hbox-watchdog-v6` (repo **HBox_PCB**) · **Pedido previsto:** 20 prototipos en JLCPCB +(PCB + ensamble) · **Fecha:** 28-sep-2026 · +[Auditoría completa (español)](v6-auditoria-completa.md) · [original en inglés](v6-full-audit.md) · +[Cambios de esquemático — resumen de 3 pasadas](v6-cambios-resumen.md) + +!!! warning "Requisito de Leo (28-sep): todos los puertos funcionan y no hay nueva versión" + *«Todos los puertos tienen que funcionar (RS-232, RS-485, Ethernet, USB) y no quiero hacer una nueva versión de la + tarjeta.»* + + → **No habrá nueva versión: todo se hace en este pedido.** Lo que no se hace queda + **[aceptado permanentemente](#9-aceptado-permanentemente)**, con su razón escrita. + +**Qué se revisó:** esquemático `ecee9fed…` (25-sep) y PCB `6ddec80d…` (28-sep), KiCad 10.0.4, en solo lectura. +Cuatro auditores por bloque y dos verificadores independientes, que volvieron a calcular **cada** Blocker y Major +desde las fuentes (0 refutados). Resultado tras fusionar duplicados: **81 hallazgos** — +11 Blocker (10 + G-01, que por la decisión D11 ya es Blocker) · 19 Major · 30 Minor · 21 Note. +**Ningún hallazgo cambia la arquitectura de la v6.** + +!!! tip "Cómo leer esta página" + - **Leo:** secciones 1 (decisiones), 8 (lista de liberación), 9 (aceptado permanentemente) y 11 (impacto en V5.6). + - **Michelle:** sección 4 (el porqué de cada punto) y sección 5 (lista de trabajo con casillas). + - **Jesús y banco:** secciones 3 (puertos) y 10 (qué medir cuando lleguen las tarjetas). + - **Firmware:** sección 6. + +--- + +## 1. Qué decidimos (y por qué) + +Leo pidió: *«si un cambio se puede hacer en el esquemático, hay que hacerlo; toma las mejores decisiones por mí»*. +Claude tomó estas decisiones el 28-sep (17:20 CST). Las preguntas vienen de la §10 del informe. + +| # | Decisión | Por qué | Hallazgos | +|---|---|---|---| +| D1 | Entrada = **24 V regulados del gabinete** (Mean Well DDR-60G-24); la tarjeta conserva su margen de 9–36 V. Ignición = **cruda de la máquina, de 12 V y de 24 V**. | Restricción del proyecto. En ICAVE: RTG, Reach Stacker, Empty Handler a 24 V; Tractoplana y Montacargas a 12 V. | F-02, D-05 | +| D2 | **U20 (buck del módem) solo desde `/MAIN5V`**: se quitan D20 y D21 (conexión directa). **Ventilador desde `/VEH5V`** (bloque U2 sin montar, JP1 puenteado). Rama `/24V` de Q10 sin montar. **F2 = 3 A (C206912), eléctricamente antes de D10.** En la misma pasada: A-04, A-05, capacitores de entrada de U20 y valores de lazo de B-02. | Quita la falla de D21 y la rama sin fusible, con menos piezas. Verificado: U25 queda en ≤ 2.95 A. | A-01, V1-01 | +| D3 | **R50 = 1.43 kΩ (C22840)** | ≥ 1.3 A en todas las esquinas y abajo del máximo de 2.5 A del LTC4040. | A-03 | +| D4 | **R121 = 57.6 k (C23082)** → 5.18 / 5.32 / 5.46 V; firmware `V5_PFI` → 4.40 V | El 5 V actual queda abajo del arranque del cargador. | A-04 | +| D5 | ESD de la antena LTE: **se monta PESD0402-240 (C1975527)** en huella 0402 | Se conserva la protección porque el cable de antena sale de la caja. | B-03 | +| D6 | Bias de antena GNSS con **TPS2552DBVR (C46506)**: ILIM→IN (75 mA), ANT_OFF→EN̅, FAULT̅→ANT_SHORT_N | Limita la corriente y avisa del corto. | C-01 | +| D7 | «Sensor a ≤ 10 mm de U6» es **obligatorio**: F-51 completo (TMP102 C99269 en 0x48 junto a U6 + NTC del paquete a PC5: 100 k C25803 / 120 k C25808 / 10 nF C1589) | Requisito R4; lección F5. | F-51 | +| D8 | **PD2 = `ETH_PWR_EN`** (habilita U12, pull-down 100 k). La identificación de tarjeta queda **solo en firmware**: al arrancar, WHO_AM_I del SC7A20 en 0x18 y el F9P respondiendo en USART2, antes de manejar cualquier pin exclusivo de la v6. PA9 queda como pad de TX de depuración. | Cortar la energía por hardware vale más que un strap; la tarjeta se puede detectar. | E-01, D-08, D-12 | +| D9 | En batería: **solo LTE** (`AT+CNMP=38`) y **Ethernet apagado** | Los picos GSM de 2.8 A superan el límite del respaldo. | A-05, B-16 | +| D10 | **J10, P11 y P12 se montan** (Ethernet y RS-485/RS-232 son funciones de la v6, decisiones EinarBoard 1.1). Huellas del esquemático corregidas a las piezas pedidas (P11/P12 de ángulo recto = la huella *Horizontal* del PCB; J10 a una librería que sí existe). Michelle quita los DNP del PCB. | Paridad esquemático ↔ PCB. | G-03 | +| D11 | La v6 debe entrar en la **placa base y standoffs de la V5.5** (el brief dice «sin rehacer gabinete») → **G-01 = Blocker**: restaurar MH4 de la V5.5 y los barrenos de la abrazadera del disipador (MH11 + pareja). L6 se mueve de todos modos por A-02. | No hay retrabajo de gabinete. | G-01 | +| D12 | Fabricación: **JLC04161H-7628 con control de impedancia, ENIG, cobre interno de 1 oz** (y aun así ensanchar las pistas internas de potencia) | Impedancia de RF real y corriente en capas internas. | F-06, A-07, J-02 | +| D13 | Herramienta de BOM: **Fabrication Toolkit** → borrar `LCSC Part` de la huella de U25 en `Drogheda-v6.pretty` y en la tarjeta | El toolkit lee ese campo primero. | H-04 | +| D14 | **20 prototipos primero**; re-verificar stock el día del pedido; pre-ordenar J14 (y U18/U19 si se va a 100) | Stock limitado. | H-02, H-02b | +| D15 | Firmware: §8 del informe → **FW 0.7.x `board_v6.h`**; no es parte de la pasada de esquemático | — | §8 | +| D16 | Minors que son solo valor/campo de esquemático: se aplican **cuando son triviales y seguros**. El resto va al layout o queda aceptado permanentemente (sección 9). **No habrá nueva versión.** | — | §7.3 | +| D17 | Se edita **en el mismo archivo** `hbox-watchdog-v6.*` (regla de Leo, 28-sep: las iteraciones de una tarjeta se editan en su lugar; lo anterior se recupera de git). Copias previas en `kicad/_to_delete/v6-apply-20260928/`. **El `.kicad_pcb` no se toca** (es el archivo de Michelle): ella corre *Actualizar PCB desde esquemático*. | Preferencias del proyecto. | — | +| D18 | **Netclasses y reglas DRC** aplicadas ya en `.kicad_pro` (patrones, clases RF y PWR_MODEM) y `.kicad_dru` (reglas corregidas por el verificador 2) | Así el DRC se vuelve la puerta de salida. | F-01 | +| D20 | **Química del paquete = LFP-HT 26650, la misma que V5.6** (decisión de Leo del 28-sep para V5.6): JP2 puenteado 2-3 (F2 a GND → flotación **3.50 V**), R55 (RNTB) = **5.6 k C23189** con NTC 10 k **B3380** → ventana de carga ≈ +8…+60 °C | Un paquete LFP en una tarjeta con estrapes Li-ion se flotaría a 4.00 V: sobrecarga. v6 usa el mismo paquete que V5.6. | A-02, F-51 | + +??? note "Alcance de las pasadas de esquemático (D19 y cierre sin nueva versión)" + - **Pasada 1 — correcciones de la auditoría:** todo lo de la §7.1 (Blockers) y §7.2 (Majors) que toca esquemático o + proyecto, con las decisiones de arriba. G-01 es solo layout (Michelle). + - **Minors aplicados en la pasada 1** (solo esquemático, bajo riesgo): A-11 (R56 → pull-up: cargador apagado por + defecto), A-13 (PFO → PB10 + 100 k), B-09 (22 Ω + 100 nF), B-10 (pull-ups/downs + R106 → 1 k), C-07 (pads de + prueba), D-02 (Y3 → 3225 C2901684 + 12 pF), D-03 (Y4 CL 7 pF + 6.8 pF), D-05 (Rigb1 → 2.2 k; el firmware lee la + ignición por ADC), D-09, D-12 (TP9), E-03 (**se queda Y1**, C95/C96 → 33 pF C1663, sin cambio de huella), E-04, + **F-52 (TMP102 del módem en 0x49)**, G-03 (huellas según D10, montadas), G-04 (JP_CUT), G-08 (3 ESD), + H-08 (textos de valor), J-04 (banderas NC huérfanas o sobre pines conectados, trozos de cable), + B-15 (R107/R108 DNP con nota «nunca montar»). + - **Pasada 2 — puertos y sin nueva versión:** RS-485, RS-232, H4, Ethernet, CTS del SC16IS752 y TP12 (sección 3); + **H-03 hecho** (huella MWSA0804S) y **B-13 hecho** (K1 DNP, enlace directo R148). + - **Pasada 3 — revisión final:** huella MWSA0804S corregida a la tierra de Sunlord, C176 en U28 (N2), Y3 confirmado (N1). + - **No aplicado → aceptado permanentemente** (sección 9): D-08 (identificación solo por firmware) y J-03 (tipos de + pin de la librería; cosmético). + +--- + +## 2. Estado por hallazgo (Blockers y Majors) + +**Quién:** *Esquemático* = Claude, 28-sep · *Layout* = Michelle · *Firmware* = FW 0.7.x · *Compras* = pedido JLC. +Cada punto de esquemático se comprobó contra el netlist final. La verificación independiente cubrió 126 ítems: +**173 PASS / 0 FAIL**, ERC 0 errores. + +| ID | Problema | Por qué importa | Corrección | Quién | Estado | +|---|---|---|---|---|---| +| **A-01** | La rama `/24V` no tiene fusible y alimenta a U20 (módem) y U2 (ventilador); D21 (30 V) la une con `/MAIN5V` | D21 puede embalarse térmicamente a 45–60 °C; en corto pone 24 V sin fusible en el 5 V | U20 solo desde `/MAIN5V` (sin D20/D21); ventilador desde `/VEH5V`; rama Q10 sin montar; F2 3 A primero | Esquemático · Layout | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| **F-02** | La ignición cruda `/IGN_IN` corre 106.5 mm en In2 a 0.221 mm de `/VEH5V` | Es la geometría del corto del 23-jul; una capa interna no se inspecciona ni se repara | TVS D35 SMBJ33A en P1.3; Rig1 a ≤ 3 mm de P1.3; el tramo largo pasa a `/IGN_SENSE` | Esquemático · Layout | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| **F-01** | Las netclasses no resolvían y una regla de 0.15 mm anulaba todas: el DRC no veía el 24 V | «DRC 0 errores» no significaba nada: F-02 lo pasó | Tabla de netclasses + `.kicad_dru` corregido; rellenar y DRC como puerta | Esquemático (reglas del proyecto) · Layout | ✅ Reglas aplicadas en el proyecto y verificadas (28-sep) · cobre pendiente | +| **H-04** | La huella de U25 trae `LCSC Part` = C2071691 (AP64350, 40 V) y Fabrication Toolkit lee ese campo primero | JLC montaría un buck de 40 V detrás de un clamp de 53 V: pasa el banco y muere en campo | Campo borrado en la librería; Michelle actualiza la huella de U25 en el PCB | Esquemático · Layout | ✅ Aplicado en la librería y verificado (28-sep) · campo en PCB pendiente | +| **C-01** | El bias de la antena GNSS no tiene límite de corriente | Un coaxial en corto (fallas H0005/H0014) daña L21 y VCC_RF del F9P, y nadie se entera | U28 TPS2552 (C46506) a 75 mA, aviso de corto a PC2; C176 de desacople | Esquemático · Layout · Firmware | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| **B-03** | El ESD de la antena LTE (D28) es unidireccional de 5 V en una línea que llega a 14.1 V pico | Recorta la señal, genera espurias (homologación) y D28 puede quedar en corto | D28 → PESD0402-240 (C1975527), bidireccional 24 V, huella 0402 | Esquemático · Layout | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| **A-02** | Cobre y colocación del cargador LTC4040 (U6) repiten la lección F5: `/SW_BAT` 0.5 mm, EP sin vías, L6 a 8.65 mm | Se calienta en carga y respaldo; no se cumple R5 (≥ 1.3 A sin ciclado térmico) | Re-agrupar U6; `/SW_BAT` polígono ≥ 2 mm; 9 vías en el EP | Layout | Pendiente — layout | +| **A-03** | R50 = 825 Ω programa 2.42 A (hasta 2.57 A, más que los 2.5 A del LTC4040) | Repite H0008; U25 trabaja en el límite de RS1 siempre que carga | R50 → 1.43 kΩ (C22840): 1.316–1.483 A | Esquemático | ✅ Aplicado en esquemático y verificado (28-sep) | +| **H-01** | U15 (SO-16 angosto) está sobre una huella SOIC-16 ancha | No se puede soldar: RS-232 muerto en todas las tarjetas | Huella `SOIC-16_3.9x9.9mm`; U15 ahora es TRS3232EIDR (sección 3) | Esquemático · Layout | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| **H-02** | U10 y R53 no tienen stock para ningún pedido | JLC no las coloca; sin R53 el respaldo de batería no regula | U10 → C57156 (SC16IS752), R53 → C177479 | Esquemático · Compras | ✅ Aplicado en esquemático y verificado (28-sep) · stock el día del pedido | +| **G-01** | Cambiaron los barrenos vs V5.5: falta MH4 en (193.2, 90.3) — L6 quedó encima — y los de la abrazadera del disipador | No entra en la placa base de la V5.5; un standoff metálico presionaría L6 / `/BAT_PLUS` | Restaurar MH4 y poner la pareja de la abrazadera junto a U19 (D11) | Layout | Pendiente — layout | +| V1-01 | D10 (TVS de entrada) está antes del fusible F2 | Con P1 al revés, D10 conduce directo sobre el arnés sin fusible de tarjeta y falla en corto | F2 primero: P1 → F2 → D10 ∥ Q23 | Esquemático · Layout | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| D-01 | U24 manda 3.3 V a RXD2 del F9P aunque el F9P esté apagado | El riel del F9P queda pre-polarizado y su reinicio por corte de energía falla sin avisar (lección 0.5.5/0.5.6) | Compuerta U27 74LVC1G125 (C12518) alimentada de `/3V3_GNSS`; Rdfu1 → 100 k | Esquemático · Layout · Firmware | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| A-04 | U25 da 5.00 V nominal (4.87–5.14 V), abajo del arranque del cargador (5.05 V) | Con los umbrales del firmware la mayoría de las unidades nunca empieza a cargar | R121 → 57.6 k (C23082): 5.18 / 5.32 / 5.46 V; `V5_PFI` 4.40 V | Esquemático · Firmware | ✅ Aplicado en esquemático y verificado (28-sep) · firmware pendiente | +| B-02 | El bulk de VBAT_MODEM es electrolítico de 85 °C y la compensación de U20 es la de 5 V | En frío o envejecido, los picos GSM bajan VBAT a < 3.4 V: «módem oscuro» en ~1 año | C130/C131 → polímero; R116 113 k, C141 6.8 nF, C142 56 pF; + C166/C167 22 µF | Esquemático · Layout | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| E-01 | 3V3_ETH (W5500) no se puede apagar | En batería gasta más que todo el presupuesto de sueño (lección F8) | EN de U12 → PD2 (`/ETH_PWR_EN`) con R139 100 k a GND | Esquemático · Layout · Firmware | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| A-05 | En batería, un pico GSM con todo encendido pide 2.25–2.33 A al boost (91–97 % de 2.5 A); CSYS efectiva 57–69 µF | En el límite cae VSYS y el módem se apaga (el síntoma de la V5.5 por otro camino) | + C161/C162 47 µF (C5440143) en VSYS de U6; secuencia de firmware y solo LTE | Esquemático · Layout · Firmware | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| F-51 | Ninguna temperatura del cargador ni de la celda llega al MCU | La inhibición térmica del firmware no tiene sensor (R4) | U29 TMP102 (C99269, 0x48) junto a U6 + NTC del paquete a PC5 (`/NTC_CELL`) | Esquemático · Layout · Firmware | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| F-12 | 69 vías de tierra (V5.5: 165); 1 bajo el módem, 0 bajo el F9P, 0 en los EP de reguladores | El LTE desensibiliza al GNSS; los chips pierden su camino de calor | ≥ 400 vías: EP, U19 ≥ 30, U18 ≥ 24, cerca de vías en la orilla | Layout | Pendiente — layout | +| F-03 | Lazos calientes grandes en U25 (≈ 311 mm²), U20 y U12 | Ruido hacia GNSS/LTE y sobrevoltaje en la entrada de U25 | Cin ≤ 2 mm, una sola isla de GND, lazo ≤ 1 cm²; U20 + C163/C164 22 µF + C165 220 µF | Esquemático · Layout | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| A-07 | El camino de 5 V (hasta 2.5 A) va por pistas internas de 0.5 y 0.8 mm | Cobre interno caliente bajo U6/Q7; es prerrequisito de A-01 | ≥ 2 mm en F.Cu o polígono; sensado Kelvin en RS1; cobre interno de 1 oz | Layout · Compras | Pendiente — layout | +| F-06 | El LTE corre 22 mm por In1 bajo pistas de potencia; ninguna línea RF es de 50 Ω en el stackup real | Desacople y desensibilización del F9P; la prueba G3 probablemente falla | Stackup real + control de impedancia; CPWG 0.30/0.20 en F.Cu; cerca de vías ≤ 3 mm | Layout · Compras | Pendiente — layout | +| F-05 | In1, el «plano de tierra», está 19 % vacío y lleva 1572 mm de pistas de 49 redes | Los retornos rodean las ranuras; diafonía entre capas | Despejar In1 bajo USB, cristales, nodos SW, RF y SIM; ≤ 3 islas | Layout | Pendiente — layout | +| C-04 | El interruptor del F9P (Q1) está a 9 mm de la antena LTE; `/SW_5V` cruza 181 mm por In1 | El transmisor LTE se mete al riel del receptor GNSS | Mover Q1/Q5/R1/R2 a la isla GNSS; `/SW_5V` ≤ 15 mm y nada en In1 | Layout | Pendiente — layout | +| G-02 | El USB-C del módem (J9) no tiene ESD | J9 es la única vía de recuperación del módem | U30 USBLC6-2SC6 (C7519) a ≤ 3 mm de J9 | Esquemático · Layout | ✅ Aplicado en esquemático y verificado (28-sep) · layout pendiente | +| C-02 | U21 (AP2112K) no tiene arranque suave; la rampa del F9P queda con margen no especificado | Arranques fallidos ocasionales del F9P (≈ 52 000 arranques al año) | U21 → TPS7A2033 (C2862740): 239–367 µs/V | Esquemático · Compras | ✅ Aplicado en esquemático y verificado (28-sep) · pre-orden de C2862740 | +| A-08 | U17 (AMS1117) se queda sin margen en batería | 3V3 degradado en batería, lectura de batería hasta +4 % alta, consumo de 25–55 mW | U17 → TLV1117LV33 (C15578) | Esquemático · Firmware | ✅ Aplicado en esquemático y verificado (28-sep) · firmware pendiente | +| E-02 | `/ETH_RST` no tiene pull-down (y uno de 100 k nunca funcionaría) | El W5500 sale de reset en cada reset del MCU y gasta hasta 128 mA (lección F8) | R140 4.7 kΩ (C23162) a GND en U11.37 | Esquemático · Firmware | ✅ Aplicado en esquemático y verificado (28-sep) · firmware pendiente | +| A-09 | C78 (bulk de 5 V) es electrolítico de 85 °C / 2000 h | ≈ 1 año de vida en una caja de puerto | C78 → polímero C881921 | Esquemático | ✅ Aplicado en esquemático y verificado (28-sep) | +| H-02b | Stock justo: C103211 alcanza para 78 tarjetas, U19 hay 96, U18 hay 104; J14 requiere pre-orden | El pedido se detiene | C103211 → C25803; pre-ordenar J14 (y U18/U19 si ≳ 100) | Esquemático · Compras | ✅ Aplicado en esquemático y verificado (28-sep) · compras pendiente | + +--- + +## 3. Puertos — todos deben funcionar + +Cada puerto se revisó de punta a punta: conector → protección → pasivos → transceptor/PHY → pin del MCU o del módem → +periférico de firmware, contra hojas de datos. **Después de la pasada de puertos, todos funcionan como están dibujados.** +La revisión final confirmó cada cambio (pinouts, polaridades, EFCR, orientación del SM712, LEDs de J10 con el plano de Hanrun). + +!!! success "USB-C: CC de 5.1 kΩ en los dos conectores ✅" + J9 (Rcc1/Rcc2) y J11 (R100/R101) tienen 5.1 kΩ 1 % (C23186) de CC1 y CC2 a GND; D+ (A6/B6) y D− (A7/B7) unidos en las + dos filas; VBUS no retro-alimenta la tarjeta. No hubo cambios. + +### RS-485 (P11) + +| Aspecto | Detalle | +|---|---| +| **Cadena** | P11.1 A / P11.2 B / P11.3 GND → **D39 SM712** → R82 120 Ω + JP5 (terminación, abierto) · R145/R146 390 Ω (polarización, DNP) → **U14 THVD1410DR** → RO `/SER_RXA` → U10 canal A (SC16IS752) · DE/RE̅ ← `/RS485_DE` ← **U32 74LVC1G04** ← RTSA̅ (U10.1) | +| **Qué estaba mal** | El SP3485 solo tenía ±2 kV HBM y fail-safe con entradas abiertas. DE/RE̅ iban directo a RTSA̅, que queda en **ALTO** tras el reset: el transceptor **transmitía y bloqueaba el bus** durante el reset, en DFU o sin firmware. | +| **Qué cambió** | U14 → **THVD1410DR (C2671345)**, mismo pinout, ±18 kV IEC contacto, fail-safe con bus abierto, en corto o inactivo · **U32 inversor 74LVC1G04 (C7827) + C175 100 nF**: arranca en recepción · **D39 SM712 (C12067)** en P11 · **R145/R146 390 Ω (C23151), DNP**: opción de polarización | +| **Estado** | ✅ Esquemático aplicado y verificado | +| **Qué falta — layout** | L-49, L-50, L-59 | +| **Qué falta — firmware** | EFCR = 0x10 (dirección automática), vaciar el FIFO RX después de cada trama, CTS sin usar (sección 6) | +| **Compras** | Pre-ordenar THVD1410DR; conector hembra 15EDGK-3.5-03P | + +### RS-232 (P12) + +| Aspecto | Detalle | +|---|---| +| **Cadena** | P12.1 TX ← U15 T1OUT · P12.2 RX → U15 R1IN · P12.3 GND · **U15 TRS3232EIDR** (bomba C85–C88 100 nF, desacople C89) ↔ U10 canal B (TXB; R1OUT → R147 1 k → RXB) | +| **Qué estaba mal** | U15 estaba sobre la huella ancha (H-01), y el MAX3232 (no-E) **no tiene especificación ESD**. | +| **Qué cambió** | Huella angosta `SOIC-16_3.9x9.9mm` (H-01) · U15 → **TRS3232EIDR (C308878)**, mismo pinout, ±15 kV HBM, **±8 kV IEC contacto**, ±15 kV aire | +| **Estado** | ✅ Esquemático aplicado y verificado | +| **Qué falta — layout** | L-37 (huella, en el paso 0), L-51, L-59 | +| **Qué falta — firmware** | 8N1 sin control de flujo. El canal B lo comparten P12 y H4: usar uno a la vez. La tarjeta transmite por el pin 1 (tipo DTE; cruzar al RX del otro extremo). | + +### Header TTL H4 (UART B) + +| Aspecto | Detalle | +|---|---| +| **Cadena** | H4.1 3V3 · H4.2 `/SER_TXB` · H4.3 `/SER_RXB` · H4.4 GND | +| **Qué estaba mal** | H4.3 estaba en paralelo directo con la salida R1OUT del transceptor: un TX TTL externo peleaba contra una salida CMOS. | +| **Qué cambió** | **R147 1 kΩ (C21190)** entre R1OUT y RXB: el dispositivo externo gana (≤ 3.3 mA) | +| **Estado** | ✅ Esquemático aplicado y verificado | +| **Qué falta — layout** | L-51 (H4.3 se conecta del lado de U10, no en U15), L-59 | +| **Qué falta — firmware** | H4 **o** P12, nunca los dos a la vez | + +### Ethernet (J10) + +| Aspecto | Detalle | +|---|---| +| **Cadena** | U11 W5500 ↔ J10 HR911105A (C12074) · SPI2 PB12–PB15, INT̅ PC0, RST̅ PA15 + R140 4.7 k · 3V3_ETH de U12 con EN = PD2 (`/ETH_PWR_EN`) + R139 100 k | +| **Qué estaba mal** | J10 DNP en el PCB · el LED amarillo (ACT) estaba **invertido** (pines 11/12) y nunca encendía · J10.8 (retorno del capacitor Bob-Smith de 1000 pF) sin conectar · 3V3_ETH no se podía apagar (E-01) · `/ETH_RST` sin pull-down (E-02) · TOCAP/1V2O (E-04) | +| **Qué cambió** | J10 montado con `Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal` (D10) · **J10.12 = ánodo amarillo** (`/ETH_ACT_A`, R97 330 Ω), **J10.11 = cátodo** (`/ETH_ACTLED` → U11.27) · **J10.8 → GND** («Connect CHS GND to PCB Ground», plano de Hanrun) · E-01, E-02, E-04 aplicados · Y1 se queda con C95/C96 de 33 pF (E-03) | +| **Estado** | ✅ Esquemático aplicado y verificado | +| **Qué falta — layout** | Quitar DNP (paso 0), L-44, L-52, L-66 | +| **Qué falta — firmware** | Secuencia de encendido del W5500 y apagado en batería (sección 6) | + +### USB-C J11 (DFU del MCU) + +| Aspecto | Detalle | +|---|---| +| **Cadena** | GCT USB4085 (C7095263) · CC1/CC2 → R100/R101 5.1 k a GND · D+ A6+B6 → D14 → PA12 · D− A7+B7 → D15 → PA11 · VBUS → D16, D13 → `/LDO_IN` (D12 bloquea el regreso a SYS5V) · BOOT0 = SW2 + R98 | +| **Qué estaba mal** | Nada en el esquemático. Los ESD cuelgan de stubs (F-14, layout) y el cristal HSE estaba lejos (D-02). | +| **Qué cambió** | Nada en el conector · Y3 → cristal 3225 (D-02) | +| **Estado** | ✅ Funciona como está dibujado | +| **Qué falta — layout** | L-42, L-43, L-58, L-59 | +| **Qué falta — firmware** | El DFU de ROM (BOOT0 + NRST) necesita el HSE de 25 MHz; en el CDC de la aplicación, **desactivar el sensado de VBUS** (PA9 es TP9) | + +### USB-C J9 (módem) + +| Aspecto | Detalle | +|---|---| +| **Cadena** | USB4085 · CC1/CC2 → Rcc1/Rcc2 5.1 k a GND · D± → **U30 USBLC6-2SC6** → U19.27/28 · VBUS → U30.5 + U19.24 (solo detección) · U19.6 USB_BOOT → TP8, con **TP12 (1V8)** al lado | +| **Qué estaba mal** | Sin ESD (G-02) · no había un pad de 1.8 V junto a TP8 para forzar el modo de descarga | +| **Qué cambió** | U30 USBLC6-2SC6 (C7519) · **TP12** en `/1V8_MODEM` | +| **Estado** | ✅ Esquemático aplicado y verificado | +| **Qué falta — layout** | L-41, L-43, L-55, L-58, L-59, L-65 | +| **Qué falta — firmware** | J9 solo enumera con el módem encendido: comando de servicio que lo mantenga encendido. Descarga forzada: TP8–TP12 (1.8 V) al encender el módem; si no enumera, TP8–GND (los documentos de SIMCom se contradicen). | + +### Otros puertos + +| Puertos | Qué estaba mal / qué cambió | Estado | Qué falta | +|---|---|---|---| +| P1 24 V + ignición, P2 banco 5 V, P3 batería, P4 ventilador, P5 corte + JP6, P6 reset externo, P7/P8 NTC, P9 LED de panel, P10 RGB externo, J12 antena GNSS, J13 antena LTE, J14 nano-SIM, pads SWD, SW1/SW2, UART del módem, UARTs del GNSS | Ya corregidos por la pasada 1: F2 primero y D35 en P1 (V1-01, A-01, F-02), C-01 en J12, B-03 en J13, B-09 en J14, D36–D38 en P6/P7/P8, JP6 en P5. **UART del módem: K1 fuera (DNP), PC6 → R148 0 Ω → `/DIN_4G` directo (B-13).** P2 sin protección (A-10, aceptado). P9: LED de panel con Vf ≤ 2.2 V. P10: azul/verde más tenues, funcional. | ✅ | L-54 (R148), L-56 (fila de pads SWD), L-62 (revisar el bloque de P1), serigrafía L-59 | + +### Mapa I²C (I²C1, PB6/PB7, pull-ups de 4.7 k a `/3V3`, bus a 100 kHz) + +| Dirección (7 bits) | Dispositivo | Ref | Strap | +|---|---|---|---| +| 0x18 | SC7A20 acelerómetro (INT1 → PB9) | U26 | SDO/SA0 = GND | +| 0x20 | PCF8574T expansor (LEDs de batería, RGB) | U13 | A0–A2 = GND | +| 0x44 | SHT40 humedad/temperatura | U3 | fija | +| 0x48 | TMP102 del cargador | U29 | ADD0 = GND | +| 0x49 | TMP102 del módem | U31 | ADD0 = V+ | +| 0x4D | SC16IS752 doble UART | U10 | A1 = A0 = GND | + +**Sin colisiones.** El rango del SC16IS752 (0x48–0x57) se cruza con el de los TMP102 (0x48–0x4B), pero 0x4D queda fuera +de los cuatro valores posibles del TMP102. El DDC del ZED-F9P (0x42) no está conectado. El PCF8574 es de **100 kHz**, +así que todo el bus corre a 100 kHz; a esa velocidad el SC16IS752 alcanza para Modbus RTU a ≤ 38.4 kBd más RS-232 a ≤ 57.6 kBd. + +--- + +## 4. Instrucciones de corrección, una por una + +Cada punto tiene: **qué pasa** (con los números), **por qué importa**, **cómo se corrige** (esquemático / layout / +firmware) y **cómo se verifica**. Los pasos de layout L-1…L-48 son los de la §6 del informe; L-49…L-66 vienen de los +informes de puertos y de revisión final. En la sección 5 están como casillas. Coordenadas = coordenadas del PCB v6, +en mm. Vías 0.3 mm de barreno / 0.6 mm de pad, salvo que se diga otra cosa. + +### Blockers + +#### A-01 · Rama de 24 V sin fusible y D21 de 30 V + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente + +**Qué pasa.** Después de Q10 sale una rama `/24V` que **no pasa por F2** y alimenta a U20 (buck del módem, vía D20) +y a U2 (buck del ventilador). D21 (Schottky PMEG3050EP, 30 V) une `/MAIN5V` con la entrada del módem. Con el bus +cargando a 28.8 V, D21 ve **23.5 V en inverso** (78 % de su máximo); con 36 V durante 60 min (ISO 16750-2) ve +**30.7 V, más que sus 30 V**. U2 (MP1584) tiene 30 V de máximo absoluto. + +**Por qué importa.** La fuga de D21 crece con la temperatura: a 45 °C ≈ 7 mA / 0.17 W, a 60 °C ≈ 20 mA / 0.48 W → +el embalamiento térmico es plausible en una caja de puerto. Si D21 falla en corto pone `/24V` **sin fusible** en +`/MAIN5V` (VSYS del LTC4040, 6 V máx., U21, U17, F9P, MCU). Un corto en C10/C22/U2/U20/D22 jala corriente del fusible +del vehículo por cobre de 0.3–1.5 mm (riesgo de fuego y de arnés). D21, U20/D20 en la rama sin fusible y el modo de +falla de D21 son **nuevos en la v6**. + +**Qué se cambió en el esquemático (Claude, 28-sep):** + +- D20 (SS34) y D21 **eliminados**; `/VIN_MODEM` desaparece y U20.2, C127, C128 quedan en `/MAIN5V`. +- Bloque del ventilador **sin montar (DNP)**: U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21. + JP1 → `Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm` (puenteado, sin pieza de BOM) → `/5V_FAN` = `/VEH5V`. + El ventilador queda apagado en batería, como hoy. +- La rama `/24V` se queda sin cargas → **DNP**: Q10, DzG1, Rrp1, C10, C11, C22. Q23 queda como el único FET de polaridad inversa. +- **F2 → 0154003.DR de 3 A, LCSC C206912**, mismo porta-fusible Nano2, eléctricamente primero (ver V1-01). +- En la misma pasada van sus prerrequisitos: A-04 (R121), A-05 (C161/C162), los capacitores de entrada de U20 de F-03 + (C163/C164 22 µF + C165 220 µF) y los valores de lazo de B-02. + +**Cómo se corrige — layout (Michelle):** + +1. (L-5) F2 eléctricamente primero: P1.1 → F2 → D10 y Q23 en paralelo a la salida de F2. En el cobre de P1.1 no hay nada más que F2. +2. (L-6) Borrar el cobre `/24V`, `/SW_FAN`, `/BST_FAN` de las piezas que quedaron DNP (Q10, DzG1, Rrp1, C10, C11, C22 y el bloque U2). +3. (L-7) Borrar la pista de 48 mm de `/VIN_MODEM` desde D20 (136.5, 113.8) hasta U20. Donde estaba D21, unir las dos redes en cobre. +4. (L-7) `/MAIN5V` de Q7/U6 hasta U20.2 de **≥ 1.5 mm** todo el camino. + +**Firmware:** la política del ventilador no cambia; con A-01 el ventilador tiene alimentación exactamente cuando hay vehículo. + +!!! note "Registro para Leo" + U20 queda **antes** del corte P5. La intención de la ECO §A («el corte apaga todo») se cumple igual: al cortar + `/SYS5V` el MCU se apaga y R113 mantiene EN de U20 en bajo (corriente de apagado de µA). La única pieza sin fusible + que queda en `/24V_IN` es el pad Q10.D del Q10 sin montar; si algún día se vuelve a montar esa rama, primero mover + Q10.D a `/VIN_FUSED`. + +**Cómo se verifica.** Con el arreglo (verificador 1): entrada de U20 ≈ 5.25 V; camino de RS1 cargando a 1.43 k +más LTE TX = **2.08 A** (< 2.35–2.65 A de límite); U25 ≤ **2.95 A** contra 3.5 A nominales; corriente de F2: +0.74 A a 24 V, 1.48 A a 12 V, 1.97 A a 9 V. En el PCB: DRC sin cobre en `/24V` ni `/VIN_MODEM`. En banco: el +arranque en frío en batería de A-05 mide la entrada de U20. + +#### F-02 · Ignición cruda en capa interna junto a `/VEH5V` + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente + +**Qué pasa.** `/IGN_IN` (ignición cruda, 9–36 V) va de P1.3 (177.5, 135.0) a Rig1 (123.55, 50.675): 4.08 mm en F.Cu + +**106.47 mm en In2**, de 0.5 mm, con una vía. En In2 pasa a **0.221 mm** de una pista `/VEH5V` de 1.0 mm en +(147.34, 67.49); también a 0.250 mm de una vía GND, 0.291 mm de `/FAN_PWM`, 0.300 mm de una vía `/5V_FAN`, +0.340 mm de una vía `/VEH5V`, y en In1 a 0.305 mm de `/NTC2`. `/IGN_IN` no tenía TVS; D5 (BAT54) solo recorta +positivos y un pulso negativo ISO 7637-2 mete ≈ −27 mA a PA5 (el MCU admite −5 mA). + +**Por qué importa.** Es la geometría que tiró la tarjeta del **23-jul**: `VEH5V ↔ IGN_IN` a 0.2 mm en In2. La v6 está +a 0.02 mm de eso, en el mismo par de redes. Un solo defecto de capa interna pone 9–36 V (y pulsos de load dump) en +`/VEH5V` (entrada del LTC4040, clase 6 V, y todo el 5 V). Las capas internas **no se pueden inspeccionar ni retrabajar**. + +**Qué se cambió en el esquemático (Claude, 28-sep):** + +- TVS nuevo **D35 = SMBJ33A (C224019**, DO-214AA) de `/IGN_IN` a GND, para ir en P1.3. También recorta los pulsos + negativos a ≈ −1 V y elimina la inyección en PA5. +- La red se divide: `/IGN_IN` = {P1.3, Rig1.1, D35.1}; el tramo largo es `/IGN_SENSE`. +- Rig1 queda en 22 k 0603 (C88614). *(Aparte, D-05: Rigb1 → 2.2 k para leer la ignición por ADC.)* + +**Cómo se corrige — layout (Michelle):** + +1. (L-8) Mover **Rig1** para que el cobre de P1.3 a Rig1.1 mida **≤ 3 mm**, solo en F.Cu. +2. (L-8) Poner D35 de `/IGN_IN` a GND justo en P1.3. +3. (L-8) El tramo largo Rig1.2 → MCU es ahora `/IGN_SENSE` (clase Default). Rig2, Rigb1, C9 y D5 se quedan junto al MCU. +4. (L-8) Borrar la pista vieja de `/IGN_IN` en In2 (106.5 mm) y la vía de In1 en (127.3, 50.5). +5. (L-9) Sacar `/24V_IN` de In1: la pista de 27 mm de (167.5, 128.65) a (143.25, 121.75) pasa a F.Cu por la orilla + sur. Si tuviera que ir en In1: ≥ 1.0 mm de cualquier red de bajo voltaje y nada cruzándola. + +Por qué basta: con Rig1 en P1.3, si el tramo largo se llegara a puentear con una red de 5 V, la corriente queda +limitada a (36 − 5 V)/22 k = 1.4 mA (2.5 mA a 58 V). C9 junto al MCU mantiene τ = 0.25 ms. + +**Firmware:** leer PA5 por ADC (sección 6). + +**Cómo se verifica.** Rellenar zonas + DRC con las reglas nuevas (F-01): desaparecen todas las violaciones internas de +`/IGN_IN`. Ojo: KiCad reporta una sola violación entre el tramo largo de In2 y `/VEH5V` (la vía a 0.340 mm), aunque las +pistas paralelas están a 0.221–0.240 mm; mover el tramo a P1.3 elimina todo el tramo de In2 de todos modos. + +#### F-01 · El DRC no veía ningún espaciado de 24 V + +**Estado:** ✅ Reglas aplicadas en el proyecto y verificadas (28-sep) · Cobre: pendiente (layout) + +**Qué pasa.** En `.kicad_pro` los patrones de HV24 sin «/» inicial no coincidían con nada: **solo `/24V_IN` estaba en +HV24**; `/24V`, `/IGN_IN`, `/VIN_PROT`, `/VIN_FUSED`, `/SW_PWRIN`, `/RF_LTE`… estaban en Default. Faltaban las clases +**RF** y **PWR_MODEM** (se pierden al guardar desde la interfaz). Además, la regla «Minimum clearance 1» de 0.15 mm, sin +capa, es la última que aplica y por eso **anula todas las demás** (Default 0.2 mm, zonas 0.3 mm). Prueba: los rellenos +guardados quedan a 0.1505 mm de cualquier red que no sea HV24. + +**Por qué importa.** El «DRC 0 errores» no podía ver una repetición del 23-jul. F-02 es exactamente eso, y pasó el DRC +con 0 errores. + +**Qué se cambió en el proyecto (Claude, 28-sep, D18).** Netclasses por nombre exacto, tal como quedaron aplicadas: + +| Clase | Redes | Separación | Pista | Vía | +|---|---|---|---|---| +| HV24 | `/24V_IN` `/VIN_FUSED` `/VIN_PROT` `/24V` `/IGN_IN` `/Q10_GATE` `/Q23_GATE` `/SW_PWRIN` `/BOOT_PWRIN` `/SW_FAN` `/BST_FAN` | 0.3 (reglas por capa abajo) | 1.0 | 0.8/0.4 | +| PWR_HI | `/BAT_PLUS` `/SW_BAT` `/MAIN5V` `/VEH5V` `/SYS5V` `/VIN_SW` | 0.15 | 1.5 | 0.8/0.4 | +| PWR_MODEM | `/VBAT_MODEM` | 0.15 | 1.5 | 0.8/0.4 | +| PWR_MID | `/SW_5V` `/SW_IN` `/5V_FAN` `/FAN_RET` | 0.15 | 0.6 | 0.8/0.4 | +| RF | `/RF_GNSS` `/RF_ANT_GNSS` `/RF_LTE` `/RF_ANT_LTE` | 0.2 (gap CPWG) | 0.3 (ancho CPWG; valor final con la calculadora de JLC) | 0.6/0.3 (sin vías previstas) | +| Default | todo lo demás (incluye `/3V3_ETH`, `/EN_FAN`, `/EN_PWRIN`, `/SW_MODEM`, `/BST_MODEM`) | **0.15** | 0.2 | 0.6/0.3 | + +Diferencias con la tabla del informe, que es anterior a A-01: `/VIN_MODEM` ya no existe; `/SW_MODEM` y `/BST_MODEM` +quedan en Default porque U20 ahora trabaja desde `/MAIN5V` (≤ 5.5 V) y en HV24 darían errores falsos alrededor de U20. +`/SW_FAN`, `/BST_FAN`, `/24V` y `/Q10_GATE` **siguen en HV24**, porque las huellas de U2 y Q10 quedan en la tarjeta como +DNP y llevarían voltaje del vehículo si algún día se montaran. El verificador lo revisó y lo dio por correcto. + +Reglas del `.kicad_dru`, en este orden (la última que aplica gana): piso de **0.15 mm** entre redes que no son HV24 ni RF · +**HV24 ↔ HV24 0.2 mm** · **HV24 ↔ otras 0.3 mm en capas externas** · **HV24 ↔ otras 0.5 mm en capas internas** · +pad a pad 0.15 mm dentro de las huellas de U2/U20/U25. + +??? note "Texto exacto del `.kicad_dru` (informe §2 4-F)" + ``` + (rule "Floor 0.15 (non-HV24, non-RF)" + (condition "A.NetClass != 'HV24' && B.NetClass != 'HV24' && A.NetClass != 'RF' && B.NetClass != 'RF'") + (constraint clearance (min 0.15mm))) + (rule "HV24 to HV24" + (condition "A.NetClass == 'HV24' && B.NetClass == 'HV24'") + (constraint clearance (min 0.2mm))) + (rule "HV24 outer" + (layer outer) + (condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'") + (constraint clearance (min 0.3mm))) + (rule "HV24 inner" + (layer inner) + (condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'") + (constraint clearance (min 0.5mm))) + (rule "HV24 IC land patterns" + (layer outer) + (condition "A.Type == 'Pad' && B.Type == 'Pad' && ((A.memberOfFootprint('U2') && B.memberOfFootprint('U2')) || (A.memberOfFootprint('U20') && B.memberOfFootprint('U20')) || (A.memberOfFootprint('U25') && B.memberOfFootprint('U25')))") + (constraint clearance (min 0.15mm))) + ``` + +De dónde salen los valores: IPC-2221B (fila 51–100 V, porque el riel llega al clamp de 53.3 V y a 58 V de load dump +suprimido) pide 0.10 mm interno y 0.13 mm externo con máscara. Los **0.5 mm internos** son margen por defectos/CAF +aprendido el 23-jul; los **0.3 mm externos** bajo máscara (2.3 × IPC) caben entre las filas de pines SO-8. El piso debe +quedarse en **0.15 mm**: con Default a 0.2 mm fallarían 471 pares de elementos. La regla de texto de serigrafía y las +tres reglas T15 de ancho **no se tocaron** en esta pasada (ver L-3). + +**Cómo se corrige — layout (Michelle):** + +1. (L-1…L-4) Poner el stackup real, revisar que las clases estén como arriba, ajustar la regla de texto y las T15, y + comprobar con *Inspeccionar → Resolución de separación* (ver sección 5-A). +2. Rellenar todas las zonas y correr el DRC. En una copia del PCB sin actualizar, con las reglas nuevas, salieron **161 + errores de separación**: **149 son proximidades del relleno** (se van al rellenar) y **12 son cobre real** (lista en 5-A). +3. (L-10) Corregir los puntos externos: pista `/VIN_PROT` de 1.5 mm contra `/VEH5V` de 0.8 mm → **≥ 0.5 mm**, y tapar (tent) + la vía `/VEH5V` de ahí; `/USB_VBUS` lejos de Q23 (≥ 0.3 mm de `/Q23_GATE` y `/VIN_PROT`); quitar el cuello GND de U20 + (F-03); `/SW_PWRIN` y `/BST_MODEM` a ≥ 0.3 mm de pistas GND. **Tapar todas las vías** salvo las de prueba. + +**Cómo se verifica.** DRC con las reglas nuevas: **0 errores de separación**. Después de cada guardado desde la interfaz, +revisar que las netclasses sigan ahí. + +#### H-04 · U25 se ensamblaría como AP64350 (40 V) + +**Estado:** ✅ Aplicado en la librería y verificado (28-sep) · Campo en PCB: pendiente (layout) + +**Qué pasa.** 14 huellas de la v6 heredadas de easyeda (`Drogheda-v6.pretty`) traen un campo `LCSC Part`. En U25 decía +**C2071691 (AP64350, 40 V)**, mientras que `LCSC` dice C524806 (TPS54360B, el correcto). Fabrication Toolkit busca +primero `LCSC Part` y usa el primero que no esté vacío. U20 y U25 comparten la huella +`SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP`. + +**Por qué importa.** Los dos chips tienen el mismo pinout y el mismo FB de 0.8 V, así que las tarjetas **pasan el banco** +y luego fallan en el primer transitorio de más de 40 V detrás de un clamp de 53 V. Riesgo de daño. + +**Qué se cambió (Claude, 28-sep):** `LCSC Part` borrado de +`Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod`. U20 (C2071691) y U25 (C524806) ahora se resuelven por +su campo `LCSC`. Los demás `LCSC Part` de la librería se revisaron contra sus piezas y están bien. + +**Cómo se corrige — layout (Michelle):** la copia de U25 en el PCB **todavía trae el campo**. Actualizar la huella de +**U25 desde la librería** (solo esa referencia), o borrar el campo en *Propiedades de la huella*. Debe quedar solo +`LCSC` = C524806. + +**Cómo se verifica.** Generar BOM/CPL con Fabrication Toolkit y confirmar que U25 = **C524806** en el BOM y en la +vista previa de JLC. + +#### C-01 · Bias de antena GNSS sin límite de corriente + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente · Firmware: pendiente + +**Qué pasa.** El bias de la antena (`/VCC_RF_GNSS`: U18.7 → L21 → antena) no tenía limitador ni supervisor. L21 es de +68 nH y **400 mA**; VCC_RF del ZED-F9P es de 50 mA en operación y **300 mA de máximo absoluto**. u-blox exige un límite +(«se requiere una resistencia de 10 Ω»). ANT_DETECT (pin 4) y ANT_SHORT_N (pin 6) son **entradas** del F9P que en la v6 +solo iban a PC1/PC2 (entradas del MCU): nadie las manejaba. ANT_OFF (pin 5) estaba al aire. + +**Por qué importa.** Un coaxial aplastado o mojado (la clase de falla de campo **H0005/H0014**) deja que U21 (límite +≈ 0.6–0.8 A) empuje más de lo que aguantan VCC_RF y L21, el 3V3_GNSS se cae en un ciclo de brown-out del F9P, y la +«telemetría de antena» en PC1/PC2 nunca lo reporta. Camino de daño de hardware. + +**Qué se cambió en el esquemático (Claude, 28-sep):** **U28 = TPS2552DBVR (C46506**, SOT-23-6): + +| Pin | Conexión | +|---|---| +| 1 IN | `/3V3_GNSS`, con **C176 100 nF (C14663)** junto al pin (revisión final, N2) | +| 2 GND | GND | +| 3 EN̅ | `/GNSS_ANT_OFF` = U18.5 ANT_OFF, con **R135 100 k (C25803) a GND** → antena encendida por defecto | +| 4 FAULT̅ | `/GNSS_ANT_SHORT_N` (U18.6 + PC2), con **R136 10 k (C25804) a `/3V3_GNSS`** | +| 5 ILIM | a IN → **75 mA típico** | +| 6 OUT | red nueva **`/ANT_BIAS`** = L21.2 + C144 + C145 | + +U18.7 (VCC_RF) queda **sin conectar**. ANT_DETECT no se implementa (la antena abierta se infiere del C/N0). En corto, +el TPS2552 entrega corriente constante (≈ 0.25 W a 3.3 V); FAULT̅ tiene 7.5 ms de filtro. El símbolo del TPS2552 se +dibujó a mano (KiCad no lo trae) y quedó embebido en el esquemático. + +**Cómo se corrige — layout (Michelle):** + +1. (L-33) U28 cerca de L21/J12; `/ANT_BIAS` a **≥ 1 mm** de la línea RF con una franja de GND cosida entre ambas (o en In2 + después de desacoplar con 100 pF + 100 nF); L21 toma la línea sin stub en J12; mover D27 sobre el pad de J12 (sin stub). +2. (L-64) **C176 a ≤ 2 mm del pin 1 (IN) de U28**, en la misma capa; su pad GND a un plano con vía a ≤ 1 mm, y el pin 2 de + U28 en la misma zona de GND. `/3V3_GNSS` llega a U28.1 pasando por el pad de C176. + +**Firmware:** `CFG-HW-ANT_CFG_VOLTCTRL` / `SHORTDET` = 1 en el F9P; PC2 pasa a ser una entrada real de «antena en +corto» (bajo = corto o riel apagado), sin pull del MCU. PC1 se queda en alta impedancia. + +**Cómo se verifica.** Prueba de corto de antena en banco (sección 10). + +#### B-03 · ESD unidireccional en la antena LTE + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente + +**Qué pasa.** D28 (onsemi ESD9L5.0ST5G, C82326) es un TVS **unidireccional de 5 V** (ruptura 5.4 V), en línea con la +antena LTE a 1.8 mm de J13, en una línea sin DC. El voltaje pico del transmisor a 50 Ω es 4.47 V en LTE (23 dBm) y +**14.1 V en GSM** (33 dBm); con ROE 3:1, 6.7 / 21.2 V. SIMCom pide un ESD **bidireccional**. + +**Por qué importa.** El diodo conduce en cada semiciclo negativo (≈ −0.6 V), aun en LTE, y entra en avalancha en los +picos de GSM: recorte, emisiones espurias (homologación), pérdida de potencia, estrés del PA; D28 se calienta y puede +fallar en corto (antena muerta). + +**Qué se cambió en el esquemático (Claude, 28-sep, D5):** D28 → **Littelfuse PESD0402-240 (C1975527)**: bidireccional, +24 V de trabajo, 0.25 pF (|Γ| ≈ 0.07 a 1.9 GHz), huella **`Diode_SMD:D_0402_1005Metric`**. D27 en la línea GNSS se queda +(bias de 3.2 V, sin TX: ahí un unidireccional de 5 V es correcto). + +**Cómo se corrige — layout (Michelle, L-31):** la huella cambia a 0402 con el *Update PCB* (paso 0); dejarla en el mismo +lugar en línea, junto con el re-ruteo del LTE de F-06. + +**Cómo se verifica.** BOM/CPL: D28 = C1975527 en 0402. El enlace LTE se valida con la prueba G3 (sección 10). + +#### A-02 · Cobre y colocación del cargador LTC4040 (U6) + +**Estado:** Pendiente — layout (no tiene parte de esquemático) + +**Qué pasa** (medido por el verificador 1): + +| Punto | v6 hoy | Objetivo (ECO D2) | +|---|---|---| +| `/SW_BAT` U6.21/22 → L6.1 | **0.5 mm × 11.89 mm**, con cuellos de 0.25 y 0.30 mm en los pines, 0 vías | polígono ≥ 2 mm | +| `/BAT_PLUS` P3 → L6.2 | 1.0 mm × 21.27 mm | ≥ 1.5 mm + vías | +| `/BAT_PLUS` L6.2 → U6.23 | 1.0 mm, luego 0.5 mm × 10.49 mm, luego 0.25 mm × 5.38 mm | toma Kelvin desde L6.2/CBAT | +| EP de U6 (2.65 × 3.65 mm) | **0 vías** | ≥ 9 vías | +| L6.1 ↔ U6.21/22 | **8.65 mm** | ≤ 5 mm | +| C30 / C31 → U6.6 (VIN) | 7.20 / 6.18 mm | ≤ 3 mm | +| C32 / C33 / C34 → U6.1 (VSYS) | 3.90 / 3.44 / 4.74 mm, tras cuellos de 0.30 mm | ≤ 2 mm, polígono | +| C35 (CBAT) → L6.2 | 20.2 mm | junto a L6.2 / pin BAT | +| In1 bajo U6 | cortado por 7 tramos de `/VFB_BST` + `/IGATE` + `/CHRG_*` | sólido ≥ 5 mm alrededor | +| Sensor de temperatura a ≤ 10 mm | ninguno; U3 (SHT40) a **71.4 mm** | ≤ 10 mm (F-51) | + +**Por qué importa.** Calentamiento IPC-2221 en `/SW_BAT` de 0.5 mm: **+32 °C a 2.42 A** y **+80 °C a 3.6 A** de +respaldo; la misma corriente en 2.0 mm da +8 °C. El LTC4040 solo tiene apagado por sobretemperatura, no regula la +corriente de carga por temperatura. Repite la **lección F5** de la V5.5 (ECO D2 / EMC 🔴 #1 y #2); no se cumple R5 +(≥ 1.3 A sin ciclado térmico). + +**Cómo se corrige — layout (Michelle):** + +1. (L-53/L-63) L6 usa ahora la huella **`Drogheda-v6:IND-SMD_MWSA0804S`** (pads 2.75 × 5.5 mm a ±3.375 mm); medir las + distancias contra los pads nuevos. +2. (L-11) Re-agrupar U6: pad 1 de L6 a **≤ 5 mm** (orilla) de los pines 21/22; C30/C31 a ≤ 3 mm del pin 6; + C32/C33/C34 **y C161/C162 (47 µF 1210 nuevos, A-05)** a ≤ 2 mm de los pines VSYS 1/24, con sus GND sobre el cobre del EP; + C35 (o un 22 µF 0805 extra, C86817) en L6.2 junto al pin BAT 23. L6 no puede quedar sobre (193.2, 90.3): ahí vuelve MH4 (G-01). +3. (L-12) `/SW_BAT`: polígono en F.Cu de **≥ 2 mm** desde la salida combinada de los pines 21+22 hasta L6.1, compacto + (es nodo de conmutación), sin cuellos de 0.25/0.30 mm después de la salida de los pines. +4. (L-13) `/BAT_PLUS`: P3 → L6.2 de ≥ 1.5 mm en F.Cu o polígono; si algún tramo va interno, ≥ 4 vías por cambio de capa + y ≥ 2.5 mm (1.5 × 1.65 por el cobre interno de 0.5 oz). El sensado del pin BAT (U6.23) como toma Kelvin desde L6.2/C35. +5. (L-14) `/MAIN5V`: polígono desde los pines 1/24 de U6 sobre C32–C34 hasta el drenador de Q7, ≥ 2 mm, sin cuellos de 0.3/0.5 mm. +6. (L-15) EP de U6: **9 vías, 3 × 3 a 0.9 × 1.2 mm de paso**, 0.3/0.6 mm, tapadas/rellenas (via-in-pad de JLC) o con + máscara; conexión del pad a la zona: **sólida**. +7. (L-16) In1 e In2 de GND **sólidos ≥ 5 mm** alrededor de U6 y L6: sacar de In1 los 7 tramos de `/VFB_BST`, `/IGATE` y `/CHRG_*` en esa zona. +8. (L-17) U29 (TMP102) va entre U6 y L6 (ver F-51). + +**Cómo se verifica.** Cámara térmica sobre U6/L6 a 1.4 A de carga y a 2.3 A de respaldo, 1 h cada una; pinza DC en el +cable del paquete + IR en U6/L6 durante la carga (seguimiento de H0008). Aceptación de layout: EP con 9 vías y +`/SW_BAT` ≥ 2 mm. + +#### A-03 · R50 programa 2.42 A de carga + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) + +**Qué pasa.** RPROG = 2000 V / ICHG, con ±5 %; máximo del LTC4040: 2.5 A. + +| R50 (1 %) | ICHG mín. | nom. | máx. | +|---|---|---|---| +| 825 Ω (antes, C50214) | 2.280 A | 2.424 A | **2.571 A** (más que 2.5 A) | +| **1.43 kΩ (ahora)** | **1.316 A** | 1.399 A | 1.483 A | +| 1.5 kΩ (ECO C, C22843) | 1.254 A | 1.333 A | 1.414 A | + +**Por qué importa.** Con 825 Ω la v6 repetía **H0008** (V5.5 con el mismo R50: ≈ 1.3 A promedio, 8.5 h hasta terminar, +carga pulsada), ponía a U25 en el límite de RS1 (≈ 2.5 A) cada vez que cargaba, y en la esquina alta pasaba el máximo +del chip. A 1.4 A la pérdida del chip baja ≈ 3 veces. **Lección F4.** + +**Qué se cambió en el esquemático (Claude, 28-sep, D3):** **R50 → 1.43 kΩ 1 % 0603, LCSC C22840** (Extended). Es el mayor +valor E96 cuyo mínimo en el peor caso es ≥ 1.3 A. + +**Cómo se verifica.** Pinza DC en el cable del paquete durante la carga: debe quedar en 1.316–1.483 A (sección 10). + +#### H-01 · U15 sobre la huella equivocada + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente + +**Qué pasa.** U15 era MAX3232**ESE** (C15846), SO-16 **angosto**. En el PCB está sobre `SOIC-16W_7.5x10.3mm`, con filas de +pads a 9.3 mm: las patas terminan 0.5–0.6 mm antes de llegar a los pads. Es una **regresión de la v6**: la V5.5 se +fabricó con la huella angosta; se rompió en la re-sincronización del 02-sep. + +**Por qué importa.** RS-232 (P12) muerto en todas las tarjetas; JLC rechaza el trabajo o coloca una pieza que no se +puede soldar. + +**Qué se cambió en el esquemático (Claude, 28-sep):** huella → `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`. En la pasada de +puertos U15 pasó además a **TRS3232EIDR (C308878)**, mismo pinout y misma huella angosta, con ESD IEC (sección 3). El campo +viejo de los esquemáticos V5.x también hay que corregirlo (sección 11). + +**Cómo se corrige — layout (Michelle):** la huella cambia con el *Update PCB* (paso 0). Luego (L-51) **C85–C88 (bomba) a +≤ 3 mm** y **C89 (desacople) a ≤ 2 mm de U15.16**, y re-rutear localmente. *Corrección a L-37: C84 es el desacople de U14, +no de U15.* + +**Cómo se verifica.** Vista 3D y vista previa de JLC: patas sobre los pads; BOM: U15 = C308878 en SOIC-16 de 3.9 mm. + +#### H-02 · U10 y R53 sin stock + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Compras: re-verificar el día del pedido + +**Qué pasa** (base de JLC, 28-sep). U10 C729142 (SC16IS762IPW): **15 piezas**. R53 C131054 (499 k 1 %): **6 piezas**, y el +mínimo de JLC es 20: no se cumple para ninguna cantidad de tarjetas. + +**Por qué importa.** JLC dejaría U10 (puente RS-485/RS-232) y R53 sin colocar. **R53 fija el voltaje del boost de +respaldo** del LTC4040: sin ella el respaldo no regula. + +**Qué se cambió en el esquemático (Claude, 28-sep):** + +- **U10 → C57156, SC16IS752IPW,128**: mismo TSSOP-28, pinout y registros; U10 trabaja en modo I²C, donde 752 y 762 son idénticos. +- **R53 → C177479**, HKR RCT03499KFLF (499 k, 1 %, 100 ppm, 0603). Los dos son reemplazos directos. + +**Compras:** re-verificar stock el día del pedido. + +**Cómo se verifica.** BOM con C57156 y C177479, y stock suficiente para 20 tarjetas en el carrito de JLC. + +#### G-01 · Barrenos de montaje distintos a la V5.5 + +**Estado:** Pendiente — layout (Blocker por la decisión D11) + +**Qué pasa.** El contorno es igual al de la V5.5 (140.00 × 100.00 mm), pero los barrenos no: la v6 tiene MH5 (65.2, 45.3), +MH6 (65.2, 135.3), MH7 (195.2, 45.3) y MH8 (195.2, 135.3), un patrón de 130 × 90 mm. La V5.5 tenía **MH4 en (193.2, 90.3)**: +en la v6 ese punto cae **dentro del courtyard de L6**. Faltan también los barrenos de la **abrazadera del disipador del +módem** (MH11 en (168.3, 84.6) y su pareja); el punto de MH11 queda ahora a 0.6 mm del courtyard de U19. En MH6 hay una +pista `/3V3` a 3.55 mm del centro. + +**Por qué importa.** En un gabinete barrenado para la V5.5 la v6 no se puede atornillar del lado derecho, y un standoff +metálico en (193.2, 90.3) presionaría L6 / `/BAT_PLUS`. Sin la abrazadera no hay disipador del módem (compuerta térmica T1). +Decisión D11: la v6 usa la placa base existente. + +**Cómo se corrige — layout (Michelle, L-40):** + +1. Restaurar **MH4 (Ø3.2, NPTH) en (193.2, 90.3)**. L6 se mueve de todos modos por A-02. +2. Poner la **pareja de barrenos de la abrazadera del disipador** junto a U19. La posición de MH11 de la V5.5 ya no sirve + (queda a 0.6 mm de U19): hay que elegir una nueva. +3. Dejar un radio **≥ 4.0 mm sin cobre** en F.Cu y B.Cu alrededor de cada barreno (mover ≥ 0.5 mm la pista `/3V3` de MH6), + o especificar rondanas de nylon. + +**Cómo se verifica.** Sobreponer los barrenos al dibujo de la placa base de la V5.5; en el visor 3D, nada de cobre ni +componentes dentro del radio de las rondanas. + +### Majors + +#### V1-01 · D10 antes del fusible derrota la protección de polaridad + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente + +**Qué pasa.** D10 (SMBJ33A, C224019) estaba en `/24V_IN`, **antes de F2** y antes de los FET de polaridad inversa Q10/Q23. + +**Por qué importa.** Si P1 se conecta al revés, D10 queda en directa sobre el arnés sin fusible de tarjeta: aguanta la +corriente del fusible del arnés hasta que falla, normalmente en corto. + +**Qué se cambió en el esquemático (Claude, 28-sep):** F2 eléctricamente primero: **P1 → F2 → D10 ∥ Q23** (D10 pasa a la +salida de F2, `/VIN_FUSED` = {F2.2, D10.1, Q23.2}). Mismo F2 que A-01 (C206912). Así, una conexión al revés **funde el +fusible Nano2**, que se cambia sin soldar; Q23 se queda apagado. El pulso 1 de ISO 7637-2 es ≈ 7 % del I²t de un Nano2 de 3 A. + +**Cómo se corrige — layout (Michelle, L-5):** P1.1 → F2 → D10 y Q23 en paralelo; en el cobre de P1.1 solo F2. + +**Cómo se verifica.** En el PCB, D10 conectado a `/VIN_FUSED` y nada más que F2 en P1.1. + +#### D-01 · U24 alimenta al F9P apagado a través de RXD2 + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente · Firmware: pendiente + +**Qué pasa.** U24 (74LVC2T45) tiene el lado B en `/3V3` (siempre encendido) y manejaba RXD2 del F9P (U18.26), aunque el +F9P estuviera apagado (PA1 bajo). El F9P admite en sus entradas VCC + 0.5 V: con VCC = 0, un alto de 3.3 V lo excede por +2.8 V. Caminos menores al mismo receptor: Rdfu1 22 k (≈ 0.12 mA), pull-up interno de PA10 (≈ 0.5 mA si se deja activo), +pull-up de PC7 por R106 (≈ 70 µA). + +**Por qué importa.** Con el módem encendido y PA1 bajo, el riel del F9P quedaba pre-polarizado (≈ 2–2.7 V, estimado): +no hay rampa limpia, el **reinicio del F9P por corte de energía falla sin avisar** y la estructura ESD de RXD2 sufre. Es el +mismo mecanismo de la lección de FW 0.5.5/0.5.6 (UART en alto que mantenía vivos los rieles de la V5.5). + +**Qué se cambió en el esquemático (Claude, 28-sep):** + +- **U27 = Nexperia 74LVC1G125GV,125 (C12518**, SOT-753): 1 OE̅ = GND, 2 A = `/DOUT_4G`, 3 GND, + 4 Y = red nueva `/DOUT_4G_F9P` → U18.26, 5 VCC = **`/3V3_GNSS`**; **C170 100 nF (C14663)** en VCC. +- PC7/R106 se quedan en `/DOUT_4G` (para no perder MODEM_STATUS ni la toma de RTCM con el F9P apagado). +- **Rdfu1 22 k → 100 k (C25803)**. + +**Cómo se corrige — layout (Michelle):** U27 + C170 junto a U18.26, alimentado de `/3V3_GNSS`; re-ruteo corto en U18.26. + +**Firmware:** con U27 montado, reiniciar solo el F9P con el módem encendido ya es seguro. Se mantienen las reglas de +0.5.5/0.5.6: con PA1 bajo, PA2 entrada sin pull, PA10 sin pull, PC7 sin pull-up, PC12 liberado, PA7/PC3 sin pull-up. + +**Cómo se verifica.** En banco: `/3V3_GNSS` **< 0.3 V** con PA1 en bajo y el módem encendido. + +#### A-04 · El 5 V de U25 queda abajo del arranque del cargador + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Firmware: pendiente + +**Qué pasa.** Vout = 0.8 V · (1 + R121/R122), con R122 = 10.2 k y Vref de 0.792–0.808 V. + +| R121 | mín. | nom. | máx. | +|---|---|---|---| +| 53.6 k (antes) | 4.871 V | **5.004 V** | 5.140 V | +| **57.6 k (ahora)** | **5.176 V** | **5.318 V** | **5.463 V** | + +El firmware 0.6.0 arranca la carga con `CHG_RAIL_ON` = 5.05 V: con 53.6 k el nominal quedaba abajo. La esquina alta con +57.6 k queda 37 mV abajo del máximo de operación del LTC4040 (5.5 V). + +**Por qué importa.** Con los umbrales actuales **la mayoría de las unidades v6 nunca empezaría a cargar** (R5 y R3′ +fallan), y el margen bajo picos del módem es delgado cuando el módem pasa a `/MAIN5V` (A-01). **Lección F7.** + +**Qué se cambió en el esquemático (Claude, 28-sep, D4):** **R121 → 57.6 k 1 % 0603, LCSC C23082**. + +**Firmware:** `V5_PFI` 4.60 → **4.40 V** (PFI del LTC4040: bajando 4.27 / 4.40 / 4.54 V, subiendo 4.38 / 4.51 / 4.66 V); +se mantienen `CHG_RAIL_ON` 5.05 / `CHG_RAIL_OFF` 4.90; calibrar VDDA con VREFINT. + +**Cómo se verifica.** Medir `/VEH5V` con 24 V de entrada: 5.18–5.46 V (nominal 5.32 V); con FW 0.7.x el cargador arranca. + +#### B-02 · Bulk y compensación de VBAT_MODEM + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente + +**Qué pasa.** C130 y C131 eran electrolíticos SamYoung MVG (85 °C / 2000 h, ≈ 8 000 h a 65 °C locales), no polímero. +La capacidad de baja ESR a la salida era solo ≈ 14 µF efectivos (SIMCom pide ≥ 300 µF). La compensación (R116 14 k / +C141 3.3 nF / C142 47 pF) era la fila de **5.0 V** de la tabla del AP64350, pero la salida es de 3.8 V. + +| Condición (modelo del verificador 1) | Caída en pico GSM de 2 A | LTE 0.7 A | +|---|---|---| +| Batería, MVG nuevos | 0.28 V (VBAT 3.52 V) | 0.08 V | +| Batería, MVG fríos o envejecidos | **0.52 V (3.29 V < 3.4 V mín.)** | 0.13 V | +| Batería, polímero + 113 k / 6.8 nF / 56 pF | 0.06 V | 0.02 V | + +**Por qué importa.** El día 1 funciona (con solo LTE en batería); en frío o con los capacitores envejecidos, los picos +GSM bajan VBAT a menos de 3.4 V → **«módem oscuro» probable en un año**. Lección F1. + +**Qué se cambió en el esquemático (Claude, 28-sep)** — todo junto (113 k solo es válido con polímero): + +- C130, C131 → **C881921** (Lelon OVZ 220 µF / 16 V polímero, 105 °C / 2000 h, misma lata 6.3 × 7.7). +- R116 14 k → **113 k 1 % (C22862)**; C141 3.3 nF → **6.8 nF X7R 0402 (C1542)**; C142 47 pF → **56 pF C0G 0402 (C1572)**. +- **C166 y C167, 22 µF 0805 (C86817)** nuevos en L20.2. Resultado: margen de fase ≈ 60°. + +**Cómo se corrige — layout (Michelle, L-36):** polígono de `/VBAT_MODEM` en F.Cu de **≥ 3 mm** de L20.2 → C130 → C131 → +C132–C136 → pines 55/56/57 de U19 (a los tres pads, sin cuello de 0.5 mm); **C131 a ≤ 5 mm** de los pads; C166/C167 +a ≤ 3 mm de L20.2. + +**Cómo se verifica.** Escalón de carga 0.1 → 2 A en VBAT_MODEM: caída **≤ 150 mV**, sin oscilación. + +#### E-01 · 3V3_ETH no se puede apagar + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente · Firmware: pendiente + +**Qué pasa.** El EN de U12 (MP1584EN, 3V3_ETH) estaba unido a su VIN (`/SYS5V`): el W5500 estaba encendido siempre que +había `/SYS5V`, en batería también. El W5500 consume 128 mA (100M), 75 mA (10M) y 13 mA apagado por software. + +**Por qué importa.** Aun los 13 mA de apagado cuestan ≈ 57 mW de batería, más que todo el piso de sueño de 20–50 mW. +Es la **lección F8** repetida. + +**Qué se cambió en el esquemático (Claude, 28-sep, D8):** red nueva **`/ETH_PWR_EN`**: U12.2 (EN) → U16 pad 54 (**PD2**), +con **R139 100 k (C25803) a GND** → apagado en reset, DFU y batería; PD2 en 3.3 V lo enciende. U12.7 (VIN) sigue en `/SYS5V`. + +**Cómo se corrige — layout (Michelle, L-38):** R139 junto a U12.2 y la pista `/ETH_PWR_EN` hasta el pad 54 del MCU. + +**Firmware:** PD2 en bajo al arrancar y en batería; RSTn en bajo ≥ 500 µs antes de liberarlo; pines de SPI2 en bajo o +alta impedancia mientras 3V3_ETH esté apagado (sección 6). + +**Cómo se verifica.** Con PD2 en bajo, 3V3_ETH apagado; en respaldo, la corriente de batería no incluye al W5500. + +#### A-05 · Presupuesto de corriente en batería + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente · Firmware: pendiente + +**Qué pasa.** En batería todo sale del boost del LTC4040 por `/MAIN5V` (VSYS 4.60 / 4.79 / 4.99 V). Con un pico GSM de +2 A y todo lo demás encendido, `/MAIN5V` pide **2.25–2.33 A (91–97 % de los 2.5 A garantizados)**. CSYS = 104 µF +nominales, **≈ 57–69 µF efectivos** a 4.8 V, abajo de los 75 µF que pide la hoja de datos. + +**Por qué importa.** Al tocar el límite, VSYS cae: primero se sale de regulación U17, luego VBAT_MODEM baja de 3.4 V — +el síntoma «módem oscuro en batería» de la V5.5, por otro mecanismo. Con los arreglos y la secuencia de firmware baja a +1.95 A (78 %); con solo LTE en batería, ≈ 1.2 A (48 %). + +**Qué se cambió en el esquemático (Claude, 28-sep):** **C161 y C162, 47 µF 16 V X7R 1210 (C5440143)**, en `/MAIN5V` en los +pines VSYS 1/24 de U6 (≈ 113 µF efectivos). Además cuentan E-01, A-01, A-07 y F-03. + +**Cómo se corrige — layout (Michelle, L-11):** C161/C162 a ≤ 2 mm de los pines 1/24, con GND sobre el cobre del EP. + +**Firmware:** en batería **solo LTE** (`AT+CNMP=38`), W5500 apagado, F9P asentado antes de encender el módem, y no +arrancar el módem en frío con VBAT < ≈ 3.4 V. + +**Cómo se verifica.** Arranque en frío solo con batería, VBAT 3.5 V, con osciloscopio en `/MAIN5V` y VIN de U20 y sonda de +corriente en `/BAT_PLUS` (ECO §I-1). + +#### F-51 · Ninguna temperatura de cargador ni de celda llega al MCU + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente · Firmware: pendiente + +**Qué pasa.** Fuentes de temperatura en la v6 antes del arreglo: SHT40 (U3) a **71.4 mm** de U6; dos sondas externas +(P7 → PB1, P8 → PC4) solo por conector; el NTC del paquete (P3.3 → `/NTC`) iba **solo a U6.17**; el TMP102 de la V5 se +borró. `CHG_CELL_HOT/COOL` (45/40 °C) no tenía sensor de celda. R4 no se cumplía en firmware (la celda seguía protegida por +la pausa NTC del LTC4040 a 42.4 °C). + +**Por qué importa.** Sin temperatura del chip cargador, el ciclado térmico tipo A-02 es invisible en la telemetría. +Decisión D7: el sensor a ≤ 10 mm de U6 es **obligatorio** (lección F5). + +**Qué se cambió en el esquemático (Claude, 28-sep):** + +- **U29 = TMP102AIDRLR (C99269**, SOT-563) en I²C1, **dirección 0x48** (ADD0 → GND), **C168 100 nF (C14663)** en V+. +- NTC del paquete al MCU: `/NTC` → **R137 100 k (C25803)** → red nueva **`/NTC_CELL`** → **PC5** (U16 pad 25); de esa red + a GND, **R138 120 k (C25808)** y **C169 10 nF (C1589)**. PC5 ≤ 0.545 × 5.46 V = 2.98 V; la carga de 220 k mueve el umbral + caliente del LTC4040 ≈ 0.7 °C. + +**Cómo se corrige — layout (Michelle, L-17):** U29 **entre U6 y L6**, a **≤ 5 mm del EP** de U6, con C168 en V+; +R138/C169 junto al pad 25 (PC5); R137 en cualquier punto de `/NTC`. + +**Firmware:** `tchg` (TMP102 0x48) y `tcell` (PC5) al final de `$PHLG`; el gobernador inhibe con `tcell` +(Li-ion 45 °C / LFP 55–60 °C) y corta la carga con `tchg` > 85 °C. `tcell` solo es válido con `/VEH5V` presente. + +**Cómo se verifica.** Durante la prueba térmica de U6/L6 (A-02), `tchg` y `tcell` aparecen en `$PHLG` y siguen a la cámara. + +#### F-12 · Vías de tierra + +**Estado:** Pendiente — layout (no agrega piezas al BOM) + +**Qué pasa.** 69 vías de GND en toda la tarjeta (V5.5: 165). **1** bajo el módem U19, **0** bajo el F9P U18, **0** en los EP +de U6, U25, U20, U2 y U12. El polígono GND del este (U19, U20, U25, J13, D34) baja a los planos por **5 vías**. 10 de 35 +celdas de 20 × 20 mm sin ninguna vía; la distancia máxima a una vía GND es 27.8 mm, junto a J13. + +**Por qué importa.** Las corrientes de retorno del módem (LTE 23 dBm, picos GSM de 2 A) llegan a los planos por 5 vías +separadas 30–70 mm: el polígono se comporta como un parche resonante a 1–2.7 GHz → el LTE desensibiliza al F9P (el riesgo +#1 del brief). U19 y los reguladores pierden su camino de calor (sin vías y con spokes, θ ≈ el doble). + +**Cómo se corrige — layout (Michelle, L-24…L-29):** + +1. EP: U25 y U20 (EP 3.2 × 2.5) → **2 × 3 = 6 vías a 1.0 mm**, o 2 × 4 = 8 a 0.8 mm con vías 0.3/0.5 (3 × 3 a 1.0 mm no cabe); + U12 → 2 × 3; U6 → 9 (A-02). +2. Conexión **sólida por pad** (no para toda la zona) en: todos los EP, todos los pads GND de U18 y U19, ánodos de D34/D11, + pads GND de Cin/Cout de los bucks. **No** poner la zona en «alivio térmico solo para PTH»: volvería sólidos 23 pads 0402 y + 142 pads 0603 de GND (efecto lápida). +3. U19: una vía tapada en cada hueco de 1.7 mm entre pads GND centrales de 2.1 mm (0.55 mm de separación por lado) + anillo + en los pads GND del perímetro: **≥ 30, meta 40**, nunca dentro de un pad. +4. U18: vías en los centros intersticiales diagonales de la rejilla de 2.1 mm (0.41 mm a las esquinas de los pads): **≥ 24**. + Bajo U18/U19, vías tapadas o «epoxy filled & capped» de JLC. +5. 2 vías GND a ≤ 1 mm de cada pad GND de J12 y J13, y en D28. +6. Toda isla GND de F.Cu ≥ 20 mm² con ≥ 2 vías; ningún punto del polígono GND a más de 5 mm de una vía (hoy mediana 10.4 mm, + máximo 29.5 mm); cerca de vías en la orilla a ≤ 5 mm de paso (≈ 96 vías); **total ≥ 400 vías GND**. + +**Cómo se verifica.** Aceptación: 0 celdas de 20 mm vacías; todo pad GND de U19/U18/U20/U25/J12/J13 en un grupo de F.Cu +con ≥ 1 vía al plano a ≤ 2 mm. En banco: prueba G3 de desensibilización. + +#### F-03 · Lazos calientes de los reguladores conmutados + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente + +**Qué pasa.** + +- **U25** (TPS54360B, 24–36 V): el GND de C149/C150/C151 está en la isla de U6, y el EP de U25 y el ánodo de D34 en el + polígono del este → lazo de entrada **≈ 311 mm²** (meta ≤ 1 cm²). EP sin vías; L22 a 13.75 mm del SW; `/SW_PWRIN` 45.8 mm². +- **U20** (AP64350): el GND de C128/C127 llega al EP (6.86 / 8.48 mm) por una **pista GND de 0.25 mm** metida entre U20.1 y + U20.2; EP sin vías. Rizo de entrada ≈ 65 mV p-p. +- **U12** (MP1584EN, 3V3_ETH): C101 a **6.40 mm** del VIN; D11 a 11.92 mm; L8 a 15.10 mm; R87 (FB) a 25.9 mm, con + `/ETH_FB` bajo `/ETH_SW` en In1. + +**Por qué importa.** Oscilaciones en SW/VIN y EMI hacia los receptores GNSS/LTE; el sobretiro en VIN de U25 (≈ 9–15 V +sobre el clamp de 53.3 V, estimado) se come el margen al máximo de 65 V; ruido en los FB. No se cumple la ECO §E.4. + +**Qué se cambió en el esquemático (Claude, 28-sep):** en U20.2 (`/MAIN5V`), **C163 y C164, 22 µF 16 V 0805 (C86817)** + +**C165, 220 µF 16 V polímero (C881921)**: rizo 65 → 17 mV p-p. Los 16 V solo son válidos con la entrada de 5 V de A-01. + +**Cómo se corrige — layout (Michelle, L-20…L-23):** + +1. Regla común (U25, U20, U12): Cin (pads VIN y GND) a **≤ 2 mm** de los pines VIN y GND/EP; GND de Cin, ánodo del diodo y EP en + **una sola área sólida de F.Cu**, sin cuellos de GND de menos de 1 mm; ≥ 2 vías a ≤ 1 mm de cada pad GND de Cin; diodo a + ≤ 3 mm del SW; inductor a ≤ 5 mm; cobre SW ≤ 25 mm²; divisor FB a ≤ 3 mm del pin FB; nada en In1 bajo el cobre SW. +2. **U25:** C149/C150 a ≤ 2 mm de los pines 2/7 sobre el cobre del EP/D34; cátodo de D34 a 2–3 mm del pin 8, ánodo en el GND de + Cin; L22 a ≤ 5 mm del pin 8; `/SW_PWRIN` ≤ 25 mm², no sobre pistas de señal de In1; 4 vías GND a ≤ 2 mm del nodo Cin/D34; + pad GND de D34 sólido. +3. **U20:** borrar la pista GND de 0.25 mm entre U20.1 y U20.2; GND de C127/C128 hacia el EP con F.Cu sólido; C163/C164 a + ≤ 3 mm de U20.2 y C165 (polímero 6.3 × 7.7) en U20.2; R110/R111 a ≤ 2 mm de U20.5, del lado opuesto al pin 8; sensado de + VBAT con pista dedicada desde C131; borrar el desvío de 5.6 mm por In1 del FB. +4. **U12:** C101 a ≤ 2 mm de U12.7 con GND junto al pin 5; D11 a ≤ 2 mm del pin 1 con su ánodo en el GND de C101; L8 a ≤ 5 mm; + R87/R88 a ≤ 3 mm de U12.4, R87 alimentado por pista Kelvin desde C102/C94; `/ETH_FB` ≤ 5 mm en F.Cu, nada bajo `/ETH_SW`; + cambiar las uniones GND de 0.2 mm por polígono. + +**Cómo se verifica.** Aceptación: cada lazo de entrada ≤ 1 cm². En banco: IR de D34/U25 a carga completa. + +#### A-07 · Camino de 5 V por pistas internas delgadas + +**Estado:** Pendiente — layout · Compras: cobre interno de 1 oz (D12) + +**Qué pasa.** `/VEH5V` L22.2 → RS1.1: **In1 de 0.5 mm × 13.6 mm** (+ In2 1.0 mm × 66.6 mm); a 2.5 A de carga → +168 °C según +IPC-2221 interno (IPC-2152 ≈ la mitad). `/VIN_SW` RS1.2 → Q7: **In2 de 0.8 mm × 23.6 mm**, +77 °C a 2.5 A. `/MAIN5V` +Q7 → U6: F.Cu de 0.5 mm. El sensado CLN (U6.7) toma 1.66 mm abajo en la pista de RS1.2 → el límite de entrada efectivo +queda en 2.14–2.41 A en vez de 2.35–2.65 A. El cobre interno de JLC04161H es de 0.5 oz por defecto. + +**Por qué importa.** Cobre interno caliente bajo U6/Q7 a corriente de carga. A-01 suma horas en el límite de RS1, así que +A-07 es **prerrequisito de A-01**. + +**Cómo se corrige — layout (Michelle, L-19 y L-14):** `/VEH5V` L22.2 → RS1.1 en F.Cu de **≥ 2 mm** o polígono (acercar +L22/C153/C154 a RS1), o ≥ 2 mm interno con ≥ 4 vías por cambio; `/VIN_SW` RS1.2 → Q7 en F.Cu ≥ 2 mm, Q7 a ≤ 5 mm de RS1/U6; +sensado de U6.7 (CLN) y U6.6 (VIN) desde el **borde interior de los pads de RS1** (Kelvin); `/MAIN5V` según A-02 y +≥ 1.5 mm hasta U20. + +**Compras:** cobre interno de **1 oz** (D12), y aun así ensanchar las pistas internas. + +**Cómo se verifica.** Con el DRC, avisos de `track_width` solo en redes dejadas a propósito con la regla T15. + +#### F-06 · Líneas de RF + +**Estado:** Pendiente — layout · Compras: control de impedancia (D12) + +**Qué pasa.** LTE: `/RF_LTE` sale de U19.60, 4.01 mm en F.Cu, **22.14 mm en In1** con vías en (174.25, 58.25) y +(194.27, 53.72), luego R118 → 5.62 mm → D28 → J13. Sobre el tramo de In1 pasan `/VBAT_MODEM`, `/SYS5V`, `/SW_IN`…; solo +1 vía GND a menos de 3.5 mm; 30–47 Ω. GNSS: el bias corre junto a la línea RF a **0.274 mm**. En el stackup real +(JLC04161H-7628) una pista de 0.5 mm da 42.1 Ω; el archivo trae el stackup genérico. + +**Por qué importa.** Desacople en LTE con dos transiciones de vía sin blindaje y la alimentación del PA cruzando la línea +RF → ruido en la antena y desensibilización del F9P vecino. La prueba G3 en banco probablemente falla. + +**Cómo se corrige — layout (Michelle, L-1, L-30…L-33):** + +1. Stackup real en *Board Setup* (sección 5-A) y pedir **control de impedancia**. +2. Las dos líneas RF solo en **F.Cu, como CPWG sobre In1 sólido**, empezando en **ancho 0.30 / gap 0.20 mm**; ajustar con + la calculadora de JLC para 50 Ω (la clase RF del proyecto usa esos valores como punto de partida). +3. LTE: re-rutear U19.60 → R118/C146/C147 → D28 → J13 todo en F.Cu (girar J13 o acercarlo al lado RF de U19); quitar el + tramo de In1 y sus dos vías; nada arriba ni abajo de la línea; `/VBAT_MODEM` a ≥ 3 mm. Con esto también desaparece la + violación RF de la vía de `/RF_LTE` contra `/PWR_CTRL` (0.150 mm). +4. Cerca de vías GND a ambos lados de las líneas RF a **≤ 3 mm de paso**, a ≤ 1 mm del borde del gap; 2 vías por pad GND de U.FL. +5. GNSS: `/ANT_BIAS` a ≥ 1 mm de la línea RF (ver C-01). + +**Cómo se verifica.** Geometría igual a la de la calculadora para 50 Ω; cercas ≤ 3 mm; prueba G3 en banco. + +#### F-05 · In1 no es un plano + +**Estado:** Pendiente — layout + +**Qué pasa.** El relleno GND de In1 tiene 8 islas y **18.8 % de vacío**; lleva **1571.9 mm de pistas de 49 redes** +(`/SW_5V` 181 mm, `/DOUT_4G` 95, `/KCOIL` 85, `/MAIN5V` 73…). Hay paralelos «de frente» sin plano entre ellos: +I2C_SDA sobre `/SER_TXB` 14.2 mm, ETH_XO sobre `/ETH_RST` 6.95 mm, NRST sobre `/USART6_RX` 7.2 mm. + +**Por qué importa.** Los retornos rodean las ranuras (emisiones, susceptibilidad) y hay diafonía entre capas; se rompe la +regla del Plan de Cobre de «In1 sin cortes» para el receptor RF. + +**Cómo se corrige — layout (Michelle, L-35):** como mínimo despejar In1 bajo los pares USB (J9 y J11), cada cristal y sus +líneas, todos los nodos SW, `/VBAT_MODEM` y la zona RF, las líneas de SIM y los tres paralelos de arriba. Pasar las pistas de +In1 a In2/B.Cu (o F.Cu si son cortas), en este orden: `/SW_5V`, `/MAIN5V`, `/KCOIL`, `/USART6_TX/RX`, `/DOUT_4G`, `/CHRG_*`, +`/SER_TXB/RXB`, `/ETH_*`, `/VFB_BST`, `/IGATE`. (Con K1 sin montar, `/KCOIL` ya no lleva corriente, pero su cobre sigue ahí.) + +**Cómo se verifica.** **≤ 3 islas en In1** y ninguna red crítica sobre un vacío de más de 1 mm. + +#### C-04 · Interruptor del F9P junto a la antena LTE + +**Estado:** Pendiente — layout + +**Qué pasa.** Q1 (AO3401A, `/SW_IN` → `/SW_5V`) está en (197.28, 59.81), **a 9.0 mm de J13**; Q5 a 7.1 mm. `/SW_5V` va de +Q1.3 a U21.1 por **181.32 mm en In1** + 19.7 mm en F.Cu. + +**Por qué importa.** La alimentación del F9P nace en el campo cercano del transmisor LTE y recorre ≈ 17–20 cm como ranura +en el plano de GND; el PSRR del LDO a frecuencias LTE es ≈ 0 dB, así que la envolvente del TX llega al riel del receptor +(desensibilización, el riesgo #1). + +**Cómo se corrige — layout (Michelle, L-34):** mover **Q1, Q5, R1, R2** (F1 opcional) y R144 a la isla GNSS junto a +U21/C3/C40/C119; llevar hasta ahí `/SYS5V` (o `/SW_IN`); `/PWR_CTRL` pasa a ser la señal larga; **`/SW_5V` ≤ 15 mm y 0 mm en In1**. + +**Cómo se verifica.** Medir en el PCB la longitud de `/SW_5V`; prueba G3 en banco. + +#### G-02 · J9 (USB del módem) sin ESD + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Layout: pendiente + +**Qué pasa.** `/USB_DP`, `/USB_DM` y `/USB_VBUS` iban de J9 a U19 sin ningún dispositivo de protección; J9 está a 64.6 mm +de U19. J9 es el puerto de actualización y recuperación (USB_BOOT) del módem. + +**Por qué importa.** Una descarga durante el servicio en campo entra directo al PHY USB del A7670SA; el módem es el único +enlace de la unidad y J9 su única vía de recuperación. Lección F8, ECO §E.5. + +**Qué se cambió en el esquemático (Claude, 28-sep):** **U30 = USBLC6-2SC6 (C7519)**: pines 1/6 → `/USB_DM`, 3/4 → `/USB_DP`, +5 → `/USB_VBUS`, 2 → GND (igual que D19 de la V5.6). + +**Cómo se corrige — layout (Michelle, L-41):** a **≤ 3 mm de cobre** de los pads de J9, D± pasando por los pads del +dispositivo (flow-through), vía GND a ≤ 1 mm. + +**Cómo se verifica.** Revisión visual del ruteo: D± pasan por los pads del USBLC6, sin stubs; en banco, J9 enumera con el módem encendido. + +#### C-02 · Rampa de alimentación del F9P + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Compras: pre-ordenar C2862740 + +**Qué pasa.** U21 (AP2112K-3.3) no tenía arranque suave. El ZED-F9P pide una rampa de VCC entre 20 y 8000 µs/V; con el +AP2112 quedaba ≈ 28 µs/V cerca de regulación: dentro, pero el margen del lado rápido (≈ 1.4×) dependía de un límite de +corriente no especificado. + +**Por qué importa.** El F9P se apaga y enciende en cada ventana de 10 min (R1: ≈ 52 000 arranques al año): un arranque +fallido deja el receptor oscuro hasta el siguiente ciclo. + +**Qué se cambió en el esquemático (Claude, 28-sep):** U21 → **TPS7A2033PDBVR (C2862740)**, mismo pinout SOT-23-5 +(1 IN / 2 GND / 3 EN / 4 NC / 5 OUT); arranque 750–1150 µs → **239–367 µs/V**. La huella no cambia. JLC lo tiene en la +categoría «Pre-ordered Chips»: hay que pre-ordenarlo como J14. + +**Cómo se verifica.** Osciloscopio en la subida de `/3V3_GNSS`: entre **100 y 1000 µs/V**. + +#### A-08 · U17 (AMS1117) sin margen en batería + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Firmware: pendiente + +**Qué pasa.** En batería la entrada del LDO es VSYS − D12 = **4.27–4.67 V**; el AMS1117 necesita ≈ 4.3 V (caída ≈ 1.0 V). +Su corriente de tierra (5–11 mA) cuesta 27–60 mW de batería. VDDA = 3V3 y el firmware supone 3.30 V → BAT_SENSE y +5V_SENSE leen hasta +4 % alto; el corte de batería baja de 3.40 V dispara en ≈ 3.27 V reales. + +**Por qué importa.** 3V3 degradado justo en batería, telemetría de batería equivocada y un piso de sueño tan grande como +toda la meta (20–50 mW). + +**Qué se cambió en el esquemático (Claude, 28-sep):** U17 → **TI TLV1117LV33DCYR (C15578)**: SOT-223, mismo pinout +(1 GND / 2 OUT / 3 IN), 1 A, 455 mV de caída a 1 A, ≈ 100 µA de consumo. **No** usar C48937499 (mismo número de parte +listado, pero otro chip: 1.2 V de caída, 12 V). La huella no cambia. + +**Firmware:** calcular VDDA con VREFINT en cada ventana; nunca suponer 3.30 V. + +**Cómo se verifica.** `/3V3` en batería se mantiene regulado; las lecturas de batería coinciden con un multímetro. + +#### E-02 · `/ETH_RST` sin pull-down + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Firmware: pendiente + +**Qué pasa.** `/ETH_RST` = {U11.37, PA15}. PA15 arranca como JTDI con pull-up (30–50 kΩ) y el RSTn del W5500 tiene su +propio pull-up interno (62–112 kΩ). Un pull-down de 100 k daría **2.75 V (lee alto)**. Con **4.7 k**: peor caso 0.62 V +(típico 0.49 V) → bajo seguro; 0.70 mA cuando el firmware lo mantiene en alto. + +**Por qué importa.** El W5500 sale de reset en cada reset del MCU, DFU o bootloader y consume hasta 128 mA; en batería es +el consumo de la **lección F8**. Una V5.6 con R112 = 100 k tiene el mismo error (sección 11). + +**Qué se cambió en el esquemático (Claude, 28-sep):** **R140 = 4.7 kΩ 0603 (C23162, Basic)** de `/ETH_RST` a GND junto a U11.37. +Con E-01 aplicado, este punto baja a Minor, pero se hizo igual. + +**Firmware:** PA15 en bajo como primera línea de `setup()`. + +**Cómo se verifica.** Con el MCU en reset, `/ETH_RST` ≈ 0.49 V típico (0.62 V en el peor caso), abajo del VIL de 0.8 V. + +#### A-09 · C78 electrolítico de 85 °C en el 5 V + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) + +**Qué pasa.** C78 (bulk de `/VEH5V`) era SamYoung MVG 16 V 220 µF, 85 °C / 2000 h, 130 mA de rizo. A 65 °C locales +(supuesto) ≈ 8 000 h: 0.9 años en operación continua. + +**Por qué importa.** La capacidad y la ESR se degradan en el primer año y afectan la respuesta de U25. + +**Qué se cambió en el esquemático (Claude, 28-sep):** C78 → **Lelon OVZ221M1CTR-0608, 220 µF 16 V polímero (C881921)**, +misma lata 6.3 × 7.7, 105 °C / 2000 h. Efecto en el lazo de U25: benigno (margen de fase ≈ 68°). + +**Cómo se verifica.** BOM: C78 = C881921. + +#### H-02b · Stock para la cantidad del pedido + +**Estado:** ✅ Aplicado en esquemático y verificado (28-sep) · Compras: pendiente + +**Qué pasa** (base de JLC, 28-sep). C103211 (RALEC 100 k **5 %**): 702 piezas, 9 por tarjeta → **78 tarjetas máximo**. +U19 A7670SA-LASC (C18548276): 96. U18 ZED-F9P-04B (C5120257): 104. J14 (C2977286) está en «Pre-ordered Products». + +**Por qué importa.** Un pedido de 100 se detiene por U18/U19/C103211; J14 falla sin pre-orden. + +**Qué se cambió en el esquemático (Claude, 28-sep):** C103211 → **C25803** (UNI-ROYAL 100 k **1 %**, Basic) en R56, R57, R58, +R85, R87, Rgs1 (R20, Ren1 y Rfreq1 quedan DNP con A-01). + +**Compras:** pre-ordenar J14; pre-ordenar o consignar U18 y U19 si se va a ≳ 100; re-verificar todo el día del pedido. + +**Cómo se verifica.** Carrito de JLC sin faltantes para 20 tarjetas. + +--- + +## 5. Lista de trabajo de Michelle (layout) + +!!! warning "Antes de empezar — tres reglas" + 1. **Primero `git pull`.** Los cambios de esquemático, reglas del proyecto y las huellas nuevas de `Drogheda-v6.pretty` + vienen en el pull. Si KiCad estaba abierto en v6, cerrarlo **sin guardar** y volver a abrir. + 2. En *Actualizar PCB desde esquemático*, **«Reemplazar huellas»** sí va marcado: solo cambia las referencias cuya huella + cambió en el esquemático (tabla del paso 0). **Nunca** correr la actualización **global** *Actualizar huellas desde + librería* (L-45): desde librería, solo por referencia (U25 y, si hiciera falta, L2/L6/L8/L20). + 3. Si KiCad avisa que el archivo **cambió en disco**, elegir **Recargar**. Nunca guardar encima una copia vieja. + +Orden: paso 0, luego reglas y stackup, luego el cobre de los Blockers, los Majors, los puertos y al final la aceptación +(L-48). El número L-n es el paso de la §6 del informe (L-1…L-48), del informe de puertos (L-49…L-62) o de la revisión +final (L-63…L-66). Detalle de cada pieza nueva en el [resumen de cambios](v6-cambios-resumen.md). + +### 0 · Actualizar el PCB desde el esquemático (primero) + +- [ ] `git pull` en HBox_PCB; abrir `hbox-watchdog-v6.kicad_pro`. +- [ ] *Herramientas → Actualizar PCB desde esquemático* con **«Eliminar huellas sin símbolo»** marcado y + **«Reemplazar huellas con las del esquemático»** marcado. **Revisar la lista del diálogo antes de aplicar:** solo + deben cambiar de huella las referencias de esta tabla, y solo deben borrarse **D20 y D21**. Si propone otra cosa + (por ejemplo borrar barrenos MH o pads TP), cancelar y avisar a Leo. + + | Ref | Huella nueva | Hallazgo | + |---|---|---| + | U15 | `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm` (SOIC angosto; ahora TRS3232EIDR) | H-01, P-2 | + | D28 | `Diode_SMD:D_0402_1005Metric` | B-03 | + | Y3 | `Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm` (pad 1 HSE_IN, pad 3 HSE_OUT, pads 2/4 GND) | D-02 | + | JP1 | `Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm` (puenteado) | A-01 | + | C91 | `C_0603_1608Metric` | E-04 | + | L2 (DNP), L6, L8, L20 | `Drogheda-v6:IND-SMD_MWSA0804S` (pads 2.75 × 5.5 mm a ±3.375 mm) | H-03, L-63 | + + J10, P11 y P12 ya tienen en el esquemático la misma huella que en el PCB (`Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal` + y `PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal`): no cambian de huella, **pasan a montadas**. Y4, F2, U10, U14, + U17 y U21 conservan su huella (reemplazos directos). + +- [ ] **Revisar los DNP** después del Update. Montadas ahora: **J10, P11, P12**. DNP: U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, + Rfreq1, Ren1, Ren2, R20, R21, Q10, DzG1, Rrp1, C10, C11, C22 (A-01); K1, Q6, D6, R40, R41 (B-13); R145, R146 (opción de + polarización RS-485). +- [ ] **U25:** *Actualizar huella desde librería* **solo en U25**, para que pierda el campo `LCSC Part` (H-04). Debe quedar solo + `LCSC` = C524806. +- [ ] Colocar las **46 piezas nuevas** (tabla abajo), cada una en el lugar que marca su grupo. +- [ ] Borrar el cobre de las piezas que quedaron DNP por A-01 (grupo B) y poner R148 en lugar de K1 (L-54). + +??? note "Las 46 piezas nuevas y dónde van" + | Ref | Pieza | Hallazgo | Dónde va | + |---|---|---|---| + | D35 | SMBJ33A (TVS de ignición) | F-02 | en P1.3 | + | U28, R135, R136 | TPS2552 + 100 k (EN̅) + 10 k (FAULT̅) | C-01 | cerca de L21/J12 (L-33) | + | C176 | 100 nF | N2 | ≤ 2 mm de U28 pin 1 (L-64) | + | U27, C170 | 74LVC1G125 + 100 nF | D-01 | junto a U18.26 | + | U29, C168 | TMP102 (0x48) + 100 nF | F-51 | entre U6 y L6, ≤ 5 mm del EP | + | R137, R138, C169 | 100 k / 120 k / 10 nF (toma NTC) | F-51 | R138/C169 junto a PC5 (pad 25) | + | C161, C162 | 47 µF 1210 | A-05 | ≤ 2 mm de VSYS 1/24 de U6 | + | C163, C164, C165 | 2 × 22 µF 0805 + 220 µF polímero | F-03 | en U20.2 | + | C166, C167 | 22 µF 0805 | B-02 | ≤ 3 mm de L20.2 | + | U30 | USBLC6-2SC6 | G-02 | ≤ 3 mm de J9 (L-41) | + | R139 | 100 k | E-01 | en U12.2; pista `/ETH_PWR_EN` a PD2 (pad 54) | + | R140 | 4.7 k | E-02 | en U11.37 | + | C172, C173 | 100 nF | E-04 | AVDD 4/8 y 11/21 del W5500 | + | U31, C174 | TMP102 (0x49) + 100 nF | F-52 | entre U19 y U20 | + | R141 | 100 k pull-up de `/PFO` | A-13 | cerca de PB10 (pad 29) | + | R142, R143 | 100 k en `/MODEM_STATUS` (a GND) y `/DIN_4G` (a 3V3) | B-10 | donde convenga | + | C171 | 100 nF 0402 | B-09 | en J14.C1 | + | R144 | 100 k | D-09 | en la base de Q5 | + | TP9 | pad 1.5 mm | D-12 | PA9, en la fila de pads de depuración (L-56) | + | TP10, TP11 | pads 1 mm | C-07 | U18.50 / U18.49, junto a un pad GND | + | JP6 | puente de soldadura abierto (JP_CUT) | G-04 | sobre P5, serigrafía «CUTOFF BYPASS» | + | D36, D37, D38 | PESD5V0S1BA | G-08 | ≤ 3 mm de P6.1, P7.1, P8.1 | + | U32, C175 | 74LVC1G04 + 100 nF | P-1 | ≤ 5 mm de U14 pines 2/3 (L-49) | + | D39 | SM712 | P-1 | ≤ 5 mm de cobre de P11 (L-50) | + | R145, R146 | 390 Ω, **DNP** | P-4 | junto a P11 (L-50) | + | R147 | 1 k | P-2 | ≤ 3 mm de U15.12 (L-51) | + | R148 | 0 Ω | B-13 | entre U16.37 (PC6) y U23.7 (L-54) | + | TP12 | pad 1.5 mm en `/1V8_MODEM` | P-5 | a 2.54 mm de TP8 (L-55) | + + R56 cambia de red (A-11): ahora va a `/3V3`. + +### A · Reglas DRC y stackup + +- [ ] **L-1 Stackup:** *Board Setup → Physical Stackup* = JLC04161H-7628: Cu 0.035 / prepreg 0.2104 (εr 4.4) / Cu 0.035 / + núcleo 1.065 (εr 4.6) / Cu 0.035 / prepreg 0.2104 (εr 4.4) / Cu 0.035; acabado **ENIG**. +- [ ] **L-2 Netclasses:** revisar que estén como en la tabla de F-01 (ya aplicadas en `.kicad_pro`): HV24 con `/SW_FAN`, + `/BST_FAN`, `/24V`, `/Q10_GATE`; `/SW_MODEM` y `/BST_MODEM` en Default; PWR_HI, PWR_MODEM, PWR_MID, RF y Default. +- [ ] **L-3 Reglas:** el `.kicad_dru` ya tiene las 5 reglas de F-01. **Falta:** cambiar la regla de texto a altura mín. + **0.8 mm** / trazo mín. **0.15 mm** (hoy 0.5 / 0.1) y relajar los avisos T15 en `/5V_FAN`, `/FAN_RET`, `/SW_FAN`, + `/SW_5V`, `/SW_IN`, `/SYS5V`, manteniendo ≥ 0.8 mm en `/VIN_PROT`/`/VIN_FUSED`. La regla T15 todavía nombra + `/VIN_MODEM`, que ya no existe: se puede quitar. +- [ ] **L-4 Comprobar:** *Inspeccionar → Resolución de separación* en una red HV24 (`/24V_IN` o `/VIN_PROT`) contra la zona + GND de In1 → **0.5 mm**, y zona GND contra una red Default → **0.15 mm**. Después de cada guardado desde la + interfaz, revisar que las netclasses sigan ahí. +- [ ] Rellenar zonas (**B**) y correr el DRC. Las proximidades del relleno se van al rellenar. Los **12 puntos de cobre real** + que salieron en la copia de prueba son la lista del grupo B y de F-06: `/IGN_IN` en In2 contra vía GND 0.250, + `/FAN_PWM` 0.291, vía `/5V_FAN` 0.300, `/NTC2` 0.305 y vía `/VEH5V` 0.340 (todos F-02, desaparecen con L-8); + `/VIN_PROT` contra `/VEH5V` 0.157 y 0.191 en (175.5, 113.8); `/USB_VBUS` contra Q23.1 `/Q23_GATE` 0.225; `/SW_PWRIN` contra + pista GND 0.270; `/24V` contra `/COMP_FAN` 0.290 × 2 (rama DNP, se va con L-6); vía de `/RF_LTE` contra `/PWR_CTRL` + 0.150 (se va con L-31). Después del Update aparecen elementos HV24 nuevos en `/VIN_FUSED` junto a D10. + +### B · Potencia: entrada de 24 V e ignición (A-01, V1-01, F-02, F-01) + +- [ ] **L-5 Fusible primero:** F2 (ahora 3 A, C206912, mismo porta-fusible Nano2) eléctricamente primero: P1.1 → F2 → + D10 (SMBJ33A) y Q23 en paralelo a la salida de F2. En el cobre de P1.1 solo F2. +- [ ] **L-6 Quitar la rama sin fusible:** borrar el cobre `/24V`, `/SW_FAN`, `/BST_FAN` de Q10, DzG1, Rrp1, C10, C11, C22 y del + bloque U2 (U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21). JP1 puenteado → `/5V_FAN` = `/VEH5V`. +- [ ] **L-7 Entrada del buck del módem:** borrar la pista de 48 mm de `/VIN_MODEM` desde D20 (136.5, 113.8) hasta U20; donde + estaba D21, unir en cobre. `/MAIN5V` de Q7/U6 a U20.2 de **≥ 1.5 mm** todo el camino. +- [ ] **L-8 Ignición:** Rig1 a **≤ 3 mm** de cobre de P1.3, solo F.Cu; D35 (SMBJ33A) de `/IGN_IN` a GND en P1.3; el tramo + largo es `/IGN_SENSE` (Default); Rig2, Rigb1, C9, D5 junto al MCU; borrar la pista vieja en In2 (106.5 mm) y la vía + de In1 en (127.3, 50.5). +- [ ] **L-9 `/24V_IN` fuera de In1:** la pista de 27 mm en In1 de (167.5, 128.65) a (143.25, 121.75) → F.Cu por la orilla sur; + si tiene que ir en In1, ≥ 1.0 mm de toda red de bajo voltaje y nada cruzándola. +- [ ] **L-10 Puntos de 24 V en capa externa** (después de rellenar + DRC): `/VIN_PROT` (1.5 mm) vs `/VEH5V` (0.8 mm) → + **≥ 0.5 mm** y tapar la vía `/VEH5V` de ahí; `/USB_VBUS` a ≥ 0.3 mm de `/Q23_GATE` y `/VIN_PROT`; quitar el cuello GND + de U20 (L-22); `/SW_PWRIN` y `/BST_MODEM` a ≥ 0.3 mm de pistas GND. **Tapar todas las vías** salvo las de prueba. +- [ ] **L-62 P1:** confirmar que los pines del DIBO DB128V-5.0-5P (C424683) entran en los barrenos de la huella MKDS-1,5 + (paso 5.0 mm) y que la entrada de cable mira al lado del arnés en el gabinete. Solo revisión; no se espera cambio. + +### C · Potencia: inductores y cargador LTC4040 (H-03, A-02, A-05, A-07, F-51, A-14) + +- [ ] **L-53 (cifras corregidas por L-63) Land MWSA0804S en L2/L6/L8/L20:** la huella cambia a `Drogheda-v6:IND-SMD_MWSA0804S` + con el *Update PCB*. Pads de **2.75 × 5.5 mm a ±3.375 mm** (separación 4.0 mm, extensión 9.5 mm), courtyard + **10.0 × 9.0 mm**, con el lado de 8.8 mm del cuerpo sobre el eje de los pads. Revisar vecinos y medir las distancias de + L-11/L-21/L-22/L-23 contra los pads nuevos. **Colocar este land antes de rutear los reguladores.** +- [ ] **L-63:** si la versión anterior de esta huella (la de la pasada de puertos, 11.5 × 9.7 mm) ya había entrado al PCB, + refrescar **solo estas cuatro referencias** desde la librería (L-45). El land correcto es más chico y parecido al + SRU8028 anterior, así que la separación con vecinos es más fácil de lo que decía L-53. +- [ ] **L-11 Re-agrupar U6:** L6 pad 1 ≤ 5 mm (orilla) de los pines 21/22; C30/C31 ≤ 3 mm del pin 6; C32/C33/C34 y + **C161/C162** ≤ 2 mm de VSYS 1/24 con GND sobre el cobre del EP; C35 (o un 22 µF 0805 extra) en L6.2 junto al pin 23. + L6 fuera de (193.2, 90.3) (vuelve MH4). +- [ ] **L-12 `/SW_BAT`:** polígono F.Cu **≥ 2 mm** desde la salida de los pines 21+22 hasta L6.1, compacto, sin cuellos de 0.25/0.30 mm. +- [ ] **L-13 `/BAT_PLUS`:** P3 → L6.2 ≥ 1.5 mm en F.Cu o polígono; si va interno, ≥ 4 vías por cambio y ≥ 2.5 mm; sensado de + U6.23 como toma Kelvin desde L6.2/C35. +- [ ] **L-14 `/MAIN5V`:** polígono de U6 pines 1/24 sobre C32–C34 hasta el drenador de Q7, ≥ 2 mm, sin cuellos de 0.3/0.5 mm. +- [ ] **L-15 EP de U6:** 9 vías, 3 × 3 a 0.9 × 1.2 mm, 0.3/0.6 mm, tapadas o via-in-pad de JLC; conexión del pad sólida. +- [ ] **L-16 Planos bajo U6:** In1 e In2 GND sólidos ≥ 5 mm alrededor de U6 y L6 (sacar de In1 `/VFB_BST`, `/IGATE`, `/CHRG_*`). +- [ ] **L-17 Sensor:** U29 (TMP102, SOT-563) entre U6 y L6, ≤ 5 mm del EP, C168 en V+, en I²C1. Toma del NTC: `/NTC` → R137 → + `/NTC_CELL` → PC5 (pad 25), con R138 (120 k) y C169 (10 nF) de ese nodo a GND. +- [ ] **L-18 BSTFB / IGATE (A-14):** R53/R54 ≤ 3 mm de los pines 18/10 de U6, rama superior con toma Kelvin en los pads + de CSYS, `/VFB_BST` en F.Cu; Q7 ≤ 5 mm de U6.15; `/IGATE` ≤ 8 mm en F.Cu, flanqueada por cobre `/MAIN5V`. +- [ ] **L-19 Camino de 5 V (A-07):** `/VEH5V` L22.2 → RS1.1 en F.Cu ≥ 2 mm (acercar L22/C153/C154 a RS1) o ≥ 2 mm interno con + ≥ 4 vías por cambio; `/VIN_SW` RS1.2 → Q7 en F.Cu ≥ 2 mm, Q7 ≤ 5 mm de RS1/U6; sensado CLN (U6.7) y VIN (U6.6) desde el + borde interior de los pads de RS1 (Kelvin), no 1.66 mm abajo como hoy. + +### D · Potencia: reguladores conmutados (F-03) + +- [ ] **L-20 Regla común U25/U20/U12:** Cin ≤ 2 mm de VIN y GND/EP; GND de Cin + ánodo del diodo + EP en una sola área sólida + de F.Cu, sin cuellos < 1 mm; ≥ 2 vías ≤ 1 mm de cada pad GND de Cin; diodo ≤ 3 mm del SW; inductor ≤ 5 mm; cobre SW + ≤ 25 mm²; divisor FB ≤ 3 mm del pin FB; nada en In1 bajo el cobre SW. Lazo de entrada ≤ 1 cm² (U25 hoy ≈ 3.1 cm²). +- [ ] **L-21 U25:** C149/C150 ≤ 2 mm de los pines 2/7 sobre el cobre del EP/D34; cátodo de D34 a 2–3 mm del pin 8, ánodo en + el GND de Cin; L22 ≤ 5 mm del pin 8 (hoy 13.75 mm); `/SW_PWRIN` ≤ 25 mm² (hoy 45.8 mm²) y no sobre pistas de In1; + 4 vías GND a ≤ 2 mm del nodo Cin/D34; pad GND de D34 sólido. +- [ ] **L-22 U20:** borrar la pista GND de 0.25 mm entre U20.1 y U20.2; GND de C127/C128 hacia el EP con F.Cu sólido; C163/C164 + ≤ 3 mm de U20.2 y C165 (220 µF, 6.3 × 7.7) en U20.2; R110/R111 ≤ 2 mm de U20.5, lejos del pin 8; sensado de VBAT con + pista dedicada desde C131; borrar el desvío de 5.6 mm por In1; `/MAIN5V` (antes `/VIN_MODEM`) a ≥ 0.3 mm de los pads + EN/RT/EP. +- [ ] **L-23 U12:** C101 ≤ 2 mm de U12.7 (hoy 6.40 mm) con GND junto al pin 5; D11 ≤ 2 mm del pin 1, ánodo en el GND de C101 + (hoy 11.92 mm); L8 ≤ 5 mm (hoy 15.10 mm); R87/R88 ≤ 3 mm de U12.4, R87 por pista Kelvin desde C102/C94; `/ETH_FB` + ≤ 5 mm en F.Cu sin nada bajo `/ETH_SW`; uniones GND de 0.2 mm → polígono. + +### E · Módem y RF (F-06, B-03, B-02, B-13, F-52, B-09) + +- [ ] **L-30 Líneas RF:** solo F.Cu, CPWG sobre In1 sólido, empezar en **ancho 0.30 / gap 0.20 mm** y ajustar con la calculadora + de JLC para 50 Ω en JLC04161H-7628. +- [ ] **L-31 LTE:** re-rutear U19.60 → R118/C146/C147 → D28 → J13 todo en F.Cu (girar J13 o acercarlo al lado RF de U19); quitar + el tramo de 22 mm en In1 y sus vías en (174.25, 58.25) y (194.27, 53.72); nada arriba ni abajo de la línea; + `/VBAT_MODEM` ≥ 3 mm. D28 (ahora 0402) en el mismo lugar en línea. +- [ ] **L-32 Cercas:** vías GND a ambos lados de RF_LTE/RF_ANT_LTE y RF_GNSS/RF_ANT_GNSS a **≤ 3 mm** de paso, ≤ 1 mm del borde del gap. +- [ ] **L-36 VBAT_MODEM:** polígono F.Cu ≥ 3 mm de L20.2 → C130 → C131 → C132–C136 → pines 55/56/57 (a los tres, sin cuello de + 0.5 mm); C131 (ahora polímero) ≤ 5 mm de los pads; C166/C167 ≤ 3 mm de L20.2. +- [ ] **L-54 UART del módem (B-13):** R148 (0603) en el camino más corto U16.37 (PC6) → U23.7 (`/DIN_4G`). K1, Q6, D6, R40, R41 + son DNP: sus huellas se quedan, sin más cambio de cobre que las dos conexiones de R148. Serigrafía «K1 XOR R148». +- [ ] **L-55 TP12:** junto a TP8 a 2.54 mm entre centros (para puentearlos con pinzas); los dos alcanzables con la tapa abierta. +- [ ] **L-65 Pads de descarga forzada:** TP12 (1V8) a 2.54 mm de TP8 (L-55), más un **contacto GND a ≤ 10 mm de TP8** (por + ejemplo la pestaña del blindaje de J9, SH = GND, u otro pad GND). Serigrafía «BOOT: TP8–1V8 (alt: TP8–GND)». +- [ ] **TMP102 del módem (F-52):** U31 (0x49) + C174 entre U19 y U20. +- [ ] **SIM (B-09):** C171 (100 nF 0402) en J14.C1; mover D23–D25 junto a J14. + +### F · GNSS (C-01, C-04, D-01, C-07) + +- [ ] **L-33 Bias de antena:** U28 cerca de L21/J12; `/ANT_BIAS` ≥ 1 mm de la línea RF con franja GND cosida entre ambas + (o en In2 tras 100 pF + 100 nF); L21 toma la línea sin stub en J12; D27 sobre el pad de J12. +- [ ] **L-64 C176:** 0603 a **≤ 2 mm del pin 1 (IN) de U28**, en la misma capa; su pad GND al plano con vía a ≤ 1 mm y el pin 2 + de U28 en la misma zona de GND; `/3V3_GNSS` llega a U28.1 pasando por el pad de C176. +- [ ] **L-34 Interruptor del F9P:** Q1, Q5, R1, R2 (F1 opcional) y R144 a la isla GNSS junto a U21/C3/C40/C119; llevar `/SYS5V` + (o `/SW_IN`); `/PWR_CTRL` es la señal larga; `/SW_5V` **≤ 15 mm y 0 mm en In1** (hoy 181 mm en In1). +- [ ] **U27 (D-01):** 74LVC1G125 + C170 junto a U18.26, alimentado de `/3V3_GNSS`. +- [ ] **Pads de prueba (C-07):** TP10 en U18.50 (SAFEBOOT_N) y TP11 en U18.49 (RESET_N), junto a un pad GND. Cu4 ≤ 2 mm de U18.36 (C-09). + +### G · Puertos serie: RS-485, RS-232, H4 y SC16IS752 (P-1, P-2, P-4) + +- [ ] **L-49 Dirección RS-485:** U32 (SOT-23-5) + C175 a ≤ 5 mm de los pines 2/3 de U14; C175 ≤ 2 mm de U32.5; `/RS485_DE` + ≤ 10 mm; `/SER_DEA` de U10.1 a U32.2. C84 ≤ 2 mm de U14.8. +- [ ] **L-50 Protección RS-485 en P11:** D39 (SM712) a ≤ 5 mm de cobre de P11.1/P11.2, A/B en flow-through (P11 → pads de D39 → + U14), D39.3 a GND con 2 vías a ≤ 1 mm; R82 + JP5 junto a P11 (terminación en el extremo del bus); R145/R146 (0603, DNP) + junto a P11. Rutear A/B como par (0.3 mm, gap ≤ 0.3 mm), ≥ 0.5 mm de otras redes, nada cruzando en la capa vecina. +- [ ] **L-51 RS-232 / H4:** R147 ≤ 3 mm de U15.12; H4.3 se conecta del lado de U10 (`/SER_RXB`), no en U15. Bomba C85–C88 + ≤ 3 mm y desacople **C89** ≤ 2 mm de U15.16. (Corrección a L-37: C84 es de U14, no de U15.) +- [ ] **L-57 SC16IS752 (U10):** Y2 + C82/C83 ≤ 5 mm de U10.6/7, sin pistas de capa interna debajo (L-39 extendido a Y2); + C81 ≤ 2 mm de U10.8. + +### H · Cristales, MCU y Ethernet (D-02, D-03, E-01…E-04, P-3, B-10, A-11, A-13, D-09, D-12) + +- [ ] **L-39 Cristales:** Y1 ≤ 3 mm de U11.30/31; **Y3 (ahora 3225) ≤ 3 mm** de PH0/PH1 (límite de aceptación 5 mm); Y4 ≤ 3 mm de + PC14/PC15; capacitores de carga pegados al cristal, 2 vías GND, ninguna pista de capa interna bajo el cristal ni sus líneas + (hoy Y3 tiene `/USART6_RX` en In1 bajo las dos líneas HSE y `/BAT_PLUS` en las 4 capas al lado). +- [ ] **Piezas chicas nuevas (L-38):** R140 (4.7 k) en U11.37 (E-02); R139 (100 k) en U12.2 y pista `/ETH_PWR_EN` al pad 54 (E-01); + R144 (100 k) en la base de Q5 (D-09); R141 (100 k) pull-up en `/PFO`, ruteado U6.20 → PB10 (A-13); R142/R143 en + `/MODEM_STATUS` y `/DIN_4G` (B-10); R56 ahora a `/3V3` (A-11). +- [ ] **L-56 Fila de pads de depuración (D-12):** TP3 SWDIO, TP4 SWCLK, TP5 NRST, TP6 GND, TP7 3V3, TP9 PA9-TX en una fila recta a + 2.54 mm de paso, ≤ 30 mm de pista desde U16, con serigrafía. Así se puede apoyar una pinza pogo 1×6 o un header, sin conector. +- [ ] **L-44 Ethernet:** C90/C91 ≤ 2 mm de U11.20/22; C172/C173 en los pares AVDD 4/8 y 11/21; cada par TX/RX acoplado solo en + F.Cu (100 Ω diferencial), ≤ 1 par de vías. +- [ ] **L-52 J10:** pin 8 → GND con pista ≥ 0.5 mm a 2 vías GND puestas **fuera** de la zona MAGJACK_NO_POUR (sin relleno bajo + los magnéticos). Re-rutear los pines 11/12: J10.12 = `/ETH_ACT_A` (desde R97), J10.11 = `/ETH_ACTLED` (a U11.27). +- [ ] **L-66 Revisión de LEDs de J10:** después del Update, confirmar pad 12 = `/ETH_ACT_A` (a R97) y pad 11 = `/ETH_ACTLED` + (a U11.27), según el plano de Hanrun (amarillo A = 12, K = 11); pad 8 = GND («Connect CHS GND to PCB Ground»). +- [ ] **L-67 JP2 = LFP (seguridad):** después del Update, JP2 debe ser `Drogheda:SolderJumper-3_P1.3mm_Bridged23_RoundedPad1.0x1.5mm` + con el puente de cobre en los pads **2-3** (`/F2_SEL` a GND) y **ningún** puente 1-2 a `/MAIN5V`. Un JP2 Bridged12 olvidado + flotaría un paquete LFP a 4.00 V. Serigrafía «F2: LFP»; SMD, fuera de BOM/CPL. +- [ ] **L-47 (parte):** capacitores de VDD del MCU a ≤ 2 mm de sus pines donde se pueda (D-15). + +### I · Tierras y vías (F-12, F-05) + +- [ ] **L-24 EP:** U25 y U20 → 2 × 3 = 6 vías a 1.0 mm (o 2 × 4 = 8 a 0.8 mm con vías 0.3/0.5); U12 → 2 × 3; U6 → L-15. +- [ ] **L-25 Conexión de pads:** sólida **por pad** en EP, pads GND de U18 y U19, ánodos de D34/D11, pads GND de Cin/Cout. + La zona se queda con alivio térmico (≥ 2 spokes) para pasivos chicos; **no** usar «alivio solo para PTH». +- [ ] **L-26 U19:** una vía tapada en cada hueco de 1.7 mm entre pads GND centrales + anillo perimetral: **≥ 30, meta 40**, nunca dentro de un pad. +- [ ] **L-27 U18:** vías en los centros intersticiales diagonales de la rejilla de 2.1 mm: **≥ 24**. Bajo U18/U19: tapadas o + «epoxy filled & capped». +- [ ] **L-28 U.FL y ESD:** 2 vías GND a ≤ 1 mm de cada pad GND de J12 y J13, y en D28. +- [ ] **L-29 Costura:** toda isla GND ≥ 20 mm² con ≥ 2 vías; ningún punto del polígono GND a > 5 mm de una vía; cerca en la orilla a + ≤ 5 mm de paso (≈ 96 vías); **total ≥ 400 vías GND** (hoy 69); 0 celdas de 20 × 20 mm vacías (hoy 10 de 35). +- [ ] **L-35 Plano In1:** despejar In1 bajo pares USB (J9, J11), cristales y sus líneas, nodos SW, `/VBAT_MODEM` y zona RF, líneas + de SIM y los tres paralelos (I2C_SDA/`/SER_TXB`, ETH_XO/`/ETH_RST`, NRST/`/USART6_RX`); pasar pistas a In2/B.Cu en el orden + de F-05. Meta: ≤ 3 islas en In1, ninguna red crítica sobre un vacío > 1 mm. + +### J · Conectores y barrenos (G-01, G-02, G-04, G-08, F-14, F-17) + +- [ ] **L-40 Barrenos (G-01, decidido D11):** restaurar **MH4 (Ø3.2 NPTH) en (193.2, 90.3)**; poner la pareja de barrenos de la + abrazadera del disipador junto a U19 (elegir posición nueva; la de MH11 de la V5.5 ya choca con U19); radio ≥ 4.0 mm sin + cobre en F.Cu/B.Cu alrededor de cada barreno (mover ≥ 0.5 mm la pista `/3V3` de MH6) o especificar rondanas de nylon. +- [ ] **L-41 ESD de J9 (G-02):** U30 (USBLC6-2SC6) a ≤ 3 mm de cobre de los pads de J9; D± pasando por sus pads (1/6 `/USB_DM`, + 3/4 `/USB_DP`, 5 `/USB_VBUS`, 2 GND); vía GND ≤ 1 mm. +- [ ] **L-42 ESD de J11 (F-14):** D+/D− de DFU pasando por los pads de D14/D15 (sin stubs); D15 ≤ 3 mm de cobre de J11 + (hoy 10.9 mm); cada pad GND de ESD con su vía ≤ 1 mm. +- [ ] **L-43 Pares USB (F-17):** pares de J9 y J11 solo en F.Cu sobre In1 sólido, acoplados (≈ 0.2/0.15 mm para 90 Ω en JLC7628, + confirmar con la calculadora), ≤ 1 par de vías, sin cruzar ranuras. +- [ ] **L-58 Resistencias CC de USB-C:** Rcc1/Rcc2 ≤ 5 mm de J9.A5/B5; R100/R101 ≤ 5 mm de J11.A5/B5. +- [ ] **ESD de cables externos (G-08):** D36, D37, D38 en P6.1, P7.1 y P8.1, cada uno a ≤ 3 mm de su conector, a GND. +- [ ] **JP_CUT (G-04):** JP6 sobre P5 (`/MAIN5V`–`/SYS5V`), abierto, serigrafía «CUTOFF BYPASS». + +### K · Serigrafía (F-18, G-05, puertos) + +- [ ] **L-46:** referencias ≥ **0.8 mm** de alto / **0.15 mm** de trazo (1.0/0.15 donde quepa); borrar «4G NTRIP RESET» en + (187.0, 124.1); SW1 «RESET MCU», SW2 «BOOT0 (DFU)»; JP2 «CHEM 1-2 Li-ion / 2-3 LFP»; leyenda de P1 + «VIN 9-36V · GND · IGN · GND · NC»; nombre de función en cada conector (FAN, RESET, NTC1, NTC2, LED, BATT, CUTOFF, + 5V BENCH); limpiar los 14 avisos de serigrafía del DRC; revisar en 3D las marcas de polaridad de D27/D28/Q10. +- [ ] **L-59 Serigrafía de puertos:** P11 «RS-485 A+ B− GND»; P12 «RS-232 TX RX GND»; JP5 «TERM»; R145/R146 «BIAS DNP»; + H4 «UART-B TTL 3V3 TX RX GND»; J9 «MODEM USB»; J11 «DFU»; TP8/TP12 «USB_BOOT / 1V8»; P2 «5 V ONLY, BENCH». + +### L · Cierre y aceptación (L-47, L-60, L-61, L-48) + +- [ ] **L-47:** alargar 0.3 mm el final de la pista `/SW_5V` en (86.35, 121.88) hasta el centro del pad U21.3. +- [ ] **L-60 Atributos de huella:** TP1–TP12 y JP1–JP6 como SMD y «excluir de BOM y de archivos de posición» en el PCB (ya está + así en el esquemático); luego reactivar la revisión DRC `footprint_type_mismatch`. +- [ ] **L-61 Fiduciales:** tres fiduciales globales (cobre 1.0 mm, abertura de máscara 2.0 mm) en F.Cu en tres esquinas (por los + LGA U18/U19 y las piezas de 0.5 mm de paso). +- [ ] **L-48 Rellenar todas las zonas → DRC** con las reglas nuevas: + - [ ] **0 errores de separación**, 0 sin conectar. + - [ ] Avisos de `track_width` solo en redes dejadas a propósito en T15. + - [ ] Vías GND ≥ 400 y 0 celdas de 20 mm vacías; todo pad GND de U19/U18/U20/U25/J12/J13 con vía al plano a ≤ 2 mm. + - [ ] Cada lazo de entrada de buck ≤ 1 cm²; ≤ 3 islas en In1. + - [ ] Líneas RF con la geometría de 50 Ω de la calculadora y cercas ≤ 3 mm. + - [ ] EP de U6 con 9 vías; `/SW_BAT` ≥ 2 mm; ninguna red HV24 en capa interna a < 0.5 mm de cobre de bajo voltaje. +- [ ] Generar BOM/CPL (Fabrication Toolkit) **solo después** de quitar el `LCSC Part` de U25. +- [ ] `git add` + `commit` + `push` en HBox_PCB y **avisar a Leo**. + +--- + +## 6. Firmware 0.7.x (`board_v6.h`) + +No detiene el pedido, pero sin esto la v6 no cumple R1/R3 en batería y los puertos no arrancan bien. Detalle: §8 del +[informe original en inglés](v6-full-audit.md#8-firmware-requirements-board_v6h-fw-07x) y las notas de firmware de los +[resumen de cambios](v6-cambios-resumen.md). + +**Arranque e identidad** + +1. **`board_v6.h` nuevo** desde `pinmap-v6.md`. Un binario **nunca** cruza entre V5.6 y v6: una compilación V5.6 maneja PC3 + (RTK_STAT, salida del F9P en v6) y PC1/PC2. **Identificación de tarjeta solo por firmware** (D-08): al arrancar, leer el + WHO_AM_I del SC7A20 en 0x18 (pieza que solo tiene la v6) y comprobar que el F9P responde en USART2, **antes** de manejar + cualquier pin exclusivo de la v6. +2. **Primeras líneas de `setup()`**, antes de cualquier espera o USB, en bajo: PC10 `MODEM_PWR_EN`, PC8 `PWRKEY`, PC11 + `MODEM_RST`, PA1 `GNSS_PWR`, **PB5** (`BYP_CTRL`, ya sin carga: salida en bajo o analógico), **PA15 `ETH_RST`**, PA6 + ventilador, PB0 LED de panel y **PD2 `ETH_PWR_EN`**. PA8 `CHRG_EN` es del gobernador (alto = carga apagada; con A-11 + el cargador ya arranca apagado por hardware). +3. **Pines nuevos:** **PD2** = `ETH_PWR_EN` (E-01) · **PB10** = PFO, EXTI10 en flanco de bajada = entrada a respaldo + (VEH5V < 4.40 V) (A-13) · **PC5** = `NTC_CELL`, ADC1_IN15, relación 120/220, válido solo con `/VEH5V` presente (F-51) · + **PC2** = antena en corto (C-01) · **PA9** = TX de depuración en TP9. +4. **Ignición por ADC** (D-05): PA5 = ADC1_IN5, sin pull interno; con Rigb1 = 2.2 k la relación es **0.0833** + (12 V → 1.00 V, 24 V → 2.00 V, 36 V → 3.00 V, lineal hasta 39.6 V). Campo nuevo `vign` en `$PHLG`. + +**Energía y temperatura** + +5. **Constantes:** `V5_PFI` 4.60 → **4.40 V** (bajando; subiendo 4.51 V); `CHG_RAIL_ON` 5.05 / `CHG_RAIL_OFF` 4.90 + (válidos con R121 = 57.6 k); VDDA desde **VREFINT** en cada ventana, nunca 3.30 V fijo. +6. **Temperaturas:** **TMP102 en 0x48** = cargador (`tchg`, F-51) · **TMP102 en 0x49** = módem (`tmodem`, F-52) · `tcell` por PC5. + Borrar el TMP102 de la V5 como sensor de celda y el parche PCF8574 P7 de reset del módem. Gobernador: `CHG_CELL_HOT/COOL` + sobre `tcell` (Li-ion 45/40 °C; LFP 55–60 °C); cortar carga con `tchg` > 85 °C. +7. **En batería (D9):** **solo LTE** (`AT+CNMP=38`) — los picos GSM de 2.8 A superan el límite de 2.5 A del respaldo — + y **Ethernet apagado** (`ETH_PWR_EN` = 0). +8. **Secuencia de ventana:** `PWR_CTRL` alto → F9P asentado (≥ 1–4 s) → BAT_SENSE ≥ 3.4 V (no arrancar el módem en frío abajo + de ≈ 3.4 V) → W5500 apagado → `MODEM_PWR_EN` alto → ≥ 100 ms → PWRKEY 100–500 ms → esperar STATUS alto (típ. 7–11.2 s, + máx. 20 s) → sincronizar AT a 115 200 → `AT+CNMP=38` en batería → reportar (≥ 2 `$PHLG` con `pwr=BATT`) → apagado. + Ya no hay paso de relé (K1 fuera). +9. **Retro-alimentación del F9P:** con U27 en la tarjeta, reiniciar solo el F9P con el módem encendido es seguro. Se mantienen + las reglas de 0.5.5/0.5.6: con PA1 bajo, PA2 entrada sin pull, PA10 sin pull, PC7 sin pull-up, PC12 liberado. +10. **Identidad en el enlace:** `$PHID` (UID de 96 bits) por el enlace del **módem** al conectar y cada 5 min; el backend + debe mapear UID → número H antes de que salga la v6. + +**Puertos** + +11. **Bus I²C a 100 kHz** (límite del PCF8574). Mapa: 0x18 SC7A20 (INT1 → PB9, EXTI9), 0x20 PCF8574 (P0–P3 LEDs de batería, + P4–P6 cátodos RGB de P10, activos en bajo), 0x44 SHT40, 0x48 y 0x49 TMP102, 0x4D SC16IS752. +12. **SC16IS752 (U10):** `BOARD_SER_XTAL_HZ 3686400`; divisor = 3 686 400/(16 · baud): 9600 → 24, 19 200 → 12, 38 400 → 6, + 57 600 → 4, 115 200 → 2. Después de **cada** reset del MCU escribir IOControl.SRESET (bit 3), porque RESET̅ no tiene + línea del MCU. Habilitar los FIFO. **IODir = 0xFF, IOState = 0x00** (GPIO0–7 como salidas en bajo). IRQ̅ en **PB8** + (EXTI8, flanco de bajada, sin pull interno; R81 es externa). +13. **CTS sin usar:** CTSA̅/CTSB̅ están a GND → dejar el auto-CTS (EFR[7]) apagado. +14. **RS-485 (canal A): EFCR = 0x10** (RTSCON = 1, RTSINVER = 0) = dirección automática. RTSA̅ baja al transmitir y U32 lo + convierte en DE = 1; en reposo y en reset queda en recepción. **Nunca** poner RTSINVER. EFR[6] (auto-RTS) y EFR[7] = 0. + **Después de cada trama:** esperar LSR[6] (TEMT), vaciar el FIFO RX (FCR[1]) y leer LSR para limpiar los errores de + la transmisión; recién entonces armar la recepción (alternativa: EFCR[1] RXDISABLE mientras se transmite). Modbus RTU: + los silencios de 3.5 caracteres los mide el MCU. +15. **RS-232 (canal B) y H4:** 8N1, sin control de flujo; P12 o H4, uno a la vez. +16. **Ethernet:** al arrancar PA15 y PD2 en bajo. Encendido: pines SPI en bajo → PD2 alto → ≥ 2 ms → RST̅ bajo ≥ 500 µs → + soltar → 1 ms (PLL) → SPI modo 0 a ≤ 21 MHz → VERSIONR = 0x04 → PHYCFGR. EXTI0 (PC0) solo con PD2 alto. Apagado o + batería: RST̅ bajo, pines SPI en bajo o analógicos, PD2 bajo. Los LEDs los maneja el PHY. +17. **USB DFU (J11):** el DFU de ROM necesita el HSE de 25 MHz (Y3). En el CDC de la aplicación, **desactivar el sensado de VBUS**. +18. **USB del módem (J9):** solo enumera con el módem encendido; agregar un comando de servicio que lo mantenga encendido para + FOTA/depuración. **Descarga forzada: TP12 (1.8 V) a TP8** al encender el módem; si J9 no enumera el puerto de descarga, + **TP8 a GND** (los documentos de SIMCom se contradicen en la polaridad). +19. **UART del módem:** **K1 ya no existe en el circuito** — PC6 USART6_TX llega directo por **R148** a `/DIN_4G`. Quitar + todo paso de `BYP_CTRL`/Modo B y dejar **PB5 en bajo** (o analógico). PC7 RX por R106 1 k, 115 200 Bd. PC9 STATUS tiene + pull-down por hardware. +20. **Otros:** LSE con `LSEMOD` (alto drive) antes de `LSEON` y respaldo a LSI (D-03); F9P con + `CFG-HW-ANT_CFG_VOLTCTRL` / `SHORTDET` = 1 (C-01); ventilador en PA6 como GPIO (TIM3 libre para el PPS); la SIM no + tiene línea de detección: dejar desactivada la detección en caliente del módem. +21. **Paquete LFP-HT (D20):** reescalar la conversión del NTC en PC5 para RBIAS 5.6 k y β 3380; subir el corte en caliente de + `CHRG_EN` en línea con la ventana de hardware de +60 °C (si no, manda el firmware); cambiar el SoC por voltaje + (`BAT_CRITICAL`/`BAT_RECOVERY`) por umbrales LFP o conteo de carga; en la primera tarjeta, **antes de conectar el paquete**, + medir `/F2_SEL` = 0 V, `/F1_SEL` = 0 V y `/F0_SEL` = MAIN5V. + +--- + +## 7. Compras y pedido + +Sin precios en esta página: el análisis de costo está en la copia del repositorio. + +- **Paquete de respaldo:** LFP-HT 26650 4P con NTC 10 k **B3380**, el mismo de V5.6 (D20). Con otro β la ventana de carga se corre. + +- [ ] **Cantidad:** **20 prototipos primero** (D14). +- [ ] **Pre-órdenes en la cuenta de JLC** (categoría «Pre-ordered», sin eso no se colocan): + **THVD1410DR (C2671345)**, **TPS7A2033PDBVR (C2862740)** y **J14 (C2977286)**. U18 y U19: pre-ordenar o consignar si + se va a ≳ 100 tarjetas. +- [ ] **Conectores hembra de P11/P12:** son headers enchufables DEGSON 15EDGRC-3.5-03P; comprar aparte los conectores + **15EDGK-3.5-03P, 2 por tarjeta**, con el arnés (no están en el BOM de la tarjeta). +- [ ] **PCB:** 4 capas, 1.6 mm, stackup **JLC04161H-7628 con control de impedancia**, **ENIG** (obligatorio por los LGA U18/U19), + **cobre interno de 1 oz** (D12). +- [ ] **Ensamble:** rayos X en U18 y U19; vías tapadas (bajo U18/U19, tapadas o «epoxy filled & capped»). +- [ ] **Stock el día del pedido:** re-verificar todo en el carrito (en la base del 28-sep: U19 96, U18 104, P11/P12 512). +- [ ] **Archivos:** BOM/CPL con Fabrication Toolkit **después** de quitar `LCSC Part` de U25 (H-04). TP1–TP12 y JP1–JP6 no van + en el BOM ni en el CPL. Revisar rotaciones en la vista previa de JLC. + +--- + +## 8. Lista de liberación (GO) + +Se puede ordenar cuando **todo** esto esté cerrado: + +- [x] **Esquemático terminado y verificado** de forma independiente (sch `d58a89ba…e7b`, ERC 0 errores, 299 piezas + montadas con número LCSC). +- [ ] **Update PCB hecho y revisado** (paso 0): huellas cambiadas, 46 piezas nuevas colocadas, DNP correctos, U25 sin `LCSC Part`. +- [ ] **JP2 en 2-3 confirmado en el PCB** (L-67): flotación LFP 3.50 V. +- [ ] **Layout de los 11 Blockers cerrado:** A-01, F-02, F-01 (cobre), H-04 (campo en el PCB), C-01, B-03, A-02, H-01 y G-01 + (MH4 restaurado en (193.2, 90.3) y la pareja de la abrazadera junto a U19). A-03 y H-02 ya quedaron cerrados en el esquemático. +- [ ] **Layout de los 19 Majors cerrado**, o con razón escrita por Leo. Cuatro son prerrequisito de A-01 y no se pueden separar: + A-04, A-05, A-07 y los Cin de U20 de F-03. +- [ ] **Layout de los puertos:** L-49…L-66. +- [ ] **Puerta de DRC:** rellenar zonas + DRC con las reglas de F-01 → **0 errores de separación**, más la aceptación completa de L-48. +- [ ] **Compras:** BOM/CPL generados después de H-04; stock re-verificado el día del pedido; THVD1410DR, TPS7A2033PDBVR y + J14 pre-ordenados (U18/U19 si ≳ 100); conectores hembra de P11/P12 comprados. + +El firmware 0.7.x (sección 6) es necesario para R1/R3 y para los puertos, pero **no** detiene el pedido. +**No habrá nueva versión: todo se hace en este pedido.** Lo que no se hace está en la sección 9. + +--- + +## 9. Aceptado permanentemente + +Estos puntos **no** se harán, en este pedido ni después. Cada uno tiene su razón. Todo lo demás de la auditoría está +aplicado en el esquemático, en la lista de Michelle o en el firmware. + +| # | ID | Qué | Por qué es seguro durante la vida del producto | +|---|---|---|---| +| 1 | **A-10** | Sin protección de sobretensión en VEH5V (corto del lado alto del TPS54360B, o más de 6 V por P2) | Requiere una falla de componente o un mal uso en banco. En campo la entrada es el 24 V regulado y limitado en corriente del gabinete (DDR-60G-24, D1), y F2 de 3 A limita la energía. La opción OVP de la hoja de datos (MN1 + 6.2 k, compartiendo IGATE con Q7) además mueve el divisor PFI al lado crudo y cambia cómo se recupera el modo respaldo: un error ahí rompería la operación normal en **todas** las tarjetas, que es peor que la falla rara que evita, y no se puede validar sin un ciclo de banco. P2 lleva la serigrafía «5 V ONLY, BENCH» (L-59). **Es el único riesgo aceptado a conciencia en la ruta de potencia.** | +| 2 | D-08 | Strap de identificación de tarjeta | Decisión D8: solo firmware. La v6 se identifica al arrancar por el WHO_AM_I del SC7A20 en 0x18 (pieza que solo tiene la v6) y el F9P respondiendo en USART2, antes de manejar cualquier pin exclusivo de la v6. Los nombres de binario llevan la tarjeta. PD2 es `ETH_PWR_EN` y PA9 es el pad de depuración. | +| 3 | E-06 (opción) | Arreglo ESD de baja capacitancia entre el magjack y U11 | Los magnéticos del HR911105A aíslan el cable (1500 Vrms), el diseño de referencia de WIZnet no lleva arreglo y el cableado queda dentro del gabinete. J10.8 (retorno Bob-Smith) ya se corrigió. | +| 4 | E-07 | PoE | No es requisito (Leo: los puertos deben funcionar; no se mencionó PoE). La decisión registrada es un splitter externo. | +| 5 | A-20a | U12 MP1584EN → AP64350 | U12 ahora se apaga con PD2 (E-01), solo trabaja con alimentación del vehículo y está probado en la V5.5. Cambiarlo exigiría nueva compensación/RT y otro land: más riesgo sin ganancia funcional. | +| 6 | G-07 | P3 XH-3 → XH-5/VH | 3 A por contacto contra 1.4 A de carga (R50 1.43 k), 0.6–1 A promedio en respaldo y ≈ 2 A de pico solo LTE (D9). XH-3 mantiene compatibles los paquetes 1S4P que ya están en campo. | +| 7 | G-06 | Alimentando solo por P2, VEH5V retro-alimenta por el diodo del cuerpo de U25 hasta P1.1 (≈ 4 V) | Benigno: con A-01 la rama Q10/U2 está DNP, así que nada en `/24V` queda alimentado. Documentado para el procedimiento de banco. | +| 8 | F-14 (opción) | Un USBLC6 en J11 en vez de D14–D16 | USB full speed tolera la capacitancia de los PESD5V0S1BA (probado en la V5.5). El problema de stubs se resuelve con el ruteo (L-42). | +| 9 | G-08 (opción) | 100 Ω en serie en NRST | D36 (PESD5V0S1BA) y C104 100 nF ya recortan y filtran el cable de P6; una R en serie partiría `/NRST` sin ganancia medible. | +| 10 | J-03 | Re-tipificar los pines `unspecified` de la librería | Cosmético. Los avisos se revisaron red por red (un solo excitador, sin conflictos); los tipos de pin no llegan al netlist, al BOM ni al PCB; la base de 134 avisos está registrada, así que un aviso nuevo se detecta por diferencia. | +| 11 | J-04 (re-enlace) | 10 símbolos «no encontrados» (+ TPS2552) sin copiar a una librería | Cosmético. Las copias embebidas hacen el esquemático autosuficiente y se revisó pin → pad → red en 25 piezas (H-09). Re-enlazar cambiaría 11 lib_ids sin efecto eléctrico. | +| 12 | B-09 (opción) | ESD (arreglo) en `/SIM_VDD` | La SIM se inserta una vez, en la instalación, dentro del gabinete. Datos, CLK y RST tienen D23–D25 (junto a J14 por L-38), y VDD tiene C171 100 nF en J14. | +| 13 | A-16 | Montar R124/R125 (UVLO de U25) | La tarjeta siempre ve el 24 V regulado del gabinete (D1): la banda de caída de 4.3–5.8 V nunca se alcanza en servicio. | +| 14 | A-18 (+ opción R123) | Compensación de U25 | El ejemplo de la hoja de datos, con margen de fase ≥ 60° (estimado de la auditoría), no requiere cambio; el escalón 0.3 → 2.5 A es parte del arranque en banco. | +| 15 | A-19 | Load dump ISO 16750-2 | El DC-DC del gabinete aísla la tarjeta del bus del alternador. SMCJ33A/SMBJ33A aguantan 36 V/60 min y los pulsos rápidos ISO 7637; F2 abre detrás de ellos si un TVS queda en corto. | +| 16 | A-20b | F1 (PPTC de 3 A) ahora solo protege la rama del LDO del F9P | Inofensivo y no necesario para protección; dejarlo evita cambiar una huella. | +| 17 | C-05 (opción) | C143 100 nF → 47 pF C0G como bloqueo de DC | Un 100 nF X7R 0402 está dominado por su ESL en L1/L2 (≈ 3–4 Ω); pérdida < 0.01 dB después de un LNA de antena de ≥ 25 dB. | +| 18 | D-06 (opción) | D5 BAT54 → BAT54S | Verificador 2: opcional una vez que el SMBJ33A (D35) está en P1.3 (aplicado). | +| 19 | A-03/A-04 (opción) | R121/R122 al 0.1 % | 5.18–5.46 V con 1 % cumple VIN ≤ 5.5 V del LTC4040 y los umbrales del gobernador; no hay piezas de 0.1 % en la base de LCSC. | +| 20 | A-13 (opción) | CLPROG → ADC | No queda pin de ADC (PC5 se usó para el NTC del paquete). CLPROG se queda en TP1 para medir corriente en banco. | + +!!! note "Dos avisos de la revisión final (no son fallas)" + - **RXA flota mientras el RS-485 transmite** (con RE̅ unido a DE el receptor queda en alta impedancia). No viola ninguna + hoja de datos y no detiene el puerto; se resuelve en firmware vaciando el FIFO RX después de cada trama (sección 6). + - **Polaridad de USB_BOOT del A7670:** los documentos de SIMCom se contradicen. Procedimiento en banco: TP8–TP12 (1.8 V) + primero; si J9 no enumera el puerto de descarga, TP8–GND (L-65). + +--- + +## 10. Validación en banco (cuando lleguen las tarjetas) + +Para **Jesús** y el banco. Antes de aceptar las tarjetas v6: + +| # | Prueba | Qué se espera | Hallazgo | +|---|---|---|---| +| 1 | Cámara térmica sobre U6/L6 a **1.4 A de carga** y a **2.3 A de respaldo**, 1 h cada una | Sin ciclado térmico del cargador | A-02 | +| 2 | Pinza DC en el cable del paquete durante la carga + IR de U6/L6 | 1.316–1.483 A de carga (seguimiento de H0008) | A-02 / A-03 | +| 3 | Arranque en frío **solo con batería** a VBAT 3.5 V: osciloscopio en `/MAIN5V` y VIN de U20, sonda de corriente en `/BAT_PLUS` | El módem registra sin que VSYS se caiga | A-05 (ECO §I-1) | +| 4 | Escalón de carga **0.1 → 2 A** en VBAT_MODEM | Caída ≤ 150 mV, sin oscilación | B-02 | +| 5 | Subida de `/3V3_GNSS` en el osciloscopio | 100–1000 µs/V | C-02 | +| 6 | Corto de antena GNSS | Corriente limitada y aviso en `/GNSS_ANT_SHORT_N` (PC2) | C-01 | +| 7 | `/3V3_GNSS` con PA1 en bajo y el módem encendido | < 0.3 V | D-01 | +| 8 | Prueba **G3** de desensibilización: potencia TX del módem contra C/N0 del F9P | Registrar el C/N0 del F9P con el módem en reposo y transmitiendo a distintas potencias | F-06 / F-12 | +| 9 | IR de D34/U25 a carga completa | Registrar la temperatura (D34 disipa ≈ 0.8 W con el arreglo de A-01) | F-03 | +| 10 | Frecuencímetro en Y1 | ±10 ppm | E-03 | +| 11 | J10 con enlace Ethernet activo | Encienden los dos LEDs: verde (LINK) y amarillo (ACT) | P-3 | +| 12 | RS-485 durante el reset del MCU y en DFU | El transceptor queda en recepción (DE bajo), no ocupa el bus | P-1 | +| 13 | Loopback RS-485 a 9 600 y 115 200 Bd con EFCR = 0x10 | Los datos regresan completos; revisar el vaciado del FIFO RX | P-1 | +| 14 | Loopback RS-232 | Los datos regresan completos | P-2 | +| 15 | Adaptador TTL en H4, con RS-232 en reposo | El adaptador maneja RXB | H4 | +| 16 | J9 con el módem encendido; modo de descarga con TP8–TP12 (si no, TP8–GND) | J9 enumera; el puerto de descarga aparece | G-02 / P-5 | +| 17 | Juntas de soldadura de L6, L8 y L20 en el land nuevo | Inspección visual correcta | H-03 | + +--- + +## 11. Impacto en V5.6 + +Dos cosas encontradas de paso que afectan a la V5.6 (antes de su pedido): + +- **R112 en `ETH_RST`: 100 k → 4.7 k (C23162).** El pull-up interno del W5500 (62–112 kΩ) más el pull-up JTDI de PA15 + anulan un pull-down de 100 k (E-02). +- **Huella de U15:** los esquemáticos V5.x todavía traen el campo viejo SOIC-16W. Corregirlo a + `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm` **antes de cualquier *Actualizar PCB*** en la V5.6, para no romper el land angosto + que funciona en la V5.5 (H-01). + +--- + +## 12. Enlaces + +- [Cambios de esquemático — resumen de 3 pasadas](v6-cambios-resumen.md): las tres pasadas, estado final por bloque y + delta de layout. Informes de cada pasada: [pasada 1 — informe de cambios al esquemático](v6-cambios-esquematico.md), + [pasada 2 — puertos y sin nueva versión (inglés)](v6-puertos-sin-nueva-version.md), + [pasada 3 — revisión final (inglés)](v6-revision-final.md). +- [Auditoría completa v6 (español)](v6-auditoria-completa.md) · [original en inglés](v6-full-audit.md): evidencia, tablas + pass/fail por bloque, §5–§10. +- [Mapa de pines del MCU v6](v6-pinmap.md) · [Revisión v6 contra lecciones V5.5](v6-revision-lecciones-v55.md) · + [Manual de la tarjeta v6](../manuales/manual-tarjeta-v6.md) +- Histórico: [Auditoría pre-fabricación (25-sep)](v6-auditoria-prefab.md) · [Pre-fabrication audit (25-Sep)](v6-prefab-audit.md) +- [Plan de cobre y colocación EMC (ES)](EinarBoard-v6_Plan-de-Cobre_ES.html) · [Copper plan & EMC placement (EN)](EinarBoard-v6_Copper-Plan_EN.html) +- En el repositorio: el análisis de costo está en la copia de la auditoría en `03-Architecture-Hardware/`; PDF del + esquemático `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf`. diff --git a/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Ports-and-No-Respin_v1.0.md b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Ports-and-No-Respin_v1.0.md new file mode 100644 index 0000000..92b5dea --- /dev/null +++ b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Ports-and-No-Respin_v1.0.md @@ -0,0 +1,288 @@ +--- +title: "EinarBoard v6 — Puertos y sin nueva versión (pasada 2, inglés)" +tags: [project-drogheda, hardware, hbox, v6, esquematico, ports] +project: Project Drogheda +author: Helgen Technologies +date: 2026-09-28 +version: 1.0 +status: FINAL — pass 2 of 3 (ports / no new version) +audience: Michelle (layout), Leo, ingenieros +--- + +# EinarBoard v6: ports end to end and the no-v6.1 close-out (v1.0) + +!!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide" + Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios. + +!!! info "Pass 2 of 3 — ports and no new version" + Spanish summary, final state per block and the combined layout delta: + **[EinarBoard v6 — Cambios de esquemático: resumen de las 3 pasadas](v6-cambios-resumen.md)**. + The final independent check ([pass 3](v6-revision-final.md)) passed this pass 26 / 27. The one FAIL was the + `IND-SMD_MWSA0804S` land in §4.3 and in L-53: the correct land is pads **2.75 × 5.5 mm at ±3.375 mm** + (gap 4.0 mm), courtyard **10.0 × 9.0 mm** (L-63). The schematic hash `f73f41a8…27ee` below was superseded by + `2b394ef9…5f33` (C176 added). + + +**Date:** 2026-09-28 · **Board:** `kicad/hbox-watchdog-v6.*` (HBOX RTK, Helgen Technologies) · **Input state:** the schematic after the apply pass (sha256 `d54e330d…`, netlist `apply/netlists/05-final.xml`; a fresh export was identical) · **Author:** Claude (ports and no-respin pass) · **Rules:** edited in place, span-scoped S-expression splices with a UUID guard, `.kicad_pcb` not touched, no git, backups in `kicad/_to_delete/v6-ports-20260928/`. + +## Resumen (ES) + +Se revisó cada puerto de la v6 corregida, de extremo a extremo (conector → protección → pasivos → transceptor/PHY → pin de MCU o módem → periférico de firmware), contra hojas de datos. **Todos los puertos funcionan como están dibujados después de este pase.** Se encontraron y corrigieron en el esquemático seis defectos que habrían dejado un puerto débil o fallando: + +1. **RS-485:** el SP3485 sólo tiene ±2 kV HBM y fail-safe con entradas abiertas; además, con DE/RE̅ atados a RTS̅ del SC16IS752 (que queda en ALTO tras el reset), el transceptor **transmitía y bloqueaba el bus** durante el reset, en DFU o sin firmware. Se cambió U14 por **THVD1410DR** (mismo pinout, ±18 kV IEC, fail-safe con bus abierto, en corto o inactivo). Se añadió **U32 (inversor 74LVC1G04)**, así que el transceptor arranca en recepción. También se añadió **D39 SM712** en P11 y la opción de polarización R145/R146 (DNP). +2. **RS-232:** el MAX3232 (sin especificación ESD) pasa a **TRS3232EIDR** (mismo pinout, ±8 kV IEC contacto). +3. **Header TTL H4:** estaba en paralelo directo con la salida R1OUT del transceptor. Se añadió **R147 1 k**, así que un dispositivo TTL puede manejar RXB sin contienda. +4. **Ethernet J10:** el LED amarillo (ACT) estaba **invertido** (pines 11/12), así que nunca encendía. El pin 8 (retorno del capacitor Bob-Smith de 1000 pF) estaba sin conectar; ahora va a GND. +5. **SC16IS752:** las entradas CTSA̅/CTSB̅ estaban flotando; ahora van a GND. +6. **Módem USB (J9):** se añadió **TP12 (1V8)** junto a TP8, para forzar el modo de descarga USB. + +USB-C (J9 y J11) ya estaba correcto: CC1/CC2 tenían 5.1 kΩ a GND, D+/D− iban en ambas filas y VBUS no retro-alimenta. No hubo cambios. + +Mapa I²C: **sin colisiones**. En el bus: SC7A20 0x18, PCF8574 0x20, SHT40 0x44, TMP102 0x48 y 0x49, SC16IS752 0x4D. Las direcciones posibles de los TMP102 (0x48–0x4B) no incluyen 0x4D. + +Cierre de «no v6.1»: **H-03 hecho** (nueva huella `IND-SMD_MWSA0804S` con la tierra recomendada por Sunlord, usada en L2/L6/L8/L20) y **B-13 hecho** (K1 DNP; enlace directo PC6 → DIN_4G con R148 0 Ω). TP1–TP8 salen del BOM y del CPL. Se añaden 14 puntos a la lista de Michelle (L-49…L-62) y se aceptan 20 ítems permanentemente, cada uno con su razón. El único riesgo aceptado a conciencia en la ruta de potencia es **A-10**: no hay protección de sobretensión en VEH5V. La opción OVP del LTC4040 mueve el divisor PFI y cambia la recuperación del modo respaldo, y no puede validarse sin banco. Cada grupo se probó con diff de netlist: **lo esperado coincide exactamente con lo obtenido**. ERC: **0 errores** (134 warnings, igual que antes). SHA-256 final del esquemático: `f73f41a8…27ee`. + +## 0. Summary + +| Item | Result | +|---|---| +| Ports traced | 24 (every J/P/H/SW/TP ref plus the internal modem, GNSS and I²C interfaces) | +| Port verdicts | 17 ✅ as drawn · 7 🔧 fixed now (RS-485, RS-232, H4, SC16IS752 CTS, Ethernet LEDs + Bob-Smith, modem USB boot pad, modem UART B-13) · 📐 layout items on 11 ports · ⚙ firmware items on 14 ports | +| USB-C CC | **J9 and J11 both correct:** Rcc1/Rcc2 and R100/R101 = 5.1 kΩ 1 % (C23186) CC→GND; D+ A6/B6 and D− A7/B7 tied; no VBUS back-feed | +| I²C collisions | **None** (map in §3) | +| Schematic groups | P1 ports · N1 no-respin · C1 cleanup: **8 parts added, 0 removed, 41 field changes, 8 pin-net changes, 0 net-class changes**. Each group: expected == actual; composed = total, 0 differences | +| ERC (kicad-cli 10 via KiCad MCP) | 0 errors after every group; warnings 134 → 134 | +| Overlaps / wire crossings | 30 → 30 / 9 → 9 (all pre-existing; none involve a new part) | +| BOM | all 298 fitted real parts have an LCSC number (TP1–TP12 and JP1–JP6 are now out of the BOM/CPL; the PF* power flags are virtual) | +| New library file | `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod` (sha256 `dbf53557…`) | +| Untouched | `.kicad_pcb` `6ddec80d…`, `.kicad_pro` `d577aa43…`, `.kicad_dru` `31ce0f4f…` | +| Michelle's list | +14: L-49 … L-62 (§5) | +| Accepted permanently | 20 items (§7); done now: 17 (§8) | + +## 1. Port-by-port verification + +Legend: ✅ works as drawn · 🔧 fixed now (schematic) · 📐 layout item added (L-nn) · ⚙ firmware item (§6). +Datasheets used: TI THVD1410, TI SN65HVD72, MaxLinear SP3485, ADI/Maxim MAX3222-MAX3241, TI TRS3232E, NXP SC16IS752/762, WIZnet W5500 v1.1.0, the KiCad `Connector:RJ45_Hanrun_HR911105A_Horizontal` symbol (drawn from the Hanrun HR911105A sheet; see §1.6), Semtech/Littelfuse SM712, ADI LTC4040 Rev B, Sunlord MWSA-S series spec, and AOS AO4264E. Pin and net evidence comes from `ports/netlists/final.xml` (= `03-cleanup.xml`). + +| # | Port | Chain (final) | Checks | Verdict | Evidence | +|---|---|---|---|---|---| +| 1 | **RS-485 (P11)** | P11.1 `/RS485_A`, P11.2 `/RS485_B`, P11.3 GND → **D39 SM712** (A/B → GND) · R82 120 Ω + JP5 (open) termination · R145/R146 390 Ω bias (DNP) → **U14 THVD1410DR** (6 A, 7 B, 8 VCC `/3V3` + C84, 5 GND) → 1 RO `/SER_RXA` → U10.4 RXA · 4 DI ← `/SER_TXA` U10.3 TXA · 2 RE̅ + 3 DE ← `/RS485_DE` ← **U32 74LVC1G04** ← `/SER_DEA` ← U10.1 RTSA̅ | A/B polarity: P11.1 = A = U14.6 ✅ · Pinout of THVD1410 D pkg = SP3485 (R, RE̅, DE, D, GND, A, B, VCC) ✅ · RTSA̅ is **HIGH after reset** (NXP DS). With the old direct tie, DE = 1 during reset, DFU and unflashed boards, so the node drove the bus (**bus hog**). U32 inverts it: receive at reset; auto-RS-485 with EFCR RTSCON=1, RTSINVER=0 ✅ · Fail-safe: SP3485 = open inputs only; THVD1410 = open, short and idle bus ✅ · ESD: SP3485 ±2 kV HBM only → THVD1410 ±18 kV IEC contact, ±30 kV HBM, EFT ±4 kV; surge by SM712 (−7/+12 V, 400 W 8/20 µs); THVD1410 bus abs max ±18 V ✅ · Termination by solder jumper (bus ends only) ✅ · 3.3 V supply, logic 3.3 V ✅ · Speed: THVD1410 500 kbps > SC16IS752 max 230.4 kBd at 3.6864 MHz ✅ | 🔧 📐 L-49/L-50/L-59 · ⚙ | `01-ports.xml`: `/RS485_DE` = {U14.2, U14.3, U32.4}; `/SER_DEA` = {U10.1, U32.2}; `/RS485_A` = {P11.1, U14.6, R82.1, D39.1, R145.2} | +| 2 | **RS-232 (P12)** | P12.1 `/RS232_TX` ← U15.14 T1OUT · P12.2 `/RS232_RX` → U15.13 R1IN · P12.3 GND · **U15 TRS3232EIDR**: C85 C1± (1/3), C86 C2± (4/5), C87 V+ (2)→GND, C88 V− (6)→GND, all 100 nF; C89 100 nF VCC (16) `/3V3`; T1IN (11) ← `/SER_TXB` U10.23 TXB; R1OUT (12) → `/RS232_R1OUT` → **R147 1 k** → `/SER_RXB` U10.24 RXB; T2IN/R2IN → GND, T2OUT/R2OUT NC | Pinout identical to MAX3232 (1 C1+ … 16 VCC) ✅ · Pump caps 0.1 µF at 3.0–3.6 V per both datasheets ✅ · V+ cap to GND allowed ✅ · Unused TX input tied, RX input tied (5 kΩ internal) ✅ · Channel B of U10 ✅ · Direction: board TX on pin 1 (DTE-style, cross to the far end's RX) ✅ · ESD: MAX3232 (non-E) has **no ESD rating** → TRS3232E ±15 kV HBM, **±8 kV IEC contact**, ±15 kV air ✅ | 🔧 📐 L-51/L-59 · ⚙ | `/RS232_R1OUT` = {U15.12, R147.1} | +| 3 | **TTL UART B (H4)** | H4.1 3V3, H4.2 `/SER_TXB` (U10.23 + U15.11), H4.3 `/SER_RXB` (U10.24 + R147.2), H4.4 GND | Before: H4.3 was hard-wired to U15 R1OUT, so an external TTL TX fought a CMOS output (R1OUT idles HIGH when R1IN is open). With R147: an external driver wins (≤ 3.3 mA, VIL ≈ 0.16 V with a 50 Ω driver); normal RS-232 RX delay 1 k × ~10 pF ≈ 10 ns ✅ · Use H4 **or** P12, not both at once | 🔧 · ⚙ | `/SER_RXB` = {U10.24, H4.3, R147.2} | +| 4 | **SC16IS752 bridge (U10)** | I2C/SPI̅ (9) = `/3V3` → **I²C mode** · A0 (10), A1 (11) = GND → **0x9A = 7-bit 0x4D** · Y2 3.6864 MHz (C2238) + C82/C83 22 pF on XTAL1/2 (6/7) · IRQ̅ (15) open-drain → R81 10 k → `/3V3`, → U16.61 **PB8** · RESET̅ (5) → R80 10 k → `/3V3` (POR inside; no MCU control) · VDD (8) `/3V3` + C81 · ch A = RS-485, ch B = RS-232/H4 · CTSA̅ (2), CTSB̅ (16) → **GND** (were floating) · GPIO0–7 NC | Address table verified (A1=VSS, A0=VSS → 0x9A) ✅ · Crystal: divisors exact for 9600…230400 ✅ · IRQ̅ is open-drain and needs the pull-up; NXP quotes 1 k for fast edges, but 10 k only slows the de-assert edge (≈ 0.2 µs), which is fine for a level-read EXTI ✅ · POR exists, so R80 is enough; firmware issues IOControl.SRESET after every MCU reset ✅ · I²C max 400 kHz (the bus runs at 100 kHz, see #5) ✅ · Floating CTS inputs removed; GPIOs set to outputs in firmware | ✅ 🔧 (CTS) · 📐 L-57 · ⚙ | `03-cleanup.xml`: U10.2, U10.16 → GND | +| 5 | **I²C1 bus** | PB6 SCL (U16.58) / PB7 SDA (U16.59), AF4; R30/R31 4.7 k to `/3V3`; U3, U10, U13, U26, U29, U31 | Map in §3: no collision ✅ · PCF8574T (C7605) is a **100 kHz** device, so the whole bus runs at 100 kHz · tr ≈ 0.85 × 4.7 k × ~80 pF ≈ 0.32 µs < 1 µs ✅ · sink 0.7 mA < 3 mA ✅ · ZED-F9P DDC (0x42) **not wired** (U18.44/45 NC), A7670 CI2C NC ✅ | ✅ · ⚙ | nets `/I2C_SCL`, `/I2C_SDA` | +| 6 | **Ethernet (J10 + U11)** | U11 TXP/TXN (2/1) → J10.1 TD+ / J10.2 TD−, each 49.9 Ω (R92/R93) to `/3V3_ETH`, J10.4 TCT = `/3V3_ETH` · RXP/RXN (6/5) → J10.3 RD+ / J10.6 RD−, R94/R95 49.9 Ω to `/ETH_RCT` = J10.5 RCT + C97 6.8 nF → GND · J10.9 green A ← R96 330 Ω ← `/3V3_ETH`, J10.10 green K → U11.25 LINKLED · **J10.12 yellow A ← R97 330 Ω, J10.11 yellow K → U11.27 ACTLED** · **J10.8 → GND** · J10.7 NC · SH → GND · Y1 25 MHz HC-49 + C95/C96 33 pF · EXRES1 12.4 k 1 % · TOCAP 4.7 µF · 1V2O 10 nF · AVDD 100 nF ×6 + 10 µF/22 µF/100 µF · PMODE[2:0] = 111 via R84 (auto-neg) · RSVD23 → GND, RSVD38–42 NC · SPI2: CS̅ PB12, SCK PB13, MISO PB14, MOSI PB15 (AF5) · INT̅ PC0 · RST̅ PA15 + R140 4.7 k PD · 3V3_ETH from U12 MP1584EN, EN = `/ETH_PWR_EN` PD2 + R139 100 k PD | Terminations and centre taps = W5500 reference topology ✅ · LED polarity: the HR911105A symbol draws the yellow LED anode on pin 12 and cathode on pin 11; v6 had 11 = anode supply and 12 = W5500 ACTLED, so **ACT never lit** → swapped 🔧 · Pin 8 is the Bob-Smith 1000 pF return (symbol pin type power_in); it was NC with a flag, so the unused-pair termination floated (EMI/ESD) → GND 🔧 · Y1 load ≈ 19–20 pF for the CL 20 pF part ✅ · W5500 pin table: TOCAP 4.7 µF, 1V2O 10 nF, EXRES1 12.4 k, RSVD23 → GND, 38–42 NC ✅ · RSTn internal pull-up 62–112 k + PA15 JTDI pull-up vs 4.7 k → ≤ 0.66 V < VIL 0.8 V ✅ · MP1584 EN: 1 µA internal pull-up, 100 k → 0.1 V = off; PD2 3.3 V > 1.5 V = on ✅ · W5500 I/O 5 V-tolerant (no back-power through SPI/RST when 3V3_ETH is off) ✅ · J10 footprint `Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal` = part C12074 ✅ | 🔧 📐 L-52 · ⚙ | `01-ports.xml`: J10.8 GND; `/ETH_ACTLED` = {J10.11, U11.27}; `/ETH_ACT_A` = {J10.12, R97.1} | +| 7 | **USB-C DFU (J11)** | GCT USB4085-GF-A (C7095263, USB 2.0 Type-C) · CC1 A5 → R100 5.1 k → GND, CC2 B5 → R101 5.1 k → GND · D+ A6+B6 `/DFU_DP` → D14 → U16.45 **PA12** · D− A7+B7 `/DFU_DM` → D15 → U16.44 **PA11** · VBUS A4/A9/B4/B9 `/DFU_VBUS` → D16 · → D13 SS34 → `/LDO_IN` (U17), OR-ed with D12 from SYS5V · SH → GND · BOOT0 = SW2 to 3V3 + R98 10 k PD; PB2 = R99 10 k PD; HSE Y3 25 MHz | Sink Rd on both CC ✅ · flip support ✅ · PA11/PA12 = OTG_FS DM/DP ✅ · VBUS back-feed: D12 blocks VBUS → SYS5V, D13 blocks the board → host; USB powers only the 3V3 domain ✅ · VBUS sensing is not needed (PA9 is TP9): ROM DFU on F411 runs without it; firmware disables it ✅ · PA10 idles high in DFU via Rdfu1 100 k (so the ROM USART1 detector sees no noise) ✅ · ESD D14–D16 PESD5V0S1BA (full speed tolerates their capacitance; V5.5 proven; routing fixed by L-42) ✅ | ✅ · 📐 L-42 (existing), L-58/L-59 · ⚙ | nets `/DFU_*` | +| 8 | **USB-C modem (J9)** | USB4085 · CC1 A5 → Rcc1 5.1 k, CC2 B5 → Rcc2 5.1 k → GND · D+ A6+B6 `/USB_DP` → U30.3/4 → U19.27 · D− A7+B7 `/USB_DM` → U30.1/6 → U19.28 · VBUS → U30.5 + U19.24 (detect only; feeds no rail) · SH → GND · U19.6 USB_BOOT → TP8, **TP12 = `/1V8_MODEM`** beside it | Rd on both CC ✅ · both D rows tied ✅ · USBLC6-2SC6 (~3.5 pF) suits high speed ✅ · no back-feed path (VBUS only reaches the modem detect pin and the USBLC6 rail pin) ✅ · J9 works only while firmware keeps the modem powered ⚙ · forced download needs VDD_EXT on USB_BOOT at power-on: there was no 1.8 V pad beside TP8 → TP12 🔧 | ✅ 🔧 (TP12) · 📐 L-41/L-43 (existing), L-55/L-58/L-59 · ⚙ | `/1V8_MODEM` gains TP12 | +| 9 | **P1 24 V + ignition** | DIBO DB128V-5.0-5P (C424683, 5.0 mm, 16 A) on `TerminalBlock_Phoenix_MKDS-1,5-5…Horizontal` · 1 `/24V_IN` → F2 3 A → `/VIN_FUSED` (D10, Q23) · 2 GND · 3 `/IGN_IN` → D35 SMBJ33A + Rig1 22 k → `/IGN_SENSE` (PA5 ADC, ratio 0.0833) · 4 GND · 5 NC | Apply-pass fixes V1-01/A-01/F-02 in place ✅ · pin numbering 1–5 = land 1–5 ✅ · 5.0 mm land fits a KF128-class block; confirm hole/pin and wire-entry side (L-62) | ✅ · 📐 L-62 | `/IGN_IN` = {P1.3, Rig1.1, D35.1} | +| 10 | **P2 bench 5 V** | XH-2 (C158012) · 1 `/VEH5V`, 2 GND | Bench-only input; no reverse or over-voltage protection (A-10 and A-20c accepted, §7; silk per L-46) | ✅ (bench use) | — | +| 11 | **P3 battery** | XH-3 (C144394) · 1 `/BAT_PLUS` (L6, U6.23), 2 GND, 3 `/NTC` (R55 10 k to VIN; U6.17; R137 tap → PC5) | 3 A/contact vs 1.4 A charge (R50 1.43 k), backup average 0.6–1 A, LTE-only peaks ≈ 2 A (D9) ✅ | ✅ (G-07 accepted) | — | +| 12 | **P4 fan** | XH-2 · 1 `/5V_FAN` (= VEH5V via JP1 bridged), 2 `/FAN_RET` → Q2 AO3400A (PA6) + D2 flyback | ✅ | ✅ · ⚙ | — | +| 13 | **P5 cut-off + JP6** | XH-2 · `/MAIN5V`–`/SYS5V`; JP6 open bypass | ✅ | ✅ | — | +| 14 | **P6 external reset** | XH-2 · 1 `/NRST` (D36 PESD5V0S1BA, C104 100 nF, SW1, TP5, U16.7), 2 GND | ✅ (renumber hazard handled by silk, L-46) | ✅ | — | +| 15 | **P7/P8 NTC probes** | XH-2 · `/NTC_TEMP` (R42 10 k to 3V3, C24, D37, PB1 ADC IN9) · `/NTC2` (R126, C157, D38, PC4 IN14) | ✅ | ✅ · ⚙ | — | +| 16 | **P9 panel LED** | XH-2 · 1 `/LED_A` (R3 120 Ω from 3V3), 2 `/LED_K` → Q4 (PB0); on-board D1 in parallel | Works with a panel LED of Vf ≤ 2.2 V (it shares ≈ 11 mA with D1) | ✅ (usage rule) | — | +| 17 | **P10 external RGB** | XH-4 · 1 3V3 (common anode), 2–4 cathodes via R89–R91 120 Ω → PCF8574 P4–P6 (sink) | Red about 11 mA; blue/green (Vf about 2.8–3.0 V at 3.3 V) run at a few mA, so they are dimmer. Functional | ✅ | — | +| 18 | **J12 GNSS antenna** | U.FL (C88374) → `/RF_ANT_GNSS`: D27, C143 DC block → U18.2; bias L21 68 nH ← `/ANT_BIAS` ← U28 TPS2552 (75 mA limit, EN̅ = F9P ANT_OFF, FAULT̅ → PC2) | Apply-pass C-01 in place ✅ | ✅ · 📐 L-30/L-33 (existing) · ⚙ | — | +| 19 | **J13 LTE antenna** | U.FL → `/RF_ANT_LTE`: D28 PESD0402-240, R118 0 Ω, C146/C147 DNP π → U19.60 | Apply-pass B-03 in place ✅ | ✅ · 📐 L-31 (existing) | — | +| 20 | **J14 nano-SIM / U22 eSIM** | J14 (C2977286, pre-order) C1 `/SIMB_VDD` (C171) via R131 0 Ω; C2/C3/C7 via R132–R134 22 Ω; ESD D23–D25 on the modem side; U22 + R127–R130 DNP | ✅ (B-09 applied; ESD move per L-38) · SIM detect unused (USIM1_DET NC) | ✅ · ⚙ | — | +| 21 | **SWD / test pads** | TP3 SWDIO (PA13), TP4 SWCLK (PA14), TP5 NRST, TP6 GND, TP7 3V3, TP9 PA9 TX | Complete SWD set, no connector (D-12) → pads grouped in one row (L-56) | ✅ · 📐 L-56 | — | +| 22 | **SW1 reset / SW2 BOOT0** | SW1 NRST→GND; SW2 3V3→BOOT0 (R98 PD) | ✅ | ✅ | — | +| 23 | **Modem UART (internal)** | PC6 USART6_TX → **R148 0 Ω** → `/DIN_4G` (R143 100 k PU) → U23 → modem RXD; modem TXD → U24 → `/DOUT_4G` → R106 1 k → PC7 and U27 → F9P RXD2 | K1 relay path removed (B-13, §4) 🔧 | 🔧 · 📐 L-54 · ⚙ | `/DIN_4G` ∋ R148.2; `/USART6_TX` = {U16.37, R148.1, K1.10 (DNP)} | +| 24 | **GNSS UARTs (internal)** | USART2 PA2/PA3 ↔ F9P UART1; F9P TXD2 → PA10 (RX-only) + Rdfu1 PU | ✅ (unchanged; `/USART1_RX` no longer reaches K1's contact in practice, since K1 is DNP) | ✅ · ⚙ | — | + +### 1.6 Note on the HR911105A LED pin evidence +The Hanrun PDF could not be read here (image-only on every mirror). The pin mapping comes from KiCad's official symbol `Connector:RJ45_Hanrun_HR911105A_Horizontal`, whose datasheet link points to the LCSC copy of the Hanrun drawing, and from the copy already embedded in the v6 sheet. Both draw the **yellow LED with its anode on pin 12 and cathode on pin 11**, and the **green LED with its anode on pin 9 and cathode on pin 10**. They also both type pin 8 as the power_in return of the 1000 pF Bob-Smith capacitor. The v6 wiring contradicted its own symbol drawing. The original designer's note said "G+/G−/Y+/Y− – VERIFY". Bench check on the first board: both LEDs light with the link up. + +## 2. Datasheet facts that decided the fixes + +| Part | Fact | Consequence | +|---|---|---| +| SP3485 (MaxLinear) | Fail-safe only for open inputs; ESD ±2 kV HBM; no IEC rating | Too weak for a cabled port on port machinery → THVD1410DR | +| THVD1410 (TI) | SOIC-8 = R, RE̅, DE, D, GND, A, B, VCC; fail-safe open/short/idle; IEC contact ±18 kV, air ±25 kV, HBM ±30 kV; EFT ±4 kV; bus abs max ±18 V; 3–5.5 V; 500 kbps; DE 2 MΩ PD, RE̅ 2 MΩ PU; 100 nF decoupling | Drop-in on U14's land; C84 is its 100 nF | +| SN74LVC1G04 DBV | 1 NC, 2 A, 3 GND, 4 Y, 5 VCC | U32 on `SOT-23-5` | +| SC16IS752 (NXP) | A1=VSS, A0=VSS → 0x9A (0x4D) · RTSA̅/RTSB̅ = logic 1 after reset · EFCR[4] RTSCON, EFCR[5] RTSINVER · POR plus RESET̅ · IRQ̅ open-drain · I²C ≤ 400 kbit/s · GPIO inputs after reset | Inverter needed for receive-by-default; firmware SRESET and GPIO direction | +| MAX3232 (non-E) | No ESD rating; 0.1 µF pump caps at 3.0–3.6 V | → TRS3232E | +| TRS3232E (TI) | Same 16-pin order as MAX3232; ±15 kV HBM, ±8 kV IEC contact, ±15 kV air; 0.1 µF at 3.3 V | Drop-in on U15's narrow SOIC-16 land (H-01 fixed it in the apply pass) | +| SM712 | 2 I/O pins + common pin 3; −7/+12 V standoff, 400 W 8/20 µs (Semtech SM712.TCT) | Standard RS-485 surge clamp; matches the THVD1410's ±18 V bus rating | +| W5500 v1.1.0 | TOCAP 4.7 µF, 1V2O 10 nF, EXRES1 12.4 k 1 %; RSVD23 → GND, RSVD38–42 NC (internal pull-down); RSTn low ≥ 500 µs, internal pull-up; SCSn internal pull-up; 5 V-tolerant I/O; SPI guaranteed ≥ 33.3 MHz | Confirms the apply-pass values and the firmware sequence | +| LTC4040 Rev B | OVP = MN1 in series VPWR→VIN with IGATE shared with MN2; 6.2 k to OVSNS; 6.1/6.4/6.7 V trip; IGATE pulled to GND in backup; recovery starts when the PFI comparator sees input power; PFI abs max = max(VIN, VBAT, VSYS) + 0.3 V | Why A-10 was **not** applied blind (§7) | +| Sunlord MWSA-S spec Table 4-1 | MWSA0804S: A 8.2±0.3, B 8.8±0.4, C 3.8±0.2, D 1.4±0.3 (electrode width), E 5.0±0.3 (electrode length); recommended land I 2.75, J 4.0, H 5.5 (typ) | New footprint (§4) | + +## 3. I²C address map (I²C1, PB6/PB7, 4.7 k pull-ups to `/3V3`, run at 100 kHz) + +| 7-bit address | Device | Ref | Strap | Range the part can take | +|---|---|---|---|---| +| 0x18 | SC7A20 accelerometer (INT1 → PB9) | U26 | SDO/SA0 = GND, CS = VDD (I²C) | 0x18–0x19 | +| 0x20 | PCF8574T I/O expander (battery gauge LEDs, RGB) | U13 | A0–A2 = GND (NXP PCF8574T/3, not the "A" version) | 0x20–0x27 | +| 0x44 | SHT40-AD1B humidity/temperature | U3 | fixed | 0x44 | +| 0x48 | TMP102 charger sensor | U29 | ADD0 = GND | 0x48–0x4B | +| 0x49 | TMP102 modem-area sensor | U31 | ADD0 = V+ | 0x48–0x4B | +| 0x4D | SC16IS752 dual UART | U10 | A1 = A0 = GND | 0x48–0x57 | +| (0x42) | ZED-F9P DDC | U18 | **not connected** (pins 44/45 NC) | — | + +**No collisions.** Only the SC16IS752 range (0x48–0x57) overlaps the TMP102 range (0x48–0x4B). It sits at 0x4D, outside the four TMP102 values, so no TMP102 strap change can reach it. **No strap change needed.** Bus speed limit: PCF8574 = 100 kHz, so the bus runs at 100 kHz. At that speed the SC16IS752 moves about 10 kB/s in total, which is enough for Modbus RTU at ≤ 38.4 kBd on RS-485 plus RS-232 at ≤ 57.6 kBd (FIFO + IRQ). + +## 4. Schematic fixes applied, with proof + +Method: the apply-pass editor (`apply/tools/ops.py`: span-scoped splices on the original text, a UUID multiset guard, canonical KiCad node layout). Each group was written as its own script (`ports/tools/gP_ports.py`, `gN_norespin.py`, `gC_cosmetic.py`), with the expected change set written before commit. After each commit to the Mac (unique staged path each time, sha256 checked on the Mac afterwards) the netlist was exported with the KiCad MCP (kicad-cli), diffed semantically with `ndiff.py` and asserted; ERC and the overlap and wire-crossing checks ran after each group. + +### 4.1 Hashes + +| State | `hbox-watchdog-v6.kicad_sch` sha256 | Backup | +|---|---|---| +| Pre (apply-pass final) | `d54e330d189910afd58e18fc7cd498bdb3e6e5b7b3c4472b6cae7f95650b34c4` | `_to_delete/v6-ports-20260928/00-pre/` (+ pro, dru, pretty, old PDF), `01-ports/…pre` | +| After P1 ports | `26f50aaa7dc7795dcc5aec12b1ed8d8c1a762c09c8d63b0190e36d1078679a0e` | `01-ports/…post`, `02-norespin/…pre` | +| After N1 no-respin | `3aceff28ac2d91624c37216e2cb83a53f37503452288a86bd52331e211d413c1` | `02-norespin/…post`, `03-cleanup/…pre` | +| **Final (after C1 cleanup)** | **`f73f41a878655896211b429c6f30d82f13d6e0b7eba78468a6bb0473de8a27ee`** | `03-cleanup/…post`; container `ports/hbox-watchdog-v6.kicad_sch.final` | +| `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod` (new) | `dbf535570b133bcb05e6ee7861f06e62cb54d554520488650e0b3c5429d5a71f` | new file (nothing overwritten) | +| Schematic PDF `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf` | `a2c94a49…` → `41241140201f8f19098b1e1c37d3b256b1b6d83df7d338e6204c0fdf0e7191b0` | old copy in `00-pre/`; new copy `ports/hbox-watchdog-v6-schematic.pdf` | + +### 4.2 Netlist proof (expected written before commit, asserted after) + +| Group | Netlists | Expected (added / removed / field / pin-net / class) | Actual | Result | +|---|---|---|---|---| +| P1 ports | `00-baseline` → `01-ports` | 7 / 0 / 11 / 6 / 0 | 7 / 0 / 11 / 6 / 0 | **MATCH** | +| N1 no-respin | `01-ports` → `02-norespin` | 1 / 0 / 30 / 0 / 0 | 1 / 0 / 30 / 0 / 0 | **MATCH** | +| C1 cleanup | `02-norespin` → `03-cleanup` | 0 / 0 / 2 / 2 / 0 | 0 / 0 / 2 / 2 / 0 | **MATCH** | +| **Total** | `00-baseline` → `03-cleanup` | composition of P1+N1+C1 | 8 / 0 / 41 / 8 / 0 | **0 differences** (`ports/netlist_diff_total.md`) | + +The 8 pin-net changes: U14.2 and U14.3 `/SER_DEA` → `/RS485_DE`; U15.12 `/SER_RXB` → `/RS232_R1OUT`; J10.8 NC → GND; J10.11 `/ETH_ACT_A` → `/ETH_ACTLED`; J10.12 `/ETH_ACTLED` → `/ETH_ACT_A`; U10.2 and U10.16 NC → GND. No existing symbol changed its UUID (asserted per group). Netlists are in `kicad/_to_delete/v6-ports-20260928/netlists/` and `ports/netlists/` (`final.xml` = `03-cleanup.xml`, sha256 `a5555894…b5b3`). + +### 4.3 What changed + +| ID | Ref | Change | LCSC (verified: stock / package) | +|---|---|---|---| +| P-1 | U14 | SP3485EN (C8963) → **THVD1410DR**, TI; symbol `Interface_UART:SP3485EN` kept (identical pinout); value text `THVD1410` | **C2671345** (8 006 / SOIC-8; JLC "pre-ordered chips") | +| P-1 | U14.2, U14.3 | `/SER_DEA` → new `/RS485_DE` | — | +| P-1 | **U32** (new) | SN74LVC1G04DBVR, `74xGxx:74LVC1G04`, `Package_TO_SOT_SMD:SOT-23-5`: 2 `/SER_DEA`, 4 `/RS485_DE`, 5 `/3V3`, 3 GND, 1 NC | **C7827** (163 327 / SOT-23-5) | +| P-1 | **C175** (new) | 100 nF 0603 at U32 | C14663 (Basic) | +| P-1 | **D39** (new) | SM712.TCT, `Diode:SM712_SOT23`, `SOT-23`: 1 `/RS485_A`, 2 `/RS485_B`, 3 GND | **C12067** (49 238 / SOT-23) | +| P-4 | **R145, R146** (new, **DNP**) | 390 Ω 0603: `/3V3`–`/RS485_A`, `/RS485_B`–GND (bias option) | C23151 (Basic, 311 280) | +| P-2 | U15 | MAX3232ESE+T (C15846) → **TRS3232EIDR**, TI; symbol `Interface_UART:MAX3232` kept; value text `TRS3232E` | **C308878** (3 564 / SOIC-16 narrow) | +| P-2 | U15.12 | `/SER_RXB` → new `/RS232_R1OUT` | — | +| P-2 | **R147** (new) | 1 kΩ 0603: `/RS232_R1OUT` → `/SER_RXB` | C21190 (Basic, 39.8 M) | +| P-3 | J10.11 / J10.12 | labels swapped: 11 = `/ETH_ACTLED` (yellow K), 12 = `/ETH_ACT_A` (yellow A) | — | +| P-3 | J10.8 | NC flag → wire + GND label (Bob-Smith return) | — | +| P-5 | **TP12** (new) | `TestPoint_Pad_D1.5mm` on `/1V8_MODEM`, excluded from BOM and CPL | no part | +| C | U10.2, U10.16 | CTSA̅/CTSB̅ NC flags → GND | — | +| H-03 | L2 (DNP), L6, L8, L20 | footprint `Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm` → **`Drogheda-v6:IND-SMD_MWSA0804S`** (parts unchanged: C17700171 / C17700165 / C17700171 / C17700167) | — | +| B-13 | K1, Q6, D6, R40, R41 | → **DNP** (relay and its driver) | — | +| B-13 | **R148** (new) | 0 Ω 0603: `/USART6_TX` → `/DIN_4G` (never together with K1) | C21189 (Basic, 13.9 M) | +| J-05 | TP1–TP8 | `in_bom no`, `in_pos_files no` (copper pads, not parts) | — | +| C | text notes | BLOCK M note (RS-485 direction and EFCR, H4 rule) and BLOCK P note (K1 DNP) updated | — | + +**New footprint `IND-SMD_MWSA0804S`** (KiCad 9/10 format, `Drogheda-v6.pretty`): two SMD round-rect pads 2.75 × 4.0 mm (rratio 0.1) at x = ±4.125 mm (inner gap 5.5 mm, outer extent ±5.5 mm); F.Fab body 8.2 × 8.8 mm; F.CrtYd 11.5 × 9.7 mm; silk lines at y = ±4.6 mm between the pads. The pad axis is the body's 8.2 mm A dimension, where the 1.4 mm electrodes sit (the inter-electrode gap of 8.2 − 2 × 1.4 = 5.4 mm matches H = 5.5). Each pad covers 1.35 of the 1.4 mm electrode depth, plus a 1.4 mm toe beyond the body, and 4.0 of the 5.0 mm electrode length. The electrode is now **≈ 77 % wetted plus a toe fillet**, against 55–64 % on the SRU8028 land. The audit's courtyard estimate (9.4 × 9.8 mm) left out the pad overhang; the true courtyard is 11.5 × 9.7 mm (L-53). The KiCad MCP cannot list project-local libraries, but the ERC footprint-link check passed with the new footprint (no `footprint_link_issues`). + +### 4.4 ERC (kicad-cli 10 via KiCad MCP) +0 errors before and after every group; 134 warnings before and after (the same pin-type, library-mismatch and not-in-library families listed in the change report §5). The new symbols (74LVC1G04, SM712_SOT23) are embedded fresh from the KiCad 10 libraries; Device:R and TestPoint are existing cached symbols. Overlaps 30 → 30 and wire crossings 9 → 9: all pre-existing, none involving a new part. I checked the new clusters in the rendered PDF (crops of U10/U14/U32/D39, U15/R147/R145–146, J10, K1/R148, TP12). + +## 5. Additions to Michelle's layout list (continue after L-48) + +49\. **RS-485 direction (P-1):** U32 (SOT-23-5) + C175 within 5 mm of U14 pins 2/3; C175 ≤ 2 mm from U32.5; `/RS485_DE` ≤ 10 mm; `/SER_DEA` U10.1 → U32.2. C84 ≤ 2 mm from U14.8. + +50\. **RS-485 protection at P11 (P-1/P-4):** D39 SM712 ≤ 5 mm of copper from P11.1/P11.2, A/B routed flow-through (P11 → D39 pads → U14), D39.3 to GND with 2 vias ≤ 1 mm; R82 + JP5 beside P11 (termination at the bus end); R145/R146 (DNP 0603) beside P11. Route A/B as a pair (0.3 mm, gap ≤ 0.3 mm), ≥ 0.5 mm from other nets, nothing crossing on the adjacent layer. + +51\. **RS-232 / H4 (P-2):** R147 ≤ 3 mm from U15.12; H4.3 connects on the U10 side (`/SER_RXB`), not at U15. U15's pump caps C85–C88 ≤ 3 mm and its decoupler **C89** ≤ 2 mm from U15.16. Correction to L-37: C84 is U14's decoupler, not U15's. + +52\. **J10 (P-3):** pin 8 → GND with a ≥ 0.5 mm track to 2 GND vias placed **outside** the MAGJACK_NO_POUR keep-out (no pour under the magnetics). Re-route pins 11/12: J10.12 = `/ETH_ACT_A` (from R97), J10.11 = `/ETH_ACTLED` (to U11.27). + +53\. **MWSA0804S land on L2/L6/L8/L20 (H-03):** the footprint swaps to `Drogheda-v6:IND-SMD_MWSA0804S` on *Update PCB from Schematic*. Pads go from 2.0 × 3.2 mm at ±3.9 mm to 2.75 × 4.0 mm at ±4.125 mm; the courtyard is **11.5 × 9.7 mm** (+0.6 mm per side on the pad axis, +0.4–0.6 mm across). Re-check neighbours and keep L-11/L-21/L-22/L-23 distances measured to the new pads. Update only through the schematic sync, never with a global "update footprints from library" (L-45). + +54\. **B-13:** place R148 (0603) on the shortest path U16.37 (PC6) → U23.7 (`/DIN_4G`). K1, Q6, D6, R40, R41 are DNP; keep their footprints, with no copper change other than R148's two connections. Silk "K1 XOR R148". + +55\. **TP12 beside TP8** (2.54 mm centre spacing) so tweezers can bridge them; both reachable with the lid open. + +56\. **Debug pad row (D-12):** TP3 SWDIO, TP4 SWCLK, TP5 NRST, TP6 GND, TP7 3V3, TP9 PA9-TX in one straight row at 2.54 mm pitch, ≤ 30 mm of track from U16, silk labels. A 1×6 pogo clip or header can then be pressed on; no connector part needed. + +57\. **SC16IS752 (U10):** Y2 + C82/C83 ≤ 5 mm from U10.6/7, no inner-layer track under them (extends L-39 to Y2); C81 ≤ 2 mm from U10.8. + +58\. **USB-C CC resistors:** Rcc1/Rcc2 ≤ 5 mm from J9.A5/B5; R100/R101 ≤ 5 mm from J11.A5/B5. + +59\. **Port silkscreen (extends L-46):** P11 "RS-485 A+ B− GND"; P12 "RS-232 TX RX GND"; JP5 "TERM"; R145/R146 "BIAS DNP"; H4 "UART-B TTL 3V3 TX RX GND"; J9 "MODEM USB"; J11 "DFU"; TP8/TP12 "USB_BOOT / 1V8"; P2 "5 V ONLY, BENCH". + +60\. **Footprint attributes (J-05):** TP1–TP12 and JP1–JP6 set to SMD and "exclude from BOM/position files" on the board (matches the schematic now); then re-enable the DRC check `footprint_type_mismatch`. + +61\. **Fiducials:** three global fiducials (1.0 mm copper, 2.0 mm mask opening) on F.Cu at three corners (LGA U18/U19 and 0.5 mm-pitch parts). The audit listed them as "optional"; no v6.1 means fit them now. + +62\. **P1 check:** confirm that the DIBO DB128V-5.0-5P (C424683) pins fit the MKDS-1,5 land's holes (5.0 mm pitch) and that its wire entry faces the harness side of the enclosure. This is a check only; no change is expected. + +Order notes for the same pass: pre-order **THVD1410DR C2671345** (JLC pre-order category, like U21 C2862740 and J14 C2977286). P11 and P12 are **pluggable headers** (DEGSON 15EDGRC-3.5-03P): buy the mating plugs (15EDGK-3.5-03P, 2 per board) with the harness, since they are not in the board BOM. + +## 6. Firmware notes per port (FW 0.7.x, `board_v6.h`) + +1. **SC16IS752 (U10, I²C1 0x4D, 100 kHz):** `BOARD_SER_XTAL_HZ 3686400`; divisor = 3 686 400/(16·baud): 9600 → 24, 19 200 → 12, 38 400 → 6, 57 600 → 4, 115 200 → 2. After every MCU reset write IOControl.SRESET (bit 3), because RESET̅ has no MCU line. Enable the FIFOs. **IODir = 0xFF, IOState = 0x00** (GPIO0–7 as outputs, driven low: no floating inputs). IRQ̅ on **PB8** (EXTI8, falling, no internal pull; R81 is external): service RHR/THR/LSR until IIR says no interrupt pending. CTSA̅/CTSB̅ are tied low, so leave auto-CTS (EFR[7]) off. +2. **RS-485 (channel A):** **EFCR = 0x10 (RTSCON = 1, RTSINVER = 0).** RTSA̅ goes LOW while transmitting, and U32 turns that into DE = 1; idle and reset leave the transceiver in receive. Never set RTSINVER (with U32 fitted it would invert the logic). Modbus RTU: time the 3.5-character gaps on the MCU; line turnaround is automatic after the last stop bit. Termination (JP5) and bias (R145/R146, DNP) are hardware options only. +3. **RS-232 (channel B) and H4:** plain 8N1, no flow control. H4 and P12 share channel B: use one at a time. H4 pin 3 can be driven by a TTL device (R147). +4. **Ethernet (U11, SPI2 PB13/PB14/PB15 AF5, CS̅ PB12 GPIO, INT̅ PC0, RST̅ PA15, power PD2):** at boot drive PA15 LOW and PD2 LOW before anything else. Power-up: SPI pins low → PD2 HIGH → wait ≥ 2 ms for 3V3_ETH → keep RST̅ LOW ≥ 500 µs → release → wait 1 ms (PLL) → SPI mode 0 at ≤ 21 MHz → check VERSIONR = 0x04 → PHYCFGR link. PC0 needs no pull; enable EXTI0 only while PD2 is HIGH. Off / battery: RST̅ LOW, SPI pins LOW or analog, PD2 LOW. LEDs are driven by the PHY (no firmware). +5. **USB DFU (J11):** ROM DFU (BOOT0 button + NRST) needs HSE 25 MHz (Y3). In the application's USB CDC (u-center passthrough) on OTG_FS PA11/PA12, **disable VBUS sensing** (PA9 is the debug-TX pad, not VBUS). +6. **Modem USB (J9):** J9 enumerates only while the modem is powered (PC10 MODEM_PWR_EN + PWRKEY sequence). Add a service command that holds the modem on for FOTA/debug. Forced download: short TP8–TP12 at modem power-on (hardware procedure, no firmware). +7. **Modem UART:** USART6 PC6 TX now reaches the modem **directly through R148** (no K1): drop every BYP_CTRL/Mode-B relay step and keep **PB5 LOW** (driver DNP). PC7 RX via R106 1 k; 115 200 Bd. PC9 STATUS has a hardware pull-down. +8. **I²C sensors:** 0x18 SC7A20 (INT1 → PB9, EXTI9); 0x20 PCF8574 (P0–P3 battery-gauge LEDs, P4–P6 RGB cathodes on P10, active LOW); 0x44 SHT40; 0x48 TMP102 charger (`tchg`); 0x49 TMP102 modem (`tmodem`). Keep I²C1 at **100 kHz** (PCF8574 limit). The SC7A20 WHO_AM_I read at 0x18 also serves as the v6 board identity check before any v6-only pin is driven (D-08, §7). +9. **ADC ports:** PB1 IN9 (P7 NTC), PC4 IN14 (P8 NTC2), PC5 IN15 (pack NTC tap), PA5 IN5 ignition (ratio 0.0833), PA4 IN4 5 V sense; compute VDDA from VREFINT. +10. **Other ports:** P4 fan on PA6 as GPIO on/off (TIM3 stays free for PPS); P9 panel LED on PB0 (Q4); P6 is a hardware reset (no firmware). SIM: no detect line (USIM1_DET NC), so keep SIM hot-swap detection disabled in the modem. + +## 7. Accepted permanently + +| # | ID | Item | Reason it is safe for the product's life | +|---|---|---|---| +| 1 | **A-10** | No over-voltage protection on VEH5V (TPS54360B high-side short, or > 6 V into P2) | It takes a component failure or bench misuse. The field input is the cabinet's regulated, current-limited 24 V (DDR-60G-24, D1), and F2 3 A caps the energy. The datasheet OVP option (MN1 + 6.2 k, sharing IGATE with Q7) also moves the PFI divider to the raw side and changes how backup mode recovers. A mistake there would break normal operation on every board, which is worse than the rare fault it guards against, and it cannot be validated without a bench cycle. P2 gets a "5 V ONLY, BENCH" silk label (L-59). | +| 2 | D-08 | Board-ID strap | Decision D8: firmware-only. The v6 is identified at boot by the SC7A20 WHO_AM_I at 0x18 (v6-only part) and the F9P answering on USART2, before any v6-only pin is driven. Binary names carry the board (memory rule). PD2 is taken by ETH_PWR_EN and PA9 by the debug pad. | +| 3 | E-06 (option) | Low-capacitance ESD array between the magjack and U11 | The HR911105A magnetics isolate the cable (1500 Vrms), the WIZnet reference design has no array, and the cabling stays inside the cabinet. J10.8 (Bob-Smith return) is fixed now. | +| 4 | E-07 | PoE | Not a requirement (Leo: ports must work; no PoE mentioned). The recorded decision is an external splitter. | +| 5 | A-20a | U12 MP1584EN → AP64350 | U12 is now PD2-gated (E-01), runs only on vehicle power and is proven on V5.5. A swap would need a new compensation/RT design and a different land, which adds risk for no functional gain. | +| 6 | G-07 | P3 XH-3 → XH-5/VH | 3 A per contact vs 1.4 A charge (R50 1.43 k), 0.6–1 A backup average, and ≈ 2 A LTE-only peaks (D9). XH-3 keeps the fielded 1S4P packs compatible. | +| 7 | G-06 | P2-only power back-feeds VEH5V → U25 body diode → P1.1 (≈ 4 V) | Benign; with A-01 the Q10/U2 branch is DNP, so nothing on `/24V` is powered. Documented for the bench procedure. | +| 8 | F-14 (option) | One USBLC6 at J11 instead of D14–D16 | Full-speed USB tolerates the PESD5V0S1BA capacitance (proven on V5.5). The stub problem is solved by routing (L-42). | +| 9 | G-08 (option) | 100 Ω series on NRST | D36 (PESD5V0S1BA) plus C104 100 nF already clamp and filter the P6 cable; a series R would split `/NRST` for no measurable gain. | +| 10 | J-03 | Retype `unspecified` library pins | Cosmetic. The warnings were checked net by net (single drivers, no conflicts), pin types do not reach the netlist, BOM or PCB, and the 134-warning baseline is recorded, so a new warning is found by diffing against it. | +| 11 | J-04 (re-link) | 10 "not found" symbols (+ TPS2552) not copied into a library | Cosmetic. The embedded copies make the schematic self-contained, and pin → pad → net was checked on 25 parts (H-09). Re-linking would change 11 lib_ids for zero electrical effect. | +| 12 | B-09 (option) | ESD on `/SIM_VDD` (array) | The SIM is inserted once at installation inside the enclosure. Data, CLK and RST have D23–D25 (moved next to J14 by L-38), and VDD has C171 100 nF at J14. | +| 13 | A-16 | Populate R124/R125 (U25 UVLO) | The board always sees the cabinet's regulated 24 V (D1), so the 4.3–5.8 V input dropout band is never reached in service. | +| 14 | A-18 (+ R123 option) | U25 compensation | The datasheet example with ≥ 60° phase margin (audit estimate) needs no change; the 0.3 → 2.5 A step is part of bring-up. | +| 15 | A-19 | ISO 16750-2 load dump | The cabinet DC-DC isolates the board from the alternator bus. SMCJ33A/SMBJ33A survive 36 V/60 min and ISO 7637 fast pulses; F2 opens behind them if a TVS ever shorts. | +| 16 | A-20b | F1 3 A PPTC now protects only the F9P LDO branch | Harmless and not needed for protection; keeping it avoids a footprint change. | +| 17 | C-05 (option) | C143 100 nF → 47 pF C0G DC block | 100 nF X7R 0402 is ESL-dominated at L1/L2 (≈ 3–4 Ω); insertion loss < 0.01 dB after a ≥ 25 dB antenna LNA. | +| 18 | D-06 (option) | D5 BAT54 → BAT54S | verify_2: optional once the SMBJ33A (D35) sits at P1.3 (applied). | +| 19 | A-03/A-04 (option) | R121/R122 at 0.1 % | 5.18–5.46 V at 1 % meets the LTC4040 VIN ≤ 5.5 V and the governor thresholds; no 0.1 % LCSC parts in the DB. | +| 20 | A-13 (option) | CLPROG → ADC | No ADC pin is left (PC5 went to the pack NTC). CLPROG stays on TP1 for bench current measurement. | + +## 8. Done now + +| # | ID | What | Where | +|---|---|---|---| +| 1 | P-1 (new) | RS-485 transceiver → THVD1410DR (IEC ESD, fail-safe on open/short/idle bus) | Schematic (U14) | +| 2 | P-1 (new) | Receive-by-default direction: U32 inverter + C175 | Schematic + L-49 | +| 3 | P-1 (new) | RS-485 surge TVS D39 SM712 at P11 | Schematic + L-50 | +| 4 | P-4 (new) | RS-485 bias option R145/R146 (DNP) | Schematic + L-50 | +| 5 | P-2 (new) | RS-232 transceiver → TRS3232EIDR (IEC ESD) | Schematic (U15) | +| 6 | P-2 (new) | H4 contention fixed: R147 1 k R1OUT → SER_RXB | Schematic + L-51 | +| 7 | P-3 (new) | J10 yellow LED polarity (pins 11/12) | Schematic + L-52 | +| 8 | P-3 / E-06 | J10.8 Bob-Smith return → GND | Schematic + L-52 | +| 9 | P-5 (new) | TP12 1V8 pad for modem USB forced download | Schematic + L-55 | +| 10 | C (new) | SC16IS752 CTSA̅/CTSB̅ tied to GND | Schematic | +| 11 | **H-03** | MWSA0804S footprint per the Sunlord land; L2/L6/L8/L20 re-pointed | Library + schematic + L-53 | +| 12 | **B-13** | K1 relay path removed: K1/Q6/D6/R40/R41 DNP, R148 0 Ω PC6 → DIN_4G | Schematic + L-54 | +| 13 | J-05 / H-09 | TP1–TP8 out of the BOM and CPL | Schematic + L-60 | +| 14 | D-12 (option) | SWD/debug access as one 2.54 mm pad row | L-56 | +| 15 | FHJ note | Fiducials | L-61 | +| 16 | L-37 (correction) | U15 decoupler is C89 (not C84) | L-51 | +| 17 | C | Block notes and value texts updated (no overlap on U14/U15) | Schematic | + +Already closed by the apply pass and so not repeated here: every §7.1/§7.2 item, the D19 Minors, F-52 (modem TMP102 0x49), B-15, G-03, G-04, G-08 diodes, and J-04's flag and stub cleanup. Layout-only Minors and Notes (A-14, B-08, E-06 routing, F-14, F-17, F-18, G-05, J-02, C-09, D-15, F-21, A-20c silk) are in Michelle's L-1…L-48 list. Firmware-only Notes (B-14, B-16, C-08, D-13) are in the audit §8 and §6 above. + +## 9. Anything that would still stop a port from working +None found in the schematic after this pass. Conditions that remain: + +- **Layout:** L-49…L-62, plus the existing L-30/31/33 (RF), L-41/42/43 (USB) and L-44 (Ethernet pairs), must be done. In particular, the new MWSA land (L-53) must be placed before routing the switchers. +- **Order logistics:** pre-order THVD1410DR, U21 and J14; buy the P11/P12 mating plugs. +- **Bench confirmation on the first board:** J10 LINK (green) and ACT (yellow) both light; RS-485 idles in receive during MCU reset and in DFU (DE low); an RS-485 loopback at 9 600 and 115 200 Bd with EFCR = 0x10; RS-232 loopback; an H4 TTL adapter drives RXB with RS-232 idle; J9 enumerates with the modem on, and download mode works with TP8–TP12 shorted. + +## 10. Files +- This report: `/home/claude/v6audit/ports/2026-09-28_Drogheda_EinarBoard-v6_Ports-and-No-Respin_v1.0.md` +- Final schematic copy: `ports/hbox-watchdog-v6.kicad_sch.final` (sha256 `f73f41a8…27ee`); PDF: `ports/hbox-watchdog-v6-schematic.pdf` and on the Mac `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf` (sha256 `41241140…91b0`) +- Final netlist: `ports/netlists/final.xml` (= `03-cleanup.xml`); per-group diffs: `ports/out/{P1-ports,N1-norespin,C1-cleanup}/netlist_diff.md`; total: `ports/netlist_diff_total.md` +- BOM: `ports/bom_final_ungrouped.csv` (also in `_to_delete/v6-ports-20260928/`) +- Scripts: `ports/tools/` (`gP_ports.py`, `gN_norespin.py`, `gC_cosmetic.py`, `pcommon.py`, `q.py`); footprint source `ports/work/IND-SMD_MWSA0804S.kicad_mod` +- Mac backups: `kicad/_to_delete/v6-ports-20260928/` (`00-pre/`, `01-ports/`, `02-norespin/`, `03-cleanup/`, `netlists/`, `scratch/`) +- **Git (for Leo; nothing was run here):** in the `kicad` submodule commit `hbox-watchdog-v6.kicad_sch` and `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod`, push to Gitea `HBox_PCB`, then bump the parent gitlink (`git -c diff.ignoreSubmodules=none commit …`). If KiCad is open on v6, close it **without saving** before Update PCB. diff --git a/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Schematic-Change-Report_v1.0.md b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Schematic-Change-Report_v1.0.md index f4fbfe1..d02c431 100644 --- a/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Schematic-Change-Report_v1.0.md +++ b/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Schematic-Change-Report_v1.0.md @@ -11,6 +11,11 @@ author: Helgen Technologies !!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide" Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios. +!!! info "Este informe cubre solo la pasada 1" + Este informe cubre la **pasada 1** (correcciones de la auditoría). La **pasada 2** (puertos y sin nueva versión) y la + **pasada 3** (revisión final independiente), con el esquemático final `d58a89ba…` (tras la pasada 4: estrapes LFP-HT), están en + [Cambios de esquemático — resumen de 3 pasadas](v6-cambios-resumen.md). + Fecha: 2026-09-28 · Proyecto: `kicad/hbox-watchdog-v6.*`, editado en su lugar (D17) · Implementa: [Auditoría completa v6](v6-auditoria-completa.md) §7.1 (Bloqueantes), §7.2 (Mayores), §7.3 Menores según D19, y las reglas de proyecto F-01 / D18 · Decisiones: `DECISIONS.md` D1–D19 (tomadas por delegación de Leo) · Autor: Helgen Technologies (elaborado con asistencia de Claude; ediciones por script sobre el texto S-expression con guarda de UUID; KiCad MCP solo para netlist, ERC, PDF, BOM, DRC y consultas de librería) · Estado: esquemático, reglas de proyecto y librería listos; **`hbox-watchdog-v6.kicad_pcb` no se tocó** (Michelle ejecuta *Update PCB from Schematic*, §10). Traducido del original en inglés (28-sep-2026). diff --git a/03-Architecture-Hardware/2026-09-28_v6-audit-attachments/Delegated-Decisions_2026-09-28.md b/03-Architecture-Hardware/2026-09-28_v6-audit-attachments/Delegated-Decisions_2026-09-28.md new file mode 100644 index 0000000..e7ac7bc --- /dev/null +++ b/03-Architecture-Hardware/2026-09-28_v6-audit-attachments/Delegated-Decisions_2026-09-28.md @@ -0,0 +1,30 @@ +# Decisions for the v6 correction pass — taken by Claude on Leo's delegation (2026-09-28 17:20 CST) + +Leo: "if a change can be done at the schematic level we should do that — make the best decisions for me". +IDs refer to `/home/claude/v6audit/report/2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md` (§5 ranked list, §6 layout list, §7 schematic change list, §8 firmware). Verification files: `findings/verify_1.md`, `findings/verify_2.md`. + +| # | Question (report §10) | Decision | Why | +|---|---|---|---| +| D1 | Supply context | HBOX input = the cabinet's **regulated 24 V** (Mean Well DDR-60G-24), per the project hard constraint; the board keeps its 9–36 V margin. Ignition = **raw machine ignition, 12 V and 24 V machines** (ICAVE: RTG / Reach Stacker / Empty Handler 24 V; Tractoplana / Montacargas 12 V). | CLAUDE.md §1c + §4 | +| D2 | Modem supply topology (A-01, B-01, V1-01) | Adopt the verified topology: **U20 fed from `/MAIN5V` only**; D20 and D21 removed (direct connection MAIN5V → U20 VIN); **fan from `/VEH5V`** (U2 fan-buck block DNP, JP1 bridged); the **Q10 `/24V` branch DNP** once it has no loads; **F2 = 3 A (C206912), electrically ahead of D10**. Prerequisites in the same pass: A-04, A-05 (CSYS + 2×47 µF), U20 input caps (2×22 µF + 220 µF), B-02 loop values. | Removes the D21 failure mode and the unfused branch with fewer parts; verify_1 checked U25 ≤ 2.95 A | +| D3 | R50 | **1.43 kΩ (C22840)**: ≥ 1.3 A at every corner, below the 2.5 A limit | A-03 verified | +| D4 | U25 set-point | **R121 = 57.6 k (C23082)** → 5.18/5.32/5.46 V; firmware `V5_PFI` → 4.40 V | A-04 | +| D5 | LTE antenna ESD | **Fit PESD0402-240 (C1975527)** on an 0402 land (keep protection; the antenna cable leaves the box) | B-03 verified | +| D6 | GNSS antenna bias | **TPS2552DBVR (C46506)**, ILIM→IN (75 mA), ANT_OFF→EN̅, FAULT̅→ANT_SHORT_N | C-01 | +| D7 | Charger temperature | "Sensor ≤ 10 mm of U6" is **binding**: implement F-51 fully (TMP102 C99269 @0x48 beside U6 + pack-NTC tap to PC5: 100 k C25803 / 120 k C25808 / 10 nF C1589) | R4; lesson F5 | +| D8 | PD2 | **PD2 = ETH_PWR_EN** (E-01, U12 enable + 100 k pull-down). Board ID = firmware-only (probe the F9P / RTK_STAT behaviour at boot, D-08); PA9 stays the debug-TX pad (D-12) | Hardware power gating beats a strap; ID can be detected | +| D9 | Battery mode | **LTE-only on battery** (`AT+CNMP=38`); **Ethernet off on battery** | A-05, B-16 | +| D10 | J10 / P11 / P12 | **Populated** (Ethernet + RS-485/RS-232 are v6 features, EinarBoard 1.1 decisions). Schematic footprints corrected to the ordered parts (P11/P12 right-angle = the PCB's Horizontal footprint; J10 to a library nickname that exists). Michelle clears the PCB DNP flags | G-03 / H-06 | +| D11 | Enclosure | v6 must fit the **existing V5.5 backplate / standoffs** (v6 brief: "no enclosure rework") → **G-01 = Blocker**: restore V5.5 MH4 and the heatsink-clamp holes (MH11 + partner); L6 moves anyway with A-02 | G-01 | +| D12 | Fab stackup | **JLC04161H-7628 with impedance control, ENIG, 1 oz inner copper** (and still widen inner power runs per A-07) | F-06, A-07, J-02 | +| D13 | BOM tool | **Fabrication Toolkit** → delete `LCSC Part` from U25's footprint in `Drogheda-v6.pretty` and on the board | H-04 | +| D14 | Order quantity | **20 prototypes first**; re-check stock on order day; pre-order J14 (and U18/U19 if going to 100) | H-02, H-02b | +| D15 | Firmware | Report §8 → **FW 0.7.x `board_v6.h`**; not part of this pass | — | +| D16 | Minors | Schematic-only value/field Minors from §7.3 are applied **when trivially safe**; the rest go to the layout list or v6.1 | — | +| D17 | Where to edit | **In place** in `hbox-watchdog-v6.*` (Leo's rule 28-Sep 20:20: iterations of a board are edited in place; old state recoverable from git). Pre-change copies in `kicad/_to_delete/v6-apply-20260928/`. The `.kicad_pcb` is **not** touched (Michelle's file); she runs Update PCB from Schematic | preferences | +| D18 | Netclasses / DRC rules (F-01) | Applied now in `.kicad_pro` (netclass patterns, RF + PWR_MODEM classes) and `.kicad_dru` (verify_2's corrected rules), so DRC becomes the release gate | F-01 | + +## D19 — Scope of the schematic pass (report §7) +- **All of §7.1 (Blockers) and §7.2 (Majors)** that touch the schematic/project, exactly as listed, with the D-decisions above. G-01 is layout-only (Michelle). +- **§7.3 Minors applied** (schematic-only, low risk): A-11 (R56 → pull-up, charger OFF by default = safe state), A-13 (PFO → PB10 + 100 k), B-09 (22 Ω + 100 nF), B-10 (pulls + R106 → 1 k), C-07 (test pads), D-02 (Y3 → 3225 C2901684 + 12 pF; Michelle places it ≤ 5 mm from the MCU), D-03 (Y4 CL 7 pF + 6.8 pF), D-05 (Rigb1 → 2.2 k; firmware reads ignition on the ADC), D-09, D-12 (TP9), E-03 (**keep Y1, C95/C96 → 33 pF C1663**; no footprint change), E-04, **F-52 (modem TMP102 at 0x49)**, G-03 (footprints per D10, populated), G-04 (JP_CUT), G-08 (3× ESD), H-08 (value texts), J-04 (orphan NC flags, NC-on-connected flags, wire stubs; re-link missing symbols only if straightforward), B-15 (R107/R108 DNP + "never fit"). +- **§7.3 NOT applied** (→ v6.1 or layout): D-08 (board-ID strap; decided firmware-only), H-03 (MWSA0804S footprint: no land drawing available; V5.5 same pairing works), J-03 (library-wide pin types; cosmetic). diff --git a/03-Architecture-Hardware/2026-09-28_v6-audit-attachments/Schematic-Change-Report_pass1_EN-original.md b/03-Architecture-Hardware/2026-09-28_v6-audit-attachments/Schematic-Change-Report_pass1_EN-original.md new file mode 100644 index 0000000..0c78b34 --- /dev/null +++ b/03-Architecture-Hardware/2026-09-28_v6-audit-attachments/Schematic-Change-Report_pass1_EN-original.md @@ -0,0 +1,419 @@ +# EinarBoard v6 — Schematic change report (v1.0) + +**Date:** 2026-09-28 · **Project:** `kicad/hbox-watchdog-v6.*`, edited in place (D17) · **Implements:** `2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md` §7.1 (Blockers), §7.2 (Majors), §7.3 Minors per D19, and F-01 / D18 project rules · **Decisions:** `DECISIONS.md` D1–D19 (taken on Leo's delegation) · **Author:** Claude (scripted span-scoped S-expression edits with a UUID guard; KiCad MCP used only for netlist, ERC, PDF, BOM, DRC, library lookups and a scratch file) · **Status:** schematic, project rules and library done; **`hbox-watchdog-v6.kicad_pcb` not touched** (Michelle runs *Update PCB from Schematic*, §10). + +## Resumen (ES) + +Se aplicaron al esquemático de v6 todos los Blockers y Majors de la auditoría que son de esquemático, y los Minors de la lista D19. El módem (U20) ahora se alimenta sólo de MAIN5V (D20/D21 eliminados), el ventilador sale de VEH5V (bloque U2 y rama Q10 en DNP) y F2 (3 A) queda antes de D10. Se añadieron limitador de antena GNSS (TPS2552), TVS en ignición, sensores TMP102 del cargador (0x48) y del módem (0x49), buffer U27 hacia el F9P, ESD en J9 y en P6/P7/P8, y se corrigieron valores (R50 1.43 k, R121 57.6 k, compensación de U20, cristales). Cada grupo se comprobó con un diff de netlist: **lo esperado coincide exactamente con lo obtenido** (137 cambios de componentes/campos/pines + 16 cambios de clase de red). ERC: **0 errores** (166 → 134 warnings, todos explicados). El PCB no se tocó; Michelle debe ejecutar *Update PCB* marcando «Delete footprints with no symbols». + +## 0. Summary + +| Item | Result | +|---|---| +| Files edited in place | `hbox-watchdog-v6.kicad_sch`, `hbox-watchdog-v6.kicad_pro` (net classes only), `hbox-watchdog-v6.kicad_dru`, `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` | +| `hbox-watchdog-v6.kicad_pcb` | **Byte-identical** (sha256 `6ddec80d…` before and after) | +| Changes applied | Group 1 Blockers: 10 finding IDs · Group 2 Majors: 13 · Group 3 Minors: 19 (D19 list) · Group 4 rules/library: F-01, H-04 | +| Parts | **37 added** (U27–U31, R135–R144, C161–C174, D35–D38, TP9–TP11, JP6), **3 removed** (D20, D21, PWR_FLAG PF15), **17 set DNP**, 1 symbol swapped (Y3 → `Device:Crystal_GND24`) | +| Netlist proof | Every group: expected == actual (0 unexpected, 0 missing). Baseline → final: 37 added / 3 removed / 125 field / 22 pin-net / 16 net-class changes; composed group expectations = final netlist with **0 differences** (`netlist_diff_total.md`) | +| ERC (kicad-cli 10.0.4) | **0 errors** before and after · warnings 166 → 134 (§5) | +| Overlaps / wire crossings | 30 → 30 overlaps (all pre-existing bbox hits) · 8 → 9 wire crossings (+1 is a tool bbox artefact on U30, checked in the PDF) | +| BOM | Every populated part has an LCSC number except the pre-existing copper pads TP1–TP8 (unchanged). New pads TP9–TP11 and JP6 are excluded from the BOM | +| PDF | `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf` (sha256 `a2c94a49…`) | + +## 1. Hashes + +| File | Before | After | +|---|---|---| +| `hbox-watchdog-v6.kicad_sch` | `ecee9fed851f02e74074340bf8361bced7c385b2502b19c368861b9851c2f04a` | `d54e330d189910afd58e18fc7cd498bdb3e6e5b7b3c4472b6cae7f95650b34c4` | +| `hbox-watchdog-v6.kicad_pro` | `25c57f3936b96a4e31cb5947668c172d318189258d6a5d2fa34d230df8958028` | `d577aa43076f5f751c291041dbf3054cb93a87facfe9f339ef91b60e073bd6ce` | +| `hbox-watchdog-v6.kicad_dru` | `47538e6cfadc0c53421ff59dadabc0e7f0ad5f11d9e2250618728788080aca1a` | `31ce0f4f23e8178b4b5e837b452e7bb8647d446ffd420559049eaaae78100831` | +| `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` | `0171be85ff9bf1d27232731a9931ad9d6c3c2bcdee2f5f3558ee94d2566413f9` | `3f38f26e435c477a7701636d4d5e1c05b4c7bd523e8dd04f9f57128657736313` | +| `hbox-watchdog-v6.kicad_pcb` | `6ddec80d1c15f79e69dff6c1a850b28345a5d826389f79cee8c61998240b36bf` | unchanged | + +Pre-flight: sch and pro hashes matched the audit baseline; no `~hbox-watchdog-v6.*.lck` (only the v5 locks exist). No git was run in the mounted folder. + +## 2. Changes by finding + +Method: every edit is a splice on the original text, scoped to one S-expression node (property value, flag atom, label name, wire point, or a whole node for deletions). Before writing, a guard compares the multiset of UUIDs: no pre-existing UUID may disappear or change except for deliberately deleted items, and no new duplicates may appear. All untouched bytes stay identical. New symbols, wires and labels are written in KiCad's canonical layout; each new part is wired with a 2.54 mm wire to a local label carrying the exact existing net name (local `GND` labels as in the rest of the sheet). The only non-standard library symbol is TPS2552 (§7). + +### 2.1 Blockers (§7.1) + +| Finding | Ref | From → To | LCSC | Pins / nets | +|---|---|---|---|---| +| A-01 | D20 | SS34 (C8678) → **removed** | — | its labels `VIN_MODEM` (K) and `24V` (A) deleted | +| A-01 | D21 | PMEG3050EP (C50603) → **removed** | — | its labels `VIN_MODEM` (K) and `MAIN5V` (A) deleted | +| A-01 | PF15 | PWR_FLAG on `/VIN_MODEM` → **removed** with its label | — | the net no longer exists; PF2 already flags `/MAIN5V` | +| A-01 | U20.2, C127.1, C128.1 | `/VIN_MODEM` → **`/MAIN5V`** (labels renamed) | — | no `VIN_MODEM` label remains (6 of 6 handled) | +| A-01 | U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21 | fitted → **DNP** | unchanged | fan now from `/VEH5V` via JP1 | +| A-01 | JP1 | `…SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm` → **`Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`** | no part | `/5V_FAN` = `/VEH5V` in copper (net-tie footprint) | +| A-01 | Q10, DzG1, Rrp1, C10, C11, C22 | fitted → **DNP** | unchanged | `/24V` loads checked first: {C10, C11, C22, D20, DzG1, Q10, Ren1, U2} + virtual PF6 → nothing left fitted | +| A-01 + V1-01 | F2 | `2A/125V-NANO2-in-holder` C206910 → **`3A/125V-NANO2-in-holder`**, MPN 0154003.DR, Littelfuse; same holder footprint | **C206912** | P1.1 → F2 → `/VIN_FUSED` | +| V1-01 | D10 | pin 1 on `/24V_IN` → **`/VIN_FUSED`** | C224019 (unchanged) | `/VIN_FUSED` = {F2.2, D10.1, Q23.2}; topology in §8 | +| A-03 | R50 | 825R/1% C50214 → **1.43k/1%** | **C22840** | 1.316–1.483 A | +| B-03 | D28 | ESD9L5.0ST5G C82326, SOD-923 → **PESD0402-240**, `Diode_SMD:D_0402_1005Metric`, Littelfuse | **C1975527** | pin 1 `/RF_ANT_LTE`, pin 2 GND (symbol kept; pins 1/2 map to the 0402 pads) | +| C-01 | **U28 (new)** | TPS2552DBVR, SOT-23-6 | **C46506** | 1 IN `/3V3_GNSS` · 2 GND · 3 ~EN `/GNSS_ANT_OFF` · 4 ~FAULT `/GNSS_ANT_SHORT_N` · 5 ILIM `/3V3_GNSS` (75 mA) · 6 OUT **`/ANT_BIAS`** | +| C-01 | **R135 (new)** | 100k, ~EN → GND (antenna ON by default) | C25803 | `/GNSS_ANT_OFF` – GND | +| C-01 | **R136 (new)** | 10k, FAULT pull-up | C25804 | `/3V3_GNSS` – `/GNSS_ANT_SHORT_N` | +| C-01 | L21.2, C144.1, C145.1 | `/VCC_RF_GNSS` → **`/ANT_BIAS`** | unchanged | | +| C-01 | U18.7 VCC_RF | `/VCC_RF_GNSS` → **NC** (label deleted, no-connect flag added) | — | | +| C-01 | U18.5 ANT_OFF | NC flag → label **`/GNSS_ANT_OFF`** | — | | +| F-02 | **D35 (new)** | SMBJ33A, `Diode_SMD:D_SMB` (same symbol as D10) | **C224019** | 1 (cathode) `/IGN_IN`, 2 GND; place at P1.3 | +| F-02 | Rig1 | unchanged (22k C88614); move to P1.3 is layout | — | `/IGN_IN` = {P1.3, Rig1.1, D35.1} | +| H-01 | U15 | `Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm` → **`Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`** | C15846 (unchanged) | | +| H-02 | U10 | C729142 (SC16IS762) → **C57156**, MPN SC16IS752IPW,128 (value already SC16IS752IPW; symbol kept) | **C57156** | pinout identical | +| H-02 | R53 | 499k/1% C131054 → same value, MPN RCT03499KFLF, HKR | **C177479** | | +| H-04 | U25 | no `LCSC Part` in the schematic symbol; the field comes from the library footprint → removed there (§7) | C524806 | | +| F-01 | project | net classes + `.kicad_dru` (§6) | — | | +| G-01 | MH4 + heatsink pair | **not applied** — board-only (§10) | — | | + +### 2.2 Majors (§7.2) + +| Finding | Ref | From → To | LCSC | Pins / nets | +|---|---|---|---|---| +| A-04 | R121 | 53.6k/1% C23074 → **57.6k/1%** | **C23082** | U25 5.18/5.32/5.46 V | +| A-05 | **C161, C162 (new)** | 47uF X7R 1210 | **C5440143** | `/MAIN5V` – GND (at U6 VSYS 1/24) | +| A-08 | U17 | AMS1117-3.3 C6186 → **TLV1117LV33DCYR** (TI); symbol `Regulator_Linear:AMS1117-3.3` kept (same 1 GND / 2 OUT / 3 IN, tab = OUT) | **C15578** | pins unchanged | +| A-09 | C78 | 220uF/10V MVG C2827940 → **220uF/16V polymer**, Lelon OVZ221M1CTR-0608, same CP_Elec_6.3x7.7 | **C881921** | pin 1 `/VEH5V` = + pad | +| B-02 | C130, C131 | same as C78 → **220uF/16V polymer** | **C881921** | | +| B-02 | R116 | 14k C22803 → **113k/1%** | **C22862** | | +| B-02 | C141 | 3.3nF C1536 → **6.8nF** X7R 0402 | **C1542** | | +| B-02 | C142 | 47pF C1567 → **56pF** C0G 0402 | **C1572** | | +| B-02 | **C166, C167 (new)** | 22uF 16 V X5R 0805 | **C86817** | `/VBAT_MODEM` – GND (at L20.2) | +| F-03 | **C163, C164 (new)** | 22uF 16 V 0805 | **C86817** | `/MAIN5V` – GND (at U20.2) | +| F-03 | **C165 (new)** | 220uF/16V polymer, `Device:C_Polarized`, CP_Elec_6.3x7.7 | **C881921** | 1 (+) `/MAIN5V`, 2 GND | +| F-51 | **U29 (new)** | TMP102AIDRLR, SOT-563, **I²C 0x48** | **C99269** | 1 SCL `/I2C_SCL` · 2 GND · 3 ALERT NC · 4 ADD0 GND · 5 V+ `/3V3` · 6 SDA `/I2C_SDA` | +| F-51 | **C168 (new)** | 100nF 0603 | C14663 | `/3V3` – GND | +| F-51 | **R137 / R138 / C169 (new)** | 100k/1% top · 120k/1% bottom · 10nF 0603 | C25803 · **C25808** · C1589 | `/NTC` → R137 → **`/NTC_CELL`** → R138/C169 → GND | +| F-51 | U16.25 PC5 | NC flag → label **`/NTC_CELL`** (ADC1_IN15) | — | | +| C-02 | U21 | AP2112K-3.3 C51118 → **TPS7A2033PDBVR** (TI); symbol `Drogheda-sym:LDO_SOT23-5` kept (its generic 1 VIN / 2 GND / 3 EN / 4 NC / 5 VOUT pinout is the TPS7A20 DBV pinout) | **C2862740** | pins unchanged | +| E-01 | U12.2 EN | `/SYS5V` → **`/ETH_PWR_EN`** (label renamed; U12.7 VIN stays on `/SYS5V`) | — | | +| E-01 | U16.54 PD2 | NC flag → label **`/ETH_PWR_EN`** | — | | +| E-01 | **R139 (new)** | 100k PD | C25803 | `/ETH_PWR_EN` – GND | +| E-02 | **R140 (new)** | 4.7k | **C23162** | `/ETH_RST` – GND (at U11.37) | +| D-01 | **U27 (new)** | 74LVC1G125GV,125 (Nexperia), SOT-753 on `Package_TO_SOT_SMD:SOT-23-5` (same SC-74A land) | **C12518** | 1 ~OE GND · 2 A `/DOUT_4G` · 3 GND · 4 Y **`/DOUT_4G_F9P`** · 5 VCC `/3V3_GNSS` | +| D-01 | **C170 (new)** | 100nF 0603 | C14663 | `/3V3_GNSS` – GND | +| D-01 | U18.26 RXD2 | `/DOUT_4G` → **`/DOUT_4G_F9P`** | — | PC7/R106 stay on `/DOUT_4G` | +| D-01 | Rdfu1 | 22k C88614 → **100k** | **C25803** | | +| G-02 | **U30 (new)** | USBLC6-2SC6, SOT-23-6 | **C7519** | 1,6 `/USB_DM` · 3,4 `/USB_DP` · 5 `/USB_VBUS` · 2 GND | +| H-02b | R56, R57, R58, R85, R87, Rgs1 | C103211 (100k 5 %) → **C25803** (100k 1 %) | **C25803** | value text kept `100k`. R20/Ren1/Rfreq1 not changed (U2 block is DNP) | +| V1-01, F-12, F-05, F-06, C-04, A-07, A-02 | — | layout-only → §10 | | | + +### 2.3 Minors (D19 list) + +| Finding | Ref | From → To | LCSC | Pins / nets | +|---|---|---|---|---| +| A-11 | R56.2 | GND → **`/3V3`** (label renamed): CHGOFF pulled up → charger **OFF** without MCU | C25803 | | +| A-13 | U6.20, TP2.1 | `/PFO_TP` → **`/PFO`** (labels renamed) | — | | +| A-13 | U16.29 PB10 | NC flag → label **`/PFO`** | — | | +| A-13 | **R141 (new)** | 100k PU | C25803 | `/3V3` – `/PFO` | +| B-09 | R132, R133, R134 | 0R C304185 → **22R** | **C23345** | R131 (VDD) stays 0R | +| B-09 | **C171 (new)** | 100nF 0402 at J14.C1 | **C1525** | **`/SIMB_VDD`** – GND (J14.C1 is on `/SIMB_VDD`, after R131; the report's "(`/SIM_VDD`)" names the modem side) | +| B-10 | **R142 (new)** | 100k PD | C25803 | `/MODEM_STATUS` – GND | +| B-10 | **R143 (new)** | 100k PU | C25803 | `/3V3` – `/DIN_4G` | +| B-10 | R106 | 100R C22775 → **1k** | **C14676** | | +| C-07 | U18.50 SAFEBOOT_N | NC flag → label **`/GNSS_SAFEBOOT_N`** | — | | +| C-07 | **TP10, TP11 (new)** | `TestPoint:TestPoint_Pad_D1.0mm`, not in BOM | no part | TP10 `/GNSS_SAFEBOOT_N`, TP11 `/GNSS_RESET_N` | +| D-02 | Y3 | `Device:Crystal` HC-49SD C14872 → **`Device:Crystal_GND24`**, `Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm`, SCTF SX3B25.000F1010F30 (25 MHz, CL 10 pF, ESR 30 Ω) | **C2901684** | pin 1 `/HSE_IN` · **pin 3 `/HSE_OUT`** · pins 2/4 **GND** (new wire + GND label). Symbol swap needed: a 2-pin symbol on the 4-pad land would have put HSE_OUT on GND pad 2. New pin 3 sits exactly where old pin 2 was, so the `HSE_OUT` label connects unchanged | +| D-02 | C113, C114 | 15pF C1644 → **12pF** C0G | **C38523** | | +| D-03 | Y4 | FC-135 CL 12.5 pF C32346 → **FC-135 CL 7 pF** (Epson Q13FC13500002; 7 pF confirmed on distributor listings) | **C48615** | footprint unchanged | +| D-03 | C115, C116 | 12pF C38523 → **6.8pF** C0G | **C1679** | | +| D-05 | Rigb1 | 3.3k C22978 → **2.2k** | **C4190** | ratio 0.0833 | +| D-09 | **R144 (new)** | 100k PD at Q5 base | C25803 | `/BASE_LS` – GND | +| D-12 | U16.42 PA9 | NC flag → label **`/USART1_TX`** | — | | +| D-12 | **TP9 (new)** | `TestPoint:TestPoint_Pad_D1.5mm`, not in BOM | no part | `/USART1_TX` | +| E-03 | C95, C96 | 18pF C1647 → **33pF** C0G (Y1 kept) | **C1663** | | +| E-04 | C91 | 4.7uF C1779 0805 → **10nF** X7R, `C_0603_1608Metric` | **C1589** | `/ETH_1V2` | +| E-04 | C90 | 10uF C440198 → **4.7uF** 0805 | **C1779** | `/ETH_TOCAP` | +| E-04 | **C172, C173 (new)** | 100nF 0603 at AVDD 4/8 and 11/21 | C14663 | `/3V3_ETH` – GND | +| F-52 | **U31 (new)** | TMP102AIDRLR, **I²C 0x49** (ADD0 → V+) | **C99269** | 1 `/I2C_SCL` · 2 GND · 3 NC · 4 `/3V3` · 5 `/3V3` · 6 `/I2C_SDA` | +| F-52 | **C174 (new)** | 100nF 0603 | C14663 | `/3V3` – GND | +| G-03 | P11, P12 | `…MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical` (not in library) → **`Connector_Phoenix_MC:PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal`**; populated (D10) | C5160226 (unchanged) | | +| G-03 | J10 | `Connector_RJ45:…` (nickname not configured) → **`Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal`**; populated | C12074 (unchanged) | | +| G-04 | **JP6 (new)** = JP_CUT | `Jumper:SolderJumper_2_Open`, open footprint, value CUTOFF_BYPASS, not in BOM | no part | 1 `/MAIN5V`, 2 `/SYS5V` | +| G-08 | **D36, D37, D38 (new)** | PESD5V0S1BA, `Diode_SMD:D_SOD-323` (same as D14–D16) | **C2827694** | pin 1 `/NRST` / `/NTC_TEMP` / `/NTC2`, pin 2 GND | +| H-08 | C22, Y2 | value text "22uF/50V" → **"10uF/50V"**; "1.8432MHz" → **"3.6864MHz"** | unchanged | | +| B-15 | R107, R108 | value "0R-DNP" → **"0R-NEVER-FIT"** + `Note` field (still DNP) | — | | +| J-04 | 23 orphan NC flags (x = 453.898 / 484.378) | **deleted** | — | | +| J-04 | NC flags on U16.37, U16.38, U10.13, U10.14 | **deleted** (pins stay on their nets) | — | | +| J-04 | wire stubs | **2b755f7f deleted** (the dangling stub over P1.4); **7c1dbfc0 trimmed** from y 219.71 to 218.948 so it ends at its GND label (R52.2 stays on GND); **46f71e27 kept** (it carries P1.4's GND label) and the P1.4 junction kept. See §12 | — | no net change | + +## 3. New parts — where they are on the sheet + +All new parts sit in free space found with an occupancy map of the sheet (symbols, pins, labels, wires, texts), on the 1.27 mm grid, each cluster with a blue note "v6 audit : …" stating the physical placement rule. Coordinates are schematic mm (A1 sheet). + +| Cluster | Refs | Sheet position | Block it belongs to | +|---|---|---|---| +| C-01 | R135, U28, R136 | (402–475, 196) | below U18 / L21 bias-T | +| F-02 | D35 | (94, 36) | beside P1 | +| A-05 | C161, C162 | (377–391, 226) | right of C32–C34 | +| F-03 | C163, C164, C165 | (184–213, 295) | left of U20 | +| B-02 | C166, C167 | (401–415, 404) | right of U19 (VBAT caps) | +| F-51 | U29, C168 | (257–287, 141) | above the charger passives (R50/R55) | +| F-51 | R137, R138, C169 | (264–298, 220) | beside R50/R56 | +| E-01 | R139 | (674, 217) | at U12 | +| E-02 | R140 | (692, 60) | at U11 | +| D-01 | U27, C170 | (268–304, 458) | below U23/U24 | +| G-02 | U30 | (489, 307) | beside J9 | +| A-13 | R141 | (218, 246) | near TP1/TP2 | +| B-09 | C171 | (328, 460) | above J14 | +| B-10 | R142, R143 | (284–298, 498) | below U24 | +| C-07 | TP10, TP11 | (522–538, 104) | right of U18 | +| D-09 | R144 | (137, 113) | at Q5 | +| D-12 | TP9 | (547, 420) | right of U16 | +| E-04 | C172, C173 | (730–745, 183) | below C94 | +| F-52 | U31, C174 | (188–218, 414) | left of U23/U24 (modem block) | +| G-04 | JP6 | (281, 25) | beside P5 | +| G-08 | D36 / D37, D38 | (328, 133) / (476–503, 232) | at P6 / near P7–P8 | + +## 4. Netlist proof + +Netlists exported with kicad-cli through the KiCad MCP after each committed group (`kicad/_to_delete/v6-apply-20260928/netlists/00…05.xml`). `tools/ndiff.py` compares refs, value, footprint, lib_id, every field and property, DNP / BOM / position flags, **ref.pin → net** and net class. The expected change set of each group was written by the edit script *before* the file was committed and asserted against the actual diff. + +| Group | Netlist | Expected (added / removed / field / pin-net / class) | Actual | Result | +|---|---|---|---|---| +| 1 Blockers | 00-baseline → 01-blockers | 4 / 3 / 38 / 9 / 0 = 54 | 4 / 3 / 38 / 9 / 0 | **MATCH** | +| 2 Majors | 01 → 02-majors | 17 / 0 / 36 / 4 / 0 = 57 | 17 / 0 / 36 / 4 / 0 | **MATCH** | +| 3 Minors | 02 → 03-minors | 16 / 0 / 51 / 9 / 0 = 76 | 16 / 0 / 51 / 9 / 0 | **MATCH** (after the J-04 correction, §12) | +| 4 Project rules | 03 → 04-rules (schematic untouched) | 0 / 0 / 0 / 0 / 16 | 0 / 0 / 0 / 0 / 16 | **MATCH** | +| 5 Cosmetic (U30 ref text) | 04 → 05-final | 0 | 0 | **MATCH** | +| **Total** | 00 → 05-final | composition of groups 1–5 | 37 / 3 / 125 / 22 / 16 | **0 differences** in every ref, attribute, pin and class | + +Field changes count both `footprint` and the `Footprint` field when a footprint changes. The 22 pin-net changes: U20.2, C127.1, C128.1 → `/MAIN5V`; D10.1 → `/VIN_FUSED`; L21.2, C144.1, C145.1 → `/ANT_BIAS`; U18.7 → NC; U18.5 → `/GNSS_ANT_OFF`; U12.2 → `/ETH_PWR_EN`; U16.54 → `/ETH_PWR_EN`; U16.25 → `/NTC_CELL`; U18.26 → `/DOUT_4G_F9P`; R56.2 → `/3V3`; U6.20, TP2.1 → `/PFO`; U16.29 → `/PFO`; U16.42 → `/USART1_TX`; U18.50 → `/GNSS_SAFEBOOT_N`; Y3.2 → GND, Y3.3 → `/HSE_OUT`, Y3.4 → GND. Full machine list: `netlist_diff_total.md`; per group: `out/0N-*/netlist_diff.md`. + +UUIDs: no existing symbol changed UUID (checked per group); the guard also held on every write. + +## 5. ERC (kicad-cli 10.0.4 via KiCad MCP) + +Per-category counts come from copies with narrowed ERC severities (`kicad/_to_delete/v6-apply-20260928/erc_work/`), because the MCP prints only 30 items. Baseline categories are the audit's (`evidence/erc_summary.md`, same file hash); final categories are from runs on the final file, and they add up to the full run. + +| Category | Before | After | Why | +|---|---|---|---| +| Errors | 0 | **0** | | +| pin_to_pin | 104 | 102 | −2 from D21 (unspecified-pin easyeda symbol) removed; new symbols have typed pins | +| no_connect_dangling | 23 | 0 | J-04 orphan flags deleted | +| lib_symbol_mismatch | 22 | 21 | Y3 now uses a fresh `Device:Crystal_GND24` copy | +| lib_symbol_issues (not in library) | 10 | 11 | +1: `Drogheda-sym:TPS2552DBV` is embedded only (§7). The 10 old ones remain (re-link skipped, §9) | +| footprint_link_issues | 3 | 0 | G-03 (P11, P12, J10) | +| no_connect_connected | 2 | 0 | J-04 | +| unconnected_wire_endpoint | 2 | 0 | J-04 (stub deleted / tail trimmed) | +| All other checks (dangling labels, unconnected pins, power pins, …) | 0 | 0 | | +| **Total warnings** | **166** | **134** | | + +During Group 3 an intermediate run showed 3 errors (label/pin not connected at P1.4 and R52.2) from my first J-04 stub deletion; the netlist diff flagged the same two pins. Both were fixed before continuing (§12). + +## 6. Project rules (F-01, D18) + +### 6.1 Net classes (`hbox-watchdog-v6.kicad_pro`) + +All old patterns were replaced by exact full net names (the un-prefixed duplicates and dead patterns `3V3_MODEM`, `SW3_NODE` are gone). In the final netlist every pattern resolves to a real net. + +| Class | Nets | Clearance | Track | Via | Priority | +|---|---|---|---|---|---| +| HV24 | `/24V_IN` `/VIN_FUSED` `/VIN_PROT` `/24V` `/IGN_IN` `/Q10_GATE` `/Q23_GATE` `/SW_PWRIN` `/BOOT_PWRIN` `/SW_FAN` `/BST_FAN` | 0.3 (was 0.5) | 1.0 (was 0.5) | 0.8/0.4 | 0 | +| PWR_HI | `/BAT_PLUS` `/SW_BAT` `/MAIN5V` `/VEH5V` `/SYS5V` `/VIN_SW` | 0.15 (was 0.2) | 1.5 | 0.8/0.4 | 1 | +| PWR_MODEM (new) | `/VBAT_MODEM` | 0.15 | 1.5 | 0.8/0.4 | 2 | +| PWR_MID | `/SW_5V` `/SW_IN` `/5V_FAN` `/FAN_RET` | 0.15 (was 0.2) | 0.6 (was 1.0) | 0.8/0.4 | 3 | +| RF (new) | `/RF_GNSS` `/RF_ANT_GNSS` `/RF_LTE` `/RF_ANT_LTE` | 0.2 (CPWG gap) | 0.3 (CPWG width; final value from JLC's calculator) | 0.6/0.3 (no vias intended) | 4 | +| Default | everything else, incl. `/3V3_ETH` (moved out of PWR_MID, J-02), `/EN_FAN`, `/EN_PWRIN`, `/SW_MODEM`, `/BST_MODEM` | 0.15 (was 0.2) | 0.2 | 0.6/0.3 | — | + +Netlist class changes (16): to HV24 `/VIN_FUSED` `/VIN_PROT` `/24V` `/IGN_IN` `/Q10_GATE` `/Q23_GATE` `/SW_PWRIN` `/BOOT_PWRIN` `/BST_FAN` (from Default) and `/SW_FAN` (from PWR_MID); `/3V3_ETH` PWR_MID → Default; `/VBAT_MODEM` → PWR_MODEM; the four RF nets → RF. + +**Decision on the HV24 list (differs from the report table, which predates A-01):** `/VIN_MODEM` no longer exists, and **`/SW_MODEM` and `/BST_MODEM` were left out of HV24**. With A-01, U20 runs from `/MAIN5V` (≤ 5.5 V), so they are 5 V-class switch/boot nodes; in HV24 they would raise false 0.3/0.5 mm errors around U20 (like `/ETH_SW`, they stay Default with the T15 width rule). `/SW_FAN`, `/BST_FAN`, `/24V` and `/Q10_GATE` **stay HV24**: the U2 and Q10 footprints remain on the board as DNP and would carry vehicle voltage if ever fitted. + +### 6.2 `.kicad_dru` (verify_2's corrected set, verbatim; replaces "Minimum clearance 1", "HV24 clearance", "HV24 exception: MP1584EN land pattern") + +``` +(rule "Floor 0.15 (non-HV24, non-RF)" + (condition "A.NetClass != 'HV24' && B.NetClass != 'HV24' && A.NetClass != 'RF' && B.NetClass != 'RF'") + (constraint clearance (min 0.15mm)) +) +(rule "HV24 to HV24" + (condition "A.NetClass == 'HV24' && B.NetClass == 'HV24'") + (constraint clearance (min 0.2mm)) +) +(rule "HV24 outer" + (layer outer) + (condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'") + (constraint clearance (min 0.3mm)) +) +(rule "HV24 inner" + (layer inner) + (condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'") + (constraint clearance (min 0.5mm)) +) +(rule "HV24 IC land patterns" + (layer outer) + (condition "A.Type == 'Pad' && B.Type == 'Pad' && ((A.memberOfFootprint('U2') && B.memberOfFootprint('U2')) || (A.memberOfFootprint('U20') && B.memberOfFootprint('U20')) || (A.memberOfFootprint('U25') && B.memberOfFootprint('U25')))") + (constraint clearance (min 0.15mm)) +) +``` + +A 3-line comment header was added above the set. The silkscreen text rule and the three T15 power-width warning rules are unchanged (the T15 rule still names `/VIN_MODEM`, now a dead name; harmless). The U20 clause of the land-pattern rule no longer matches anything after the HV24 decision above; it was kept to stay verbatim with verify_2. + +## 7. Library + +- **H-04 fixed:** `(property "LCSC Part" "C2071691")` deleted from `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` (one line, span-scoped; the rest of the file is byte-identical). That footprint is shared by U20 (AP64350, C2071691) and U25 (TPS54360B, C524806); both now resolve through their `LCSC` fields. The board copy of U25 still carries the field until Michelle updates the footprint from the library (§10). +- **Other `LCSC Part` values in `Drogheda-v6.pretty` checked against their users (not stripped):** IND-SMD_L13.5-W12.5 C840531 = L22 ✓ · LCC-LGA-102 C5120257 = U18 ✓ · LGA-124 C18548276 = U19 ✓ · LGA-12 C5126709 = U26 ✓ · RF-SMD_FRF05002 C88374 = J12, J13 ✓ · SMA_L4.4 C113952 = D22 ✓ · VSSOP-8 C730237 = U23, U24 ✓ · SOD-923 C82326 = D27 ✓ (D28 moved to 0402) · **SOD-128 C50603 now unused** (D21 removed). None is wrong. +- **TPS2552 symbol:** KiCad 10 has no TPS2552 symbol (the MIC2007/2008 SOT-23-6 switches have a different pinout), so `Drogheda-sym:TPS2552DBV` was authored and **embedded in the schematic only**: box symbol, 1 IN power_in, 2 GND power_in, 3 ~EN input, 4 ~FAULT open_collector, 5 ILIM passive, 6 OUT power_out, footprint SOT-23-6, TI datasheet link. `Drogheda-sym.kicad_sym` was not edited (outside this pass's file set; shared with v5), which is the +1 ERC "not found in library" warning. Copy it into the library in a library pass. +- New library symbols embedded from KiCad 10: `74xGxx:74LVC1G125`, `Power_Protection:USBLC6-2SC6`, `Device:Crystal_GND24`. `Sensor_Temperature:TMP102xxDRL` was already cached in the sheet and is content-identical to the library. + +## 8. Reverse-polarity and fusing topology after V1-01 / A-01 + +``` +P1.1 ─ /24V_IN ─ F2 (3 A Nano2, socketed) ─ /VIN_FUSED ─┬─ D10 SMBJ33A (pad 1 cathode) ─ GND + └─ Q23 IRFR5305: D=/VIN_FUSED, S=/VIN_PROT, G=/Q23_GATE + D33 zener S→G clamp, R119 gate to GND +/VIN_PROT ─ D32 SMCJ33A, C149–C151, U25 (TPS54360B) → /VEH5V +/24V_IN also ─ Q10.D (Q10 branch DNP: /24V carries no fitted part) +``` + +- **Correct polarity:** current flows P1 → F2 → Q23 body diode (drain→source), Q23 enhances with its gate pulled to GND (V_GS clamped at −15 V by D33) → /VIN_PROT. D10 and D32 clamp transients; D10 is now behind F2, so a TVS that fails short opens F2 instead of loading the harness. +- **Reversed P1:** /VIN_FUSED goes negative; Q23's gate (to GND) is positive against its source, so Q23 stays off and its body diode is reverse-biased. D10 forward-conducts GND → /VIN_FUSED through F2 → **F2 blows** (socketed, replaceable). Before V1-01, D10 sat on /24V_IN ahead of F2 and would have carried harness-fuse current. +- The only unfused copper left on /24V_IN is P1.1 → F2.1 and the Q10.D pad of the DNP Q10. If the Q10 branch is ever re-fitted, move Q10.D to /VIN_FUSED first. +- U20 now sits on /MAIN5V, upstream of the P5 cutoff (A-01 note): P5 still removes SYS5V → MCU unpowered → R113 holds U20 EN low (µA). + +## 9. Skipped items and decisions + +**Not applied** +1. **G-01** (restore MH4 at (193.2, 90.3), heatsink-clamp holes MH11 + partner): board-only mounting holes; Michelle (D11 makes it a Blocker). +2. **J-04, re-linking the 10 "not found" symbols** (Q_*MOS_G?S ×7, D_Zener_ANK ×2, PCF8574): needs writing their definitions into the shared `Drogheda-sym.kicad_sym` (outside the allowed file set) and swapping 10 lib_ids. Cosmetic; left as warnings. The 22 library mismatches were left alone as the report asks (no bulk update). +3. **G-08, optional 100 Ω series resistor on NRST:** optional in the report; it would split `/NRST`. Not applied. +4. **D-08** (board-ID strap), **H-03** (MWSA0804S land), **J-03** (library pin types): excluded by D19. +5. Layout-only Majors (V1-01 layout, F-12, F-05, F-06, C-04, A-07) and A-02: layout list, §10. + +**Decisions taken while applying (beyond the letter of §7)** +- DNP marking follows the sheet's existing convention (`(dnp yes)` only, as on C146/C147, R107/R108, R124/R125, R127–R130, U22): footprints stay on the board with the DNP attribute, and KiCad leaves DNP parts out of BOM/CPL outputs. +- U17, U21, U10 kept their symbols (identical pin numbering) and changed fields only; the netlist diff shows value/LCSC/MPN changes only for them. +- New test pads (TP9–TP11) and JP6 are excluded from BOM and position files (no purchasable part). TP1–TP8 were left as they are. +- HV24 net list: §6.1. PF15 removal: §2.1. C171 net: §2.3. + +## 10. Layout delta for Michelle + +Run **Tools → Update PCB from Schematic** on `hbox-watchdog-v6.kicad_pcb` with **"Delete footprints with no symbols" ticked** (earlier runs did not delete removed footprints), and "Update footprints" on so the changed footprints are swapped. Then run DRC (new rules, below). + +**New footprints to place (37)** + +| Ref | Footprint | Where / constraint (from the audit) | +|---|---|---| +| U28 | SOT-23-6 | GNSS bias switch next to L21/C144/C145 at J12; `/ANT_BIAS` ≥ 1 mm from the RF line with a stitched GND strip (F-06); short feed from `/3V3_GNSS` | +| R135, R136 | 0603 | at U28 pins 3 and 4 | +| D35 | D_SMB | **at P1.3**; with Rig1 moved to ≤ 3 mm of copper from P1.3 so `/IGN_IN` is ≤ 3 mm on F.Cu and the long run becomes `/IGN_SENSE` (F-02) | +| C161, C162 | 1210 | ≤ 2 mm from U6 VSYS pins 1/24, GND on the U6 EP copper (A-05/A-02) | +| C163, C164 | 0805 | ≤ 2–3 mm from U20.2, GND on the U20 EP copper (F-03) | +| C165 | CP_Elec_6.3x7.7 | at U20.2 (F-03) | +| C166, C167 | 0805 | ≤ 3 mm from L20.2 (B-02) | +| U29 + C168 | SOT-563 + 0603 | **between U6 and L6, ≤ 5 mm from the U6 EP** (F-51, R4) | +| R137, R138, C169 | 0603 | pack-NTC tap: R138/C169 at U16 pad 25 (PC5); R137 anywhere on `/NTC` | +| R139 | 0603 | at U12 pin 2 (EN); new track `/ETH_PWR_EN` to U16 pad 54 (PD2) | +| R140 | 0603 | at U11.37 (`/ETH_RST`) | +| U27 + C170 | SOT-23-5 (SOT-753) + 0603 | **at U18.26 (RXD2)**; VCC from `/3V3_GNSS` | +| U30 | SOT-23-6 | **≤ 3 mm of copper from the J9 pads**, D+/D− routed through the device pads, GND via ≤ 1 mm (G-02) | +| R141 | 0603 | `/PFO` pull-up near U16 pad 29 (PB10) | +| C171 | 0402 | at J14.C1 | +| R142, R143 | 0603 | on `/MODEM_STATUS` (PC9) and `/DIN_4G`, any convenient spot | +| TP10, TP11 | TestPoint_Pad_D1.0mm | near U18 pins 50 (SAFEBOOT_N) and 49 (RESET_N), next to a GND pad (C-07) | +| R144 | 0603 | at Q5 base | +| TP9 | TestPoint_Pad_D1.5mm | PA9 debug-TX pad next to TP3–TP5 (D-12) | +| C172, C173 | 0603 | at W5500 AVDD pins 4/8 and 11/21 | +| U31 + C174 | SOT-563 + 0603 | **between U19 and U20** (F-52) | +| JP6 | SolderJumper 2-pad, open | across P5 (`/MAIN5V`–`/SYS5V`), silk "CUTOFF BYPASS" (G-04) | +| D36, D37, D38 | SOD-323 | ≤ 3 mm from P6.1, P7.1, P8.1 to GND (G-08) | + +**Removed footprints:** D20 (D_SMA), D21 (SOD-128). (PF15 is a virtual power flag, no footprint.) + +**Footprint changes:** U15 → narrow `SOIC-16_3.9x9.9mm` (re-place C84–C88, local reroute) · D28 → `D_0402_1005Metric` (with the F-06 LTE reroute) · Y3 → `Crystal_SMD_3225-4Pin_3.2x2.5mm` (pad 1 HSE_IN, pad 3 HSE_OUT, pads 2/4 GND; ≤ 3–5 mm from PH0/PH1, no inner track under it) · C91 → 0603 · JP1 → Bridged (net-tie) · J10 → `Connector_RJ:` nickname (same geometry) · P11/P12 → Horizontal (already so on the PCB) · U25 → re-pull the footprint from the library so its board copy loses `LCSC Part` (H-04) · Y4 and F2 keep their footprints. + +**DNP changes:** set DNP: U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21, Q10, DzG1, Rrp1, C10, C11, C22. **Clear DNP:** J10, P11, P12 (populated per D10). + +**Nets that change routing** +- `/VIN_MODEM` disappears: U20.2, C127, C128 go to **`/MAIN5V`** (≥ 1.5–2 mm all the way to U20; delete the 48 mm `/VIN_MODEM` run, A-01/A-07). +- `/VIN_FUSED` gains D10.1: P1.1 → F2 → {D10, Q23.D}; `/24V_IN` = P1.1, F2.1, Q10.D only. +- `/ANT_BIAS` (U28.6 → L21.2, C144, C145); U18.7 is now NC; `/GNSS_ANT_OFF` (U18.5 → U28.3, R135); `/GNSS_ANT_SHORT_N` gains U28.4 and R136. +- `/ETH_PWR_EN` (U12.2, U16.54, R139); U12.2 leaves `/SYS5V`. +- `/DOUT_4G_F9P` (U27.4 → U18.26); U18.26 leaves `/DOUT_4G`; U27.2 joins `/DOUT_4G`. +- `/PFO` (renamed from `/PFO_TP`: U6.20, TP2, plus U16.29 and R141). +- `/NTC_CELL` (U16.25, R137, R138, C169); `/NTC` gains R137. +- `/GNSS_SAFEBOOT_N` (U18.50, TP10); `/USART1_TX` (U16.42, TP9). +- R56.2 moves from GND to `/3V3`; Y3 pads re-netted as above. + +**DRC with the new rules (run on a copy of the current, not-yet-updated board):** 161 clearance errors (was 0). **149 of them are zone-fill proximities** (stored fills at 0.15 mm to HV24 and RF nets); a zone refill clears them. **12 are real copper spacings:** `/IGN_IN` on In2 vs GND via 0.250, `/FAN_PWM` 0.291, `/5V_FAN` via 0.300, `/NTC2` 0.305, `/VEH5V` via 0.340 (all F-02, disappear with the P1.3 move); `/VIN_PROT` vs `/VEH5V` 0.157 and 0.191 at (175.5, 113.8); `/USB_VBUS` vs Q23.1 `/Q23_GATE` 0.225; `/SW_PWRIN` vs GND track 0.270; `/24V` vs `/COMP_FAN` 0.290 ×2 (DNP branch, but the copper exists); RF class: `/RF_LTE` via vs `/PWR_CTRL` 0.150 (goes away with the F-06 F.Cu reroute). **Caveat:** KiCad lists only one violation between the long In2 `/IGN_IN` segment and `/VEH5V` (the via at 0.340 mm); the parallel `/VEH5V` 1.0 mm tracks beside it are 0.221–0.240 mm away (recomputed from the track coordinates, matching the audit's 0.221 mm) and are not listed as separate items. So do not read the DRC count as the full list; the F-02 move removes the whole In2 `/IGN_IN` run anyway. `track_width` warnings drop 183 → 121 (`/3V3_ETH` now Default, PWR_MID width 0.6). Other DRC items unchanged (82 lib_footprint_mismatch, 4 lib_footprint_issues, 11 silk_overlap, 2 silk_over_copper, 1 silk_edge). After Update PCB, expect new HV24 items on `/VIN_FUSED` at D10 and removal of the `/VIN_MODEM` ones. Check once with Inspect → Clearance Resolution that the classes survived the GUI save (resync protocol §5). + +**Order notes (from the part lookups):** C2862740 (TPS7A2033PDBVR, U21) is listed by JLC under "Pre-ordered Chips": pre-order it into the account like J14. P11/P12 C5160226 stock 512 (enough for 20 boards). Re-check stock on order day (D14). + +## 11. Firmware notes (for FW 0.7.x `board_v6.h`, D15) + +1. **PD2 = `ETH_PWR_EN`**: U12 (3V3_ETH) enable, R139 100 k pull-down → Ethernet OFF in reset/DFU/battery; drive HIGH only on vehicle power when Ethernet is needed; keep SPI2 and PA15 low while it is off. +2. **PB10 = `PFO`**: LTC4040 PFO, open-drain, R141 100 k pull-up to 3V3; EXTI10 falling = backup entry (VEH5V < PFI 4.40 V falling / 4.51 V rising). Update `V5_PFI` to 4.40 V. +3. **PC5 = `NTC_CELL`** (ADC1_IN15): pack NTC through 100 k/120 k (ratio 120/220) + 10 nF; Rntc = R55·Vntc/(VEH5V − Vntc) with VEH5V from PA4; valid only with VEH5V present. Feed `tcell` into `CHG_CELL_HOT/COOL`. +4. **CHGOFF default:** R56 is now a pull-**up** to 3V3 → PA8 (`CHRG_EN`, drives LTC4040 CHGOFF) high = charger **off** whenever the MCU is not driving. Polarity unchanged: firmware drives PA8 LOW to allow charging. +5. **Ignition on PA5 (ADC1_IN5), read analog**, no internal pull: Rigb1 = 2.2 k → ratio 2.0 k/24.0 k = **0.0833**: 12 V → 1.00 V, 24 V → 2.00 V, 36 V → 3.00 V, full scale 39.6 V. Add `vign` to `$PHLG`. +6. **TMP102 at 0x48 = charger sensor (U29)**, **0x49 = modem-area sensor (U31)**; no address clash (0x18 SC7A20, 0x20 PCF8574, 0x44 SHT40, 0x4D SC16IS752). Add `tchg`, `tmodem` to `$PHLG`; shed charge on `tchg` > 85 °C. +7. GNSS antenna: F9P ANT_OFF now drives TPS2552 ~EN (set `CFG-HW-ANT_CFG_VOLTCTRL` = 1, `SHORTDET` = 1). PC2 `GNSS_ANT_SHORT_N` is driven by TPS2552 ~FAULT (open drain, 10 k to 3V3_GNSS): LOW = short or rail off. PC1 `GNSS_ANT_DETECT` remains undriven (keep hi-Z, infer open antenna from C/N0). +8. U27 now isolates F9P RXD2: F9P-only power cycles with the modem up become safe on boards that have it; keep the 0.5.5/0.5.6 back-feed rules for PA2/PA10/PC7/PC12. Rdfu1 is 100 k (≤ 27 µA into TXD2 with the F9P off). +9. `/MODEM_STATUS` (PC9) has a 100 k pull-down and `/DIN_4G` a 100 k pull-up in hardware: no internal pulls needed. R106 is 1 k. +10. PA9 is a test pad (TP9, `USART1_TX`): usable as a TX-only debug log or ROM USART bootloader. +11. U25 set-point is now 5.32 V nominal (R121 57.6 k): keep `CHG_RAIL_ON` 5.05 V / `CHG_RAIL_OFF` 4.90 V; compute VDDA from VREFINT. +12. LSE: Y4 is CL 7 pF → set `LSEMOD` (high drive) before `LSEON`, LSI fallback. HSE is still 25 MHz (new 3225 crystal); `BOARD_SER_XTAL_HZ` = 3 686 400 (Y2 value text now matches). +13. Battery mode (D9): LTE-only (`AT+CNMP=38`), Ethernet off. + +## 12. Incidents and surprises + +1. **J-04 wire stubs were not all dangling.** The audit listed three stub UUIDs. Deleting all three broke two connections: at P1.4 the GND label sits at the far end of 46f71e27 (only 2b755f7f is the dangling overhang), and at R52.2 the GND label sits mid-segment on 7c1dbfc0 (only a 0.76 mm tail past the label was dangling). ERC showed 3 new errors and the netlist diff flagged exactly P1.4 and R52.2 as unexpected. Fixed by deleting only 2b755f7f, keeping 46f71e27 and the P1.4 junction, and trimming 7c1dbfc0 to end at its label. Re-verified: expected == actual, ERC 0 errors. +2. **`device_commit_files` re-sent a cached upload** when a staged path was reused: my second commit of Group 1 wrote the first version. Caught by hashing the Mac file after every commit; from then on every commit used a unique staged path. Every committed state in this report was hash-checked on the Mac. +3. **Y3 needed a symbol swap**, not a footprint swap: `Device:Crystal` (2 pins) on the 3225-4P land would have put HSE_OUT on GND pad 2. Swapped to `Device:Crystal_GND24` in place (UUIDs kept, pins 3/4 added), proven by the netlist. +4. **The TPS2552 has no KiCad library symbol** (embedded one authored, §7). +5. **TPS7A2033PDBVR is in JLC's "Pre-ordered Chips" category** (stock 28 370): pre-order like J14. +6. One wire-crossing hit on U30 remains: the MCP tool's bounding box for the vertically asymmetric USBLC6 symbol; the PDF shows the VBUS wire leaving the pin outward. + +## 13. New LCSC numbers (JLC DB lookup via KiCad MCP, 2026-09-28) + +| LCSC | Part | Package | Stock | Type | Used on | +|---|---|---|---|---|---| +| C206912 | Littelfuse 0154003.DR 3 A | SMD 9.7×5 (Nano2 holder) | 2 217 | Ext | F2 | +| C22840 | 1.43 kΩ 1 % | 0603 | 4 965 | Ext | R50 | +| C1975527 | Littelfuse PESD0402-240 | 0402 | 9 394 | Ext | D28 | +| C46506 | TI TPS2552DBVR | SOT-23-6 | 3 002 | Ext | U28 | +| C224019 | Littelfuse SMBJ33A | DO-214AA | 9 624 | Ext | D35 | +| C57156 | NXP SC16IS752IPW,128 | TSSOP-28 | 2 670 | Ext | U10 | +| C177479 | HKR RCT03499KFLF 499 k | 0603 | 26 862 | Ext | R53 | +| C23082 | 57.6 kΩ 1 % | 0603 | 3 673 | Ext | R121 | +| C5440143 | Samwha 47 µF 16 V X7R | 1210 | 242 640 | Ext | C161, C162 | +| C15578 | TI TLV1117LV33DCYR | SOT-223 | 26 999 | Ext | U17 | +| C881921 | Lelon OVZ221M1CTR-0608 220 µF 16 V polymer | 6.3×7.7 | 2 442 | Ext | C78, C130, C131, C165 | +| C22862 | 113 kΩ 1 % | 0603 | 59 728 | Ext | R116 | +| C1542 | 6.8 nF 50 V X7R | 0402 | 128 063 | Pref | C141 | +| C1572 | 56 pF C0G | 0402 | 83 992 | Ext | C142 | +| C86817 | Murata 22 µF 16 V X5R | 0805 | 4 144 | Ext | C163, C164, C166, C167 | +| C99269 | TI TMP102AIDRLR | SOT-563 | 34 854 | Ext | U29, U31 | +| C25808 | 120 kΩ 1 % | 0603 | 773 686 | Basic | R138 | +| C1589 | 10 nF 50 V X7R | 0603 | 6 584 349 | Ext | C169, C91 | +| C2862740 | TI TPS7A2033PDBVR | SOT-23-5 | 28 370 | Ext (**pre-order category**) | U21 | +| C23162 | 4.7 kΩ 1 % | 0603 | 21 915 184 | Basic | R140 | +| C12518 | Nexperia 74LVC1G125GV,125 | SOT-753 | 5 234 | Ext | U27 | +| C7519 | ST USBLC6-2SC6 | SOT-23-6 | 1 415 | Ext | U30 | +| C25803 | 100 kΩ 1 % | 0603 | 10 814 547 | Basic | new pull resistors, Rdfu1, H-02b set | +| C14663 | 100 nF 50 V X7R | 0603 | 37 493 696 | Basic | C168, C170, C172–C174 | +| C23345 | 22 Ω 1 % | 0603 | 4 031 533 | Basic | R132–R134 | +| C1525 | 100 nF 16 V X7R | 0402 | 43 509 060 | Basic | C171 | +| C14676 | 1 kΩ 5 % | 0603 | 757 955 | Ext | R106 | +| C2901684 | SCTF SX3B25.000F1010F30 25 MHz CL 10 pF | 3225-4P | 11 076 | Ext | Y3 | +| C38523 | 12 pF C0G | 0603 | 3 346 489 | Basic | C113, C114 | +| C48615 | Epson Q13FC13500002 FC-135 CL 7 pF | 3215-2P | 101 342 | Ext | Y4 | +| C1679 | 6.8 pF C0G | 0603 | 1 445 998 | Pref | C115, C116 | +| C4190 | 2.2 kΩ 1 % | 0603 | 2 920 710 | Basic | Rigb1 | +| C1663 | 33 pF C0G | 0603 | 2 808 576 | Basic | C95, C96 | +| C1779 | 4.7 µF 25 V X5R | 0805 | 4 715 349 | Basic | C90 | +| C2827694 | PESD5V0S1BA | SOD-323 | 303 975 | Ext | D36–D38 | +| C25804 | 10 kΩ 1 % | 0603 | (existing Basic) | Basic | R136 | + +Final BOM (`kicad/_to_delete/v6-apply-20260928/bom_final*.csv`, kicad-cli): 306 populated BOM lines; only TP1–TP8 have no LCSC (copper pads, as before). + +## 14. Files and backups + +- Edited in place: `03-Architecture-Hardware/kicad/hbox-watchdog-v6.kicad_sch`, `.kicad_pro`, `.kicad_dru`, `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod`. +- PDF: `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf`. +- Backups (nothing deleted): `kicad/_to_delete/v6-apply-20260928/` — `00-pre/` (sch, pro, dru, prl, SO-8 footprint, DRC side-file), `01-blockers/`, `02-majors/`, `03-minors/`, `04-rules/`, `05-final/`, `netlists/00-baseline … 05-final.xml`, `erc_work/` (ERC isolation copies), `drc_work/` (DRC on a board copy with the new rules; report + JSON), `scratch/` (intermediate PDFs, library-extraction file), `bom_final.csv`, `bom_final_ungrouped.csv`. +- Container: `/home/claude/v6audit/apply/` — this report, `netlist_diff_total.md`, `out/0N-*/` (edit logs, expected sets, per-group diffs), `tools/` (editor, model, diff, group scripts), `drc/`, the PDF. +- The `.kicad_pcb` is untouched. If KiCad was open on v6 during this pass, close it **without saving** and reopen before Update PCB (resync protocol §5). + +**Git (for Leo to run; nothing was committed from here):** commit inside the `kicad` submodule (sch, pro, dru, SO-8 footprint), push to Gitea `HBox_PCB`, then bump the parent gitlink; `_to_delete/` is gitignored. diff --git a/03-Architecture-Hardware/2026-09-28_v6-audit-attachments/verify_apply.md b/03-Architecture-Hardware/2026-09-28_v6-audit-attachments/verify_apply.md new file mode 100644 index 0000000..c6d81ac --- /dev/null +++ b/03-Architecture-Hardware/2026-09-28_v6-audit-attachments/verify_apply.md @@ -0,0 +1,150 @@ +# EinarBoard v6 — Independent verification of the schematic apply pass (v1.0) + +**Date:** 2026-09-28 18:45 CST · **Verifier:** independent Claude agent (read-only, own scripts) · **Object:** `hbox-watchdog-v6.kicad_sch` sha256 `d54e330d…4c4` (the apply pass result, before the ports pass), `.kicad_pro` `d577aa43…`, `.kicad_dru` `31ce0f4f…`, SO-8-EP footprint `3f38f26e…`. + +## Result: 173 PASS · 0 FAIL · 15 NOTE + +- **Provenance:** the apply pass's baseline netlist equals the audit's evidence netlist; connectivity re-derived directly from the .kicad_sch (own union-find extractor) reproduces `05-final.xml` exactly (353 nets). +- **Completeness:** all 126 intended items (§7.1, §7.2, D19 Minors) present with the intended value, footprint, LCSC, DNP state and pin→net; no unintended electrical change (only extras: C174 decoupling at U31 and MPN/Manufacturer metadata; the Fabrication Toolkit reads `LCSC` before `MPN`). +- **Datasheet pinouts (all PASS):** TPS2552DBVR hand-built symbol (TI SLVS841F), 74LVC1G125GV (Nexperia rev 17.1), USBLC6-2SC6 (ST DS4260), TMP102 DRL (TI SBOS397I; 0x48/0x49), PESD0402-240 (bidirectional), SMBJ33A IGN TVS (cathode on /IGN_IN), PESD5V0S1BA ×3, polymer cap polarity, Y3 `Crystal_GND24` ↔ 3225-4P pads. +- **Pin-compatible swaps (all PASS):** U17 → TLV1117LV33DCYR (TI SBVS160C), U21 → TPS7A2033PDBVR (TI SBVS338H), U10 → SC16IS752IPW (NXP rev 9.1; I²C 0x4D). +- **Topology (all PASS):** F2 → /VIN_FUSED → {D10, Q23}; reversed P1 forward-biases D10 and blows F2, Q23 stays off; Q10 branch fully DNP with no populated loads on /24V; /VIN_MODEM fully merged into /MAIN5V; JP1 bridged; U20 loop 113 k / 6.8 nF / 56 pF; R50 1.43 k; R121 57.6 k; ETH_PWR_EN → PD2 + 100 k; ETH_RST 4.7 k; U27 drives only U18.26; NTC tap → PC5. +- **BOM/JLC:** 28 DNP parts flagged; every populated part has an LCSC number; 30 LCSC numbers spot-checked (part, package, stock). +- **Project rules:** netclass patterns resolve exactly as KiCad's netlist says (no dead patterns); `.kicad_dru` parses and holds verify_2's five rules verbatim; `LCSC Part` removed from the SO-8-EP library footprint. +- **ERC:** 0 errors, 134 warnings (all pre-existing cosmetic categories). + +## Notes acted on afterwards +- **N1 (Y3 pad map):** confirmed later from the SCTF 3X datasheet (pins 1/3 crystal, 2/4 GND) — no change (Final Check). +- **N2 (TPS2552 IN bypass):** C176 100 nF (C14663) added at U28 (Final Check). +- Other notes (N3–N15): symbol graphic of D28, TPS2552 symbol only embedded, HV24 list deviations judged correct, RF class widths are placeholders until the JLC impedance calculator, pre-order C2862740, check DNP/footprints on the board after Update PCB. + +## Per-item table (126 rows, generated by the verifier's `make_report.py`) + +| # | Finding | Ref / net | Intended (§7 + D19) | Found in `05-final.xml` | Result | +|---|---|---|---|---|---| +| I1 | A-01 | D20 | removed | removed | PASS | +| I2 | A-01 | D21 | removed | removed | PASS | +| I3 | A-01 | U20 | 2:/MAIN5V | 2:/MAIN5V | PASS | +| I4 | A-01 | C127 | 1:/MAIN5V | 1:/MAIN5V | PASS | +| I5 | A-01 | C128 | 1:/MAIN5V | 1:/MAIN5V | PASS | +| I6 | A-01 | /VIN_MODEM | net absent | absent | PASS | +| I7 | A-01 | U2 | DNP | DNP | PASS | +| I8 | A-01 | L2 | DNP | DNP | PASS | +| I9 | A-01 | Dbk1 | DNP | DNP | PASS | +| I10 | A-01 | Cbst1 | DNP | DNP | PASS | +| I11 | A-01 | Rcomp1 | DNP | DNP | PASS | +| I12 | A-01 | Ccomp1 | DNP | DNP | PASS | +| I13 | A-01 | Rfreq1 | DNP | DNP | PASS | +| I14 | A-01 | Ren1 | DNP | DNP | PASS | +| I15 | A-01 | Ren2 | DNP | DNP | PASS | +| I16 | A-01 | R20 | DNP | DNP | PASS | +| I17 | A-01 | R21 | DNP | DNP | PASS | +| I18 | A-01 | JP1 | SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm; 1:/5V_FAN 2:/VEH5V | fp ok · 1:/5V_FAN 2:/VEH5V | PASS | +| I19 | A-01 | Q10 | DNP | DNP | PASS | +| I20 | A-01 | DzG1 | DNP | DNP | PASS | +| I21 | A-01 | Rrp1 | DNP | DNP | PASS | +| I22 | A-01 | C10 | DNP | DNP | PASS | +| I23 | A-01 | C11 | DNP | DNP | PASS | +| I24 | A-01 | C22 | DNP | DNP | PASS | +| I25 | A-01/V1-01 | F2 | value ∋ 3A; C206912; Fuseholder_Littelfuse_Nano2_154x; fitted; 1:/24V_IN 2:/VIN_FUSED | LCSC C206912 · val 3A/125V-NANO2-in-holder · fp ok · fitted · 1:/24V_IN 2:/VIN_FUSED | PASS | +| I26 | V1-01 | D10 | C224019; fitted; 1:/VIN_FUSED 2:GND | LCSC C224019 · fitted · 1:/VIN_FUSED 2:GND | PASS | +| I27 | V1-01 | Q23 | fitted; 1:/Q23_GATE 2:/VIN_FUSED 3:/VIN_PROT | fitted · 1:/Q23_GATE 2:/VIN_FUSED 3:/VIN_PROT | PASS | +| I28 | A-03 | R50 | value ∋ 1.43k; C22840; R_0603_1608Metric; 1:/PROG 2:GND | LCSC C22840 · val 1.43k/1% · fp ok · 1:/PROG 2:GND | PASS | +| I29 | B-03 | D28 | value ∋ PESD0402-240; C1975527; D_0402_1005Metric; 1:/RF_ANT_LTE 2:GND | LCSC C1975527 · val PESD0402-240 · fp ok · 1:/RF_ANT_LTE 2:GND | PASS | +| I30 | C-01 | U28 | value ∋ TPS2552; C46506; SOT-23-6; fitted; 1:/3V3_GNSS 2:GND 3:/GNSS_ANT_OFF 4:/GNSS_ANT_SHORT_N 5:/3V3_GNSS 6:/ANT_BIAS | LCSC C46506 · val TPS2552DBVR · fp ok · fitted · 1:/3V3_GNSS 2:GND 3:/GNSS_ANT_OFF 4:/GNSS_ANT_SHORT_N 5:/3V3_GNSS 6:/ANT_BIAS | PASS | +| I31 | C-01 | U18 | 5:/GNSS_ANT_OFF 6:/GNSS_ANT_SHORT_N 7:NC | 5:/GNSS_ANT_OFF 6:/GNSS_ANT_SHORT_N 7:unconnected-(U18-VCC_RF-Pad7) | PASS | +| I32 | C-01 | R135 | value ∋ 100k; C25803; /GNSS_ANT_OFF↔GND | LCSC C25803 · val 100k · {'1': '/GNSS_ANT_OFF', '2': 'GND'} | PASS | +| I33 | C-01 | R136 | value ∋ 10k; C25804; /3V3_GNSS↔/GNSS_ANT_SHORT_N | LCSC C25804 · val 10k · {'1': '/3V3_GNSS', '2': '/GNSS_ANT_SHORT_N'} | PASS | +| I34 | C-01 | L21 | 2:/ANT_BIAS | 2:/ANT_BIAS | PASS | +| I35 | C-01 | C144 | 1:/ANT_BIAS | 1:/ANT_BIAS | PASS | +| I36 | C-01 | C145 | 1:/ANT_BIAS | 1:/ANT_BIAS | PASS | +| I37 | F-02 | D35 | value ∋ SMBJ33A; C224019; D_SMB; fitted; 1:/IGN_IN 2:GND | LCSC C224019 · val SMBJ33A · fp ok · fitted · 1:/IGN_IN 2:GND | PASS | +| I38 | F-02 | Rig1 | value ∋ 22k; C88614; 1:/IGN_IN 2:/IGN_SENSE | LCSC C88614 · val 22k · 1:/IGN_IN 2:/IGN_SENSE | PASS | +| I39 | F-02 | /IGN_IN | = {D35.1, P1.3, Rig1.1} | [('D35', '1'), ('P1', '3'), ('Rig1', '1')] | PASS | +| I40 | H-01 | U15 | C15846; SOIC-16_3.9x9.9mm_P1.27mm | LCSC C15846 · fp ok | PASS | +| I41 | H-02 | U10 | value ∋ 752; C57156 | LCSC C57156 · val SC16IS752IPW | PASS | +| I42 | H-02 | R53 | value ∋ 499k; C177479 | LCSC C177479 · val 499k/1% | PASS | +| I43 | A-04 | R121 | value ∋ 57.6k; C23082; 1:/VEH5V 2:/FB_PWRIN | LCSC C23082 · val 57.6k/1% · 1:/VEH5V 2:/FB_PWRIN | PASS | +| I44 | A-05 | C161 | value ∋ 47; C5440143; C_1210_3225Metric; fitted; 1:/MAIN5V 2:GND | LCSC C5440143 · val 47uF · fp ok · fitted · 1:/MAIN5V 2:GND | PASS | +| I45 | A-05 | C162 | value ∋ 47; C5440143; C_1210_3225Metric; fitted; 1:/MAIN5V 2:GND | LCSC C5440143 · val 47uF · fp ok · fitted · 1:/MAIN5V 2:GND | PASS | +| I46 | A-08 | U17 | value ∋ TLV1117LV33; C15578; 1:GND 2:/3V3 3:/LDO_IN | LCSC C15578 · val TLV1117LV33DCYR · 1:GND 2:/3V3 3:/LDO_IN | PASS | +| I47 | A-09 | C78 | value ∋ 220; C881921; CP_Elec_6.3x7.7; 1:/VEH5V 2:GND | LCSC C881921 · val 220uF/16V polymer · fp ok · 1:/VEH5V 2:GND | PASS | +| I48 | B-02 | C130 | value ∋ 220; C881921; CP_Elec_6.3x7.7; 1:/VBAT_MODEM 2:GND | LCSC C881921 · val 220uF/16V polymer · fp ok · 1:/VBAT_MODEM 2:GND | PASS | +| I49 | B-02 | C131 | value ∋ 220; C881921; CP_Elec_6.3x7.7; 1:/VBAT_MODEM 2:GND | LCSC C881921 · val 220uF/16V polymer · fp ok · 1:/VBAT_MODEM 2:GND | PASS | +| I50 | B-02 | R116 | value ∋ 113k; C22862 | LCSC C22862 · val 113k/1% | PASS | +| I51 | B-02 | C141 | value ∋ 6.8n; C1542; C_0402_1005Metric | LCSC C1542 · val 6.8nF · fp ok | PASS | +| I52 | B-02 | C142 | value ∋ 56p; C1572; C_0402_1005Metric | LCSC C1572 · val 56pF · fp ok | PASS | +| I53 | B-02 | C166 | value ∋ 22u; C86817; C_0805_2012Metric; 1:/VBAT_MODEM 2:GND | LCSC C86817 · val 22uF · fp ok · 1:/VBAT_MODEM 2:GND | PASS | +| I54 | B-02 | C167 | value ∋ 22u; C86817; C_0805_2012Metric; 1:/VBAT_MODEM 2:GND | LCSC C86817 · val 22uF · fp ok · 1:/VBAT_MODEM 2:GND | PASS | +| I55 | F-03 | C163 | value ∋ 22u; C86817; C_0805_2012Metric; 1:/MAIN5V 2:GND | LCSC C86817 · val 22uF · fp ok · 1:/MAIN5V 2:GND | PASS | +| I56 | F-03 | C164 | value ∋ 22u; C86817; C_0805_2012Metric; 1:/MAIN5V 2:GND | LCSC C86817 · val 22uF · fp ok · 1:/MAIN5V 2:GND | PASS | +| I57 | F-03 | C165 | value ∋ 220; C881921; CP_Elec_6.3x7.7; 1:/MAIN5V 2:GND | LCSC C881921 · val 220uF/16V polymer · fp ok · 1:/MAIN5V 2:GND | PASS | +| I58 | F-51 | U29 | value ∋ TMP102; C99269; SOT-563; 1:/I2C_SCL 2:GND 4:GND 5:/3V3 6:/I2C_SDA | LCSC C99269 · val TMP102AIDRLR · fp ok · 1:/I2C_SCL 2:GND 4:GND 5:/3V3 6:/I2C_SDA | PASS | +| I59 | F-51 | C168 | value ∋ 100n; C14663; /3V3↔GND | LCSC C14663 · val 100nF · {'1': '/3V3', '2': 'GND'} | PASS | +| I60 | F-51 | R137 | value ∋ 100k; C25803; /NTC↔/NTC_CELL | LCSC C25803 · val 100k/1% · {'1': '/NTC', '2': '/NTC_CELL'} | PASS | +| I61 | F-51 | R138 | value ∋ 120k; C25808; /NTC_CELL↔GND | LCSC C25808 · val 120k/1% · {'1': '/NTC_CELL', '2': 'GND'} | PASS | +| I62 | F-51 | C169 | value ∋ 10n; C1589; /NTC_CELL↔GND | LCSC C1589 · val 10nF · {'1': '/NTC_CELL', '2': 'GND'} | PASS | +| I63 | F-51 | U16 | 25:/NTC_CELL | 25:/NTC_CELL | PASS | +| I64 | C-02 | U21 | value ∋ TPS7A2033; C2862740; 1:/SW_5V 2:GND 3:/SW_5V 5:/3V3_GNSS | LCSC C2862740 · val TPS7A2033PDBVR · 1:/SW_5V 2:GND 3:/SW_5V 5:/3V3_GNSS | PASS | +| I65 | E-01 | U12 | 2:/ETH_PWR_EN 7:/SYS5V | 2:/ETH_PWR_EN 7:/SYS5V | PASS | +| I66 | E-01 | U16 | 54:/ETH_PWR_EN | 54:/ETH_PWR_EN | PASS | +| I67 | E-01 | R139 | value ∋ 100k; C25803; /ETH_PWR_EN↔GND | LCSC C25803 · val 100k · {'1': '/ETH_PWR_EN', '2': 'GND'} | PASS | +| I68 | E-02 | R140 | value ∋ 4.7k; C23162; R_0603_1608Metric; /ETH_RST↔GND | LCSC C23162 · val 4.7k · fp ok · {'1': '/ETH_RST', '2': 'GND'} | PASS | +| I69 | D-01 | U27 | value ∋ 74LVC1G125; C12518; 1:GND 2:/DOUT_4G 3:GND 4:/DOUT_4G_F9P 5:/3V3_GNSS | LCSC C12518 · val 74LVC1G125GV,125 · 1:GND 2:/DOUT_4G 3:GND 4:/DOUT_4G_F9P 5:/3V3_GNSS | PASS | +| I70 | D-01 | C170 | C14663; /3V3_GNSS↔GND | LCSC C14663 · {'1': '/3V3_GNSS', '2': 'GND'} | PASS | +| I71 | D-01 | U18 | 26:/DOUT_4G_F9P | 26:/DOUT_4G_F9P | PASS | +| I72 | D-01 | /DOUT_4G_F9P | = {U18.26, U27.4} | [('U18', '26'), ('U27', '4')] | PASS | +| I73 | D-01 | Rdfu1 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS | +| I74 | G-02 | U30 | value ∋ USBLC6; C7519; SOT-23-6; 1:/USB_DM 2:GND 3:/USB_DP 4:/USB_DP 5:/USB_VBUS 6:/USB_DM | LCSC C7519 · val USBLC6-2SC6 · fp ok · 1:/USB_DM 2:GND 3:/USB_DP 4:/USB_DP 5:/USB_VBUS 6:/USB_DM | PASS | +| I75 | H-02b | R56 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS | +| I76 | H-02b | R57 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS | +| I77 | H-02b | R58 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS | +| I78 | H-02b | R85 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS | +| I79 | H-02b | R87 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS | +| I80 | H-02b | Rgs1 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS | +| I81 | A-11 | R56 | 1:/CHRG_EN 2:/3V3 | 1:/CHRG_EN 2:/3V3 | PASS | +| I82 | A-13 | R141 | value ∋ 100k; C25803; /3V3↔/PFO | LCSC C25803 · val 100k · {'1': '/3V3', '2': '/PFO'} | PASS | +| I83 | A-13 | /PFO | = {R141.2, TP2.1, U16.29, U6.20} | [('R141', '2'), ('TP2', '1'), ('U16', '29'), ('U6', '20')] | PASS | +| I84 | B-09 | R132 | value ∋ 22; C23345; R_0603_1608Metric | LCSC C23345 · val 22R · fp ok | PASS | +| I85 | B-09 | R133 | value ∋ 22; C23345; R_0603_1608Metric | LCSC C23345 · val 22R · fp ok | PASS | +| I86 | B-09 | R134 | value ∋ 22; C23345; R_0603_1608Metric | LCSC C23345 · val 22R · fp ok | PASS | +| I87 | B-09 | C171 | value ∋ 100n; C1525; C_0402_1005Metric; /SIMB_VDD↔GND | LCSC C1525 · val 100nF · fp ok · {'1': '/SIMB_VDD', '2': 'GND'} | PASS | +| I88 | B-10 | R142 | value ∋ 100k; C25803; /MODEM_STATUS↔GND | LCSC C25803 · val 100k · {'1': '/MODEM_STATUS', '2': 'GND'} | PASS | +| I89 | B-10 | R143 | value ∋ 100k; C25803; /3V3↔/DIN_4G | LCSC C25803 · val 100k · {'1': '/3V3', '2': '/DIN_4G'} | PASS | +| I90 | B-10 | R106 | value ∋ 1k; C14676 | LCSC C14676 · val 1k | PASS | +| I91 | C-07 | TP10 | excl. BOM/pos; 1:/GNSS_SAFEBOOT_N | excl BOM · 1:/GNSS_SAFEBOOT_N | PASS | +| I92 | C-07 | TP11 | excl. BOM/pos; 1:/GNSS_RESET_N | excl BOM · 1:/GNSS_RESET_N | PASS | +| I93 | C-07 | /GNSS_SAFEBOOT_N | = {TP10.1, U18.50} | [('TP10', '1'), ('U18', '50')] | PASS | +| I94 | C-07 | /GNSS_RESET_N | ⊇ {TP11.1, U18.49} | [('R105', '2'), ('TP11', '1'), ('U16', '53'), ('U18', '49')] | PASS | +| I95 | D-02 | Y3 | value ∋ 25; C2901684; Crystal_SMD_3225-4Pin_3.2x2.5mm; 1:/HSE_IN 2:GND 3:/HSE_OUT 4:GND | LCSC C2901684 · val 25MHz · fp ok · 1:/HSE_IN 2:GND 3:/HSE_OUT 4:GND | PASS | +| I96 | D-02 | C113 | value ∋ 12p; C38523 | LCSC C38523 · val 12pF | PASS | +| I97 | D-02 | C114 | value ∋ 12p; C38523 | LCSC C38523 · val 12pF | PASS | +| I98 | D-03 | Y4 | C48615; Crystal_SMD_3215-2Pin_3.2x1.5mm | LCSC C48615 · fp ok | PASS | +| I99 | D-03 | C115 | value ∋ 6.8p; C1679 | LCSC C1679 · val 6.8pF | PASS | +| I100 | D-03 | C116 | value ∋ 6.8p; C1679 | LCSC C1679 · val 6.8pF | PASS | +| I101 | D-05 | Rigb1 | value ∋ 2.2k; C4190 | LCSC C4190 · val 2.2k | PASS | +| I102 | D-09 | R144 | value ∋ 100k; C25803; /BASE_LS↔GND | LCSC C25803 · val 100k · {'1': '/BASE_LS', '2': 'GND'} | PASS | +| I103 | D-12 | TP9 | excl. BOM/pos; 1:/USART1_TX | excl BOM · 1:/USART1_TX | PASS | +| I104 | D-12 | U16 | 42:/USART1_TX | 42:/USART1_TX | PASS | +| I105 | E-03 | Y1 | C14872; Crystal_SMD_HC49-SD | LCSC C14872 · fp ok | PASS | +| I106 | E-03 | C95 | value ∋ 33p; C1663 | LCSC C1663 · val 33pF | PASS | +| I107 | E-03 | C96 | value ∋ 33p; C1663 | LCSC C1663 · val 33pF | PASS | +| I108 | E-04 | C91 | value ∋ 10n; C1589; C_0603_1608Metric; 1:/ETH_1V2 | LCSC C1589 · val 10nF · fp ok · 1:/ETH_1V2 | PASS | +| I109 | E-04 | C90 | value ∋ 4.7u; C1779; C_0805_2012Metric; 1:/ETH_TOCAP | LCSC C1779 · val 4.7uF · fp ok · 1:/ETH_TOCAP | PASS | +| I110 | E-04 | C172 | value ∋ 100n; C14663; /3V3_ETH↔GND | LCSC C14663 · val 100nF · {'1': '/3V3_ETH', '2': 'GND'} | PASS | +| I111 | E-04 | C173 | value ∋ 100n; C14663; /3V3_ETH↔GND | LCSC C14663 · val 100nF · {'1': '/3V3_ETH', '2': 'GND'} | PASS | +| I112 | F-52 | U31 | value ∋ TMP102; C99269; SOT-563; 1:/I2C_SCL 2:GND 4:/3V3 5:/3V3 6:/I2C_SDA | LCSC C99269 · val TMP102AIDRLR · fp ok · 1:/I2C_SCL 2:GND 4:/3V3 5:/3V3 6:/I2C_SDA | PASS | +| I113 | G-03 | P11 | C5160226; PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal; fitted | LCSC C5160226 · fp ok · fitted | PASS | +| I114 | G-03 | P12 | C5160226; PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal; fitted | LCSC C5160226 · fp ok · fitted | PASS | +| I115 | G-03 | J10 | C12074; RJ45_Hanrun_HR911105A_Horizontal; fitted | LCSC C12074 · fp ok · fitted | PASS | +| I116 | G-04 | JP6 | SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm; excl. BOM/pos; /MAIN5V↔/SYS5V | fp ok · excl BOM · {'1': '/MAIN5V', '2': '/SYS5V'} | PASS | +| I117 | G-08 | D36 | value ∋ PESD5V0S1BA; C2827694; D_SOD-323; 1:/NRST 2:GND | LCSC C2827694 · val PESD5V0S1BA · fp ok · 1:/NRST 2:GND | PASS | +| I118 | G-08 | D37 | value ∋ PESD5V0S1BA; C2827694; D_SOD-323; 1:/NTC_TEMP 2:GND | LCSC C2827694 · val PESD5V0S1BA · fp ok · 1:/NTC_TEMP 2:GND | PASS | +| I119 | G-08 | D38 | value ∋ PESD5V0S1BA; C2827694; D_SOD-323; 1:/NTC2 2:GND | LCSC C2827694 · val PESD5V0S1BA · fp ok · 1:/NTC2 2:GND | PASS | +| I120 | G-08 | /NRST | ⊇ {P6.1} | [('C104', '1'), ('D36', '1'), ('P6', '1'), ('SW1', '1'), ('TP5', '1'), ('U16', '7')] | PASS | +| I121 | G-08 | /NTC_TEMP | ⊇ {P7.1} | [('C24', '1'), ('D37', '1'), ('P7', '1'), ('R42', '2'), ('U16', '27')] | PASS | +| I122 | G-08 | /NTC2 | ⊇ {P8.1} | [('C157', '1'), ('D38', '1'), ('P8', '1'), ('R126', '2'), ('U16', '24')] | PASS | +| I123 | H-08 | C22 | value ∋ 10uF/50V | val 10uF/50V | PASS | +| I124 | H-08 | Y2 | value ∋ 3.6864MHz | val 3.6864MHz | PASS | +| I125 | B-15 | R107 | value ∋ NEVER; DNP | val 0R-NEVER-FIT · DNP | PASS | +| I126 | B-15 | R108 | value ∋ NEVER; DNP | val 0R-NEVER-FIT · DNP | PASS | diff --git a/03-Architecture-Hardware/2026-09-29_Drogheda_EinarBoard-v6_Proximos-Pasos-Pedido_v1.0.md b/03-Architecture-Hardware/2026-09-29_Drogheda_EinarBoard-v6_Proximos-Pasos-Pedido_v1.0.md new file mode 100644 index 0000000..92d8d4e --- /dev/null +++ b/03-Architecture-Hardware/2026-09-29_Drogheda_EinarBoard-v6_Proximos-Pasos-Pedido_v1.0.md @@ -0,0 +1,184 @@ +--- +title: "EinarBoard v6 — Próximos pasos para ordenar (29-sep-2026)" +tags: [project-drogheda, hardware, hbox, v6, pcb, pedido, jlcpcb, proximos-pasos] +project: Project Drogheda +author: Helgen Technologies +date: 2026-09-29 +version: 1.0 +status: ACTIVO — camino crítico al pedido de v6 +audience: Leo, Michelle (layout), compras +--- + +# EinarBoard v6 — Próximos pasos para ordenar (29-sep-2026) + +!!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide" + Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios. + +Esta página es la versión corta: **qué falta, en qué orden, quién lo hace y cuánto tarda**. Las cifras de cada paso +(anchos, distancias, número de vías, piezas) están en el [Plan de corrección y estado](v6-plan-correccion.md). + +!!! danger "Hoy todavía no se puede ordenar: el PCB no tiene ninguna corrección" + - **Esquemático: listo y verificado** (`d58a89ba…e7b`, ERC 0 errores). Todos los puertos revisados de punta a punta. + - **PCB: sin actualizar.** `hbox-watchdog-v6.kicad_pcb` sigue igual que el 28-sep a las 11:36 (`6ddec80d…`). No se ha + hecho *Actualizar PCB desde esquemático* ni el layout de las correcciones. + - Si se ordena así, la tarjeta sale con los 11 Blockers: rama de 24 V sin fusible, ignición a 0.22 mm de 5 V en + capa interna (la geometría del corto del 23-jul), RS-232 imposible de soldar, cargador LTC4040 sin disipar, + JP2 en Li-ion con paquete LFP, entre otros. Eso obliga a otra versión, que es justo lo que no queremos. + - **Fecha realista de pedido: viernes 2-oct** si Michelle trabaja en esto desde hoy (jueves 1-oct si todo sale a la + primera). Son estimaciones; el detalle está en la tabla de abajo. + +--- + +## 1. Camino crítico + +| # | Paso | Quién | Tiempo estimado | Listo cuando | +|---|---|---|---|---| +| 1 | [Subir los cambios de v6 a git y publicar el sitio](#paso-1-leo-subir-a-git-y-publicar-hoy) | Leo | 15 min | Michelle hace `git pull` y ve el esquemático `d58a89ba…` | +| 2 | [Pre-órdenes y compras](#paso-2-compras-hoy-en-paralelo) (en paralelo) | Leo / compras | 30 min hoy; las piezas pre-ordenadas suelen tardar unos días hábiles en quedar disponibles en JLC | THVD1410DR, TPS7A2033PDBVR y J14 en «Pre-ordered» de la cuenta | +| 3 | [Actualizar el PCB y colocar las piezas nuevas](#paso-3-michelle-actualizar-el-pcb) | Michelle | 3–4 h | Paso 0 de su lista cerrado | +| 4 | [Layout de las correcciones](#paso-4-michelle-layout-en-este-orden) | Michelle | 2–2.5 días | Lista L-1…L-67 cerrada | +| 5 | [Rellenar zonas y DRC](#paso-5-michelle-drc-la-puerta-de-salida) | Michelle | 2–4 h | **0 errores de separación**, 0 sin conectar | +| 6 | [Re-auditoría del PCB](#paso-6-claude-re-auditoria-del-pcb) | Claude | 1–2 h después del push | GO por escrito en este sitio | +| 7 | [Archivos y pedido](#paso-7-leo-archivos-y-pedido) | Leo | 1 h | Pedido en JLC | + +El paso 1 bloquea todo lo demás: **sin él, Michelle no puede traer el esquemático corregido.** +El paso 2 no depende de nadie y es lo que más tarda en llegar, así que conviene hacerlo hoy. + +--- + +## Paso 1 — Leo: subir a git y publicar (hoy) + +Los cambios de v6 de la noche del 28-sep **no están en ningún commit**: el último commit de `HBox_PCB` es de la V5.6 +(`b1e1677`), y el sitio se publicó antes de que existieran las páginas de v6. Los comandos, en este orden: + +```bash +# 1) Repo de KiCad (HBox_PCB): solo los archivos de v6 +cd ~/Documents/Claude/Projects/Drogheda/03-Architecture-Hardware/kicad +git add hbox-watchdog-v6.kicad_sch hbox-watchdog-v6.kicad_pro hbox-watchdog-v6.kicad_dru \ + Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod +git commit -m "v6: correcciones de auditoría, puertos, revisión final y estrapes LFP (sch d58a89ba)" +git push helgen main + +# 2) Sitio (hbox-docs) +cd ../../hbox-docs +git status +git add -A && git commit -m "v6: próximos pasos, plan de corrección, cambios, puertos, revisión final, auditoría EN" +git push + +# 3) Repo padre (Drogheda): fuentes, PDF del esquemático y los dos submódulos +cd .. +git add 03-Architecture-Hardware/2026-09-2*_Drogheda_EinarBoard-v6_*.md 03-Architecture-Hardware/pinmap-v6.md \ + 03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf 03-Architecture-Hardware/2026-09-28_v6-audit-attachments \ + 03-Architecture-Hardware/kicad hbox-docs +git -c diff.ignoreSubmodules=none commit -m "v6: auditoría, correcciones de esquemático y próximos pasos (fuentes + gitlinks)" +git push helgen main + +# 4) Publicar el sitio +cd hbox-docs && ./scripts/deploy.sh +``` + +Después, avisar a Michelle con la liga a esta página. + +--- + +## Paso 2 — Compras hoy, en paralelo + +- [ ] **Pre-órdenes en la cuenta de JLC** (categoría «Pre-ordered»; sin esto JLC no las coloca): + **THVD1410DR (C2671345)**, **TPS7A2033PDBVR (C2862740)** y **J14 (C2977286)**. + Si el pedido llega a ≳ 100 tarjetas: pre-ordenar también U18 (ZED-F9P) y U19 (A7670SA). +- [ ] **Conectores hembra de P11/P12:** DEGSON **15EDGK-3.5-03P, 2 por tarjeta** (no van en el BOM de la tarjeta). +- [ ] **Paquete de respaldo para las pruebas:** LFP-HT 26650 4P con NTC 10 k **B3380**, el mismo de V5.6. +- [ ] **Cotizar el PCB** para tener costo y tiempo listos: 4 capas, 1.6 mm, **JLC04161H-7628 con control de impedancia**, + **ENIG**, **cobre interno 1 oz**, rayos X en U18/U19, vías tapadas bajo U18/U19. +- [ ] **Cantidad:** 20 prototipos (decisión D14 del plan). + +--- + +## Paso 3 — Michelle: actualizar el PCB + +Detalle completo: [paso 0 de la lista de Michelle](v6-plan-correccion.md#5-lista-de-trabajo-de-michelle-layout). + +1. `git pull` en `HBox_PCB`. Si KiCad tenía la v6 abierta, **cerrar sin guardar** antes del pull. +2. Abrir `hbox-watchdog-v6` y correr *Herramientas → Actualizar PCB desde esquemático* con + **«Eliminar huellas sin símbolo»** marcado (así desaparecen D20 y D21) y reemplazando las huellas que cambiaron: + U15 (SOIC-16 angosto), D28 (0402), Y3 (3225 de 4 pads), JP1 (Bridged), **JP2 (Bridged23, LFP)**, J10/P11/P12 (ya + poblados), L2/L6/L8/L20 (`Drogheda-v6:IND-SMD_MWSA0804S`). +3. Colocar las **46 piezas nuevas** junto a su bloque. La lista con su lugar está en el + [resumen de cambios](v6-cambios-resumen.md). +4. Revisar que queden **35 piezas DNP**, y que U25 ya no tenga el campo `LCSC Part` (refrescar su huella desde la librería). + +--- + +## Paso 4 — Michelle: layout, en este orden + +Los números L-x son los de la [lista de trabajo](v6-plan-correccion.md#5-lista-de-trabajo-de-michelle-layout), +donde está cada cifra. El orden va de lo que más riesgo tiene a lo que menos. + +| Orden | Bloque de la lista | Pasos | Por qué va en este lugar | Tiempo estimado | +|---|---|---|---|---| +| 1 | A · Reglas DRC y stackup | L-1…L-4 | Sin esto el DRC no ve los errores de 24 V | 0.5 h | +| 2 | B · Entrada de 24 V e ignición | L-5…L-10, L-62 | Seguridad: fusible primero, rama sin fusible fuera, ignición lejos de 5 V (corto del 23-jul) | 2 h | +| 3 | C · Cargador LTC4040 e inductores | L-11…L-19, L-53/L-63, **L-67** | Lección F5 (cargador caliente, carga lenta) y **JP2 en LFP** (si no, sobrecarga a 4.00 V) | 4 h | +| 4 | D · Reguladores conmutados | L-20…L-23 | Lazos calientes y vías en los pads térmicos | 2 h | +| 5 | E + F · Módem, RF y GNSS | L-30…L-36, L-54, L-55, L-65, L-33, L-64, L-34 | Líneas RF a 50 Ω, módem estable en batería, antena GNSS protegida | 4 h | +| 6 | I · Tierras y vías | L-24…L-29, L-35 | Que el LTE no desensibilice al GNSS; disipación del módem y del F9P | 3 h | +| 7 | G + H · Puertos, cristales y Ethernet | L-49…L-52, L-56, L-57, L-39, L-44, L-66, L-47 | **Todos los puertos funcionan** (RS-485, RS-232, Ethernet) | 3 h | +| 8 | J · Conectores y barrenos | L-40…L-43, L-58 | Que entre en la placa base de la V5.5 (MH4 y abrazadera) y los USB | 2 h | +| 9 | K · Serigrafía | L-46, L-59 | Legible para ensamble y campo | 1.5 h | +| 10 | L · Cierre | L-47, L-60, L-61 | Atributos de huella y fiduciales | 1 h | + +**Total estimado: 23 h de layout**, más el DRC del paso 5. + +!!! tip "Cómo acelerar sin saltarse nada" + - **Subir avances a git** después de los bloques B y C (y después de E + F). Claude revisa cada avance mientras + Michelle sigue con el siguiente bloque. Así los errores salen el mismo día y la re-auditoría final es corta. + - **No repartir el mismo archivo `.kicad_pcb` entre dos personas.** KiCad no combina bien dos ediciones del PCB. + - Dejar la serigrafía (bloque K) para el final: es lo único que se puede hacer rápido. + +--- + +## Paso 5 — Michelle: DRC, la puerta de salida + +- [ ] Rellenar **todas** las zonas. +- [ ] DRC con las reglas nuevas (ya están en `.kicad_dru`): **0 errores de separación**, **0 sin conectar**. +- [ ] Cerrar la aceptación completa de **L-48** (en la lista de Michelle). +- [ ] `git push` del PCB. + +--- + +## Paso 6 — Claude: re-auditoría del PCB + +Con el PCB subido, Claude revisa (1–2 h): + +- esquemático ↔ PCB sincronizados: 46 piezas nuevas colocadas, 28 DNP, huellas correctas; +- las medidas de cada Blocker: ignición y 24 V a ≥ 0.5 mm en capas internas, `/SW_BAT` ≥ 2 mm, 9 vías en el pad de U6, + vías bajo U18/U19, impedancia de las líneas RF, MH4 en su lugar, **JP2 puenteado 2-3**, U25 sin `LCSC Part`; +- DRC propio con las reglas nuevas. + +El resultado se publica aquí como **GO / NO-GO** con la lista de lo que falte. + +--- + +## Paso 7 — Leo: archivos y pedido + +- [ ] BOM y CPL con **Fabrication Toolkit**. Revisar que la línea de U25 diga **C524806 (TPS54360B)**, y que TP1–TP12 y + JP1–JP6 no aparezcan. +- [ ] Opciones del PCB como en la cotización del paso 2 (stackup con control de impedancia, ENIG, 1 oz interno, rayos X, + vías tapadas). +- [ ] Revisar rotaciones en la vista previa de JLC y el stock en el carrito. +- [ ] Ordenar **20 prototipos**. + +--- + +## Lo que NO detiene el pedido + +- **Firmware 0.7.x (`board_v6.h`):** hace falta para probar las tarjetas, no para ordenarlas. Se puede empezar hoy con + la [sección 6 del plan](v6-plan-correccion.md) y el [mapa de pines](v6-pinmap.md). +- **Lo aceptado permanentemente** (20 puntos, sección 9 del plan): ya está decidido y documentado. + +## Ligas + +- [Plan de corrección y estado](v6-plan-correccion.md): decisiones, estado por hallazgo, puertos, lista completa de + Michelle con cifras, lista de liberación (GO). +- [Cambios de esquemático: resumen de las 4 pasadas](v6-cambios-resumen.md): qué cambió y dónde van las piezas nuevas. +- [Mapa de pines MCU v6](v6-pinmap.md) · [Auditoría completa](v6-auditoria-completa.md) ([inglés](v6-full-audit.md)). diff --git a/03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf b/03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf index 5244dabe65f7831eff1473467e507825e8453d54..b3af26a1c36039265768f5ff0cc634048e83847b 100644 GIT binary patch delta 146672 zcma&NWmq1u)-H?|D-MNHq&O6Z;$Ga{-HJB+LVY# zEoR}QeQQxejH)|x9fqYgRA9|8Q<#EfBAJTXy+wm#2;hf+5k&hL%QV&Y_38Z?@P57f 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