v6 T11 accelerometer (submodule 23ed361) + T11 script
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
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Subproject commit 83ed72e2d63ef357640189df993fd8765a87f543
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Subproject commit 23ed361f0d1bbb72e6ba2978d9f0834dae5c9e79
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scripts/2026-09-01_v6_T11_accel.py
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scripts/2026-09-01_v6_T11_accel.py
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#!/usr/bin/env python3
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"""v6 T11 - Block U: SC7A20TR 3-axis accelerometer (vibration telemetry).
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U26 SC7A20TR (Silan, LGA-12 2x2, LCSC C5126709, ~$0.25; register-compatible with ST
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LIS3DH driver). I2C mode on the existing bus: CS->3V3, SDO/SA0->GND (addr 0x18 - no
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clash: SHT40 0x44, PCF8574 0x20+). INT1 -> /ACC_INT1 -> U16 PB9 (pin 62, EXTI9).
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INT2 left NC. Decoupling 100nF x2 + 10uF.
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Pin mapping is resolved FROM THE VENDOR SYMBOL'S PIN NAMES (Drogheda-v6.kicad_sym,
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easyeda2kicad C5126709) and asserted - nothing is guessed by pin number. Review the
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printed pin->net table in the dry run before --apply.
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Prereq on the Mac:
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easyeda2kicad --full --lcsc_id C5126709 --output ~/Documents/Claude/Projects/Drogheda/03-Architecture-Hardware/kicad/Drogheda-v6
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Usage: python3 2026-09-01_v6_T11_accel.py [--apply]
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"""
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import os, sys, shutil, uuid, re, glob
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KI = os.path.join(os.path.dirname(os.path.abspath(__file__)), '..', '03-Architecture-Hardware', 'kicad')
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SCH = os.path.join(KI, 'hbox-watchdog-v6.kicad_sch')
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VSYM= os.path.join(KI, 'Drogheda-v6.kicad_sym')
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APPLY = '--apply' in sys.argv
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ROOT = '/561403b3-895e-4153-a7be-3876ae930d43'
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NC = '<NC>'
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def f(v):
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v = 0.0 if abs(v) < 1e-9 else v
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return '%.10g' % v
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def bal(t):
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d=0; instr=False; esc=False
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for ch in t:
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if esc: esc=False; continue
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if ch=='\\': esc=True; continue
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if ch=='"': instr = not instr; continue
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if instr: continue
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if ch=='(': d+=1
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elif ch==')': d-=1
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return d
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def span_from(text, i):
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d=0; instr=False; esc=False; j=i
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while j < len(text):
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ch=text[j]
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if esc: esc=False
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elif ch=='\\': esc=True
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elif ch=='"': instr = not instr
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elif not instr:
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if ch=='(': d+=1
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elif ch==')':
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d-=1
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if d==0: return j+1
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j+=1
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raise ValueError('unbalanced')
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# pin extractor that also captures the pin NAME
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PIN_NAMED = re.compile(r'\(pin \w+ \w+\s*\n\s*\(at ([-\d.]+) ([-\d.]+) (\d+)\)(?:(?!\(pin ).)*?'
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r'\(name "([^"]*)"(?:(?!\(pin ).)*?\(number "([^"]+)"', re.S)
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def libpins_named(libsrc, name):
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i = libsrc.find('(symbol "%s"' % name)
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if i < 0: return None
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j = libsrc.find('\n (symbol "', i+10)
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if j < 0: j = libsrc.find('\n\t\t(symbol "', i+10)
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body = libsrc[i: j if j>0 else len(libsrc)]
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return [(num, nm, float(x), float(y)) for x,y,rot,nm,num in PIN_NAMED.findall(body)]
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sch = open(SCH, encoding='utf-8').read()
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vsym = open(VSYM, encoding='utf-8').read()
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uuids_before = set(re.findall(r'\(uuid "([0-9a-f-]+)"\)', sch))
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# ---------- 1. find the vendor symbol + footprint ----------
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symname = None
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for m in re.finditer(r'\(symbol "((?:SC7A20|Sc7a20)[^"]*)"', vsym):
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symname = m.group(1); break
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if not symname:
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sys.exit('SC7A20 symbol not found in Drogheda-v6.kicad_sym - run on the Mac first:\n'
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' easyeda2kicad --full --lcsc_id C5126709 --output ~/Documents/Claude/Projects/Drogheda/03-Architecture-Hardware/kicad/Drogheda-v6')
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fp_hits = [p for p in glob.glob(os.path.join(KI,'Drogheda-v6.pretty','*.kicad_mod'))
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if re.search(r'LGA-12_L2|SC7A20', os.path.basename(p), re.I)]
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if not fp_hits:
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sys.exit('SC7A20 LGA-12 footprint not found in Drogheda-v6.pretty - run easyeda2kicad C5126709 first')
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u26_fp = 'Drogheda-v6:' + os.path.basename(fp_hits[0])[:-len('.kicad_mod')]
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pins = libpins_named(vsym, symname)
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if not pins or len(pins) < 10:
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sys.exit('pin extraction failed for %s: got %s' % (symname, pins))
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# ---------- 2. map pins to nets BY NAME ----------
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RULES = [(r'^VDD_?IO$','3V3'), (r'^VDD$','3V3'),
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(r'^(GND|RES|RESERVED)',' GND'.strip()),
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(r'(SDO.*SA0|SA0.*SDO|^SDO$|^SA0$)','GND'), # addr select -> 0x18 (before SDA rule)
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(r'(SCL|SPC|^SCX$)','I2C_SCL'),
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(r'(SDA|SDI|^SDX$)','I2C_SDA'),
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(r'^CS','3V3'),
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(r'INT_?1','ACC_INT1'), (r'INT_?2',NC),
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(r'^(NC|N\.C\.?)$',NC)]
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mapping = {}
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for num, nm, px, py in pins:
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nmu = nm.upper().replace('~','').strip()
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net = None
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for pat, tgt in RULES:
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if re.search(pat, nmu):
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net = tgt; break
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if net is None: sys.exit('unmapped pin: number %s name %r - extend RULES' % (num, nm))
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mapping[num] = (nm, net, px, py)
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print('U26 %s (fp %s) pin -> net:' % (symname, u26_fp))
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for num in sorted(mapping, key=lambda n: int(re.sub(r'\D','',n) or 0)):
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nm, net, _, _ = mapping[num]
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print(' %3s %-12s -> %s' % (num, nm, net))
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nets_used = [net for _,(nm,net,_,_) in mapping.items()]
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for req, cnt in (('I2C_SCL',1),('I2C_SDA',1),('ACC_INT1',1)):
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assert nets_used.count(req) == cnt, 'expected exactly %d %s pin, got %d' % (cnt, req, nets_used.count(req))
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assert nets_used.count('3V3') >= 2, 'expected VDD+VDDIO/CS on 3V3'
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# ---------- 3. guards ----------
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for r in ('U26','C158','C159','C160'):
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if '(property "Reference" "%s"' % r in sch: sys.exit('refdes %s already used' % r)
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lib_cached = sch.split('(lib_symbols',1)[1]
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PIN_RE2= re.compile(r'\(pin \w+ \w+\s*\n\s*\(at ([-\d.]+) ([-\d.]+) (\d+)\)(?:(?!\(pin ).)*?\(number "([^"]+)"', re.S)
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def cachedpins(name):
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i = lib_cached.find('(symbol "%s"' % name)
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if i < 0: return None
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j = lib_cached.find('\n\t\t(symbol "', i+10)
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body = lib_cached[i: j if j>0 else len(lib_cached)]
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return [(num, float(x), float(y)) for x,y,rot,num in PIN_RE2.findall(body)]
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# U16 PB9 = pin 62: coords + existing NC
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u16 = None
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for b in re.finditer(r'\n\t\(symbol\n(?:(?!\n\t\(symbol\n).)*', sch, re.S):
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blk=b.group(0)
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if '(property "Reference" "U16"' in blk:
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l=re.search(r'\(lib_id "([^"]+)"',blk).group(1)
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a=re.search(r'\(at ([-\d.]+) ([-\d.]+) (\d+)\)',blk)
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assert a.group(3)=='0' and '(mirror' not in blk[:400]
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u16=(l,float(a.group(1)),float(a.group(2))); break
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assert u16, 'U16 not found'
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pb9 = [(px,py) for num,px,py in cachedpins(u16[0]) if num=='62']
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assert len(pb9)==1, 'U16 pin 62 (PB9) not found'
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PB9 = (round(u16[1]+pb9[0][0],3), round(u16[2]-pb9[0][1],3))
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print('PB9 sheet coord:', PB9)
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# ---------- 4. cache vendor symbol into schematic ----------
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def grab(libsrc, name, prefix):
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i = libsrc.find(' (symbol "%s"\n' % name)
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if i < 0: sys.exit('symbol %s not found for caching' % name)
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j = libsrc.index('(', i)
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k = span_from(libsrc, j)
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return libsrc[j:k].replace('(symbol "%s"' % name, '(symbol "%s:%s"' % (prefix,name), 1)
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if '(symbol "Drogheda-v6:%s"' % symname not in sch:
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m = re.search(r'\n\t\(lib_symbols\n', sch)
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k = span_from(sch, sch.index('(', m.start()))
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sch = sch[:k-1] + '\n\t\t' + grab(vsym, symname, 'Drogheda-v6') + '\n\t' + sch[k-1:]
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lib_cached = sch.split('(lib_symbols',1)[1]
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# ---------- 5. build additions ----------
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add = ''
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newlabels=[]; nnc=0
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def add_lab(net,x,y,rot,just):
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global add
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add += ('\n\t(label "%s"\n\t\t(at %s %s %d)\n\t\t(effects\n\t\t\t(font\n\t\t\t\t(size 1.27 1.27)\n'
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'\t\t\t)\n\t\t\t(justify %s)\n\t\t)\n\t\t(uuid "%s")\n\t)') % (net,f(x),f(y),rot,just,uuid.uuid4())
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newlabels.append((net,round(x,3),round(y,3)))
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def add_nc(x,y):
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global add,nnc
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add += '\n\t(no_connect\n\t\t(at %s %s)\n\t\t(uuid "%s")\n\t)' % (f(x),f(y),uuid.uuid4())
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nnc += 1
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def mksym(lib_id, ref, val, x, y, fp, npins, lcsc=''):
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props=[('Reference',ref,x-3,y-3,''),('Value',val,x+3,y-3,''),('Footprint',fp,x,y,'\n\t\t\t(hide yes)'),
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('Datasheet','~',x,y,'\n\t\t\t(hide yes)'),('Description','',x,y,'\n\t\t\t(hide yes)')]
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if lcsc: props.append(('LCSC',lcsc,x,y,'\n\t\t\t(hide yes)'))
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p=''
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for nm,v,px,py,hide in props:
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p += ('\t\t(property "%s" "%s"\n\t\t\t(at %s %s 0)%s\n\t\t\t(show_name no)\n\t\t\t(do_not_autoplace no)\n'
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'\t\t\t(effects\n\t\t\t\t(font\n\t\t\t\t\t(size 1.27 1.27)\n\t\t\t\t)\n\t\t\t)\n\t\t)\n') % (nm,v,f(px),f(py),hide)
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pn=''.join('\t\t(pin "%s"\n\t\t\t(uuid "%s")\n\t\t)\n' % (n,uuid.uuid4()) for n in npins)
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return ('\n\t(symbol\n\t\t(lib_id "%s")\n\t\t(at %s %s 0)\n\t\t(unit 1)\n\t\t(body_style 1)\n'
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'\t\t(exclude_from_sim no)\n\t\t(in_bom yes)\n\t\t(on_board yes)\n\t\t(in_pos_files yes)\n'
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'\t\t(dnp no)\n\t\t(uuid "%s")\n%s%s\t\t(instances\n\t\t\t(project "hbox-watchdog-v6"\n'
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'\t\t\t\t(path "%s"\n\t\t\t\t\t(reference "%s")\n\t\t\t\t\t(unit 1)\n\t\t\t\t)\n\t\t\t)\n\t\t)\n\t)'
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) % (lib_id,f(x),f(y),uuid.uuid4(),p,pn,ROOT,ref)
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def orient(px,py):
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if abs(px) < 0.01: return 90,'left bottom'
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return (0,'left bottom') if px>0 else (180,'right bottom')
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add += ('\n\t(text "BLOCK U - VIBRATION (T11): U26 SC7A20 3-axis accel, I2C addr 0x18 '
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'(CS=3V3, SA0=GND), INT1 -> PB9. LAYOUT: place near a mounting hole for rigid '
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'chassis coupling; not on a flexy board edge."\n'
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'\t\t(exclude_from_sim no)\n\t\t(at 40 390 0)\n\t\t(effects\n\t\t\t(font\n\t\t\t\t(size 1.6 1.6)\n'
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'\t\t\t)\n\t\t\t(justify left bottom)\n\t\t)\n\t\t(uuid "%s")\n\t)') % uuid.uuid4()
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U26X,U26Y = 60.0, 408.0
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add += mksym('Drogheda-v6:%s'%symname,'U26','SC7A20TR',U26X,U26Y,u26_fp,
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[num for num,_,_,_ in pins],'C5126709')
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for num,(nm,net,px,py) in mapping.items():
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rot,just = orient(px,py)
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x,y = U26X+px, U26Y-py
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if net==NC: add_nc(x,y)
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else: add_lab(net,x,y,rot,just)
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for ref,val,fp,x,y,n1,n2 in (
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('C158','100nF','Capacitor_SMD:C_0402_1005Metric',85.0,404.0,'3V3','GND'),
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('C159','100nF','Capacitor_SMD:C_0402_1005Metric',91.0,404.0,'3V3','GND'),
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('C160','10uF','Capacitor_SMD:C_0805_2012Metric',97.0,404.0,'3V3','GND')):
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pp={num:(px,py) for num,px,py in cachedpins('Device:C')}
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add += mksym('Device:C',ref,val,x,y,fp,['1','2'])
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add_lab(n1,x+pp['1'][0],y-pp['1'][1],90,'left bottom')
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add_lab(n2,x+pp['2'][0],y-pp['2'][1],90,'left bottom')
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# PB9 label + stale NC removal
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add_lab('ACC_INT1', PB9[0], PB9[1], 0, 'left bottom')
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out=[]; last=0; pb9_nc=0
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for m in re.finditer(r'\n\t\(no_connect\s*\n\s*\(at ([-\d.]+) ([-\d.]+)\)(?:(?!\n\t\().)*?\n\t\)', sch, re.S):
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c=(round(float(m.group(1)),3),round(float(m.group(2)),3))
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if c == PB9:
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out.append(sch[last:m.start()]); last=m.end(); pb9_nc+=1
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out.append(sch[last:]); sch=''.join(out)
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# ---------- 6. collision check ----------
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labs=set()
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for m in re.finditer(r'\n\t\((label|global_label) "[^"]+"\s*\n\s*\(at ([-\d.]+) ([-\d.]+)', sch):
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labs.add((round(float(m.group(2)),3), round(float(m.group(3)),3)))
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wire_vts=set()
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for m in re.finditer(r'\(wire\s*\n\s*\(pts\s*\n((?:\s*\(xy [-\d.]+ [-\d.]+\)\s*\n?)+)', sch):
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for a,b in re.findall(r'\(xy ([-\d.]+) ([-\d.]+)\)', m.group(1)):
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wire_vts.add((round(float(a),3), round(float(b),3)))
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pin_coords=set()
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for b in re.finditer(r'\n\t\(symbol\n(?:(?!\n\t\(symbol\n).)*', sch, re.S):
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blk=b.group(0)
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ll=re.search(r'\(lib_id "([^"]+)"',blk); aa=re.search(r'\(at ([-\d.]+) ([-\d.]+) (\d+)\)',blk)
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if ll and aa:
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for num,px,py in (cachedpins(ll.group(1)) or []):
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pin_coords.add((round(float(aa.group(1))+px,3), round(float(aa.group(2))-py,3)))
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INTENTIONAL = {PB9}
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existing = (labs | wire_vts | pin_coords) - INTENTIONAL
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coll = [(n,x,y) for n,x,y in newlabels if (x,y) in existing]
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if coll: sys.exit('LABEL COLLISION: %s' % coll[:8])
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end = sch.rstrip(); assert end.endswith(')')
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sch = end[:-1].rstrip('\n') + add + '\n)\n'
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lost = uuids_before - set(re.findall(r'\(uuid "([0-9a-f-]+)"\)', sch))
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if len(lost) > pb9_nc: sys.exit('REFUSING: %d unexpected pre-existing UUIDs vanished' % len(lost))
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print('added: U26 + C158/C159/C160; labels %d, NCs %d; PB9 label placed, stale NC removed: %d'
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% (len(newlabels), nnc, pb9_nc))
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print('paren: %d' % bal(sch))
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if not APPLY:
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print('\nDRY RUN - review the pin->net table above, then re-run with --apply.'); sys.exit(0)
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if bal(sch)!=0: sys.exit('REFUSING: paren imbalance')
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shutil.copy2(SCH,SCH+'.T11bak')
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open(SCH,'w',encoding='utf-8').write(sch)
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print('\nAPPLIED. Backup: .T11bak')
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