diff --git a/03-Architecture-Hardware/2026-07-24_Drogheda_EinarBoard-1.1_Design-Brief_v1.0.md b/03-Architecture-Hardware/2026-07-24_Drogheda_EinarBoard-1.1_Design-Brief_v1.0.md new file mode 100644 index 0000000..668b514 --- /dev/null +++ b/03-Architecture-Hardware/2026-07-24_Drogheda_EinarBoard-1.1_Design-Brief_v1.0.md @@ -0,0 +1,181 @@ +--- +title: EinarBoard 1.1 — Design Brief & Execution Prompt +tags: [project-drogheda, hardware, einarboard, respin, ethernet, rs485, design-brief, prompt] +project: Project Drogheda +author: Helgen CTO + Claude (decisions locked 2026-07-24) +date: 2026-07-24 +status: Active — THE prompt for the 1.1 design sessions. Read this first, then execute the phases in §9. +authority: supplements [[watchdog-electrical-design-state]] (canonical) + [[watchdog-production-schematic-delta]]; where they conflict on 1.1 scope, THIS file wins. +--- + +# EinarBoard 1.1 — Design Brief ("the prompt") + +> **How to use this doc.** This is the self-contained instruction set for turning +> `hbox-watchdog-v3-PROD` (EinarBoard 1.0, as-fabbed, errata E-J1/E-CLR/E-PFI) into +> **EinarBoard 1.1**. A design session (human or Claude) should be able to start from this +> file alone. Standing rules: **file-level KiCad edits only** (the KiCad MCP backend +> corrupted disk state on 2026-07-24 — see [[drogheda-respin-status]]); git checkpoint +> after every phase; verify every structural edit with an independent parse; bench gates +> unchanged (nothing fabs without the LTC4040 backup + charge-cutoff validation). + +## 0. Decisions locked 2026-07-24 (Leo) + +| Topic | Decision | +|---|---| +| Customer external comms | **RS-485/Modbus RTU AND RS-232/TTL** — one SC16IS752 dual-UART bridge serves both | +| Ethernet | **On-board W5500 + MagJack**, hardware TCP/IP, SPI2 | +| External indicators | **1 RGB status LED** (color-coded states), expander-driven | +| Board outline | **Grow as needed**; ASA case/plate reprinted around the new outline | + +Bench context driving this: board 1.0 is alive on the bench via the external J1 inverter +adapter; battery-gauge LEDs dark = **firmware** (v2.3 never drives PB12–15 — review F3), +fan off on a cool bench = **correct** (curve starts 45–48 °C). Neither is a 1.0 hardware bug. + +## 1. The keystone architectural move (read this before touching anything) + +The F411 has no third USART, no CAN, no Ethernet MAC, and as-built the board has ~6 free +GPIO. Everything new hangs off two buses we already have: + +**Move the battery gauge (PB12–15) to an I²C GPIO expander → SPI2 is freed → W5500 +Ethernet rides SPI2 → customer serial rides the I²C bus via SC16IS752 → RGB LED rides the +expander.** Net result: all features land AND the free-pin count *increases*. + +Pin plan after 1.1: + +| Pin | 1.0 use | 1.1 use | +|---|---|---| +| PB12 | BATLED1 | **W5500 SPI2 CS** | +| PB13/14/15 | BATLED2–4 | **W5500 SPI2 SCK/MISO/MOSI** | +| PA15 (free) | — | **W5500 RSTn** | +| PB2 (free) | — | **W5500 INTn** (BOOT1: irrelevant with BOOT0=0; do not strap) | +| PB8 (free) | — | **SC16IS752 IRQn** | +| PA7, PB9, PB10, PC14, PC15 | free/DNP | still free (reserve; PB10 keeps DNP tach provision) | +| BATLED1–4, RGB | PB12–15 / n/a | **PCF8574 P0–P3 (gauge), P4–P6 (RGB), P7 spare** | + +I²C1 (PB6/PB7, 4.7 k pull-ups) roster: SHT40 **0x44**, TMP102 **0x48**, PCF8574 **0x20**, +SC16IS752 **strap A1/A0 AWAY from 0x48 — e.g. 0x4C/0x4D** (its address range 0x48–0x57 +collides with the TMP102; this WILL bite if left at default). 4 devices @100 kHz is fine; +drop pull-ups to 2.2 k only if rise-time says so on the bench. + +## 2. Carry-over fixes from 1.0 (state as of git `19c15e2`) + +- **E-J1 (socket mirrored)** — pads renumbered end-for-end at file level, verified twice + (module landing map 20/20; backend pad read). Footprint id deliberately renamed + `Drogheda:PinSocket_1x20_P2.54mm_Vertical_RevNum_EJ1` (library-update can't revert; + "not found in library" warning is expected — save it into a project `.pretty` in Phase A). + **Pending:** re-route the 11 ripped signal nets (channel between the socket rows); + **regenerate the J1 silkscreen net-name labels** — the current text row describes the OLD + mapping (this is why the fix "looks not flipped" in the editor — trust pad numbers, not silk). +- **E-CLR (24 V clearance, 23-Jul dead unit)** — netclass `HV24` (0.5 mm) assigned to + `/24V_IN, 24V, IGN_IN, Q10_GATE`. **Pending:** DRC → re-route the flagged 24 V spots, + prefer outer layers for 24 V copper. **Decision needed:** pre-existing `PWR_HI/PWR_MID` + netclass patterns lack the `/` prefix and likely never matched (5 V nets have been on + Default rules all along — plausibly related to how 1.0 shipped with 0.2 mm gaps). Fix the + patterns in Phase A and absorb the new DRC flags, or consciously leave them. +- **E-PFI** — R51 287k→270k DONE (trip 4.40 V falling; bench-proven need). Source 270k 1% 0603. +- **Pending small:** 220 µF/10 V elco on VEH5V near P2/RS (modem-inrush bulk); + silkscreen sweep (USB→ arrow + pin-1 dots on J1/J2, P11 `1=MAIN5V IN / 2=SYS5V OUT`, + P2 `5V VEH IN`, J1 label row regenerated); P11 ships with jumper plug. +- **Field/bench rules (no board change):** bench modem work at 5.2–5.4 V in or with pack + connected; install SOP trims SD-15B-05 to ~5.2 V. + +## 3. NEW Block M — customer serial (SC16IS752 + RS-485 + RS-232) + +- **U10 SC16IS752** (I²C mode, addr per §1; XTAL 1.8432 MHz + 2×22 pF → standard bauds to + 115200; IRQn → PB8, 10 k pull-up). +- **Channel A → RS-485 half-duplex:** SP3485/MAX3485-class transceiver, **auto-direction via + the SC16IS752's RS-485 RTS mode** (no GPIO). A/B/GND on a 3-pos Phoenix; 120 Ω termination + behind a jumper (DNP default); optional bias resistors (DNP). Add an **isolated-transceiver + DNP alternative** (ISO3082-class footprint overlay) — decide once the customer says how far + off-cabinet the bus runs. +- **Channel B → RS-232:** MAX3232 + caps, TX/RX/GND on a 3-pos Phoenix; a 4-pin 2.54 mm TTL + header (3V3 levels) in parallel behind solder jumpers — covers the "plain TTL UART" ask. +- Firmware (v3.1): SC16IS752 driver + **Modbus RTU slave** exposing the telemetry registers + (state, link, fix, sats, vbat, v5v, temps, charge status, fault flags, uptime, fw version — + formal register map to be agreed with the customer, draft it in Phase A notes) + optional + NMEA-out mode on either channel. + +## 4. NEW Block N — Ethernet (W5500 + MagJack) + +- **U11 W5500** (QFN48): SPI2 @ ≤25 MHz (PB13 SCK / PB14 MISO / PB15 MOSI / PB12 CS), + RSTn → PA15, INTn → PB2. 25 MHz crystal + load caps, per-datasheet decoupling, 12.4 k RSET. +- **J10 MagJack** HR911105A-class (integrated magnetics + LEDs) on a case-reachable edge. + **Layout rules:** no copper pour under the magnetics area; keep the TX/RX pairs short, + matched-ish, away from the switchers; W5500 + jack in their own corner, far from P3/GNSS RF + and the SW nodes (existing §8 RF rule stands). +- **Power: NEW 3V3_ETH rail** — reuse the proven Block-K MP1584 recipe (U12, FB 100k/31.6k), + fed from **SYS5V** — explicitly NOT `3V3_MODEM` (Ethernet must survive stack power-cycles: + it is the watchdog's reporting path during recovery) and NOT the Blackpill LDO (W5500 + ~132 mA would cook the module regulator's budget). Budget 500 mA. +- Firmware (v3.2): W5500 socket driver (8 hw sockets); transports in priority order — + (1) $PHLG/telemetry + STREAM mirror to the htracker backend over TCP, (2) tracker-feed + mirror using the existing Modo-B PA10 tap, (3) **NTRIP-over-Ethernet client** (fixed + LAN-connected sites run RTK with NO 4G — a real product unlock for warehouse/port installs), + (4) Modbus TCP for the customer if they land on Ethernet later. +- Power/current sanity: +132 mA (W5500) +5 mA (M/O blocks) on 5 V side ≈ +0.1 A at SYS5V — + SD-15B-05 (3 A) and LTC4040 SYSLIM (3.1 A) both have headroom; battery backup runtime with + Ethernet up ≈ 12 Ah / ~0.5 A ≈ 24 h — still ample. + +## 5. NEW Block O — expander + indicators + +- **U13 PCF8574 @0x20** on I²C1. LEDs wired **common-anode to 3V3, expander SINKS through + resistors** (PCF8574 sinks 25 mA/pin, sources almost nothing — active-LOW outputs). +- P0–P3 → BATLED1–4 (existing on-board gauge LEDs, rewired from PB12–15). +- P4–P6 → **RGB status LED** on a 4-pos JST (**P14**, replaces/absorbs single-LED P8 — decide + in Phase A whether P8 stays for backward compatibility): common-anode RGB, one enclosure + hole. State map (v3.1 firmware): GREEN solid RTK-OK · GREEN blink searching/SPS · + YELLOW solid low-battery · YELLOW blink degraded/limp · RED solid fault + (CHRG_FAULT/thermal/fan) · RED blink recovery cycling · BLUE boot. Exact table goes in the + operator manual (es-MX) when firmware lands. +- P7 spare output (future buzzer/4th LED). +- Existing PB0 EXT_LED path stays as the hardwired fallback indicator (works even if I²C dies). +- Firmware: gauge refresh ≤1 Hz over I²C is trivial; **power-on self-test walks gauge + RGB + + spins the fan 2 s** (assembly-line visual check; kills the "is the fan dead?" ambiguity). + +## 6. Depopulation / cleanup (1.1) + +REMOVE outright: P3, P13, H3 (harness alternatives obsoleted by the carrier + Modo-B), +stale J1 label row. KEEP: J7 USB path (modem config access), PB10 tach DNP provision, +P10 external reset, P11 (with jumper plug), P12 NTC. DECIDE in Phase A: H1 SWD DNP 4-pad +(add it this time — it costs nothing and 1.0 bring-up would have used it), P8 vs P14. + +## 7. Sourcing adds (LCSC pass in Phase E) + +W5500 · HR911105A MagJack · 25 MHz + 1.8432 MHz crystals · SC16IS752IPW · SP3485EN · +MAX3232 · PCF8574T · RGB LED (plus JST 4-pos) · MP1584EN #3 + FB/L/C set (Block-K clone) · +220 µF/10 V elco · 270k 1% 0603 (E-PFI) · isolated-RS485 DNP footprint part TBD. +Availability check is part of Phase E, not assumed. + +## 8. Risks / open items + +- SC16IS752 vs TMP102 **address collision if left at default** (§1) — strap check is a + Phase-D ERC-notes item. +- Magjack footprint + keepout correctness (first Ethernet on a Helgen board) — copy a proven + reference layout; DRC can't catch magnetics mistakes. +- Modbus register map needs customer sign-off before v3.1 firmware freezes. +- Flash/RAM: F411 (512 K/128 K) comfortably fits W5500 driver + Modbus + existing v2.3; + revisit only if an RTOS enters the picture. +- Case redesign (RJ45 + RGB + serial glands) rides the outline growth — coordinate with the + ASA reprint; connector edge placement must be agreed BEFORE routing (Phase B gate). +- Existing 1.0 boards: bench/pilot use via Leo's J1 inverter adapter (consider panelizing it + as a rework PCB); 1.1 is the production article. + +## 9. Execution phases (each ends with git commit + parse-verify + snapshot) + +- **A. Schematic** — blocks M/N/O; gauge nets moved to expander; bulk cap; depop §6; + PWR_* pattern decision; save the RevNum_EJ1 footprint into a project `.pretty`; + ERC = 0. *(file-level edits + `kicad-cli sch erc` if available, else parse checks)* +- **B. Outline & placement** — grow the board (target set by connector-edge plan + case), + move/place new blocks (Ethernet corner rule §4), mounting holes, keepouts. **Gate: Leo + approves the connector-edge plan before routing.** +- **C. Routing** — J1 11-net re-route (inter-socket channel) · 24 V re-clear per HV24 · + new blocks · zones refill. +- **D. Verify** — DRC/ERC clean (courtyard-cosmetics excepted), silkscreen sweep done, + strap/address notes, visual SVG/PDF review pack for Leo. +- **E. Outputs & sync** — gerbers/drill/pos/BOM, LCSC pass, delta-doc §-updates, PINOUT.md + rewrite, errata page (E-J1/E-CLR/E-PFI closed in 1.1), firmware v3.0/3.1/3.2 tickets into + the Notion tracker. + +*Firmware reminder (independent of the board): v3.0 scope in +[[drogheda-firmware-v23-review]] §4 is unchanged and still blocks fleet flashing — the +rollover fix and fan-tach fix don't wait for 1.1 silicon.*