diff --git a/03-Architecture-Hardware/2026-09-02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html b/03-Architecture-Hardware/2026-09-02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html new file mode 100644 index 0000000..359ba29 --- /dev/null +++ b/03-Architecture-Hardware/2026-09-02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html @@ -0,0 +1,217 @@ +EinarBoard v6 Copper Plan + + +
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EinarBoard v6 Copper Plan

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Placement companion for the 140 × 100 re-layout — every capacitor's owner, what clusters together, and the EMC order of work. Cap ownership below is computed from the board netlist, not from memory.

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Before placing anything: run Update PCB from Schematic once more. The NTC2 label was sitting on PA7 (TIMEPULSE) and merged the nets — it is fixed in the schematic (commit ba70f62), and the sync re-nets P18/R126/C157 to a clean /NTC2. Tick “delete footprints with no symbol” in that dialog.
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§0Three laws that decide EMC at placement time

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Loop area is the antenna

Emission scales with the area of each switching current loop. A hot loop closed in 1 cm² is ~20 dB quieter than the same loop at 10 cm². Placement fixes this; routing can't rescue a bad placement.

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Smallest cap closest

A capacitor filters up to the frequency its trace inductance allows. Order banks by descending value toward the pin: bulk → 10 µF → 100 nF → pF, with the pF parts within 2–3 mm.

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Aggressors far from victims

Four switchers, one LTE transmitter, one −167 dBm GNSS receiver on one board. Distance and an unbroken In1 ground plane are the only broadband shields you get for free.

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§1Suggested floorplan

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+ + + 140 × 100 mm · connectors on the top (harness) edge · antennas leave at opposite ends + + + HARNESS EDGE — P1 24V · P2 5V bench · P4 batt · P6 fan · P12/P18 NTC · P15/P16 serial · J10 ETH · J9/J11 USB + + + POWER ENTRY + F2 Q23 D32 → U25 buck + L22 · C149–C154 + then U6 LTC4040 + RS1 + C30/31/78 · C32/33/34 + + + MCU U16 + C104–C116 · Y3/Y4 + sense RCs C5/7/9/24/157 + + + ETH U11/U12 + C90–C103 · Y1 + tight to J10 + + + GNSS ISLAND + U18 F9P · U21 LDO + C119–C124 · C143/144/145 + L21 bias tee · D27 · J12 ↓ + quiet corner — no switchers + + + LTE ISLAND + U20 buck · L20 · C127–129 + U19 A7670SA + VBAT bank C130–C136 + U22 SIM · U23/24 shift + J13 → edge + + + RF islands at opposite ends · antennas ≥ 20 cm at the enclosure + + + U26 accel ≤ 10 mm from a mounting hole + +
A proposal, not a constraint — keep the two RF islands at opposite ends and the power entry beside P1/P2, and the rest is yours to optimize.
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§2Vehicle power entry — U25 TPS54360B hot loop

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Chain order along the copper, left to right from P1: F2 → Q23 (with R119, D33 beside its gate) → D32 SMCJ33A → input caps → U25 → D34/L22 → output caps. D10 stays glued to P1 pin 1.

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Loudest loop on the board: C149/C150 (+) → U25 VIN ⟶ U25 SW → D34 cathode ⟶ D34 anode → C149/C150 (−). This is a non-synchronous buck, so the input loop carries the full di/dt. Put C149/C150 within 2–3 mm of U25 pins 2/7, D34 directly across from them, and close the loop over solid ground. Under 1 cm² or do it again.
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RefValueBelongs toPlacement
C149 C1502.2 µF/100 VU25 VIN2–3 mm from pins 2/7; the hot loop
C151100 µF/50 Vinput bulkright behind C149/C150
C152100 nFU25 BOOTdirectly across pins 1–8
C153 C15447 µF/16 V5 V outputat L22 output; FB tap (R121) here, not at the inductor
D34B560Ccatch diodeanode ground ties straight into C149/C150 ground
D32SMCJ33Asurge clampbetween Q23 and the input caps, short fat ties
R120 · R123 C155 C156 · R121 R122 · R124 R125RT · COMP · FB · UVLO (DNP)U25 analog sidecluster at pins 3–6, opposite the SW node; keep FB thin and away from L22
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24 V rail housekeeping: C10/C22 bulk near Q10, C11 100 nF at the load side. Keep the whole entry block in one corner so the dirty 24 V copper never crosses the board.

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§3Battery backup — U6 LTC4040 kelvin

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RefValueBelongs toPlacement
C30 C31 C7810 µF · 2.2 µF · 220 µFVEH5V inputat U6 input pins, after RS1
C32 C33 C3447 µF ×2 · 10 µFMAIN5V outputat U6/Q7 output side
C3522 µFBAT_PLUSnear P4; /SW_BAT ≥ 2 mm polygon, /BAT_PLUS ≥ 1.5 mm — the blackout path, a hard v6 requirement
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RS1 (10 mΩ) is a Kelvin part: the LTC4040 sense pins must tap the pad faces themselves, not the power trace. Place RS1 immediately at U6 with L22's output feeding it directly.
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§4LTE island — U20 buck + U19 A7670SA hot loop

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Second hot loop: C127/C128 → U20 VIN/GND. Synchronous buck, so the input loop is the loud one — C127 10 µF within 2–3 mm of U20 pin 2, C128 1 µF even closer. C129 boot across BOOT–SW, L20 right at SW with a minimal SW pour.
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The VBAT bank is a one-direction gradient into pins 55/56/57 — largest farthest, smallest touching the module:

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RefValueOrderPlacement
C130 C131220 µF/10 V ×2far endthe ≥300 µF droop reservoir (2.8 A bursts, ≤300 mV sag)
C132 → C133 → C13422 µF → 1 µF → 100 nFmiddlestepping toward the module
C135 C13633 pF · 10 pFat the pinswithin 2–3 mm of pins 55/56/57 — these keep TX harmonics off VBAT
D22SMAJ5.0Aat the bankacross VBAT near C130/C131
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VBAT copper ≥ 3 mm wide the whole way. Around the module: C125 at pin 15 (1V8 out); U22 SIM within 5 mm of pins 30–33 with C126 at its VCC pad and D23–D25 PESD at the SIM pads; U23/U24 level shifters between U19 and the MCU side, each with its supply pair (C137/C139 on 1V8, C138/C140 on 3V3) at the pins; Q20–Q22 near the control pins they drive. J13 U.FL at the board edge; the DNP pi network C146/C147 (+ its series element) sits inline in the 50 Ω run right at the connector, D28 ESD at the connector ground side.

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§5GNSS island — U18 ZED-F9P + U21 LDO quiet

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RefValueBelongs toPlacement
C11910 µFU21 input (SW_5V)at the LDO input pin
C120 C12410 µF ×23V3_GNSSone at U21 output, one at U18's main VCC entry
C121 C122 C123100 nF ×3U18 VCC pinsone per supply pin, at the pin
C144 C145100 nF · 100 pFVCC_RF / bias teeat L21's feed side — the antenna supply injection
C143100 nF RFDC blockinline in the 50 Ω run between L21 tap and J12
D27ESD9L (≤0.5 pF)J12at the connector, stub-less tap on the RF line
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This corner is the victim: no switcher, no inductor, no fast digital within ~25 mm; nothing but solid In1 ground under the module and the RF run. TIMEPULSE to the MCU is the one digital line that leaves — route it away from the RF path.

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§6MCU core — U16 analog care

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RefValueBelongs toPlacement
C1114.7 µFVCAP1≤ 3 mm from the pin — the core regulator, non-negotiable
C109 C112100 nF · 1 µFVDDAat the VDDA pin, on the quiet side, away from the switchers
C105–C108 + C110100 nF ×4 + 4.7 µFVDD pinsone 100 nF per VDD pin, bulk nearby
C104100 nFNRSTat the pin, with P10 reset routed clean
Y3 + C113 C114HSE + 15 pFcrystaltight triangle at the pins, local ground, ≥10 mm from any inductor
Y4 + C115 C116LSE 32 kHz + 12 pFcrystaleven tighter — high-impedance oscillator, guard with ground
C5 C7 C9 C24 C157100 nF ×5ADC sense filterswith their dividers (R42, R126…) at the MCU pins, not at the jacks — the wire filters at the pin
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§7The rest of the families

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§8Separation rules

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Keep apartMinWhy
GNSS island ↔ any switcher L / SW node25 mm−167 dBm receiver vs. dV/dt fields
GNSS RF run ↔ LTE RF runopposite endsdesense is risk #1; antennas ≥ 20 cm at the enclosure
Any crystal ↔ any inductor10 mmmagnetic pickup into the oscillator
ADC sense traces ↔ SW nodes5 mm + ground betweentntc/vbat readings ride on µV
USB pairs (J9/J11) ↔ switchersroute as 90 Ω pairs, shorteye + radiated emissions
U26 accel ↔ mounting hole≤ 10 mm (close!)chassis coupling, not board flex
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§9Order of work from here

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  1. Update PCB from Schematic (NTC2 re-net), then place by §1–§8. Field connectors on one edge — every cable is an antenna, and one entry edge keeps their common-mode currents off the board.
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  2. Say the word and I re-add the four zones — F.Cu GND pour, In1 GND (unbroken, especially under both RF runs and the crystals), In2 3V3, B.Cu GND — plus a stitching-via plan: 5 mm grid around RF, via fence along the board edge.
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  3. Route in this order: ① both 50 Ω RF runs (CPWG on F.Cu over In1, JLC7628 ≈ 0.35/0.25 mm — confirm in the JLC calculator and order controlled impedance) · ② the two hot loops and VBAT ≥ 3 mm · ③ /SW_BAT ≥ 2 mm + /BAT_PLUS ≥ 1.5 mm with via farms · ④ USB and ETH pairs · ⑤ sense lines · ⑥ everything else.
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  4. Refill zones, full DRC, then the G2 external review checkpoint before ordering.
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  5. Bench items carried forward: measure U21's 3V3_GNSS rise (F9P ramp window), verify U25's EP against the TI DDA drawing, and the DzG1 jumper check on the fabbed v5.5 boards.
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EinarBoard HBOX v6 · Helgen · generated 02-Sep-2026 from the live netlist (commit ba70f62).

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diff --git a/03-Architecture-Hardware/kicad b/03-Architecture-Hardware/kicad index 05f8e23..ba70f62 160000 --- a/03-Architecture-Hardware/kicad +++ b/03-Architecture-Hardware/kicad @@ -1 +1 @@ -Subproject commit 05f8e233945ad192e3108824e815cf6533f1e534 +Subproject commit ba70f62b5e26577c1572912ffdbbb52b0f74093f