From 31d0e43a7fdbdefc76c7398d96140c056c5db009 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Leopoldo=20Rodr=C3=ADguez?= Date: Fri, 25 Sep 2026 18:37:54 +0000 Subject: [PATCH] v6 T14b: J14 LCSC + bump kicad T14 script extended (idempotent): J14 gets LCSC C2977286 and a primary-SIM description. ERC 0 errors. Co-Authored-By: Claude Opus 5.5 Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt --- 03-Architecture-Hardware/kicad | 2 +- .../2026-09-25_v6_T14_sim_holder_primary.py | 27 +++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/03-Architecture-Hardware/kicad b/03-Architecture-Hardware/kicad index bb78cb8..0288bd0 160000 --- a/03-Architecture-Hardware/kicad +++ b/03-Architecture-Hardware/kicad @@ -1 +1 @@ -Subproject commit bb78cb8888264a55cfa52187e36521bc50e21dd7 +Subproject commit 0288bd0f3f0fe1be59ccb173f1e303e48d227a9b diff --git a/scripts/2026-09-25_v6_T14_sim_holder_primary.py b/scripts/2026-09-25_v6_T14_sim_holder_primary.py index 913c55e..99401fa 100644 --- a/scripts/2026-09-25_v6_T14_sim_holder_primary.py +++ b/scripts/2026-09-25_v6_T14_sim_holder_primary.py @@ -12,6 +12,8 @@ This script (schematic only — the PCB picks it up via Update PCB from Schemati - no-connect flags on J14 C6 (VPP), CSW, DSW - PWR_FLAG on /SIMB_VDD and /SIMA_VDD (both are fed through 0R jumpers, so ERC could not see a driver) + 3. Gives J14 its LCSC field (C2977286) so it lands in the JLCPCB BOM, and rewrites its + instance Description (was "DNP alternate to U22"). Method: clone-and-transform from existing blocks in the same file (PF19 for the flags, an existing no_connect), fresh UUIDs, invariant guards. Dry-run by default. @@ -25,6 +27,9 @@ POPULATE = ['J14', 'R131', 'R132', 'R133', 'R134'] MAKE_DNP = ['U22', 'R127', 'R128', 'R129', 'R130'] NO_CONNECT = [(327.3, 487.54), (352.7, 482.46), (352.7, 485.0)] # J14 C6, CSW, DSW FLAGS = [('PF20', 310.0, 453.81, 'SIMB_VDD'), ('PF21', 310.0, 423.81, 'SIMA_VDD')] +J14_LCSC = 'C2977286' # JAE SF72S006VBDR2500 — JLC "Pre-ordered Products": pre-order stock before PCBA +J14_DESC = ('Nano-SIM holder JAE SF72S006VBDR2500 (LCSC C2977286) - PRIMARY SIM since T14 ' + '(2026-09-25, Telcel will not supply MFF2). U22 MFF2 is the DNP alternate.') def span(s, i): d = 0; instr = False; esc = False; j = i @@ -106,6 +111,26 @@ def main(): cut = s.rstrip().rfind('\n)') s = s[:cut] + add + s[cut:] + # 3. J14 becomes a JLCPCB-assembled part: give it the LCSC field (cloned from R131's + # LCSC property block) and fix its instance Description, which still said "DNP alternate". + a, e = sym_block(s, 'J14'); blk = s[a:e] + if not re.search(r'\(property "LCSC" ', blk): + ra, re_ = sym_block(s, 'R131'); rblk = s[ra:re_] + m = re.search(r'\n\t\t\(property "LCSC" "', rblk) + pa = m.start() + 3; lc = rblk[pa:span(rblk, pa)] # from '(' — indent added below + lc = re.sub(r'"LCSC" "[^"]*"', f'"LCSC" "{J14_LCSC}"', lc, count=1) + jx, jy = re.search(r'\n\t\t\(at (-?[\d.]+) (-?[\d.]+) ', blk).groups() + lc = re.sub(r'\(at [^)]*\)', f'(at {jx} {jy} 0)', lc, count=1) + d = re.search(r'\n\t\t\(property "Description" "', blk) + da = d.start() + 1; de = span(blk, da) + blk = blk[:de] + '\n\t\t' + lc + blk[de:] + changes.append(f'J14: + LCSC {J14_LCSC}') + old_desc = '"Nano-SIM holder JAE SF72S006 (LCSC C2977286) - DNP alternate to U22"' + if old_desc in blk: + blk = blk.replace(old_desc, '"' + J14_DESC + '"', 1) + changes.append('J14: Description -> primary SIM') + s = s[:a] + blk + s[e:] + # guards assert balanced(s), 'output not paren-balanced' uuids1 = UUID.findall(s) @@ -118,6 +143,8 @@ def main(): a, e = sym_block(s, ref); assert '\n\t\t(dnp no)' in s[a:e], ref for ref in MAKE_DNP: a, e = sym_block(s, ref); assert '\n\t\t(dnp yes)' in s[a:e], ref + a, e = sym_block(s, 'J14') + assert f'(property "LCSC" "{J14_LCSC}"' in s[a:e], 'J14 LCSC missing' print(f'{len(changes)} change(s):'); [print(' ', c) for c in changes] print(f'UUIDs: {len(uuids0)} kept, {len(uuids1) - len(uuids0)} new, 0 duplicated; paren-balanced')