From 538b62b72c5507a5b29c44f8c15dd967c8ef9966 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Leopoldo=20Rodr=C3=ADguez?= Date: Fri, 4 Sep 2026 00:53:32 +0000 Subject: [PATCH] v6 connector renumber (submodule b007c7c) + Copper Plan map Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt --- ...02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html | 10 +++++----- 03-Architecture-Hardware/kicad | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/03-Architecture-Hardware/2026-09-02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html b/03-Architecture-Hardware/2026-09-02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html index a1e937c..04311c9 100644 --- a/03-Architecture-Hardware/2026-09-02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html +++ b/03-Architecture-Hardware/2026-09-02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html @@ -63,7 +63,7 @@ a{color:var(--plane)}

EinarBoard v6 Copper Plan

Placement companion for the 140 × 100 re-layout — every capacitor's owner, what clusters together, and the EMC order of work. Cap ownership below is computed from the board netlist, not from memory.

-
Before placing anything: run Update PCB from Schematic once more. The NTC2 label was sitting on PA7 (TIMEPULSE) and merged the nets — it is fixed in the schematic (commit ba70f62), and the sync re-nets P18/R126/C157 to a clean /NTC2. Tick “delete footprints with no symbol” in that dialog.
+
Connector renumber (03-Sep, commit b007c7c): P-refs now follow function order — P1 24V · P2 5V bench · P3 battery (was P4) · P4 fan (was P6) · P5 cutoff (was P11) · P6 reset (was P10) · P7 NTC probe 1 (was P12) · P8 NTC probe 2 (was P18) · P9 panel LED (was P8) · P10 RGB (was P14) · P11 RS485 (was P15) · P12 RS232 (was P16). ⚠ v5 field docs say "P12 = NTC" — in v6 that name is the RS232 port; update harness docs. The NTC2 net fix is applied and synced.
Known leftovers from the auto-clustering: ~54 small courtyard overlaps, nearly all against the legacy V5 regulator families that kept their old spots — L2/D2 (under U19's new outline), L6/DB2/DB3/Q2/Dbk1 near U25, C40, R40/R41 at Y3. Drag those few aside first and the board is clean.

§0Three laws that decide EMC at placement time

@@ -136,7 +136,7 @@ a{color:var(--plane)} RefValueBelongs toPlacement C30 C31 C7810 µF · 2.2 µF · 220 µFVEH5V inputat U6 input pins, after RS1 C32 C33 C3447 µF ×2 · 10 µFMAIN5V outputat U6/Q7 output side -C3522 µFBAT_PLUSnear P4; /SW_BAT ≥ 2 mm polygon, /BAT_PLUS ≥ 1.5 mm — the blackout path, a hard v6 requirement +C3522 µFBAT_PLUSnear P3; /SW_BAT ≥ 2 mm polygon, /BAT_PLUS ≥ 1.5 mm — the blackout path, a hard v6 requirement
RS1 (10 mΩ) is a Kelvin part: the LTC4040 sense pins must tap the pad faces themselves, not the power trace. Place RS1 immediately at U6 with L22's output feeding it directly.
@@ -179,12 +179,12 @@ a{color:var(--plane)}

§7The rest of the families

§8Separation rules

@@ -207,5 +207,5 @@ a{color:var(--plane)}
  • Bench items carried forward: measure U21's 3V3_GNSS rise (F9P ramp window), verify U25's EP against the TI DDA drawing, and the DzG1 jumper check on the fabbed v5.5 boards.
    • -

    EinarBoard HBOX v6 · Helgen · updated 03-Sep-2026 to the clustered layout (commits ba70f62 · c7d2552).

    +

    EinarBoard HBOX v6 · Helgen · updated 03-Sep-2026: clustered layout + connector renumber (c7d2552 · 43a967b · b007c7c).

    diff --git a/03-Architecture-Hardware/kicad b/03-Architecture-Hardware/kicad index 43a967b..b007c7c 160000 --- a/03-Architecture-Hardware/kicad +++ b/03-Architecture-Hardware/kicad @@ -1 +1 @@ -Subproject commit 43a967b78e76f03840f14a9ebbe236fca4560040 +Subproject commit b007c7c1b10ccd86e49052852f392027c284f04d