1.1 Phase C1: W5500 datasheet verification — 2 bugs fixed, Ethernet unblocked
Checked against WIZnet W5500 datasheet v1.1.0 (official pin table): - CONFIRMED correct: pin 23 RSVD->GND, pin 18 VBG floating, EXRES1 12.4k/1%, PMODE[2:0]=111 autoneg via pins 43-45, LINKLED/ACTLED pins 25/27 active-low sink topology, TXN/TXP/RXN/RXP order (1/2/5/6), SPI on 32-37 - BUG FIXED: RSVD pins 38-42 were floating; datasheet requires GND. Added 5 GND stubs on U11 in the schematic + (net GND) on board pads 38-42 - BUG FIXED: TOCAP/1V2O caps were 10uF/4.7uF; datasheet requires 4.7uF/10nF. C90 -> 4.7uF, C91 -> 10nF (sch + board values; footprints unchanged) - R83 board value harmonized to sch's 12.4k/1% Magjack HR911105A: wiring matches the standard table (TX 1/2, RX 3/6, TCT pin4->3V3_ETH, RCT pin5->6.8nF, internal Bob Smith). Bench-check with DMM before flash: pins 4/5 CT assignment + LED anode/cathode on 9-12. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
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