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@ -21,6 +21,15 @@ status: CLOSED 2026-07-07 — all four HIGH findings fixed and re-verified; bare
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> D2=RX2 (shared XBee-TX), D3–D7 empty, D8=TX2 (shared XBee-RX). Carrier mapping confirmed
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> D2=RX2 (shared XBee-TX), D3–D7 empty, D8=TX2 (shared XBee-RX). Carrier mapping confirmed
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> position-for-position.
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> position-for-position.
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>
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>
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> **H5 FINAL DISPOSITION (2026-07-07 evening, OWNER DECISION):** board released at J1↔J2 =
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> **15.03 mm** (J2 y=71.35). Leo measured the physical module repeatedly with a vernier and
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> stands on **15.0 mm** centers; the auditor's reading of the evidence remains **15.24 mm**
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> (600 mil: breadboard compatibility requires N×2.54; the KiCad-forum production footprint;
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> Leo's own outer-faces measurement 15.87 − 0.64 = 15.23). Dissent recorded, decision accepted —
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> under either value the module mates (≤0.1 mm/row elastic offset worst-case). **Mandatory
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> assembly mitigation for all units: solder the J1/J2 (and MOD1) female strips with the module
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> plugged in as an alignment jig** — hole clearance absorbs the delta, zero preload either way.
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>
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> **H5 — NEW HIGH (2026-07-07, caught by the M4 gate / CAD engineer): Blackpill socket rows one
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> **H5 — NEW HIGH (2026-07-07, caught by the M4 gate / CAD engineer): Blackpill socket rows one
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> grid step too wide.** Board J1↔J2 = 17.78 mm (0.7"); the physical WeAct Blackpill measures
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> grid step too wide.** Board J1↔J2 = 17.78 mm (0.7"); the physical WeAct Blackpill measures
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> **15.24 mm (600 mil)** row-to-row (calipers: 15.87 outer − 0.64 pin = 15.23 c-c; corroborated by
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> **15.24 mm (600 mil)** row-to-row (calipers: 15.87 outer − 0.64 pin = 15.23 c-c; corroborated by
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03-Architecture-Hardware/CAD FIles/JLCSMT_Sample_CPL1.xlsx
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03-Architecture-Hardware/CAD FIles/JLCSMT_Sample_CPL1.xlsx
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03-Architecture-Hardware/bom.xls
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03-Architecture-Hardware/bom.xls
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