auto-sync 2026-07-07 18:00

03-Architecture-Hardware/2026-07-06_Drogheda_EinarBoard-1.0-PreFab-Audit_v1.0.md

@@ -4,9 +4,61 @@ tags: [project-drogheda, hardware, watchdog, pcb, audit, einarboard]
 project: Project Drogheda
 author: Helgen CTO (Claude audit, reviewed by Leo)
 date: 2026-07-06
-status: BLOCKING — do NOT order until HIGH items are cleared
+status: CLOSED 2026-07-07 — all four HIGH findings fixed and re-verified; bare-board order released (see closure note)
 ---
 
+> **CLOSURE NOTE (2026-07-07):** H1 (Q7 S/D) fixed board-side by Leo + schematic redrawn (D=MAIN5V,
+> S=VIN_SW, verified visually and in file); H2 (Q5/Q6 BEC) fixed in schematic (Q_NPN_BEC) + board pads
+> swapped and rerouted; H3 (Rig 22k + dangling pin) fixed both sides — fab BOM now reads "RDFU1, RIG1 =
+> 22k"; H4 (SW_IN) in PWR_MID at 1.0 mm (19 segs). Re-verification: ERC 0 errors (172 cosmetic warnings) ·
+> DRC 0 errors / 0 unconnected (14 warnings: 10 lib-mismatch + 4 silk) · U2/U7 EP GND intact · refdes
+> converged on numbered names (annotator-proof) · fab package regenerated 11:59 after last board save.
+> **F8 is permanently retired on this board** — sync is manual (see memory/process note). Bare-board
+> order RELEASED conditional on the two physical gates (M3: D0/D1 on a physical Pro; M4: HBOX fit).
+> PCBA still blocked by M1 (LCSC coverage 18/77 lines).
+>
+> **M3 CLOSED (2026-07-07):** verified on a physical simpleRTK2B Pro — silk reads D0=TX1, D1=RX1,
+> D2=RX2 (shared XBee-TX), D3–D7 empty, D8=TX2 (shared XBee-RX). Carrier mapping confirmed
+> position-for-position.
+>
+> **H5 — NEW HIGH (2026-07-07, caught by the M4 gate / CAD engineer): Blackpill socket rows one
+> grid step too wide.** Board J1↔J2 = 17.78 mm (0.7"); the physical WeAct Blackpill measures
+> **15.24 mm (600 mil)** row-to-row (calipers: 15.87 outer − 0.64 pin = 15.23 c-c; corroborated by
+> the KiCad forum footprint thread — "standard DIP", 600 mil — and a pixel re-measure of the WeAct
+> dimensions drawing: rows ≈15.5 mm, insets ≈2.7 mm on the 20.78 board). **Order RETRACTED until
+> fixed.** Fix: move **J2** from y=74.1031 → **y=71.5631** (Δ−2.54; the landing strip is
+> footprint- and via-free; moving J1 instead would collide with Q1/Q5), re-drag the 20 stubs,
+> refill, DRC 0, re-export, **then 1:1 paper test with the real module before ordering** (and same
+> paper test for MOD1 + J7/J8 + the physical modem while at it). Pin functions are unaffected —
+> layout-only fix; schematic untouched.
+>
+> **H6 — NEW HIGH (2026-07-07, surfaced by Leo's "silk on the back" question): MOD1 footprint is
+> FLIPPED to B.Cu** — has been since the Jul-3/4 re-placement (preCarrier backup shows F.Cu; preusb
+> onward B.Cu). The UNO socket pattern is x-mirrored: a shield plugged from the top cannot mate.
+> The back-side silkscreen was the symptom, not the problem. Only MOD1 is flipped (full 132-footprint
+> side sweep clean). Fix: select MOD1 → **F** (flip to F.Cu — silk returns to front automatically) →
+> reposition the envelope back over the shield field (check P3-notch + J8 clearance per the Jul-2
+> review notes) → reroute the 6 attached pads (2=3V3, 5=SW_5V @1.0 mm, 15/16=GNSS_RX/TX,
+> 17=DOUT_4G, 23=USART1_RX) → refill → DRC → re-STEP for the CAD engineer. Audit lesson recorded:
+> **footprint SIDE is now a standing checklist item; the 1:1 paper test with real modules is
+> mandatory before any socketed-carrier order.**
+>
+> **H6 RESOLVED 2026-07-07 — NOT A DEFECT (auditor false alarm). DO NOT FLIP MOD1.** The pad
+> pattern was physically validated by Leo: 1:1 print + the real simpleRTK2B Pro in the intended
+> orientation (antenna top-left, USB-C pair at bottom), including the discriminating count check —
+> 18-pin digital edge on the 18-hole row (y≈81) with the 10-pin subgroup at the correct (right)
+> end, 14-pin edge on the 14-hole row. Pads are correct as-placed; the B.Cu hosting is a
+> modeling/visual quirk only (outline on B.Fab, 3D model rendered underneath). Action taken:
+> move MOD1's B.Fab/B.CrtYd (and any B.Silk) graphics to the front layers — pads untouched.
+> **Auditor lesson:** the hand-derived back-side mirror transform produced a false positive;
+> for back-footprint geometry trust KiCad-computed outputs (IPC-D-356, gerbers, 3D/STEP) and the
+> physical 1:1 test — never a manually reconstructed flip. **Pro revisions differ:** older Pros have an "XBEE TO GPS UART" switch —
+> park it on UART1; newer Pros (like the verified sample) have NO switch — the XBee socket is
+> hardwired to UART2 (silk: "XBEE-TX/GPS RX2", "XBEE-RX/GPS TX2" on the rail pins). Assembly
+> checklist, both revisions: Pro's XBee socket stays EMPTY; if a switch exists → UART1; **never
+> plug the Pro's "USB XBee" port while the unit is in service** (its FTDI sits across UART2 on the
+> new rev = directly on the RTCM3 downlink). Only M4 (HBOX fit) gates the PO.
+
 # EINARBoard HBOX 1.0 (`hbox-watchdog-v3-PROD`) — Pre-Fab Audit
 
 **Scope:** read-only audit of the KiCad project as of 2026-07-06 17:14 (PCB saved 17:06, fab

03-Architecture-Hardware/EinarBoard-Manual/einarboard-manual.tex

@@ -0,0 +1,436 @@
+% =====================================================================
+%  2026-07-07_Drogheda_EinarBoard-1.0_Engineering-Manual_v1.1
+%  Helgen Technologies — Project Drogheda (GPS RTK)
+%  HELGEN EINARBOARD 1.0 (hbox-watchdog-v3-PROD) — Rev 1.1 Post-Audit
+%  Production Engineering Manual / Engineering Memory
+%
+%  BOM table is AUTO-SYNCED: edit helgen_einarboard_1.0_production_bom.xlsx,
+%  run tools/sync_bom.py (regenerates pcba_bom.tex), recompile.
+%  Compile: pdflatex einarboard-manual.tex  (x2 for longtable/TOC)
+% =====================================================================
+\documentclass[11pt,a4paper]{article}
+
+\usepackage[T1]{fontenc}
+\usepackage[utf8]{inputenc}
+\usepackage{lmodern}
+% Brand fonts (League Spartan / MADE Evolve Sans) are license-gated for
+% embedded client-facing use — sans-serif fallback per brand working summary.
+\renewcommand{\familydefault}{\sfdefault}
+
+\usepackage[margin=2.1cm,headheight=14pt]{geometry}
+\usepackage[table]{xcolor}
+\definecolor{HelgenIndigo}{HTML}{2C3C5B}
+\definecolor{HelgenCyan}{HTML}{51F3DA}
+\definecolor{HelgenSlate}{HTML}{44597A}
+\definecolor{HelgenMist}{HTML}{EAEFF5}
+
+\usepackage{graphicx,booktabs,longtable,array,tabularx,enumitem,fancyhdr,titlesec,caption,microtype,textcomp}
+\usepackage{pdfpages} % full-sheet schematic + per-layer plots (assets/)
+\usepackage{tikz}
+\usetikzlibrary{arrows.meta,positioning,fit,calc}
+\usepackage[colorlinks=true,linkcolor=HelgenIndigo,urlcolor=HelgenSlate,pdftitle={Helgen EinarBoard 1.0 — Production Engineering Manual v1.1}]{hyperref}
+
+\titleformat{\section}{\Large\bfseries\color{HelgenIndigo}}{\thesection}{0.8em}{}[{\color{HelgenCyan}\titlerule[1.2pt]}]
+\titleformat{\subsection}{\large\bfseries\color{HelgenSlate}}{\thesubsection}{0.7em}{}
+\captionsetup{font=small,labelfont={bf,color=HelgenIndigo}}
+\setlist{nosep,leftmargin=1.4em}
+\newcolumntype{L}[1]{>{\raggedright\arraybackslash}p{#1}}
+
+\pagestyle{fancy}\fancyhf{}
+\fancyhead[L]{\small\color{HelgenSlate}EinarBoard 1.0 --- Rev 1.1 Production Master}
+\fancyhead[R]{\small\color{HelgenSlate}Helgen Technologies}
+\fancyfoot[L]{\small\color{HelgenSlate}CONFIDENTIAL --- Project Drogheda (GPS RTK)}
+\fancyfoot[R]{\small\color{HelgenSlate}\thepage}
+\renewcommand{\headrulewidth}{0.4pt}
+
+\newcommand{\net}[1]{\texttt{#1}}
+\newcommand{\warn}[1]{\par\medskip\noindent\colorbox{HelgenMist}{\parbox{\dimexpr\linewidth-2\fboxsep}{\textbf{\color{HelgenIndigo}\textbardbl~WARNING.} #1}}\medskip}
+
+\begin{document}
+
+% ------------------------------------------------------------------ COVER
+\begin{titlepage}
+\centering
+\vspace*{8mm}
+\IfFileExists{assets/Logo_Helgen_Azul_2026.png}{\includegraphics[width=0.42\linewidth]{assets/Logo_Helgen_Azul_2026.png}}{\textbf{\Huge\color{HelgenIndigo}HELGEN}}\par
+\vspace{14mm}
+{\color{HelgenCyan}\rule{\linewidth}{2pt}}\par\vspace{6mm}
+{\Huge\bfseries\color{HelgenIndigo} HELGEN EINARBOARD 1.0\par}
+\vspace{3mm}
+{\Large\color{HelgenSlate} HBOX RTK Watchdog Carrier --- Production Engineering Manual\par}
+\vspace{2mm}
+{\large\color{HelgenSlate} Rev 1.1 --- Post-Audit Production Master\par}
+\vspace{6mm}
+{\color{HelgenCyan}\rule{\linewidth}{2pt}}\par
+\vspace{16mm}
+\begin{tabular}{ll}
+\textbf{Document code} & \texttt{2026-07-07\_Drogheda\_EinarBoard-1.0\_Engineering-Manual\_v1.1}\\
+\textbf{Project} & Drogheda (GPS RTK) --- Hutchison Ports ICAVE / TIMSA / EIT / LCT\\
+\textbf{KiCad project} & \texttt{kicad/hbox-watchdog-v3-PROD.kicad\_pcb}\\
+\textbf{Board} & $135.1 \times 100.1$\,mm, 4-layer, 132 footprints, 130 nets\\
+\textbf{Verification} & ERC 0 errors $\cdot$ DRC 0 errors / 0 unconnected (2026-07-07)\\
+\textbf{Author} & Helgen CTO/CSO --- principal HW/SW architect\\
+\textbf{Status} & Bare-board order RELEASED $\cdot$ PCBA gated (\S\ref{sec:readiness})\\
+\end{tabular}
+\vfill
+{\small\color{HelgenSlate} CONFIDENTIAL --- Helgen Technologies. Client-facing derivatives are produced in Spanish and routed through Leo.\par}
+\end{titlepage}
+
+% ------------------------------------------------------------------ DOC CONTROL
+\section*{Revision history}
+\begin{tabular}{@{}llL{9.6cm}@{}}
+\toprule
+\rowcolor{HelgenMist}\textbf{Rev} & \textbf{Date} & \textbf{Change}\\
+\midrule
+1.0 & 2026-07-06 & Initial production master; pre-fab audit executed same day (4 HIGH, 6 MED findings).\\
+1.1 & 2026-07-07 & \textbf{Post-audit master.} H1 Q7 S/D corrected (S=\net{VIN\_SW}, D=\net{MAIN5V}); H2 Q5/Q6 to \texttt{Q\_NPN\_BEC} map; H3 \net{RIG1}/\net{RDFU1}=22\,k$\Omega$ + dangling pin fixed; H4 \net{SW\_IN} in PWR\_MID @1.0\,mm. M3 closed (physical Pro pinout verified). Refdes converged to numbered names. Fab package regenerated after last save.\\
+\bottomrule
+\end{tabular}
+
+\tableofcontents
+
+% ------------------------------------------------------------------ 1
+\section{System overview}
+\textbf{EinarBoard 1.0} (title-block \emph{EINARBoard HBOX 1.0}; KiCad lineage \texttt{hbox-watchdog-v3-PROD}) is the HBOX carrier/motherboard for the Drogheda GPS-RTK fleet tracker deployed on heavy port equipment. It hosts the full electronics stack of an HBOX unit on plug-in sockets and carries the watchdog, power, backup-battery, thermal-sensing, and fail-safe corrections infrastructure on its own copper:
+
+\begin{itemize}
+\item \textbf{STM32F411 Blackpill} (watchdog MCU) on J1/J2 $1{\times}20$ sockets --- supervises the stack, power-cycles it on lost corrections, gauges the battery, qualifies charging by temperature, and injects \texttt{\$PHLG} diagnostics on the Modo-B uplink.
+\item \textbf{simpleRTK2B Pro} (u-blox ZED-F9P) as an Arduino-UNO-form shield on MOD1 --- GNSS RTK engine.
+\item \textbf{4G NTRIP Master} (XBee-form LTE) on J7/J8 2.00\,mm sockets at \net{3V3\_MODEM} --- corrections downlink and NMEA uplink. USB-C service port J9 firmware-updates the modem in place.
+\item \textbf{LTC4040} battery-backup manager with a 1S4P ($\sim$12\,Ah) 18650 pack --- rides through power loss on a parked machine; charge voltage strapped to 4.00\,V Li-ion for cycle life and hot-cell margin (RCA \#1 answer).
+\item \textbf{K1 normally-closed relay bypass} --- RTCM3 corrections survive a dead, hung, or physically absent MCU.
+\end{itemize}
+
+Deployment context: machine power (12/24\,V classes at ICAVE) enters the IP67 cabinet (breaker, SPD, Mean~Well DDR-60G-24); the HBOX receives regulated 24\,V, vehicle 5\,V (SD-15B-05), and \emph{raw} machine ignition through the GX16-5 bulkhead. Corrections arrive over LTE/NTRIP --- never through the GNSS --- so link recovery is always a stack power-cycle.
+
+\subsection{Power tree (as built, Rev 1.1)}
+\begin{center}
+\resizebox{\linewidth}{!}{%
+\begin{tikzpicture}[
+  font=\scriptsize,
+  box/.style={draw=HelgenIndigo, fill=HelgenMist, rounded corners=1pt, minimum height=5.5mm, inner sep=2pt, align=center},
+  pow/.style={draw=HelgenIndigo, fill=HelgenIndigo, text=white, rounded corners=1pt, minimum height=5.5mm, inner sep=2pt, align=center},
+  acc/.style={draw=HelgenIndigo, fill=HelgenCyan, rounded corners=1pt, minimum height=5.5mm, inner sep=2pt, align=center},
+  a/.style={-{Stealth[length=2mm]}, HelgenSlate, thick},
+  node distance=3.5mm and 5mm]
+\node[pow] (gx) {P1 GX16-5\\24\,V / IGN / GND};
+\node[box, right=of gx] (fe) {D10 SMBJ33A +\\Q10 IRFR5305 rev-pol};
+\node[box, right=of fe] (u2) {U2 MP1584\\24$\to$5.0\,V};
+\node[box, right=of u2] (fan) {\net{5V\_FAN}\\P6 fan (Q2 PWM)};
+\node[pow, below=7mm of gx] (p2) {P2 \net{VEH5V}\\SD-15B-05 5\,V};
+\node[box, right=of p2] (rs) {RS1 8\,m$\Omega$\\3.1\,A limit};
+\node[acc, right=of rs] (ltc) {U6 LTC4040 + Q7\\backup mgr};
+\node[box, right=of ltc] (main) {\net{MAIN5V}\\(backed-up)};
+\node[box, right=of main] (cut) {P11 cutoff\\$\to$ \net{SYS5V}};
+\node[box, below=7mm of rs] (bat) {P4 1S4P $\sim$12\,Ah\\+ cell NTC};
+\node[box, below=7mm of cut] (mcu) {Blackpill 5\,V\\+ K1 coil};
+\node[box, right=of cut] (f1) {F1 PPTC $\to$ \net{SW\_IN}\\Q1 load switch};
+\node[acc, below=7mm of f1] (sw5) {\net{SW\_5V}\\MOD1 (Pro 5\,V)};
+\node[box, right=of sw5] (u7) {U7 MP1584\\$\to$ \net{3V3\_MODEM}};
+\node[box, below=7mm of u7] (xbee) {J7/J8 XBee\\4G NTRIP Master};
+\draw[a] (gx) -- (fe); \draw[a] (fe) -- (u2); \draw[a] (u2) -- (fan);
+\draw[a] (p2) -- (rs); \draw[a] (rs) -- (ltc); \draw[a] (ltc) -- (main);
+\draw[a] (main) -- (cut); \draw[a] (cut) -- (f1);
+\draw[a, {Stealth[length=2mm]}-{Stealth[length=2mm]}] (ltc) -- node[left]{L6 2.2\,\textmu H} (bat);
+\draw[a] (cut) -- (mcu);
+\draw[a] (f1) -- (sw5); \draw[a] (sw5) -- (u7); \draw[a] (u7) -- (xbee);
+\end{tikzpicture}}
+\end{center}
+
+\noindent\textbf{Ignition sense (Rev 1.1 topology --- DFR1015 removed):} GX16 pin 3 carries \emph{raw} machine ignition (12--24\,V) to \net{IGN\_IN} $\to$ \net{RIG1} 22\,k$\Omega$ / \net{Rigb} 10\,k$\Omega$ divider $\to$ D5 BAT54 clamp to 3V3 $+$ C9 100\,nF $\to$ PA5 (digital input). At 24\,V the clamp carries $<$1\,mA. \emph{The stale 100\,$\Omega$ value (audit H3) would have burned D5 and the resistor at 24\,V --- corrected on board, schematic, and fab BOM.}
+
+% ------------------------------------------------------------------ 2
+\section{Canonical invariants (engineering memory)}
+Every change to this board is checked against the project ethos. In copper, Rev 1.1 realizes them as:
+\begin{enumerate}
+\item \textbf{Power-off is the safe state.} R2 10\,k$\Omega$ pulls the Q1 gate to rail; only PA1 (\net{PWR\_CTRL}) via Q5 can enable the RTK stack. MCU absent $\Rightarrow$ stack OFF.
+\item \textbf{Never vanish, never loop.} Watchdog power-cycles the stack (modem included, via U7 fed from \net{SW\_5V}) instead of letting a unit go silent; firmware rate-limits reboots.
+\item \textbf{Corrections ride the 4G modem, not the GNSS.} RTCM3 downlink (modem DOUT $\to$ MOD1 D2 $\to$ F9P RX2) is hardwired and never touches the MCU; uplink survives a dead MCU through K1's NC contacts.
+\item \textbf{No sub-80\,$^{\circ}$C-softening material in the thermal path;} enclosure is ASA; cooling is conduction (IP67 --- no vents). Thermal telemetry: SHT40 + TMP102 (I$^2$C) + hotspot NTC (PB1) + cell NTC (charger-owned).
+\item \textbf{Backend must not black-hole a healthy unit} --- board-side contribution is honest telemetry (\texttt{\$PHLG}, charge status, temperatures) on the STREAM log.
+\item \textbf{No secrets in the repo} --- this manual and the BOM workbook carry none.
+\end{enumerate}
+
+% ------------------------------------------------------------------ 3
+\section{Electrical architecture by block}
+\begin{center}
+\small
+\begin{tabular}{@{}lL{6.4cm}L{5.6cm}@{}}
+\toprule
+\rowcolor{HelgenIndigo}\textcolor{white}{\textbf{Block}} & \textcolor{white}{\textbf{Function}} & \textcolor{white}{\textbf{Key parts / nets}}\\
+\midrule
+A & Fan buck 24\,V$\to$5.0\,V, dedicated rail (inrush never sags \net{MAIN5V}) & U2 MP1584EN, L2 10\,\textmu H, FB 100k/19.1k, \net{5V\_FAN}, JP1 OPEN\\
+\rowcolor{HelgenMist}
+B & Battery backup: charger + power path + 2.5\,A boost & U6 LTC4040, Q7 AO4406A, RS1 8\,m$\Omega$, L6 2.2\,\textmu H, P4, straps 4.00\,V\\
+C & Reset & SW1 on-board + P10 external $\to$ \net{NRST}\\
+\rowcolor{HelgenMist}
+D & 4-LED battery gauge & PB12--15, RB1--4 330\,$\Omega$, DB1--4\\
+E & Power cutoff (kills vehicle \emph{and} battery) & P11 in series \net{MAIN5V}$\to$\net{SYS5V}; jumper plug when unused\\
+\rowcolor{HelgenMist}
+F & Vehicle-power sense on the vehicle side & PA4 divider taps \net{VEH5V} (never the backed-up rail)\\
+H & Modo-B fail-safe uplink bypass & K1 G5V-1 NC, Q6 driver (PB5), D6 flyback\\
+\rowcolor{HelgenMist}
+I & Hot-spot NTC channel & R42 10\,k$\Omega$ 1\,\% + C24 $\to$ PB1 (ADC1\_IN9), P12 probe\\
+J & Carrier sockets & J1/J2 Blackpill $\cdot$ MOD1 UNO shield $\cdot$ J7/J8 XBee 2.00\,mm\\
+\rowcolor{HelgenMist}
+K & Modem rail & U7 MP1584EN \net{SW\_5V}$\to$\net{3V3\_MODEM} (3.33\,V), FB 100k/31.6k\\
+U & USB-C service port (modem DFU in place) & J9 USB4085, Rcc 5.1\,k$\Omega\times2$, SW4G reset, D4G/Rmled LED\\
+\bottomrule
+\end{tabular}
+\end{center}
+
+\subsection{Block B --- LTC4040 backup manager (sized to the 12\,Ah pack)}
+Single-inductor architecture: step-down charger (\net{VSYS}$\to$BAT) while input is good; 2.5\,A step-up backup (BAT$\to$\net{VSYS}) when PFI trips. Q7 (gate = IGATE) disconnects the dead input during backup --- \textbf{Rev 1.1 orientation: S = \net{VIN\_SW}, D = \net{MAIN5V}} (audit H1: reversed, the body diode would have back-fed the dead vehicle rail and collapsed backup \emph{exactly when needed}).
+
+\begin{center}
+\small
+\begin{tabular}{@{}llL{6.8cm}@{}}
+\toprule
+\rowcolor{HelgenIndigo}\textcolor{white}{\textbf{Parameter}} & \textcolor{white}{\textbf{Value}} & \textcolor{white}{\textbf{Sizing (ADI 4040fb)}}\\
+\midrule
+Charge current & 2.42\,A $\approx$ C/5 & $I_{CHG}=2000/R_{PROG}$, $R_{PROG}=825\,\Omega$ 1\,\% (R50)\\
+\rowcolor{HelgenMist} Input current limit & 3.1\,A & $25\,\mathrm{mV}/R_S$, $R_S=8$\,m$\Omega$ (RS1) --- protects the SD-15B-05 (3\,A); charge sheds first\\
+PFI trip & 4.60\,V falling ($\approx$4.72\,V recover) & 287k/100k from \net{VEH5V} (R51/R52)\\
+\rowcolor{HelgenMist} Backup voltage & 4.79\,V (RST $-7.5\,\%\approx4.43$\,V) & BSTFB=RSTFB shared divider 499k/100k (R53/R54)\\
+Charge voltage & \textbf{4.00\,V Li-ion} & F2=1, F1=0, F0=1 via JP2/3/4 strapped to \net{VSYS} (chemistry survives absent MCU); LiFePO$_4$ = re-strap F2\\
+\rowcolor{HelgenMist} Inductor & 2.2\,\textmu H, $I_{sat}\geq8$\,A & L6 (Sunlord MWSA0804S-2R2MT sub)\\
+VSYS hold-up & 104\,\textmu F $\geq$ 100\,\textmu F min & C32/C33 47\,\textmu F 1210 + C34\\
+\rowcolor{HelgenMist} Cell NTC & charger-owned (U6 NTC pin) & RT1 on the cell via P4.3; R55 10\,k$\Omega$ bias --- charging stays temperature-qualified with the MCU dead\\
+CHGOFF & \net{CHRG\_EN} (PA8) + 100\,k$\Omega$ pull-down & MCU absent $\Rightarrow$ charging enabled, NTC still guards; MCU cuts charge on hot cell (RCA \#1)\\
+\bottomrule
+\end{tabular}
+\end{center}
+
+\noindent\textbf{Safety-timer note:} a deep-discharge full recharge (12\,Ah @ 2.42\,A $\approx$ 5\,h) exceeds the internal safety timer --- firmware restarts the cycle via \net{CHRG\_EN} while the cell is cool and \net{BAT\_SENSE} is low.
+
+\subsection{Block H --- fail-safe Modo-B bypass}
+K1 (Omron G5V-1, 5\,V coil) de-energized routes F9P TX2 $\to$ 4G DIN through its \textbf{normally-closed} contacts: corrections and position flow exactly as if the watchdog were not there --- with the Blackpill hung, unpowered, or physically removed. PB5 (\net{BYP\_CTRL}) via Q6 energizes the coil to insert the MCU in-line (USART1: PA10 monitor tap, PA9 injection of \texttt{\$PHLG}). Verified against the Omron datasheet at net level: coil pins 2/9, COM 5\&6 (internally doubled), NC\,=\,1\,=\,F9P TX2, NO\,=\,10\,=\,PA9. Q6 is a Rev 1.1 (H2) BEC-map correction --- with the old BCE map it could not sink the 30\,mA coil and Modo-B injection was dead.
+
+% ------------------------------------------------------------------ 4
+\section{Pinout matrices}
+
+\subsection{STM32F411 Blackpill core signals (J1/J2 sockets)}
+SWD is not on the $2{\times}20$ --- flash via USB-C DFU (BOOT0), diagnose via USB CDC STREAM log.
+
+{\small
+\begin{longtable}{@{}llllL{6.1cm}@{}}
+\toprule
+\rowcolor{HelgenIndigo}\textcolor{white}{\textbf{Pin}} & \textcolor{white}{\textbf{Hdr}} & \textcolor{white}{\textbf{Net}} & \textcolor{white}{\textbf{Group}} & \textcolor{white}{\textbf{Function / notes}}\\
+\midrule\endhead
+PA0 & J1 & \net{BAT\_SENSE} & ADC & Pack voltage $\div2$ (R5/R6) --- feeds gauge logic\\
+\rowcolor{HelgenMist} PA1 & J1 & \net{PWR\_CTRL} & Relay/Switch & RTK-stack load-switch enable via Q5$\to$Q1; HIGH = stack ON; pull-down default OFF (invariant \#1)\\
+PA2 & J1 & \net{GNSS\_TX} & UART & USART2 TX $\to$ MOD1 D1 (F9P UART1 RX)\\
+\rowcolor{HelgenMist} PA3 & J1 & \net{GNSS\_RX} & UART & USART2 RX $\gets$ MOD1 D0 (F9P UART1 TX) --- NMEA\\
+PA4 & J1 & \net{5V\_SENSE} & ADC & Vehicle 5\,V present, $\div2$ from \net{VEH5V} (vehicle side --- Block F; on the backed-up rail it would never drop and the cell would drain)\\
+\rowcolor{HelgenMist} PA5 & J1 & \net{IGN\_SENSE} & Ignition & \textbf{Digital} \texttt{INPUT\_PULLDOWN}; raw 12--24\,V $\to$ 22k/10k divider + BAT54 clamp + 100\,nF (Rev 1.1/H3)\\
+PA6 & J1 & \net{FAN\_PWM} & PWM & TIM3\_CH1, 25\,kHz $\to$ Q2 low-side\\
+\rowcolor{HelgenMist} PA7 & J1 & --- & Reserve & Proto-only LM35 channel; unassigned on EinarBoard\\
+PA8 & J2/5 & \net{CHRG\_EN} & LTC status & U6 CHGOFF; HIGH = charge OFF; 100\,k$\Omega$ pull-down = charging enabled if MCU absent (NTC still guards). \emph{Proto TP4056 rig is INVERTED (\net{CHRG\_RUN}) --- firmware flag}\\
+\rowcolor{HelgenMist} PA9 & J2 & \net{USART1\_TX} & UART/Modo-B & $\to$ K1 NO --- \texttt{\$PHLG} injection when K1 energized\\
+PA10 & J2/7 & \net{USART1\_RX} & UART/Modo-B & $\gets$ F9P TX2 (K1 NC node, MOD1 D8) --- passive monitor tap\\
+\rowcolor{HelgenMist} PB0 & J1/14 & \net{EXT\_LED} & GPIO & Status LED low-side (Q4); panel LED on P8\\
+PB1 & J1/15 & \net{NTC\_TEMP} & ADC & ADC1\_IN9 hotspot NTC (R42 10\,k 1\,\% + C24; P12 probe at battery/modem) --- may drive the charge cutoff\\
+\rowcolor{HelgenMist} PB3 & J2/11 & \net{CHRG\_STAT} & LTC status & U6 CHRG open-drain, 100\,k$\uparrow$3V3; LOW = charging ($>$C/8)\\
+PB4 & J2/12 & \net{CHRG\_FAULT} & LTC status & U6 FAULT open-drain, 100\,k$\uparrow$3V3; LOW = NTC/bad-battery fault\\
+\rowcolor{HelgenMist} PB5 & J2/13 & \net{BYP\_CTRL} & Relay control & K1 coil driver via Q6 (BEC map --- Rev 1.1/H2); HIGH = MCU in-line on the uplink; de-energized/absent = NC = corrections direct\\
+PB6 & J2/14 & \net{I2C\_SCL} & I$^2$C & SHT40 (0x44) + TMP102 (0x48), 4.7\,k pulls; P5 probe port\\
+\rowcolor{HelgenMist} PB7 & J2/15 & \net{I2C\_SDA} & I$^2$C & (proto uses AHT10 0x38 \emph{alone} on the bus --- PCB unaffected)\\
+PB10 & J1 & \net{FAN\_TACH} & DNP & 2-wire fans: tach unused; DNP provision (fan fault inferred from temperature)\\
+\rowcolor{HelgenMist} PB12--15 & J2/1--4 & \net{BATLED1--4} & GPIO & Battery gauge 25/50/75/100\,\% (330\,$\Omega$ each)\\
+PC13 & --- & on-module LED & GPIO & WeAct module\\
+\rowcolor{HelgenMist} NRST & J1/5 & \net{NRST} & Reset & SW1 on-board + P10 external, both $\to$ GND\\
+\bottomrule
+\end{longtable}}
+
+\subsection{ArduSimple carrier socket (MOD1) --- incl.\ switchless Pro behavior}
+\label{sec:mod1}
+UNO-form shield socket, pin map \textbf{verified against a physical simpleRTK2B Pro (M3 closed, 2026-07-07)} --- silk reads D0=TX1, D1=RX1, D2=RX2, D3--D7 empty, D8=TX2.
+
+\begin{center}
+\small
+\begin{tabular}{@{}llllL{5.6cm}@{}}
+\toprule
+\rowcolor{HelgenIndigo}\textcolor{white}{\textbf{Shield pin}} & \textcolor{white}{\textbf{F9P signal}} & \textcolor{white}{\textbf{Dir (Pro)}} & \textcolor{white}{\textbf{Carrier net}} & \textcolor{white}{\textbf{Role}}\\
+\midrule
+D0 & TX1 (UART1 TX) & out & \net{GNSS\_RX} $\to$ PA3 & NMEA to the watchdog\\
+\rowcolor{HelgenMist} D1 & RX1 (UART1 RX) & in & \net{GNSS\_TX} $\gets$ PA2 & Watchdog commands/poll\\
+D2 & RX2 (UART2 RX) & in & \net{DOUT\_4G} & \textbf{RTCM3 downlink --- modem-direct, never through the MCU} (silk: \emph{XBEE-TX/GPS RX2})\\
+\rowcolor{HelgenMist} D8 & TX2 (UART2 TX) & out & K1.NC + PA10 tap & Modo-B uplink source (silk: \emph{XBEE-RX/GPS TX2})\\
+5V & shield power & in & \net{SW\_5V} & Pro's ``5V=OUTPUT'' switch \textbf{OFF}\\
+\rowcolor{HelgenMist} IOREF & logic reference & in & \net{3V3} & Defines Pro TX/RX levels\\
+GND $\times3$ & --- & --- & \net{GND} & \\
+\rowcolor{HelgenMist} \multicolumn{5}{@{}L{16.2cm}@{}}{\emph{All other shield positions (3V3, VIN, RESET, A0--A5, D3--D7, D9--D13, AREF, SDA, SCL): NC per ArduSimple guidance --- do not connect unused special pins.}}\\
+\bottomrule
+\end{tabular}
+\end{center}
+
+\paragraph{Switchless Pro variants --- hardwired UART2 behavior.} Pro revisions differ and the difference is operationally critical:
+\begin{itemize}
+\item \textbf{Older Pros} carry an \emph{XBEE TO GPS UART} slide switch --- it must be \textbf{parked on UART1} so the (empty) on-Pro XBee socket does not sit on UART2.
+\item \textbf{Newer Pros have no switch}: the on-Pro XBee socket is \emph{hardwired to UART2}, i.e.\ permanently in parallel with the carrier's D2/D8 rail pins.
+\end{itemize}
+
+\warn{On \textbf{both} revisions the Pro's own XBee socket stays \textbf{EMPTY} --- the modem lives on the carrier's J7/J8. On switchless Pros, \textbf{never plug the Pro's ``USB XBee'' port while the unit is in service}: its FTDI sits directly across UART2 --- that is the live RTCM3 corrections downlink. Bench configuration via that port only with the unit out of service.}
+
+\subsection{XBee socket J7/J8 --- including the J8 mirror map}
+J7 carries module pins 1--10 in order; \textbf{J8 pad $k$ = XBee pin $(21-k)$} --- the mirror is easy to get wrong and was previously undocumented outside the copper.
+
+\begin{center}
+\small
+\begin{tabular}{@{}lllL{5.2cm}@{}}
+\toprule
+\rowcolor{HelgenIndigo}\textcolor{white}{\textbf{Pad}} & \textcolor{white}{\textbf{XBee pin}} & \textcolor{white}{\textbf{Net}} & \textcolor{white}{\textbf{Role}}\\
+\midrule
+J7.1 & 1 VCC & \net{3V3\_MODEM} & 3.3--3.6\,V, 2\,A peak (U7 rail --- \textbf{not 5\,V})\\
+\rowcolor{HelgenMist} J7.2 & 2 TX & \net{DOUT\_4G} & RTCM3 out $\to$ F9P RX2 (direct)\\
+J7.3 & 3 RX & \net{DIN\_4G} & $\gets$ K1 COM (uplink in)\\
+\rowcolor{HelgenMist} J7.4 & 4 GND & \net{GND} & \\
+J7.5 & 5 RESET & \net{MODEM\_RST} & SW4G button $\to$ GND\\
+\rowcolor{HelgenMist} J7.6 & 6 V\_USB & \net{USB\_VBUS} & 5\,V from J9 enables modem USB (laptop-powered only --- no rail backfeed)\\
+J7.7 / J7.8 & 7 USB+ / 8 USB$-$ & \net{USB\_DP}/\net{USB\_DM} & Service USB to J9\\
+\rowcolor{HelgenMist} J7.9 / J7.10 & 9 DTR / 10 GND & NC / \net{GND} & \\
+J8.1 & 20 ON/OFF & \net{GND} & \textbf{GND = always ON} (floating may never power up)\\
+\rowcolor{HelgenMist} J8.5 / J8.9 & 16 RTS / 12 CTS & NC & Flow control disabled\\
+J8.6 / J8.10 & 15 / 11 GND & \net{GND} & \\
+\rowcolor{HelgenMist} J8.7 & 14 VREF & \net{3V3\_MODEM} & \textbf{Must equal VCC}\\
+J8.8 & 13 LED & \net{MODEM\_LED} & 1.8\,V drive $\to$ Rmled 1\,k + D4G (dim --- accepted, audit L4)\\
+\bottomrule
+\end{tabular}
+\end{center}
+
+\subsection{Harness connectors (external interface summary)}
+Full netlist-derived pin tables: \texttt{harness-connector-pinout.md}.
+
+\begin{center}
+\small
+\begin{tabular}{@{}llL{9.8cm}@{}}
+\toprule
+\rowcolor{HelgenIndigo}\textcolor{white}{\textbf{Conn}} & \textcolor{white}{\textbf{Type}} & \textcolor{white}{\textbf{Function / key pins}}\\
+\midrule
+P1 & Phoenix 5-pos & GX16-5: 1=\net{24V\_IN}, 2=\net{GND}, 3=\net{IGN\_IN} (\textbf{raw} 12--24\,V)\\
+\rowcolor{HelgenMist} P2 & XH-2 & \net{VEH5V} in from SD-15B-05\\
+P4 & XH-3 & Battery: 1=\net{BAT\_PLUS}, 2=\net{GND}, 3=\net{NTC} (cell)\\
+\rowcolor{HelgenMist} P5 & XH-4 & External I$^2$C probe (3V3/GND/SDA/SCL)\\
+P6 & XH-4 & Fan: \net{5V\_FAN}/\net{FAN\_RET}/GND/\net{FAN\_TACH\_RAW}\\
+\rowcolor{HelgenMist} P8 & XH-2 & Panel LED (\net{LED\_A}/\net{LED\_K})\\
+P10 & XH-2 & External reset (\net{NRST}/GND)\\
+\rowcolor{HelgenMist} P11 & XH-2 & Cutoff: 1=\net{MAIN5V}, 2=\net{SYS5V} --- \textbf{jumper plug installed when no switch fitted; open P11 = dead board}\\
+P12 & XH-2 & Hotspot NTC probe (\net{NTC\_TEMP}/GND)\\
+\rowcolor{HelgenMist} P3 / P13 / H3 & --- & \textbf{DNP} --- harness alternatives superseded by carrier sockets + K1 bypass\\
+\bottomrule
+\end{tabular}
+\end{center}
+
+% ------------------------------------------------------------------ 5
+\section{PCB fabrication specification}
+\label{sec:fab}
+\begin{center}
+\small
+\begin{tabular}{@{}lL{10.6cm}@{}}
+\toprule
+\rowcolor{HelgenIndigo}\textcolor{white}{\textbf{Parameter}} & \textcolor{white}{\textbf{Specification}}\\
+\midrule
+Stackup & \textbf{4-layer}: F.Cu (signal/power) / In1.Cu (\textbf{solid GND plane}) / In2.Cu (signal) / B.Cu\\
+\rowcolor{HelgenMist} Material & FR-4, \textbf{standard TG150} (JLCPCB 4-layer default stackup)\\
+Thickness / copper & \textbf{1.6\,mm} finished; \textbf{1\,oz} outer copper\\
+\rowcolor{HelgenMist} Finish & \textbf{ENIG} --- required in practice for the QFN-24 (LTC4040), DFN-4 (SHT40), SOT-563 (TMP102) and USB-C fine pitch\\
+Soldermask / silk & \textbf{Blue mask, white silkscreen} (nearest standard to Helgen indigo \#2C3C5B); \textbf{black} is the approved alternate --- no other colors without brand approval\\
+\rowcolor{HelgenMist} Min track/space & 0.15\,mm present on board (JLC 4-layer capability 0.09\,mm)\\
+Netclasses & PWR\_HI \textbf{1.5\,mm} $\cdot$ PWR\_MID \textbf{1.0\,mm} (Rev 1.1/H4 added \net{SW\_IN}) $\cdot$ default 0.2\,mm; exceeds the kicad-guide minimums (5\,V $\geq$ 0.5\,mm, \net{SW\_5V} $\geq$ 0.8\,mm)\\
+\rowcolor{HelgenMist} Impedance & Not controlled --- USB 2.0 FS service port only (audit M5: functional-grade; next spin routes D$\pm$ as a pair + ESD array)\\
+Vias & Tented (default); EP stitching under U6/U2/U7 to In1\\
+\rowcolor{HelgenMist} Mounting & 4$\times$ 3.2\,mm (MH1--4) at 4--5\,mm edge margins --- M3 brass standoffs\\
+Order & 5\,pcs minimum; PCBA = \textbf{Standard} (QFN/fine pitch); SMD by JLC, THT hand-soldered per order guide\\
+\bottomrule
+\end{tabular}
+\end{center}
+
+Fab exports live in \texttt{kicad/production/} (Fabrication Toolkit: Gerbers + BOM.csv + CPL, regenerated \emph{after} the final Rev 1.1 save). The stale \texttt{fab-jlc-usb/} package is superseded --- do not order from it (audit M6).
+
+% ------------------------------------------------------------------ 6
+\section{Schematic --- Rev 1.1 full sheet}
+\label{sec:schematic}
+The complete Rev 1.1 production schematic (all blocks A--K + USB service port, post-audit state: Q7 S/D corrected, Q5/Q6 BEC map, RIG1/RDFU1 22\,k$\Omega$) is reproduced on the following page, exported from \texttt{kicad/hbox-watchdog-v3-PROD.kicad\_sch} \emph{after} the 2026-07-07 closure save. The vector original lives at \texttt{assets/schematic-rev11.pdf} --- zoom there for net-level reading; this page is the archival copy. \textbf{Reminder: sch$\leftrightarrow$board sync on this project is manual (F8 retired)} --- if the schematic changes, the board does not follow automatically.
+
+\includepdf[pages=1,landscape,pagecommand={\thispagestyle{fancy}}]{assets/schematic-rev11.pdf}
+
+% ------------------------------------------------------------------ 7
+\section{PCB layer plots \& assembly view}
+\label{sec:layers}
+Per-layer copper plots of the routed board (135.1$\times$100.1\,mm, 1317 tracks, 249 vias), each with \texttt{Edge.Cuts} overlaid and the KiCad title block, exported from the Rev 1.1 \texttt{.kicad\_pcb}. All plots are viewed \textbf{from the top} (X-ray convention --- B.Cu is \emph{not} mirrored). Originals in \texttt{assets/layers/}.
+
+\begin{center}
+\small
+\begin{tabular}{@{}llL{9.2cm}@{}}
+\toprule
+\rowcolor{HelgenIndigo}\textcolor{white}{\textbf{Page}} & \textcolor{white}{\textbf{Layer}} & \textcolor{white}{\textbf{Content}}\\
+\midrule
+1 & F.Cu & Top copper: power routing (PWR\_HI 1.5\,mm / PWR\_MID 1.0\,mm incl.\ \net{SW\_IN}), module socket fields, LTC4040 block\\
+\rowcolor{HelgenMist} 2 & In1.Cu & Solid GND plane (stitched; EP thermal ties for U6/U2/U7)\\
+3 & In2.Cu & Inner signal (autoroute overflow; no pour --- audit L7)\\
+\rowcolor{HelgenMist} 4 & B.Cu & Bottom copper: signal + sense routing\\
+5 & F.SilkS & Assembly view: silkscreen + outline, DNP footprints crossed out (P3/P13/H3)\\
+\bottomrule
+\end{tabular}
+\end{center}
+
+\includepdf[pages=1,landscape,pagecommand={\thispagestyle{fancy}}]{assets/layers/hbox-watchdog-v3-PROD-F_Cu.pdf}
+\includepdf[pages=1,landscape,pagecommand={\thispagestyle{fancy}}]{assets/layers/hbox-watchdog-v3-PROD-In1_Cu.pdf}
+\includepdf[pages=1,landscape,pagecommand={\thispagestyle{fancy}}]{assets/layers/hbox-watchdog-v3-PROD-In2_Cu.pdf}
+\includepdf[pages=1,landscape,pagecommand={\thispagestyle{fancy}}]{assets/layers/hbox-watchdog-v3-PROD-B_Cu.pdf}
+\includepdf[pages=1,landscape,pagecommand={\thispagestyle{fancy}}]{assets/board-assembly-top.pdf}
+
+% ------------------------------------------------------------------ 8
+\section{Production BOMs (synchronized)}
+\label{sec:boms}
+Both tables below are \textbf{generated} --- do not edit here. Source of truth: \texttt{helgen\_einarboard\_1.0\_production\_bom.xlsx}; regenerate both with \texttt{tools/sync\_bom.py}.
+
+\subsection{Internal PCBA BOM (per board --- JLC order)}
+\IfFileExists{pcba_bom.tex}{\input{pcba_bom.tex}}{\emph{pcba\_bom.tex missing --- run \texttt{python3 tools/sync\_bom.py} first.}}
+
+\subsection{External Integration BOM (per HBOX unit --- Helgen procurement)}
+Everything the unit needs \emph{around} the PCBA: enclosure set (HBOX-135100), the three plug-in modules, antennas, the 1S4P pack, cabinet-side power and panel hardware, and the pre-wired JST harnesses. Order these in parallel with the boards --- module lead times (ArduSimple) usually pace the build, not the PCB.
+
+\IfFileExists{external_bom.tex}{\input{external_bom.tex}}{\emph{external\_bom.tex missing --- run \texttt{python3 tools/sync\_bom.py} first.}}
+
+% ------------------------------------------------------------------ 7
+\section{Assembly \& field warnings}
+\begin{enumerate}
+\item \textbf{Switchless simpleRTK2B Pro variants} --- see \S\ref{sec:mod1}: XBee socket empty on both revisions; switch (if present) parked on UART1; \textbf{never} the Pro's USB-XBee port in service.
+\item \textbf{P11 cutoff} ships with a jumper plug when no panel switch is fitted --- an open P11 is a dead unit that looks like a field failure.
+\item \textbf{GX16 pin 3 = raw ignition.} Harnesses must feed 12--24\,V machine ignition, \emph{not} a pre-conditioned 5\,V (the DFR1015 stage no longer exists).
+\item \textbf{Battery pack}: 1S4P only, cell NTC bonded and wired to P4.3 --- the charger owns that NTC. Verify the 4.00\,V strap set (JP2/3/4) before connecting a pack.
+\item \textbf{Modules are hand-fitted} after PCBA; they are never on the JLC BOM. Seat the Pro with the notch/silk alignment --- D0/D1 reversal is fatal to the GNSS UART and invisible electrically.
+\item \textbf{IP67 discipline}: conduction cooling only; thermal pads from pack/modem hotspot to the enclosure wall; no vents.
+\item \textbf{CPL rotation spot-check} at JLC review: LTC4040 (QFN-24) and both MP1584 (SOIC-8-EP) orientations, plus Q7 --- rotation errors are the \#1 PCBA failure and H1 taught us what a reversed Q7 costs.
+\end{enumerate}
+
+% ------------------------------------------------------------------ 8
+\section{Order readiness \& open gates}
+\label{sec:readiness}
+\begin{itemize}
+\item \textbf{CLEARED:} H1--H4 fixed and re-verified (ERC 0 / DRC 0); M3 closed on a physical Pro; M4 (HBOX mechanical fit) verified 2026-07-07; fab package regenerated after the last save. \textbf{Bare-board order: RELEASED.}
+\item \textbf{OPEN --- M1 remainder (PCBA):} specialty + semiconductor LCSC numbers are verified and baked into the schematic (18 pinned lines); passives ride JLC auto-match at upload; DNP attributes on P3/P13/H3 confirmed in Rev 1.1. Re-confirm live stock at upload --- the pacing item is parts, not fab.
+\item \textbf{OPEN --- M2 (deliberate risk posture):} the declared fab gate --- \emph{bench-validate the LTC4040 backup transition + hot-cell charge cutoff} --- remains unmet by the TP4056 proto. Bare boards at 5\,pcs are the cheap, conscious way to retire it; \textbf{do not commit the 30-unit PCBA run before the LTC4040 block passes on real copper.}
+\item \textbf{Known-accepted:} USB service port is functional-grade (M5); D4G dim at 1.8\,V drive (L4); L7 saturation margin thin vs 2\,A modem peak (L5) --- 3\,A part next spin.
+\end{itemize}
+
+% ------------------------------------------------------------------ APPENDIX
+\section*{Appendix --- BOM synchronization toolchain}
+\textbf{Single source of truth = the Excel workbook.} Flow:
+\begin{enumerate}
+\item \texttt{python3 tools/generate\_production\_bom.py} --- (re)builds \texttt{helgen\_einarboard\_1.0\_production\_bom.xlsx} (Summary + Internal PCBA + External Integration, Helgen palette, live line-cost and cross-sheet roll-up formulas).
+\item Edit costs/parts in Excel as quotes land (or edit the generator and re-run).
+\item \texttt{python3 tools/sync\_bom.py} --- extracts the \emph{Internal PCBA BOM} and \emph{External Integration BOM} tabs, drops section bars / blanks / TOTAL rows, escapes LaTeX reserved tokens (\&, \_, \%, \$, \#, \{\}, \textasciitilde, \textasciicircum, \textbackslash), recomputes line costs, writes \texttt{pcba\_bom.tex} + \texttt{external\_bom.tex}.
+\item \texttt{pdflatex einarboard-manual.tex} $\times2$ --- the manual ingests both snippets via \texttt{\textbackslash input\{\}}.
+\end{enumerate}
+\textbf{Drawing assets} (\texttt{assets/}): \texttt{schematic-rev11.pdf} (full A2 sheet) + \texttt{layers/} (per-layer plots) + \texttt{board-assembly-top.pdf} are exported from the Rev 1.1 KiCad files via kicad-cli (KiCad MCP) --- re-export after \emph{any} board/schematic save, or the manual silently archives stale copper. The Jun-22 \texttt{watchdog-pcb-v3-blockdiagram.svg} predates the carrier conversion and is deliberately \emph{not} included.
+KiCad board $\leftrightarrow$ schematic sync on this project is \textbf{manual} (F8 retired after the refdes-duplication incident) --- never let a BOM edit imply a netlist push.
+
+\vspace{6mm}
+\begin{center}
+{\color{HelgenCyan}\rule{0.6\linewidth}{1.2pt}}\\[2mm]
+{\small\color{HelgenSlate} Helgen Technologies --- precise, fail-safe first. \\ Canonical electrical state: \texttt{watchdog-electrical-design-state.md} $\cdot$ Audit: \texttt{2026-07-06\_Drogheda\_EinarBoard-1.0-PreFab-Audit\_v1.0.md}}
+\end{center}
+
+\end{document}

03-Architecture-Hardware/EinarBoard-Manual/external_bom.tex

@@ -0,0 +1,46 @@
+% AUTO-GENERATED 2026-07-07 by tools/sync_bom.py from helgen_einarboard_1.0_production_bom.xlsx.
+% DO NOT HAND-EDIT — edit the workbook and re-run.
+\begin{small}
+\setlength{\LTleft}{0pt}\setlength{\LTright}{0pt}
+\begin{longtable}{@{}r p{3.4cm} p{7.2cm} p{2.9cm} r r@{}}
+\caption{External Integration BOM --- per HBOX unit (enclosure, modules, pack, panel, harnesses; NOT in the JLC order).}
+\label{tab:ext-bom}\\
+\toprule
+\rowcolor{HelgenIndigo}
+\textcolor{white}{\textbf{Qty}} & \textcolor{white}{\textbf{Part}} & \textcolor{white}{\textbf{Description / notes}} & \textcolor{white}{\textbf{Source / MPN}} & \textcolor{white}{\textbf{Unit\,\$}} & \textcolor{white}{\textbf{Line\,\$}} \\
+\midrule\endfirsthead
+\toprule
+\rowcolor{HelgenIndigo}
+\textcolor{white}{\textbf{Qty}} & \textcolor{white}{\textbf{Part}} & \textcolor{white}{\textbf{Description / notes}} & \textcolor{white}{\textbf{Source / MPN}} & \textcolor{white}{\textbf{Unit\,\$}} & \textcolor{white}{\textbf{Line\,\$}} \\
+\midrule\endhead
+\midrule\multicolumn{6}{r}{\emph{continues}}\\\endfoot
+\endlastfoot
+1 & HBOX-135100 enclosure set & ASA printed base + top + brackets, resized for the 135x100 mm carrier (IP67 strategy: conduction, no vents) \emph{--- Mechanical fit VERIFIED 2026-07-07 (audit M4 closed).} & Helgen in-house (SKU HBOX-135100) & 18.00 & 18.00 \\
+4 & M3 brass standoff M3x10 & Board mount — MH1-MH4, 3.2 mm holes \emph{--- 4-5 mm edge margins per audit.} & generic brass & 0.15 & 0.60 \\
+8 & M3x6 screw, zinc & Standoff top + enclosure boss & generic & 0.03 & 0.24 \\
+1 & Thermal interface pad set & Conduction path: pack/modem hotspot -> enclosure wall \emph{--- Supports canonical invariant \#4.} & generic silicone 1.5 mm & 1.20 & 1.20 \\
+1 & simpleRTK2B Pro (ZED-F9P) & GNSS RTK receiver, seats into MOD1 as UNO shield \emph{--- Switch/switchless revisions — see manual field warnings.} & ArduSimple AS-RTK2B-PROF9P-L1L2-NH-00 & 210.00 & 210.00 \\
+1 & 4G NTRIP Master (XBee LTE) & Corrections modem, seats into J7/J8 (3V3\_MODEM) \emph{--- 2 A peak at 3.3 V (audit L5).} & ArduSimple AS-XBEE-4G-NA-UFL-00 & 155.00 & 155.00 \\
+1 & STM32F411 Blackpill (WeAct) & Watchdog MCU, seats into J1/J2 \emph{--- Flash via USB-C DFU (H1 SWD dropped).} & WeAct STM32F411CEU6 & 6.50 & 6.50 \\
+1 & u-blox multiband GNSS antenna & L1/L2 survey antenna, SMA & ArduSimple AS-ANT2B-ANN-L1L2-50SMA & 65.00 & 65.00 \\
+2 & LTE antenna & 4G blade antenna, u.FL/SMA per modem kit & AR1582 & 8.00 & 16.00 \\
+4 & 18650 Li-ion cell \textasciitilde{}3 Ah & 1S4P pack, 3.6 V nominal — charge 4.00 V strap (cycle life + hot-cell margin, RCA \#1) \emph{--- Pack \textasciitilde{}12 Ah confirmed 2026-06-30.} & quality tier-1 cell (e.g. INR18650) & 4.50 & 18.00 \\
+1 & 1S4P pack hardware & Holder / nickel strip / lead set + heatshrink & generic & 3.00 & 3.00 \\
+1 & Pack NTC 10k B3950 & Bonded to cell, wired to P4.3 (charger-owned NTC) \emph{--- B3380 ideal; B3950 accepted (trip shifts a few degC — bring-up note).} & generic epoxy bead & 0.30 & 0.30 \\
+1 & Mean Well SD-15B-05 & 24->5 V 3 A supply feeding VEH5V (P2) \emph{--- RS1 3.1 A input limit protects this unit.} & Mean Well SD-15B-05 & 14.50 & 14.50 \\
+1 & GX16-5 connector pair & Panel + cable plug: 1=24V\_IN, 2=GND, 3=IGN\_IN (RAW 12-24 V) \emph{--- Pin 3 carries RAW ignition — Rev 1.1 divider (22k/10k) expects it.} & GX16-5 & 2.20 & 2.20 \\
+1 & Panel-mount dual LED & External status indicator, wired to P8 (LED\_A/LED\_K) & generic 8 mm dual-color & 0.80 & 0.80 \\
+1 & Cutoff switch SPST panel & P11 in series MAIN5V->SYS5V — kills vehicle AND battery \emph{--- Ship P11 with jumper plug installed — open P11 = dead board.} & generic 21x15 rocker/toggle & 1.50 & 1.50 \\
+1 & External reset button & Panel momentary NO, wired to P10 (NRST/GND) & generic 12 mm & 0.60 & 0.60 \\
+1 & Fan 5 V 2-wire & Ducted per thermal v3.0 concept; PWM low-side \emph{--- 2-wire: no tach — fan fault inferred from temperature.} & generic 40x40 5 V & 3.50 & 3.50 \\
+1 & External NTC probe 10k B3950 & Cabinet hot-spot probe, wired to P12 & generic sealed probe & 0.50 & 0.50 \\
+5 & JST-XH 2-pin pre-wired harness & P2 5V-IN / P8 panel LED / P10 reset / P11 cutoff / P12 NTC — 22-24 AWG, 300 mm \emph{--- Power pairs (P2/P11) in 22 AWG.} & JST XHP-2 + pre-crimped & 0.35 & 1.75 \\
+1 & JST-XH 3-pin pre-wired harness & P4 battery: BAT+ / GND / NTC — 20 AWG power pair & JST XHP-3 + pre-crimped & 0.40 & 0.40 \\
+2 & JST-XH 4-pin pre-wired harness & P5 I2C probe / P6 fan & JST XHP-4 + pre-crimped & 0.45 & 0.90 \\
+1 & JST-PH pre-wired set (spares) & PH 2.0 mm pigtails for space-constrained sensor drops \emph{--- Optional — XH is the board standard.} & JST PHR-2/3 & 0.40 & 0.40 \\
+1 & Telcel M2M micro-SIM & LTE data for NTRIP corrections \emph{--- Cost = monthly plan, not BOM.} & Telcel M2M plan & 0.00 & 0.00 \\
+\midrule
+\multicolumn{5}{r}{\textbf{TOTAL --- external integration per unit}} & \textbf{520.89} \\
+\bottomrule
+\end{longtable}
+\end{small}

03-Architecture-Hardware/EinarBoard-Manual/pcba_bom.tex

@@ -0,0 +1,83 @@
+% AUTO-GENERATED 2026-07-07 by tools/sync_bom.py from helgen_einarboard_1.0_production_bom.xlsx.
+% DO NOT HAND-EDIT — edit the workbook and re-run.
+\begin{small}
+\setlength{\LTleft}{0pt}\setlength{\LTright}{0pt}
+\begin{longtable}{@{}r p{2.6cm} p{5.4cm} p{1.5cm} p{2.6cm} p{1.7cm} p{1.4cm} r r@{}}
+\caption{Internal PCBA BOM --- per board (synchronized from the production workbook).}
+\label{tab:pcba-bom}\\
+\toprule
+\rowcolor{HelgenIndigo}
+\textcolor{white}{\textbf{Qty}} & \textcolor{white}{\textbf{RefDes}} & \textcolor{white}{\textbf{Description}} & \textcolor{white}{\textbf{Pkg}} & \textcolor{white}{\textbf{Part}} & \textcolor{white}{\textbf{LCSC}} & \textcolor{white}{\textbf{Assy}} & \textcolor{white}{\textbf{Unit\,\$}} & \textcolor{white}{\textbf{Line\,\$}} \\
+\midrule\endfirsthead
+\toprule
+\rowcolor{HelgenIndigo}
+\textcolor{white}{\textbf{Qty}} & \textcolor{white}{\textbf{RefDes}} & \textcolor{white}{\textbf{Description}} & \textcolor{white}{\textbf{Pkg}} & \textcolor{white}{\textbf{Part}} & \textcolor{white}{\textbf{LCSC}} & \textcolor{white}{\textbf{Assy}} & \textcolor{white}{\textbf{Unit\,\$}} & \textcolor{white}{\textbf{Line\,\$}} \\
+\midrule\endhead
+\midrule\multicolumn{9}{r}{\emph{continues}}\\\endfoot
+\endlastfoot
+1 & U6 & Battery-backup manager: 1S Li-ion charger + power-path + 2.5 A boost (Rev 1.1 values: RPROG 825R -> 2.42 A \textasciitilde{} C/5, RS 8 mR -> 3.1 A, F-straps 4.00 V Li-ion) & QFN-24 4x5 & Analog Devices LTC4040EUFD\#TRPBF & C687163 & SMD (JLC) & 6.800 & 6.800 \\
+2 & U2, U7 & Buck 1.5 MHz 3 A — U2: 24 V -> 5V\_FAN; U7: SW\_5V -> 3V3\_MODEM (stack cycle reboots modem) & SOIC-8-EP & MPS MP1584EN-LF-Z & C15051 & SMD (JLC) & 0.550 & 1.100 \\
+1 & U3 & Relative humidity / temperature sensor, I2C 0x44 & DFN-4 1.5x1.5 & Sensirion SHT40-AD1B-R3 & C2848306 & SMD (JLC) & 2.600 & 2.600 \\
+1 & U4 & Temperature sensor +/-0.5 degC, I2C 0x48 (ADD0=GND) & SOT-563 & Texas Instruments TMP102AIDRLR & C99269 & SMD (JLC) & 1.100 & 1.100 \\
+1 & Q7 & N-FET 30 V <=13.6 mR — LTC4040 VIN->VSYS disconnect. Rev 1.1 (H1): S=VIN\_SW, D=MAIN5V (gate=IGATE) & SOIC-8 & AOS AO4406AL & C35349 & SMD (JLC) & 0.280 & 0.280 \\
+1 & Q10 & P-FET -55 V, 24 V reverse-polarity front end (with DzG 15 V gate zener) & TO-252 & Infineon IRFR5305TRPBF & C2624 & SMD (JLC) & 0.650 & 0.650 \\
+1 & Q1 & P-FET -30 V, RTK-stack high-side load switch (SW\_IN -> SW\_5V) & SOT-23 & AOS AO3401A & C15127 & SMD (JLC) & 0.050 & 0.050 \\
+2 & Q2, Q4 & N-FET — fan low-side PWM / status-LED driver & SOT-23 & AOS AO3400A & C20917 & SMD (JLC) & 0.040 & 0.080 \\
+2 & Q5, Q6 & NPN drivers — load-switch / K1 coil. Rev 1.1 (H2): Q\_NPN\_BEC pin map (1=B,2=E,3=C) & SOT-23 & onsemi MMBT3904 & C20526 & SMD (JLC) & 0.020 & 0.040 \\
+1 & K1 & Signal relay SPDT 5 V coil — Modo-B fail-safe bypass, NC = F9P TX2 -> 4G DIN (corrections survive dead MCU) & THT DIP & Omron G5V-1 DC5 & verify at LCSC & THT (hand) & 1.900 & 1.900 \\
+1 & L6 & Power inductor 2.2 uH, Isat 14 A (LTC4040 SW<->BAT) & 8.8x8.2 molded & Sunlord MWSA0804S-2R2MT & C17700165 & SMD (JLC) & 0.350 & 0.350 \\
+2 & L2, L7 & Power inductor 10 uH, Isat 6.5 A (fan buck / modem buck) & 8.8x8.2 molded & Sunlord MWSA0804S-100MT & C17700171 & SMD (JLC) & 0.320 & 0.640 \\
+1 & RS1 & Current-sense resistor 8 mR 1\% 1 W (LTC4040 input limit 3.1 A) & 1206 & FOJAN FRM121WFR008TM & C7420012 & SMD (JLC) & 0.150 & 0.150 \\
+1 & F1 & PPTC resettable fuse 3 A 24 V (SYS5V -> SW\_IN) & 1812 & LUTE 1812L300/24GR & C20627123 & SMD (JLC) & 0.250 & 0.250 \\
+1 & D10 & TVS 33 V 600 W, 24 V input clamp & SMB & Littelfuse SMBJ33A & C224019 & SMD (JLC) & 0.120 & 0.120 \\
+1 & DzG & Zener 15 V (Q10 gate protection) & SOT-23 & onsemi BZX84C15LT1G & C80857 & SMD (JLC) & 0.030 & 0.030 \\
+1 & D5 & Schottky BAT54 — PA5 ignition clamp to 3V3 & SOD-123 & BAT54 & auto-match & SMD (JLC) & 0.020 & 0.020 \\
+1 & D6 & 1N4148W — K1 coil flyback & SOD-123 & 1N4148W & C2099 & SMD (JLC) & 0.010 & 0.010 \\
+3 & D2, Dbk, Dbk2 & Schottky 40 V 3 A — fan flyback / buck freewheel x2 & SMA & SS34 & C8678 & SMD (JLC) & 0.060 & 0.180 \\
+6 & D1, D4G, DB1-DB4 & LED green 0805 — status, modem, 4-LED battery gauge & 0805 & — & C28105 & SMD (JLC) & 0.010 & 0.060 \\
+1 & R50 & 825R — LTC4040 PROG: I\_CHG = 2000/RPROG = 2.42 A \textasciitilde{} C/5 (12 Ah pack) & 0603 & — & Basic auto & SMD (JLC) & 0.010 & 0.010 \\
+1 & R51 & 287k — PFI divider top (VEH5V trip 4.60 V falling) & 0603 & — & Basic auto & SMD (JLC) & 0.010 & 0.010 \\
+1 & R53 & 499k — BSTFB/RSTFB divider top (backup 4.79 V; RST -7.5\%) & 0603 & — & Basic auto & SMD (JLC) & 0.010 & 0.010 \\
+1 & R21 & 19.1k — U2 FB bottom (5V\_FAN = 5.0 V) & 0603 & — & Basic auto & SMD (JLC) & 0.010 & 0.010 \\
+1 & R61 & 31.6k — U7 FB bottom (3V3\_MODEM = 3.33 V) & 0603 & — & Basic auto & SMD (JLC) & 0.010 & 0.010 \\
+3 & R52, R54, R60 & 100k 1\% — PFI / FB dividers & 0603 & — & Basic auto & SMD (JLC) & 0.010 & 0.030 \\
+2 & R42, R55 & 10k 1\% — NTC dividers (PB1 hotspot / LTC4040 NTC bias) & 0603 & — & Basic auto & SMD (JLC) & 0.010 & 0.020 \\
+2 & RIG1, RDFU1 & 22k — ignition divider top (raw 12-24 V) / DFU pull. Rev 1.1 (H3): corrected from stale 100R & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.008 \\
+10 & R2, R5, R6, R7, R8, R41, Rigb, Rled, Rrp, Rtp & 10k — pulls, sense divider halves, Rigb ignition divider bottom & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.040 \\
+8 & R20, R56, R57, R58, Ren1, Rfreq, Rfreq2, Rgs & 100k — FB tops, pulls, FREQ set, EN UVLO top & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.032 \\
+5 & R1, R3, R40, Rts, Rmled & 1k — base drives, LED limits, tach series & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.020 \\
+4 & RB1-RB4 & 330R — battery-gauge LED limits (PB12-PB15) & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.016 \\
+2 & R30, R31 & 4.7k — I2C1 pull-ups (SCL/SDA) & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.008 \\
+2 & Rcomp, Rcomp2 & 40.2k — MP1584 COMP loop & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.008 \\
+2 & Rcc1, Rcc2 & 5.1k — USB-C CC1/CC2 device-mode pulldowns & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.008 \\
+1 & Rg & 100R — Q2 gate series & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.004 \\
+1 & Ren2 & 20k — MP1584 EN UVLO bottom (EN abs-max 6 V — never tie EN to 24 V) & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.004 \\
+7 & C5, C7, C9, C11, C24, Cu3, Cu4 & 100 nF X7R — decoupling, PA5/PB1 filters & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.028 \\
+2 & Cbst, Cbst2 & 10 nF — MP1584 BST bootstrap (U2/U7) & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.008 \\
+2 & Ccomp, Ccomp2 & 2.2 nF — MP1584 COMP & 0603 & — & Basic auto & SMD (JLC) & 0.004 & 0.008 \\
+1 & C31 & 2.2 uF — U6 VIN aux & 0603 & — & Basic auto & SMD (JLC) & 0.010 & 0.010 \\
+2 & C30, C34 & 10 uF X5R — U6 VIN / VSYS & 0805 & — & Basic auto & SMD (JLC) & 0.010 & 0.020 \\
+3 & C35, C40, C41 & 22 uF >=16 V — U6 BAT / U7 in / U7 out & 0805 & — & Basic auto & SMD (JLC) & 0.020 & 0.060 \\
+1 & C23 & 22 uF 16 V — U2 buck out & 0805 & — & Basic auto & SMD (JLC) & 0.020 & 0.020 \\
+1 & C22 & 22 uF 50 V — U2 buck in (24 V node) & 1210 & — & Basic auto & SMD (JLC) & 0.060 & 0.060 \\
+2 & C32, C33 & 47 uF >=25 V low-ESR ceramic — VSYS hold-up (with C34: 104 uF >= datasheet 100 uF min) & 1210 & — & Basic auto & SMD (JLC) & 0.080 & 0.160 \\
+1 & C3 & 47 uF radial electrolytic — SW\_5V bulk & radial 5x7 & — & auto/hand & THT (hand) & 0.030 & 0.030 \\
+1 & C10 & 47 uF 50 V radial — 24 V bulk & radial 6.3x7.7 & — & auto/hand & THT (hand) & 0.040 & 0.040 \\
+1 & C43 & 100 uF 6.3 V radial — 3V3\_MODEM bulk (LTE TX bursts) & radial 6.3x7.7 & — & auto/hand & THT (hand) & 0.040 & 0.040 \\
+1 & J9 & USB-C receptacle USB 2.0 (modem service console: VBUS->J7.6 enables modem USB; no rail backfeed) & SMD 14P & GCT USB4085-GF-A & search USB4085 & THT/SMD (hand rec.) & 0.450 & 0.450 \\
+1 & SW4G & Tactile switch SMD — modem RESET (J7.5 -> GND) & 6x3.5 gull-wing & C\&K PTS636SK25SMTRLFS & C2689642 & SMD (JLC) & 0.150 & 0.150 \\
+1 & SW1 & Tactile 6 mm THT — MCU RESET (NRST -> GND) & THT 6 mm & — & hand & THT (hand) & 0.050 & 0.050 \\
+1 & P1 & Terminal block 5-pos 5.08 mm — GX16 machine power in (24V\_IN / GND / IGN\_IN) & THT & Phoenix MKDS 1,5/5-5,08 & hand & THT (hand) & 1.200 & 1.200 \\
+5 & P2, P8, P10, P11, P12 & JST-XH 2-pin top-entry — 5V-IN, panel LED, ext reset, cutoff switch, hotspot NTC & THT B2B-XH & JST B2B-XH-A & hand & THT (hand) & 0.080 & 0.400 \\
+1 & P4 & JST-XH 3-pin — battery 1S4P: BAT+ / GND / NTC & THT B3B-XH & JST B3B-XH-A & hand & THT (hand) & 0.090 & 0.090 \\
+2 & P5, P6 & JST-XH 4-pin — I2C probe port / fan (5V\_FAN, RET, GND, TACH) & THT B4B-XH & JST B4B-XH-A & hand & THT (hand) & 0.100 & 0.200 \\
+2 & J1, J2 & Female header 1x20 2.54 mm — Blackpill socket & THT & — & hand & THT (hand) & 0.350 & 0.700 \\
+2 & J7, J8 & Female socket 1x10 2.00 mm — XBee 4G socket (rows 22.35 mm) & THT & — & hand & THT (hand) & 0.600 & 1.200 \\
+1 & MOD1 & Arduino-UNO female header kit 10+8+8+6 — simpleRTK2B Pro shield socket & THT 2.54 & — & hand & THT (hand) & 0.900 & 0.900 \\
+0 & P3, P13, H3 & DNP — harness alternatives made redundant by carrier sockets + K1 NC bypass (P3 UART1 tap, P13 Modo-B uplink, H3 USART1 header) & THT & — & — & DNP & 0.000 & 0.000 \\
+0 & JP1 & 0R rail-select option — OPEN by default (dedicated fan buck); close ONLY if SD-15B-05 upsized & 0603 & — & C21189 & DNP & 0.000 & 0.000 \\
+\midrule
+\multicolumn{8}{r}{\textbf{TOTAL --- PCBA parts per board}} & \textbf{22.48} \\
+\bottomrule
+\end{longtable}
+\end{small}

03-Architecture-Hardware/EinarBoard-Manual/tools/generate_production_bom.py

@@ -0,0 +1,355 @@
+#!/usr/bin/env python3
+"""
+generate_production_bom.py — Helgen EinarBoard 1.0 (hbox-watchdog-v3-PROD) Rev 1.1
+Builds helgen_einarboard_1.0_production_bom.xlsx:
+  Tab 1  Summary            — project properties, fab rules, live cross-sheet cost roll-up
+  Tab 2  Internal PCBA BOM  — on-board parts (JLC SMD / hand THT / DNP), live line-cost formulas
+  Tab 3  External Integration BOM — enclosure, modules, pack, harnesses, hardware
+
+Source of truth: Assembly-BOM-Split.md + LCSC-search-list.md (2026-07-06, verified vs JLC live
+stock) + 2026-07-06 Pre-Fab Audit closure (Rev 1.1: RIG1/RDFU1 = 22k, Q5/Q6 = BEC map, Q7 S/D
+corrected). Re-confirm LCSC stock at upload — stock moves.
+
+Usage: python3 generate_production_bom.py [outdir]   (default: parent of tools/)
+"""
+import sys
+from datetime import date
+from pathlib import Path
+
+from openpyxl import Workbook
+from openpyxl.styles import Alignment, Border, Font, PatternFill, Side
+from openpyxl.utils import get_column_letter
+
+# ---------------------------------------------------------------- Helgen palette
+INDIGO = "2C3C5B"   # primary (brand)
+SLATE  = "44597A"   # secondary panel
+CYAN   = "51F3DA"   # accent (brand)
+MIST   = "EAEFF5"   # row banding
+WHITE  = "FFFFFF"
+DARK   = "1B2436"
+
+F_TITLE  = Font(name="Calibri", size=16, bold=True, color=INDIGO)
+F_SUB    = Font(name="Calibri", size=10, italic=True, color=SLATE)
+F_HDR    = Font(name="Calibri", size=10, bold=True, color=WHITE)
+F_SEC    = Font(name="Calibri", size=11, bold=True, color=WHITE)
+F_BODY   = Font(name="Calibri", size=10, color=DARK)
+F_BOLD   = Font(name="Calibri", size=10, bold=True, color=INDIGO)
+F_TOTAL  = Font(name="Calibri", size=11, bold=True, color=INDIGO)
+FILL_HDR = PatternFill("solid", fgColor=INDIGO)
+FILL_SEC = PatternFill("solid", fgColor=SLATE)
+FILL_ACC = PatternFill("solid", fgColor=CYAN)
+FILL_BAND= PatternFill("solid", fgColor=MIST)
+FILL_TOT = PatternFill("solid", fgColor=CYAN)
+THIN     = Side(style="thin", color="B9C4D6")
+B_ALL    = Border(left=THIN, right=THIN, top=THIN, bottom=THIN)
+A_L = Alignment(horizontal="left",   vertical="center", wrap_text=True)
+A_C = Alignment(horizontal="center", vertical="center", wrap_text=True)
+A_R = Alignment(horizontal="right",  vertical="center")
+
+MONEY3 = '"$"#,##0.000'
+MONEY2 = '"$"#,##0.00'
+
+def style_header_row(ws, row, ncols):
+    for c in range(1, ncols + 1):
+        cell = ws.cell(row=row, column=c)
+        cell.font, cell.fill, cell.border, cell.alignment = F_HDR, FILL_HDR, B_ALL, A_C
+
+def section_bar(ws, row, ncols, text):
+    ws.cell(row=row, column=1, value=text)
+    ws.merge_cells(start_row=row, start_column=1, end_row=row, end_column=ncols)
+    c = ws.cell(row=row, column=1)
+    c.font, c.fill, c.alignment = F_SEC, FILL_SEC, A_L
+
+# ================================================================ Tab 2 — Internal PCBA BOM
+# (qty, refdes, description, package, manufacturer, mpn, lcsc, assy, unit_usd, notes)
+PCBA = [
+    ("— Active / power semiconductors —",),
+    (1, "U6",  "Battery-backup manager: 1S Li-ion charger + power-path + 2.5 A boost (Rev 1.1 values: RPROG 825R -> 2.42 A ~ C/5, RS 8 mR -> 3.1 A, F-straps 4.00 V Li-ion)", "QFN-24 4x5", "Analog Devices", "LTC4040EUFD#TRPBF", "C687163", "SMD (JLC)", 6.80, "Ext part, stock 2341 (2026-07-06). EP = GND stitch."),
+    (2, "U2, U7", "Buck 1.5 MHz 3 A — U2: 24 V -> 5V_FAN; U7: SW_5V -> 3V3_MODEM (stack cycle reboots modem)", "SOIC-8-EP", "MPS", "MP1584EN-LF-Z", "C15051", "SMD (JLC)", 0.55, "Only in-stock LCSC variant — do not let auto-match pick a 0-stock clone."),
+    (1, "U3",  "Relative humidity / temperature sensor, I2C 0x44", "DFN-4 1.5x1.5", "Sensirion", "SHT40-AD1B-R3", "C2848306", "SMD (JLC)", 2.60, "R2 alt: C2909890."),
+    (1, "U4",  "Temperature sensor +/-0.5 degC, I2C 0x48 (ADD0=GND)", "SOT-563", "Texas Instruments", "TMP102AIDRLR", "C99269", "SMD (JLC)", 1.10, "UMW clone alt: C5692997."),
+    (1, "Q7",  "N-FET 30 V <=13.6 mR — LTC4040 VIN->VSYS disconnect. Rev 1.1 (H1): S=VIN_SW, D=MAIN5V (gate=IGATE)", "SOIC-8", "AOS", "AO4406AL", "C35349", "SMD (JLC)", 0.28, "Orientation is the audit's board-killer #1 — verify at CPL review."),
+    (1, "Q10", "P-FET -55 V, 24 V reverse-polarity front end (with DzG 15 V gate zener)", "TO-252", "Infineon", "IRFR5305TRPBF", "C2624", "SMD (JLC)", 0.65, ""),
+    (1, "Q1",  "P-FET -30 V, RTK-stack high-side load switch (SW_IN -> SW_5V)", "SOT-23", "AOS", "AO3401A", "C15127", "SMD (JLC)", 0.05, "JLC Basic."),
+    (2, "Q2, Q4", "N-FET — fan low-side PWM / status-LED driver", "SOT-23", "AOS", "AO3400A", "C20917", "SMD (JLC)", 0.04, "JLC Basic."),
+    (2, "Q5, Q6", "NPN drivers — load-switch / K1 coil. Rev 1.1 (H2): Q_NPN_BEC pin map (1=B,2=E,3=C)", "SOT-23", "onsemi", "MMBT3904", "C20526", "SMD (JLC)", 0.02, "JLC Basic. BCE symbol on this part was audit finding H2."),
+    ("— Relay, protection, inductors —",),
+    (1, "K1",  "Signal relay SPDT 5 V coil — Modo-B fail-safe bypass, NC = F9P TX2 -> 4G DIN (corrections survive dead MCU)", "THT DIP", "Omron", "G5V-1 DC5", "verify at LCSC", "THT (hand)", 1.90, "Coil pins 2/9; COM 5&6 doubled; NC=1. Verified vs Omron K048-E1-07."),
+    (1, "L6",  "Power inductor 2.2 uH, Isat 14 A (LTC4040 SW<->BAT)", "8.8x8.2 molded", "Sunlord", "MWSA0804S-2R2MT", "C17700165", "SMD (JLC)", 0.35, "SUB for Bourns SRU8028-2R2Y (JLC out of stock) — pad overlap verified rule: confirm before commit."),
+    (2, "L2, L7", "Power inductor 10 uH, Isat 6.5 A (fan buck / modem buck)", "8.8x8.2 molded", "Sunlord", "MWSA0804S-100MT", "C17700171", "SMD (JLC)", 0.32, "SUB for SRU8028-100Y. L7 margin vs 2 A modem peak = audit L5 (OK, thin)."),
+    (1, "RS1", "Current-sense resistor 8 mR 1% 1 W (LTC4040 input limit 3.1 A)", "1206", "FOJAN", "FRM121WFR008TM", "C7420012", "SMD (JLC)", 0.15, "Premium alt: Vishay WSLP C2076276."),
+    (1, "F1",  "PPTC resettable fuse 3 A 24 V (SYS5V -> SW_IN)", "1812", "LUTE", "1812L300/24GR", "C20627123", "SMD (JLC)", 0.25, "If node <=6 V: genuine Littelfuse C127824."),
+    (1, "D10", "TVS 33 V 600 W, 24 V input clamp", "SMB", "Littelfuse", "SMBJ33A", "C224019", "SMD (JLC)", 0.12, "Cheap alt: C353366."),
+    (1, "DzG", "Zener 15 V (Q10 gate protection)", "SOT-23", "onsemi", "BZX84C15LT1G", "C80857", "SMD (JLC)", 0.03, ""),
+    (1, "D5",  "Schottky BAT54 — PA5 ignition clamp to 3V3", "SOD-123", "—", "BAT54", "auto-match", "SMD (JLC)", 0.02, "Left to JLC auto-match on purpose (ambiguous variants)."),
+    (1, "D6",  "1N4148W — K1 coil flyback", "SOD-123", "—", "1N4148W", "C2099", "SMD (JLC)", 0.01, ""),
+    (3, "D2, Dbk, Dbk2", "Schottky 40 V 3 A — fan flyback / buck freewheel x2", "SMA", "—", "SS34", "C8678", "SMD (JLC)", 0.06, "JLC Basic."),
+    (6, "D1, D4G, DB1-DB4", "LED green 0805 — status, modem, 4-LED battery gauge", "0805", "—", "—", "C28105", "SMD (JLC)", 0.01, "Single SKU by design; recolor D4G/gauge in JLC BOM editor if desired. D4G dim @1.8 V drive (audit L4 — accepted)."),
+    ("— Precision resistors (0603, 1%) —",),
+    (1, "R50", "825R — LTC4040 PROG: I_CHG = 2000/RPROG = 2.42 A ~ C/5 (12 Ah pack)", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.010, "Critical value — do not substitute."),
+    (1, "R51", "287k — PFI divider top (VEH5V trip 4.60 V falling)", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.010, "With R52 100k."),
+    (1, "R53", "499k — BSTFB/RSTFB divider top (backup 4.79 V; RST -7.5%)", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.010, "With R54 100k; shared divider is datasheet-endorsed."),
+    (1, "R21", "19.1k — U2 FB bottom (5V_FAN = 5.0 V)", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.010, ""),
+    (1, "R61", "31.6k — U7 FB bottom (3V3_MODEM = 3.33 V)", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.010, ""),
+    (3, "R52, R54, R60", "100k 1% — PFI / FB dividers", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.010, ""),
+    (2, "R42, R55", "10k 1% — NTC dividers (PB1 hotspot / LTC4040 NTC bias)", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.010, "R55 low-drift; B3950 NTC trip shift noted at bring-up."),
+    ("— Standard resistors (0603, 5%) —",),
+    (2, "RIG1, RDFU1", "22k — ignition divider top (raw 12-24 V) / DFU pull. Rev 1.1 (H3): corrected from stale 100R", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, "100R here burns D5 + Rig at 24 V ignition — audit board-killer #3."),
+    (10, "R2, R5, R6, R7, R8, R41, Rigb, Rled, Rrp, Rtp", "10k — pulls, sense divider halves, Rigb ignition divider bottom", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, ""),
+    (8, "R20, R56, R57, R58, Ren1, Rfreq, Rfreq2, Rgs", "100k — FB tops, pulls, FREQ set, EN UVLO top", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, ""),
+    (5, "R1, R3, R40, Rts, Rmled", "1k — base drives, LED limits, tach series", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, ""),
+    (4, "RB1-RB4", "330R — battery-gauge LED limits (PB12-PB15)", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, ""),
+    (2, "R30, R31", "4.7k — I2C1 pull-ups (SCL/SDA)", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, ""),
+    (2, "Rcomp, Rcomp2", "40.2k — MP1584 COMP loop", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, "Bench-tune placeholder per delta doc."),
+    (2, "Rcc1, Rcc2", "5.1k — USB-C CC1/CC2 device-mode pulldowns", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, ""),
+    (1, "Rg",   "100R — Q2 gate series", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, ""),
+    (1, "Ren2", "20k — MP1584 EN UVLO bottom (EN abs-max 6 V — never tie EN to 24 V)", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, ""),
+    ("— Capacitors —",),
+    (7, "C5, C7, C9, C11, C24, Cu3, Cu4", "100 nF X7R — decoupling, PA5/PB1 filters", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, ""),
+    (2, "Cbst, Cbst2", "10 nF — MP1584 BST bootstrap (U2/U7)", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, ""),
+    (2, "Ccomp, Ccomp2", "2.2 nF — MP1584 COMP", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.004, ""),
+    (1, "C31", "2.2 uF — U6 VIN aux", "0603", "—", "—", "Basic auto", "SMD (JLC)", 0.01, ""),
+    (2, "C30, C34", "10 uF X5R — U6 VIN / VSYS", "0805", "—", "—", "Basic auto", "SMD (JLC)", 0.01, ""),
+    (3, "C35, C40, C41", "22 uF >=16 V — U6 BAT / U7 in / U7 out", "0805", "—", "—", "Basic auto", "SMD (JLC)", 0.02, ""),
+    (1, "C23", "22 uF 16 V — U2 buck out", "0805", "—", "—", "Basic auto", "SMD (JLC)", 0.02, ""),
+    (1, "C22", "22 uF 50 V — U2 buck in (24 V node)", "1210", "—", "—", "Basic auto", "SMD (JLC)", 0.06, "Voltage rating critical."),
+    (2, "C32, C33", "47 uF >=25 V low-ESR ceramic — VSYS hold-up (with C34: 104 uF >= datasheet 100 uF min)", "1210", "—", "—", "Basic auto", "SMD (JLC)", 0.08, ""),
+    (1, "C3",  "47 uF radial electrolytic — SW_5V bulk", "radial 5x7", "—", "—", "auto/hand", "THT (hand)", 0.03, ""),
+    (1, "C10", "47 uF 50 V radial — 24 V bulk", "radial 6.3x7.7", "—", "—", "auto/hand", "THT (hand)", 0.04, ""),
+    (1, "C43", "100 uF 6.3 V radial — 3V3_MODEM bulk (LTE TX bursts)", "radial 6.3x7.7", "—", "—", "auto/hand", "THT (hand)", 0.04, "Verify body fit under shield."),
+    ("— USB service port + switches —",),
+    (1, "J9",  "USB-C receptacle USB 2.0 (modem service console: VBUS->J7.6 enables modem USB; no rail backfeed)", "SMD 14P", "GCT", "USB4085-GF-A", "search USB4085", "THT/SMD (hand rec.)", 0.45, "Hand-solder recommended per order guide."),
+    (1, "SW4G", "Tactile switch SMD — modem RESET (J7.5 -> GND)", "6x3.5 gull-wing", "C&K", "PTS636SK25SMTRLFS", "C2689642", "SMD (JLC)", 0.15, "Confirm pads vs footprint."),
+    (1, "SW1", "Tactile 6 mm THT — MCU RESET (NRST -> GND)", "THT 6 mm", "—", "—", "hand", "THT (hand)", 0.05, ""),
+    ("— Connectors & module sockets (THT, hand-solder per order guide) —",),
+    (1, "P1",  "Terminal block 5-pos 5.08 mm — GX16 machine power in (24V_IN / GND / IGN_IN)", "THT", "Phoenix", "MKDS 1,5/5-5,08", "hand", "THT (hand)", 1.20, ""),
+    (5, "P2, P8, P10, P11, P12", "JST-XH 2-pin top-entry — 5V-IN, panel LED, ext reset, cutoff switch, hotspot NTC", "THT B2B-XH", "JST", "B2B-XH-A", "hand", "THT (hand)", 0.08, ""),
+    (1, "P4",  "JST-XH 3-pin — battery 1S4P: BAT+ / GND / NTC", "THT B3B-XH", "JST", "B3B-XH-A", "hand", "THT (hand)", 0.09, ""),
+    (2, "P5, P6", "JST-XH 4-pin — I2C probe port / fan (5V_FAN, RET, GND, TACH)", "THT B4B-XH", "JST", "B4B-XH-A", "hand", "THT (hand)", 0.10, ""),
+    (2, "J1, J2", "Female header 1x20 2.54 mm — Blackpill socket", "THT", "—", "—", "hand", "THT (hand)", 0.35, ""),
+    (2, "J7, J8", "Female socket 1x10 2.00 mm — XBee 4G socket (rows 22.35 mm)", "THT", "—", "—", "hand", "THT (hand)", 0.60, ""),
+    (1, "MOD1", "Arduino-UNO female header kit 10+8+8+6 — simpleRTK2B Pro shield socket", "THT 2.54", "—", "—", "hand", "THT (hand)", 0.90, ""),
+    ("— DNP / options (populate cost = 0) —",),
+    (0, "P3, P13, H3", "DNP — harness alternatives made redundant by carrier sockets + K1 NC bypass (P3 UART1 tap, P13 Modo-B uplink, H3 USART1 header)", "THT", "—", "—", "—", "DNP", 0.00, "Real DNP attribute set in board rev 1.1; drop rows before JLC upload."),
+    (0, "JP1", "0R rail-select option — OPEN by default (dedicated fan buck); close ONLY if SD-15B-05 upsized", "0603", "—", "—", "C21189", "DNP", 0.00, "JP2/JP3/JP4 = copper solder jumpers, F-straps 4.00 V Li-ion — no BOM part."),
+]
+
+PCBA_HEADERS = ["Item", "Qty", "RefDes", "Description", "Package", "Manufacturer",
+                "MPN", "JLCPCB / LCSC", "Assembly", "Est. Unit Cost (USD)",
+                "Line Cost (USD)", "Notes"]
+
+def build_pcba(ws):
+    ws.sheet_view.showGridLines = False
+    ws.cell(row=1, column=1, value="EinarBoard 1.0 — Internal PCBA BOM (on-board, per board)").font = F_TITLE
+    ws.cell(row=2, column=1, value="Rev 1.1 Post-Audit Production Master · 132 footprints · LCSC verified vs JLC live stock 2026-07-06 — re-confirm at upload").font = F_SUB
+    hdr_row = 4
+    for c, h in enumerate(PCBA_HEADERS, 1):
+        ws.cell(row=hdr_row, column=c, value=h)
+    style_header_row(ws, hdr_row, len(PCBA_HEADERS))
+    r, item, band = hdr_row + 1, 1, False
+    first_data, last_data = None, None
+    for row in PCBA:
+        if len(row) == 1:                       # section bar
+            section_bar(ws, r, len(PCBA_HEADERS), row[0]); r += 1; band = False
+            continue
+        qty, refs, desc, pkg, mfr, mpn, lcsc, assy, unit, notes = row
+        vals = [item, qty, refs, desc, pkg, mfr, mpn, lcsc, assy, unit,
+                f"=B{r}*J{r}", notes]
+        for c, v in enumerate(vals, 1):
+            cell = ws.cell(row=r, column=c, value=v)
+            cell.font, cell.border = F_BODY, B_ALL
+            cell.alignment = A_C if c in (1, 2, 5, 8, 9) else A_L
+            if band:
+                cell.fill = FILL_BAND
+        ws.cell(row=r, column=10).number_format = MONEY3
+        ws.cell(row=r, column=11).number_format = MONEY3
+        ws.cell(row=r, column=10).alignment = A_R
+        ws.cell(row=r, column=11).alignment = A_R
+        if first_data is None:
+            first_data = r
+        last_data = r
+        item += 1; r += 1; band = not band
+    # TOTAL row
+    ws.cell(row=r, column=4, value="TOTAL — PCBA parts per board").font = F_TOTAL
+    tc = ws.cell(row=r, column=11, value=f"=SUM(K{first_data}:K{last_data})")
+    tc.font, tc.number_format, tc.alignment = F_TOTAL, MONEY2, A_R
+    for c in range(1, len(PCBA_HEADERS) + 1):
+        ws.cell(row=r, column=c).fill = FILL_TOT
+        ws.cell(row=r, column=c).border = B_ALL
+    widths = [6, 6, 24, 58, 14, 16, 22, 16, 13, 12, 12, 44]
+    for c, w in enumerate(widths, 1):
+        ws.column_dimensions[get_column_letter(c)].width = w
+    ws.freeze_panes = f"A{hdr_row + 1}"
+    ws.auto_filter.ref = f"A{hdr_row}:L{last_data}"
+    return r  # total row index
+
+# ================================================================ Tab 3 — External Integration BOM
+EXT = [
+    ("— Enclosure & mechanical —",),
+    (1, "HBOX-135100 enclosure set", "ASA printed base + top + brackets, resized for the 135x100 mm carrier (IP67 strategy: conduction, no vents)", "Helgen in-house (SKU HBOX-135100)", 18.00, "Mechanical fit VERIFIED 2026-07-07 (audit M4 closed)."),
+    (4, "M3 brass standoff M3x10", "Board mount — MH1-MH4, 3.2 mm holes", "generic brass", 0.15, "4-5 mm edge margins per audit."),
+    (8, "M3x6 screw, zinc", "Standoff top + enclosure boss", "generic", 0.03, ""),
+    (1, "Thermal interface pad set", "Conduction path: pack/modem hotspot -> enclosure wall", "generic silicone 1.5 mm", 1.20, "Supports canonical invariant #4."),
+    ("— Plug-in modules (installed by Helgen, NEVER on the JLC BOM) —",),
+    (1, "simpleRTK2B Pro (ZED-F9P)", "GNSS RTK receiver, seats into MOD1 as UNO shield", "ArduSimple AS-RTK2B-PROF9P-L1L2-NH-00", 210.00, "Switch/switchless revisions — see manual field warnings."),
+    (1, "4G NTRIP Master (XBee LTE)", "Corrections modem, seats into J7/J8 (3V3_MODEM)", "ArduSimple AS-XBEE-4G-NA-UFL-00", 155.00, "2 A peak at 3.3 V (audit L5)."),
+    (1, "STM32F411 Blackpill (WeAct)", "Watchdog MCU, seats into J1/J2", "WeAct STM32F411CEU6", 6.50, "Flash via USB-C DFU (H1 SWD dropped)."),
+    ("— Antennas & RF —",),
+    (1, "u-blox multiband GNSS antenna", "L1/L2 survey antenna, SMA", "ArduSimple AS-ANT2B-ANN-L1L2-50SMA", 65.00, ""),
+    (2, "LTE antenna", "4G blade antenna, u.FL/SMA per modem kit", "AR1582", 8.00, ""),
+    ("— Battery pack (1S4P ~12 Ah) —",),
+    (4, "18650 Li-ion cell ~3 Ah", "1S4P pack, 3.6 V nominal — charge 4.00 V strap (cycle life + hot-cell margin, RCA #1)", "quality tier-1 cell (e.g. INR18650)", 4.50, "Pack ~12 Ah confirmed 2026-06-30."),
+    (1, "1S4P pack hardware", "Holder / nickel strip / lead set + heatshrink", "generic", 3.00, ""),
+    (1, "Pack NTC 10k B3950", "Bonded to cell, wired to P4.3 (charger-owned NTC)", "generic epoxy bead", 0.30, "B3380 ideal; B3950 accepted (trip shifts a few degC — bring-up note)."),
+    ("— Cabinet-side power & panel —",),
+    (1, "Mean Well SD-15B-05", "24->5 V 3 A supply feeding VEH5V (P2)", "Mean Well SD-15B-05", 14.50, "RS1 3.1 A input limit protects this unit."),
+    (1, "GX16-5 connector pair", "Panel + cable plug: 1=24V_IN, 2=GND, 3=IGN_IN (RAW 12-24 V)", "GX16-5", 2.20, "Pin 3 carries RAW ignition — Rev 1.1 divider (22k/10k) expects it."),
+    (1, "Panel-mount dual LED", "External status indicator, wired to P8 (LED_A/LED_K)", "generic 8 mm dual-color", 0.80, ""),
+    (1, "Cutoff switch SPST panel", "P11 in series MAIN5V->SYS5V — kills vehicle AND battery", "generic 21x15 rocker/toggle", 1.50, "Ship P11 with jumper plug installed — open P11 = dead board."),
+    (1, "External reset button", "Panel momentary NO, wired to P10 (NRST/GND)", "generic 12 mm", 0.60, ""),
+    (1, "Fan 5 V 2-wire", "Ducted per thermal v3.0 concept; PWM low-side", "generic 40x40 5 V", 3.50, "2-wire: no tach — fan fault inferred from temperature."),
+    (1, "External NTC probe 10k B3950", "Cabinet hot-spot probe, wired to P12", "generic sealed probe", 0.50, ""),
+    ("— Pre-wired harnesses (JST) —",),
+    (5, "JST-XH 2-pin pre-wired harness", "P2 5V-IN / P8 panel LED / P10 reset / P11 cutoff / P12 NTC — 22-24 AWG, 300 mm", "JST XHP-2 + pre-crimped", 0.35, "Power pairs (P2/P11) in 22 AWG."),
+    (1, "JST-XH 3-pin pre-wired harness", "P4 battery: BAT+ / GND / NTC — 20 AWG power pair", "JST XHP-3 + pre-crimped", 0.40, ""),
+    (2, "JST-XH 4-pin pre-wired harness", "P5 I2C probe / P6 fan", "JST XHP-4 + pre-crimped", 0.45, ""),
+    (1, "JST-PH pre-wired set (spares)", "PH 2.0 mm pigtails for space-constrained sensor drops", "JST PHR-2/3", 0.40, "Optional — XH is the board standard."),
+    ("— Connectivity —",),
+    (1, "Telcel M2M micro-SIM", "LTE data for NTRIP corrections", "Telcel M2M plan", 0.00, "Cost = monthly plan, not BOM."),
+]
+
+EXT_HEADERS = ["Item", "Qty / unit", "Part", "Description", "Source / MPN",
+               "Est. Unit Cost (USD)", "Line Cost (USD)", "Notes"]
+
+def build_ext(ws):
+    ws.sheet_view.showGridLines = False
+    ws.cell(row=1, column=1, value="EinarBoard 1.0 — External Integration BOM (per HBOX unit)").font = F_TITLE
+    ws.cell(row=2, column=1, value="Secondary assembly: enclosure, plug-in modules, pack, panel hardware, harnesses — NOT in the JLC order").font = F_SUB
+    hdr_row = 4
+    for c, h in enumerate(EXT_HEADERS, 1):
+        ws.cell(row=hdr_row, column=c, value=h)
+    style_header_row(ws, hdr_row, len(EXT_HEADERS))
+    r, item, band = hdr_row + 1, 1, False
+    first_data, last_data = None, None
+    for row in EXT:
+        if len(row) == 1:
+            section_bar(ws, r, len(EXT_HEADERS), row[0]); r += 1; band = False
+            continue
+        qty, part, desc, src, unit, notes = row
+        vals = [item, qty, part, desc, src, unit, f"=B{r}*F{r}", notes]
+        for c, v in enumerate(vals, 1):
+            cell = ws.cell(row=r, column=c, value=v)
+            cell.font, cell.border = F_BODY, B_ALL
+            cell.alignment = A_C if c in (1, 2) else A_L
+            if band:
+                cell.fill = FILL_BAND
+        ws.cell(row=r, column=6).number_format = MONEY2
+        ws.cell(row=r, column=7).number_format = MONEY2
+        ws.cell(row=r, column=6).alignment = A_R
+        ws.cell(row=r, column=7).alignment = A_R
+        if first_data is None:
+            first_data = r
+        last_data = r
+        item += 1; r += 1; band = not band
+    ws.cell(row=r, column=4, value="TOTAL — external integration per unit").font = F_TOTAL
+    tc = ws.cell(row=r, column=7, value=f"=SUM(G{first_data}:G{last_data})")
+    tc.font, tc.number_format, tc.alignment = F_TOTAL, MONEY2, A_R
+    for c in range(1, len(EXT_HEADERS) + 1):
+        ws.cell(row=r, column=c).fill = FILL_TOT
+        ws.cell(row=r, column=c).border = B_ALL
+    widths = [6, 9, 30, 56, 30, 13, 12, 46]
+    for c, w in enumerate(widths, 1):
+        ws.column_dimensions[get_column_letter(c)].width = w
+    ws.freeze_panes = f"A{hdr_row + 1}"
+    ws.auto_filter.ref = f"A{hdr_row}:H{last_data}"
+    return r
+
+# ================================================================ Tab 1 — Summary dashboard
+def build_summary(ws, pcba_total_row, ext_total_row):
+    ws.sheet_view.showGridLines = False
+    ws.cell(row=1, column=2, value="HELGEN EINARBOARD 1.0").font = Font(name="Calibri", size=22, bold=True, color=INDIGO)
+    ws.cell(row=2, column=2, value="HBOX RTK Watchdog Carrier — Production BOM Workbook · Rev 1.1 Post-Audit Production Master").font = F_SUB
+    ws.cell(row=3, column=2, value=f"Generated {date.today().isoformat()} · Project Drogheda (GPS RTK) · Helgen Technologies").font = F_SUB
+    for c in range(1, 9):
+        ws.cell(row=4, column=c).fill = FILL_ACC
+
+    props = [
+        ("Assembly", "Helgen EinarBoard 1.0 (EINARBoard HBOX 1.0)"),
+        ("KiCad project", "kicad/hbox-watchdog-v3-PROD.kicad_pcb"),
+        ("Revision", "1.1 — Post-Audit Production Master (H1-H4 fixed, M3/M4 closed 2026-07-07)"),
+        ("Board", "135.1 x 100.1 mm · 132 footprints · 130 nets"),
+        ("Verification", "ERC 0 errors · DRC 0 errors / 0 unconnected · fab package regenerated after last save"),
+        ("Order status", "Bare-board RELEASED · PCBA gated by M1 remainder (passives auto-match) + M2 (LTC4040 bench validation)"),
+        ("Modules (plug-in)", "Blackpill -> J1/J2 · simpleRTK2B Pro -> MOD1 · 4G NTRIP Master -> J7/J8 — never on the JLC BOM"),
+    ]
+    fab = [
+        ("Layers", "4 — F.Cu / In1.Cu (solid GND) / In2.Cu / B.Cu"),
+        ("Material / TG", "FR-4, standard TG150 (JLC 4-layer default)"),
+        ("Thickness / copper", "1.6 mm · 1 oz outer"),
+        ("Surface finish", "ENIG (QFN-24 + DFN + SOT-563 fine pitch)"),
+        ("Soldermask / silk", "Blue mask, white silk (Helgen indigo family; black = approved alternate)"),
+        ("Min track/space", "0.15 mm present (JLC 4-layer capability 0.09 mm)"),
+        ("Netclasses", "PWR_HI 1.5 mm · PWR_MID 1.0 mm (SW_IN in PWR_MID per Rev 1.1/H4)"),
+        ("Impedance control", "No (USB 2.0 FS service port only)"),
+        ("Vias", "Tented (default)"),
+        ("PCBA type", "Standard (QFN/fine-pitch) · SMD by JLC, THT hand-soldered"),
+    ]
+
+    r = 6
+    section_bar(ws, r, 8, "PROJECT PROPERTIES"); r += 1
+    for k, v in props:
+        ws.cell(row=r, column=2, value=k).font = F_BOLD
+        ws.cell(row=r, column=3, value=v).font = F_BODY
+        ws.merge_cells(start_row=r, start_column=3, end_row=r, end_column=8)
+        ws.cell(row=r, column=3).alignment = A_L
+        r += 1
+    r += 1
+    section_bar(ws, r, 8, "TARGET FABRICATION RULES (JLCPCB)"); r += 1
+    for k, v in fab:
+        ws.cell(row=r, column=2, value=k).font = F_BOLD
+        ws.cell(row=r, column=3, value=v).font = F_BODY
+        ws.merge_cells(start_row=r, start_column=3, end_row=r, end_column=8)
+        ws.cell(row=r, column=3).alignment = A_L
+        r += 1
+    r += 1
+    section_bar(ws, r, 8, "LIVE COST ROLL-UP (cross-sheet formulas)"); r += 1
+    qty_row = r
+    ws.cell(row=r, column=2, value="Build quantity (boards / units)").font = F_BOLD
+    qc = ws.cell(row=r, column=4, value=5)
+    qc.font, qc.fill, qc.border, qc.alignment = F_TOTAL, FILL_ACC, B_ALL, A_C
+    ws.cell(row=r, column=5, value="<- edit: JLC min 5; fleet target 30 by Aug").font = F_SUB
+    r += 1
+    rows = [
+        ("Internal PCBA parts / board",  f"='Internal PCBA BOM'!K{pcba_total_row}"),
+        ("External integration / unit",  f"='External Integration BOM'!G{ext_total_row}"),
+        ("Combined cost / unit",         f"=D{r}+D{r+1}"),
+        ("Order total (x build qty)",    f"=D{r+2}*D{qty_row}"),
+    ]
+    for i, (k, f) in enumerate(rows):
+        rr = r + i
+        ws.cell(row=rr, column=2, value=k).font = F_BOLD
+        cc = ws.cell(row=rr, column=4, value=f)
+        cc.font, cc.number_format, cc.alignment, cc.border = F_TOTAL, MONEY2, A_R, B_ALL
+    r += len(rows)
+    ws.cell(row=r, column=2, value="Excludes: bare-PCB fab + PCBA service fees (live JLC quote), SIM plan, labor.").font = F_SUB
+    for col, w in zip("ABCDEFGH", [3, 30, 26, 16, 44, 12, 12, 12]):
+        ws.column_dimensions[col].width = w
+
+def main():
+    outdir = Path(sys.argv[1]) if len(sys.argv) > 1 else Path(__file__).resolve().parent.parent
+    wb = Workbook()
+    ws_sum = wb.active
+    ws_sum.title = "Summary"
+    ws_pcba = wb.create_sheet("Internal PCBA BOM")
+    ws_ext = wb.create_sheet("External Integration BOM")
+    pcba_total = build_pcba(ws_pcba)
+    ext_total = build_ext(ws_ext)
+    build_summary(ws_sum, pcba_total, ext_total)
+    wb.properties.title = "Helgen EinarBoard 1.0 — Production BOM"
+    wb.properties.creator = "Helgen Technologies — Project Drogheda"
+    out = outdir / "helgen_einarboard_1.0_production_bom.xlsx"
+    wb.save(out)
+    print(f"OK  {out}  (PCBA total row K{pcba_total} · EXT total row G{ext_total})")
+
+if __name__ == "__main__":
+    main()

03-Architecture-Hardware/EinarBoard-Manual/tools/sync_bom.py

@@ -0,0 +1,147 @@
+#!/usr/bin/env python3
+"""
+sync_bom.py — Excel -> LaTeX BOM synchronization (Helgen EinarBoard 1.0)
+
+Reads helgen_einarboard_1.0_production_bom.xlsx and writes TWO LaTeX snippets:
+  pcba_bom.tex      <- tab "Internal PCBA BOM"        (on-board, per board)
+  external_bom.tex  <- tab "External Integration BOM" (per HBOX unit)
+
+Both are pulled into einarboard-manual.tex via \\input{}. Filters section bars /
+blank rows / TOTAL rows, escapes LaTeX reserved tokens, and recomputes line
+costs (openpyxl stores formulas without cached values).
+
+The Excel workbook is the single source of truth for BOM content.
+Edit the workbook (or its generator), re-run this, recompile the manual.
+
+Usage: python3 sync_bom.py [workbook.xlsx] [outdir]
+"""
+import sys
+from datetime import date
+from pathlib import Path
+
+from openpyxl import load_workbook
+
+HERE = Path(__file__).resolve().parent
+
+# LaTeX reserved-token escape map (backslash first).
+_ESC = [("\\", r"\textbackslash{}"), ("&", r"\&"), ("%", r"\%"), ("$", r"\$"),
+        ("#", r"\#"), ("_", r"\_"), ("{", r"\{"), ("}", r"\}"),
+        ("~", r"\textasciitilde{}"), ("^", r"\textasciicircum{}")]
+
+def esc(v) -> str:
+    if v is None:
+        return ""
+    s = str(v).strip()
+    for raw, rep in _ESC:
+        s = s.replace(raw, rep)
+    return s
+
+def num(v):
+    try:
+        return float(v)
+    except (TypeError, ValueError):
+        return None
+
+def find_header(ws):
+    for row in ws.iter_rows(min_row=1, max_row=12):
+        if str(row[0].value).strip() == "Item":
+            return row[0].row
+    sys.exit(f"sync_bom: header row ('Item') not found on '{ws.title}'")
+
+def clean_rows(ws, ncols, key_cols, qty_col, unit_col):
+    """Yield escaped column tuples + (qty, unit, line) numerics for data rows."""
+    hdr = find_header(ws)
+    for row in ws.iter_rows(min_row=hdr + 1, values_only=True):
+        cells = (list(row) + [None] * ncols)[:ncols]
+        # Filters: section bars (text only in col A), blanks, Excel TOTAL rows.
+        if any(cells[k] in (None, "") for k in key_cols):
+            continue
+        a = str(cells[0]).strip() if cells[0] is not None else ""
+        if a.upper().startswith("TOTAL") or str(cells[3]).upper().startswith("TOTAL"):
+            continue
+        q, u = num(cells[qty_col]), num(cells[unit_col])
+        if q is None or u is None:
+            continue
+        yield cells, q, u, q * u
+
+HEADER_CELLS = lambda names: (
+    r"\rowcolor{HelgenIndigo}" + "\n" +
+    " & ".join(rf"\textcolor{{white}}{{\textbf{{{n}}}}}" for n in names) + r" \\")
+
+def longtable(colspec, caption, label, header_names, body_lines, total_label, total):
+    hdr = HEADER_CELLS(header_names)
+    n = len(header_names)
+    return "\n".join([
+        r"\begin{small}",
+        r"\setlength{\LTleft}{0pt}\setlength{\LTright}{0pt}",
+        rf"\begin{{longtable}}{{{colspec}}}",
+        rf"\caption{{{caption}}}",
+        rf"\label{{{label}}}\\",
+        r"\toprule", hdr, r"\midrule\endfirsthead",
+        r"\toprule", hdr, r"\midrule\endhead",
+        rf"\midrule\multicolumn{{{n}}}{{r}}{{\emph{{continues}}}}\\\endfoot",
+        r"\endlastfoot",
+        *body_lines,
+        r"\midrule",
+        rf"\multicolumn{{{n-1}}}{{r}}{{\textbf{{{total_label}}}}} & \textbf{{{total:.2f}}} \\",
+        r"\bottomrule",
+        r"\end{longtable}",
+        r"\end{small}",
+    ])
+
+def gen_pcba(wb):
+    ws = wb["Internal PCBA BOM"]
+    lines, total = [], 0.0
+    # cols: 0 Item 1 Qty 2 RefDes 3 Desc 4 Pkg 5 Mfr 6 MPN 7 LCSC 8 Assy 9 Unit 10 Line 11 Notes
+    for cells, q, u, line in clean_rows(ws, 12, key_cols=(2, 3), qty_col=1, unit_col=9):
+        total += line
+        qs = str(int(q)) if q == int(q) else f"{q:g}"
+        part = " ".join(x for x in (esc(cells[5]), esc(cells[6])) if x and x != "—") or "—"
+        lines.append(f"{qs} & {esc(cells[2])} & {esc(cells[3])} & {esc(cells[4])} & "
+                     f"{part} & {esc(cells[7])} & {esc(cells[8])} & {u:.3f} & {line:.3f} \\\\")
+    tex = longtable(
+        r"@{}r p{2.6cm} p{5.4cm} p{1.5cm} p{2.6cm} p{1.7cm} p{1.4cm} r r@{}",
+        "Internal PCBA BOM --- per board (synchronized from the production workbook).",
+        "tab:pcba-bom",
+        ["Qty", "RefDes", "Description", "Pkg", "Part", "LCSC", "Assy", r"Unit\,\$", r"Line\,\$"],
+        lines, "TOTAL --- PCBA parts per board", total)
+    return tex, len(lines), total
+
+def gen_external(wb):
+    ws = wb["External Integration BOM"]
+    lines, total = [], 0.0
+    # cols: 0 Item 1 Qty 2 Part 3 Desc 4 Source/MPN 5 Unit 6 Line 7 Notes
+    for cells, q, u, line in clean_rows(ws, 8, key_cols=(2, 3), qty_col=1, unit_col=5):
+        total += line
+        qs = str(int(q)) if q == int(q) else f"{q:g}"
+        desc = esc(cells[3])
+        note = esc(cells[7])
+        if note:
+            desc += rf" \emph{{--- {note}}}"
+        lines.append(f"{qs} & {esc(cells[2])} & {desc} & {esc(cells[4])} & "
+                     f"{u:.2f} & {line:.2f} \\\\")
+    tex = longtable(
+        r"@{}r p{3.4cm} p{7.2cm} p{2.9cm} r r@{}",
+        "External Integration BOM --- per HBOX unit (enclosure, modules, pack, panel, harnesses; NOT in the JLC order).",
+        "tab:ext-bom",
+        ["Qty", "Part", "Description / notes", "Source / MPN", r"Unit\,\$", r"Line\,\$"],
+        lines, "TOTAL --- external integration per unit", total)
+    return tex, len(lines), total
+
+def main():
+    wb_path = Path(sys.argv[1]) if len(sys.argv) > 1 else HERE.parent / "helgen_einarboard_1.0_production_bom.xlsx"
+    outdir = Path(sys.argv[2]) if len(sys.argv) > 2 else HERE.parent
+    wb = load_workbook(wb_path, data_only=False)
+    stamp = date.today().isoformat()
+    banner = (f"% AUTO-GENERATED {stamp} by tools/sync_bom.py from {wb_path.name}.\n"
+              f"% DO NOT HAND-EDIT — edit the workbook and re-run.\n")
+    for fname, (tex, n, total) in {
+        "pcba_bom.tex": gen_pcba(wb),
+        "external_bom.tex": gen_external(wb),
+    }.items():
+        out = outdir / fname
+        out.write_text(banner + tex + "\n", encoding="utf-8")
+        print(f"OK  {out}  ({n} line items, total ${total:.2f})")
+
+if __name__ == "__main__":
+    main()

03-Architecture-Hardware/LCSC-search-list.md

@@ -2,7 +2,7 @@
 title: HBOX Watchdog v3 PROD — LCSC / JLC Assembly Parts List
 project: Project Drogheda
 date: 2026-07-06
-status: §1 specialty parts VERIFIED against JLC live stock (2026-07-06). Passives/common semis → JLC auto-match. LCSC filled into production/HBOX_v3_PROD_bom.csv.
+status: §1 + §2 VERIFIED against JLC live stock (2026-07-06) and BAKED into the schematic as hidden LCSC fields (persist across plugin runs). production/HBOX_v3_PROD_bom.csv filled (20 lines). Only D5 BAT54 + generic passives left to JLC auto-match.
 tags: [project-drogheda, hardware, pcb, jlcpcb, bom, lcsc]
 ---
 
@@ -47,20 +47,25 @@ pulled from JLC's live parts search on **2026-07-06**; stock moves, so re-confir
 
 ---
 
-## §2 — Common semiconductors → JLC **Basic**, let auto-match fill (search MPN to confirm)
+## §2 — Common semiconductors — VERIFIED LCSC (live JLC, 2026-07-06)
 
-| Ref(s) | Qty | MFR Part | Pkg |
+| Ref(s) | Qty | LCSC # | MFR Part | Pkg | Type · Stock |
-|---|---|---|---|
+|---|---|---|---|---|---|
-| Q1 | 1 | AO3401A (P-ch) | SOT-23 |
+| Q1 | 1 | **C15127** | AO3401A (AOS, P-ch) | SOT-23 | Basic · 489k |
-| Q2, Q4 | 2 | AO3400A (N-ch) | SOT-23 |
+| Q2, Q4 | 2 | **C20917** | AO3400A (AOS, N-ch) | SOT-23 | Basic · 1.19M |
-| Q5, Q6 | 2 | MMBT3904 (NPN) | SOT-23 |
+| Q5, Q6 | 2 | **C20526** | MMBT3904 (NPN) | SOT-23 | Basic · 724k |
-| D2, DBK, DBK2 | 3 | SS34 (40 V 3 A Schottky) | SMA |
+| D2, Dbk, Dbk2 | 3 | **C8678** | SS34 (40 V 3 A Schottky) | SMA | Basic · 2.99M |
-| D5 | 1 | BAT54 | SOD-123 |
+| D6 | 1 | **C2099** | 1N4148W | SOD-123 | Ext · 33k |
-| D6 | 1 | 1N4148W | SOD-123 |
+| D1, D4G, DB1–DB4 | 6 | **C28105** | LED green-yellow 0805 | 0805 | Basic · in stock |
-| D1, D4G, DB1–DB4 | 6 | LED 0805 | 0805 — pick color per function |
+| D5 | 1 | — | BAT54 | SOD-123 | **auto-match** (ambiguous search; 1 pc) |
 
-> These are all JLC Basic/common; on BOM upload JLC auto-suggests an in-stock part. Want me to
+> **LED color:** all six pinned to one green 0805 Basic (C28105) to keep a single SKU — swap D4G to
-> fill exact LCSC #s for these too? Say the word.
+> blue or vary the DB1–4 gauge colors in JLC's BOM editor if you want. **D5 (BAT54)** left blank on
+> purpose — let JLC auto-match it (one diode; the live search returned conflicting variants).
+
+> **All §1 + §2 numbers are now hidden `LCSC` fields in the schematic**, so a fresh Fabrication
+> Toolkit run regenerates a fully-populated BOM automatically. The current `production/…_bom.csv`
+> is also filled, so you can upload it as-is.
 
 ---
 

03-Architecture-Hardware/kicad/hbox-watchdog-v3-PROD.kicad_pro

@@ -39,9 +39,9 @@
         "other_text_thickness": 0.15,
         "other_text_upright": false,
         "pads": {
-          "drill": 0.8,
+          "drill": 0.95,
-          "height": 1.27,
+          "height": 1.95,
-          "width": 1.27
+          "width": 1.7
         },
         "silk_line_width": 0.1,
         "silk_text_italic": false,
@@ -250,6 +250,10 @@
         {
           "diameter": 0.3,
           "drill": 0.15
+        },
+        {
+          "diameter": 0.8,
+          "drill": 0.3
         }
       ],
       "zones_allow_external_fillets": false
@@ -262,7 +266,7 @@
       "internal_id": "",
       "mfg": "",
       "mpn": "",
-      "sch_revision": ""
+      "sch_revision": "1.1"
     },
     "layer_pairs": [],
     "layer_presets": [],
@@ -538,7 +542,6 @@
         "bus_width": 12,
         "clearance": 0.2,
         "diff_pair_gap": 0.25,
-        "diff_pair_via_gap": 0.25,
         "diff_pair_width": 0.2,
         "line_style": 0,
         "microvia_diameter": 0.3,
@@ -557,14 +560,13 @@
         "bus_width": 12,
         "clearance": 0.2,
         "diff_pair_gap": 0.25,
-        "diff_pair_via_gap": 0.25,
         "diff_pair_width": 0.2,
         "line_style": 0,
         "microvia_diameter": 0.3,
         "microvia_drill": 0.1,
         "name": "PWR_MID",
         "pcb_color": "rgba(0, 0, 0, 0.000)",
-        "priority": 0,
+        "priority": 1,
         "schematic_color": "rgba(0, 0, 0, 0.000)",
         "track_width": 1.0,
         "tuning_profile": "",
@@ -638,6 +640,10 @@
       {
         "netclass": "PWR_MID",
         "pattern": "FAN_RET"
+      },
+      {
+        "netclass": "PWR_MID",
+        "pattern": "SW_IN"
       }
     ]
   },

03-Architecture-Hardware/kicad/production/HBOX_v3_PROD_bom.csv

@@ -9,16 +9,17 @@ C31,0603,1,2.2uF,
 "C32, C33",1210,2,47uF,
 "C35, C40, C41",0805,3,22uF,
 C43,CP_Elec_6.3x7.7,1,100uF/6.3V,
-"CBST, CBST2",0603,2,10nF,
+"CBST1, CBST2",0603,2,10nF,
-"CCOMP, CCOMP2",0603,2,2.2nF,
+"CCOMP1, CCOMP2",0603,2,2.2nF,
-"D1, D4G, DB1, DB2, DB3, DB4",0805,6,LED,
+"D1, DB1, DB2, DB3, DB4",0805,5,LED,C28105
 D10,D_SMB,1,SMBJ33A,C224019
-"D2, DBK, DBK2",D_SMA,3,SS34,
+"D2, DBK2",D_SMA,2,SS34,C8678
+D4G1,0805,1,LED,
 D5,D_SOD-123,1,BAT54,
-D6,D_SOD-123,1,1N4148W,
+D6,D_SOD-123,1,1N4148W,C2099
-DZG,SOT-23,1,BZX84C15,C80857
+DBK1,D_SMA,1,SS34,
+DZG1,SOT-23,1,BZX84C15,
 F1,1812,1,PPTC 3A,C20627123
-H3,PinHeader_1x03_P2.54mm_Vertical,1,USART1-RSV (DNP),
 J1,PinSocket_1x20_P2.54mm_Vertical,1,Blackpill-L,
 J2,PinSocket_1x20_P2.54mm_Vertical,1,Blackpill-R,
 J7,PinSocket_1x10_P2.00mm_Vertical,1,XBEE-ROW-1 (VCC/DOUT/DIN),
@@ -39,21 +40,19 @@ P1,"TerminalBlock_Phoenix_MKDS-1,5-5_1x05_P5.00mm_Horizontal",1,GX16-5,
 P10,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,RESET-EXT,
 P11,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,CUTOFF-SW,
 P12,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,NTC-HOTSPOT,
-P13,JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical,1,MODO-B-UPLINK (DNP — harness alt),
 P2,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,5V-IN-SD15B05,
-P3,JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical,1,RTK2B-UART1 (DNP — harness alt),
 P4,JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical,1,BATT-1S4P+NTC,
 P5,JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical,1,TEMP_PROBE,
 P6,JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical,1,FAN,
 P8,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,PANEL_LED,
-Q1,SOT-23,1,AO3401A,
+Q1,SOT-23,1,AO3401A,C15127
 Q10,TO-252-2,1,IRFR5305,C2624
-"Q2, Q4",SOT-23,2,AO3400A,
+"Q2, Q4",SOT-23,2,AO3400A,C20917
-"Q5, Q6",SOT-23,2,MMBT3904,
+"Q5, Q6",SOT-23,2,MMBT3904,C20526
 Q7,SOIC-8_3.9x4.9mm_P1.27mm,1,AO4406A,C35349
-"R1, R3, R40, RMLED, RTS",0603,5,1k,
+"R1, R3, R40, RMLED1, RTS1",0603,5,1k,
-"R2, R41, R5, R6, R7, R8, RIGB, RLED, RRP, RTP",0603,10,10k,
+"R2, R41, R5, R6, R7, R8, RIGB1, RLED1, RRP1, RTP1",0603,10,10k,
-"R20, R56, R57, R58, REN1, RFREQ, RFREQ2, RGS",0603,8,100k,
+"R20, R56, R57, R58, REN1, RFREQ1, RFREQ2, RGS1",0603,8,100k,
 R21,0603,1,19.1k,
 "R30, R31",0603,2,4.7k,
 "R42, R55",0603,2,10k/1%,
@@ -64,13 +63,13 @@ R53,0603,1,499k/1%,
 R61,0603,1,31.6k/1%,
 "RB1, RB2, RB3, RB4",0603,4,330R,
 "RCC1, RCC2",0603,2,5.1k,
-"RCOMP, RCOMP2",0603,2,40.2k,
+"RCOMP1, RCOMP2",0603,2,40.2k,
-RDFU,0603,1,22k,
+"RDFU1, RIG1",0603,2,22k,
 REN2,0603,1,20k,
-"RG, RIG",0603,2,100R,
+RG1,0603,1,100R,
 RS1,1206,1,8mR/1%,C7420012
 SW1,SW_PUSH_6mm,1,RESET,
-SW4G,SW_Tactile_SPST_NO_Straight_CK_PTS636Sx25SMTRLFS,1,RESET,C2689642
+SW4G1,SW_Tactile_SPST_NO_Straight_CK_PTS636Sx25SMTRLFS,1,RESET,
 TP1,TestPoint_Pad_D1.5mm,1,CLPROG,
 TP2,TestPoint_Pad_D1.5mm,1,PFO,
 "U2, U7",SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm,2,MP1584EN,C15051

03-Architecture-Hardware/kicad/production/HBOX_v3_PROD_bom.csv.bak-lcsc2

@@ -0,0 +1,79 @@
+Designator,Footprint,Quantity,Value,LCSC Part #
+C10,CP_Elec_6.3x7.7,1,47uF/50V,
+"C11, C24, C5, C7, C9, CU3, CU4",0603,7,100nF,
+C22,1210,1,22uF/50V,
+C23,0805,1,22uF/16V,
+C3,CP_Elec_6.3x7.7,1,47uF,
+"C30, C34",0805,2,10uF,
+C31,0603,1,2.2uF,
+"C32, C33",1210,2,47uF,
+"C35, C40, C41",0805,3,22uF,
+C43,CP_Elec_6.3x7.7,1,100uF/6.3V,
+"CBST, CBST2",0603,2,10nF,
+"CCOMP, CCOMP2",0603,2,2.2nF,
+"D1, D4G, DB1, DB2, DB3, DB4",0805,6,LED,
+D10,D_SMB,1,SMBJ33A,C224019
+"D2, DBK, DBK2",D_SMA,3,SS34,
+D5,D_SOD-123,1,BAT54,
+D6,D_SOD-123,1,1N4148W,
+DZG,SOT-23,1,BZX84C15,C80857
+F1,1812,1,PPTC 3A,C20627123
+H3,PinHeader_1x03_P2.54mm_Vertical,1,USART1-RSV (DNP),
+J1,PinSocket_1x20_P2.54mm_Vertical,1,Blackpill-L,
+J2,PinSocket_1x20_P2.54mm_Vertical,1,Blackpill-R,
+J7,PinSocket_1x10_P2.00mm_Vertical,1,XBEE-ROW-1 (VCC/DOUT/DIN),
+J8,PinSocket_1x10_P2.00mm_Vertical,1,XBEE-ROW-2,
+J9,USB_C_Receptacle_GCT_USB4085,1,USB-C,
+JP1,SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm,1,0R,
+JP2,SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm,1,F2:Li-ion,
+JP3,SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm,1,F1:0,
+JP4,SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm,1,F0:1,
+K1,Relay_SPDT_Omron_G5V-1,1,G5V-1 DC5,
+L2,L_Bourns-SRU8028_8.0x8.0mm,1,10uH,C17700171
+L6,L_Bourns-SRU8028_8.0x8.0mm,1,2.2uH/8A,C17700165
+L7,L_Bourns-SRU8028_8.0x8.0mm,1,10uH/2A,C17700171
+MH1,MountingHole_3.2mm,1,MH1_3.2mm,
+"MH2, MH3, MH4",MountingHole_3.2mm,3,MountingHole_3.2mm,
+MOD1,Arduino_UNO_R3,1,simpleRTK2B-Pro on UNO female headers,
+P1,"TerminalBlock_Phoenix_MKDS-1,5-5_1x05_P5.00mm_Horizontal",1,GX16-5,
+P10,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,RESET-EXT,
+P11,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,CUTOFF-SW,
+P12,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,NTC-HOTSPOT,
+P13,JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical,1,MODO-B-UPLINK (DNP — harness alt),
+P2,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,5V-IN-SD15B05,
+P3,JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical,1,RTK2B-UART1 (DNP — harness alt),
+P4,JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical,1,BATT-1S4P+NTC,
+P5,JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical,1,TEMP_PROBE,
+P6,JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical,1,FAN,
+P8,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,PANEL_LED,
+Q1,SOT-23,1,AO3401A,
+Q10,TO-252-2,1,IRFR5305,C2624
+"Q2, Q4",SOT-23,2,AO3400A,
+"Q5, Q6",SOT-23,2,MMBT3904,
+Q7,SOIC-8_3.9x4.9mm_P1.27mm,1,AO4406A,C35349
+"R1, R3, R40, RMLED, RTS",0603,5,1k,
+"R2, R41, R5, R6, R7, R8, RIGB, RLED, RRP, RTP",0603,10,10k,
+"R20, R56, R57, R58, REN1, RFREQ, RFREQ2, RGS",0603,8,100k,
+R21,0603,1,19.1k,
+"R30, R31",0603,2,4.7k,
+"R42, R55",0603,2,10k/1%,
+R50,0603,1,825R/1%,
+R51,0603,1,287k/1%,
+"R52, R54, R60",0603,3,100k/1%,
+R53,0603,1,499k/1%,
+R61,0603,1,31.6k/1%,
+"RB1, RB2, RB3, RB4",0603,4,330R,
+"RCC1, RCC2",0603,2,5.1k,
+"RCOMP, RCOMP2",0603,2,40.2k,
+RDFU,0603,1,22k,
+REN2,0603,1,20k,
+"RG, RIG",0603,2,100R,
+RS1,1206,1,8mR/1%,C7420012
+SW1,SW_PUSH_6mm,1,RESET,
+SW4G,SW_Tactile_SPST_NO_Straight_CK_PTS636Sx25SMTRLFS,1,RESET,C2689642
+TP1,TestPoint_Pad_D1.5mm,1,CLPROG,
+TP2,TestPoint_Pad_D1.5mm,1,PFO,
+"U2, U7",SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm,2,MP1584EN,C15051
+U3,Sensirion_DFN-4_1.5x1.5mm_P0.8mm_SHT4x_NoCentralPad,1,SHT40-AD1B,C2848306
+U4,SOT-563,1,TMP102,C99269
+U6,QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm,1,LTC4040EUFD,C687163

03-Architecture-Hardware/kicad/production/HBOX_v3_PROD_designators.csv

@@ -16,25 +16,25 @@ C43:1
 C5:1
 C7:1
 C9:1
-CBST:1
+CBST1:1
 CBST2:1
-CCOMP:1
+CCOMP1:1
 CCOMP2:1
 CU3:1
 CU4:1
 D1:1
 D10:1
 D2:1
-D4G:1
+D4G1:1
 D5:1
 D6:1
 DB1:1
 DB2:1
 DB3:1
 DB4:1
-DBK:1
+DBK1:1
 DBK2:1
-DZG:1
+DZG1:1
 F1:1
 H3:1
 J1:1
@@ -104,25 +104,25 @@ RB3:1
 RB4:1
 RCC1:1
 RCC2:1
-RCOMP:1
+RCOMP1:1
 RCOMP2:1
-RDFU:1
+RDFU1:1
 REN1:1
 REN2:1
-RFREQ:1
+RFREQ1:1
 RFREQ2:1
-RG:1
+RG1:1
-RGS:1
+RGS1:1
-RIG:1
+RIG1:1
-RIGB:1
+RIGB1:1
-RLED:1
+RLED1:1
-RMLED:1
+RMLED1:1
-RRP:1
+RRP1:1
 RS1:1
-RTP:1
+RTP1:1
-RTS:1
+RTS1:1
 SW1:1
-SW4G:1
+SW4G1:1
 TP1:1
 TP2:1
 U2:1

03-Architecture-Hardware/kicad/production/HBOX_v3_PROD_positions.csv

@@ -17,29 +17,28 @@ C43,185.19165,-122.3231,180.0,top
 C5,92.19165,-116.3231,0.0,top
 C7,96.19165,-116.3231,0.0,top
 C9,101.59165,-83.3231,0.0,top
-CBST,168.41665,-45.3231,0.0,top
+CBST1,168.41665,-45.3231,0.0,top
 CBST2,187.91665,-109.8231,0.0,top
-CCOMP,175.84165,-53.4731,270.0,top
+CCOMP1,175.84165,-53.4731,270.0,top
 CCOMP2,187.96665,-114.8231,0.0,top
 CU3,132.91665,-112.3231,0.0,top
 CU4,136.91665,-112.3231,0.0,top
 D1,100.19165,-116.3231,0.0,top
 D10,91.19165,-61.8231,0.0,top
 D2,94.19165,-98.3231,0.0,top
-D4G,203.1,-92.1,0.0,top
+D4G1,203.1,-92.1,0.0,top
 D5,95.19165,-83.3231,0.0,top
 D6,199.69165,-61.8231,180.0,top
 DB1,194.25415,-44.3231,0.0,top
 DB2,198.25415,-44.3231,0.0,top
 DB3,202.25415,-44.3231,0.0,top
 DB4,206.25415,-44.3231,0.0,top
-DBK,168.19165,-65.8231,270.0,top
+DBK1,168.19165,-65.8231,270.0,top
 DBK2,188.49165,-103.8231,0.0,top
-DZG,99.19165,-61.3231,180.0,top
+DZG1,99.19165,-61.3231,180.0,top
 F1,147.19165,-46.3231,0.0,top
-H3,111.19165,-48.8631,0.0,top
 J1,131.32165,-56.3231,90.0,top
-J2,131.32165,-74.1031,90.0,top
+J2,131.33,-71.35,90.0,top
 J7,174.19165,-83.8231,0.0,top
 J8,196.54165,-83.8231,0.0,top
 J9,164.15,-131.855,0.0,top
@@ -60,9 +59,7 @@ P1,182.69165,-133.8231,0.0,top
 P10,210.16665,-78.8231,90.0,top
 P11,137.04165,-46.3231,0.0,top
 P12,210.19165,-120.0731,90.0,top
-P13,118.69165,-46.3231,0.0,top
 P2,128.44165,-46.3231,0.0,top
-P3,210.19165,-91.5731,90.0,top
 P4,210.19165,-105.8231,90.0,top
 P5,101.94165,-46.3231,0.0,top
 P6,210.19165,-58.0731,90.0,top
@@ -105,25 +102,25 @@ RB3,202.25415,-48.3231,0.0,top
 RB4,206.25415,-48.3231,0.0,top
 RCC1,161.425,-124.75,90.0,top
 RCC2,165.4,-124.75,90.0,top
-RCOMP,175.84165,-48.6231,270.0,top
+RCOMP1,175.84165,-48.6231,270.0,top
 RCOMP2,179.69165,-116.3231,0.0,top
-RDFU,110.91665,-112.3231,0.0,top
+RDFU1,110.91665,-112.3231,0.0,top
 REN1,174.19165,-59.3231,0.0,top
 REN2,178.19165,-59.3231,0.0,top
-RFREQ,161.13595,-55.5552,90.0,top
+RFREQ1,161.13595,-55.5552,90.0,top
 RFREQ2,179.51665,-111.8231,0.0,top
-RG,94.19165,-94.3231,0.0,top
+RG1,94.19165,-94.3231,0.0,top
-RGS,99.19165,-94.3231,0.0,top
+RGS1,99.19165,-94.3231,0.0,top
-RIG,101.36665,-69.3231,180.0,top
+RIG1,101.36665,-69.3231,180.0,top
-RIGB,101.36665,-74.3231,180.0,top
+RIGB1,101.36665,-74.3231,180.0,top
-RLED,95.41665,-112.3231,0.0,top
+RLED1,95.41665,-112.3231,0.0,top
-RMLED,203.05,-84.45,0.0,top
+RMLED1,203.05,-84.45,0.0,top
-RRP,85.19165,-61.3231,0.0,top
+RRP1,85.19165,-61.3231,0.0,top
 RS1,100.19165,-88.3231,0.0,top
-RTP,100.86665,-102.3231,0.0,top
+RTP1,100.86665,-102.3231,0.0,top
-RTS,96.86665,-102.3231,0.0,top
+RTS1,96.86665,-102.3231,0.0,top
 SW1,202.44165,-135.5731,0.0,top
-SW4G,148.175,-135.6,0.0,top
+SW4G1,148.175,-135.6,0.0,top
 TP1,113.19165,-107.3231,0.0,top
 TP2,127.69165,-87.3231,0.0,top
 U2,169.21665,-52.7281,90.0,top

03-Architecture-Hardware/kicad/production/netlist.ipc

@@ -2,7 +2,7 @@ P  CODE 00
 P  UNITS CUST 0
 P  arrayDim   N
 317/GATE_LS         VIA        MD0118PA00X+063265Y-023497X0236Y0000R000S3
-317/GATE_LS         VIA        MD0118PA00X+060925Y-024950X0236Y0000R000S3
+317/GATE_LS         VIA        MD0118PA00X+061181Y-024902X0236Y0000R000S3
 317USART1_RX        VIA        MD0118PA00X+065370Y-029893X0236Y0000R000S3
 317USART1_RX        VIA        MD0118PA00X+050618Y-036394X0236Y0000R000S3
 317USART1_RX        VIA        MD0118PA00X+043613Y-043913X0236Y0000R000S3
@@ -38,6 +38,7 @@ P  arrayDim   N
 317GND              VIA        MD0118PA00X+043166Y-035737X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+040410Y-049517X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+059701Y-046761X0236Y0000R000S3
+317GND              VIA        MD0118PA00X+072441Y-021220X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+062457Y-052273X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+054190Y-052273X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+062457Y-032982X0236Y0000R000S3
@@ -47,7 +48,8 @@ P  arrayDim   N
 317GND              VIA        MD0118PA00X+034898Y-030226X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+032142Y-024714X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+034898Y-019202X0236Y0000R000S3
-317GND              VIA        MD0118PA00X+051434Y-027470X0236Y0000R000S3
+317GND              VIA        MD0118PA00X+051614Y-025630X0236Y0000R000S3
+317GND              VIA        MD0118PA00X+058524Y-024055X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+039094Y-045157X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+070046Y-017844X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+045922Y-049517X0236Y0000R000S3
@@ -65,7 +67,7 @@ P  arrayDim   N
 317GND              VIA        MD0118PA00X+048678Y-032982X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+051260Y-039252X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+032142Y-044005X0236Y0000R000S3
-317GND              VIA        MD0118PA00X+048678Y-027470X0236Y0000R000S3
+317GND              VIA        MD0118PA00X+048701Y-029134X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+045922Y-030226X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+032142Y-041249X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+073760Y-024782X0236Y0000R000S3
@@ -75,6 +77,7 @@ P  arrayDim   N
 317GND              VIA        MD0118PA00X+051260Y-041732X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+051434Y-030226X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+032142Y-019202X0236Y0000R000S3
+317GND              VIA        MD0118PA00X+069685Y-020157X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+045922Y-024714X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+043166Y-038493X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+045922Y-019202X0236Y0000R000S3
@@ -93,20 +96,22 @@ P  arrayDim   N
 317GND              VIA        MD0118PA00X+059701Y-016446X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+053150Y-038268X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+034898Y-046761X0236Y0000R000S3
-317GND              VIA        MD0118PA00X+062457Y-027470X0236Y0000R000S3
+317GND              VIA        MD0118PA00X+062500Y-027185X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+043166Y-046761X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+065213Y-019202X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+062457Y-016446X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+040410Y-019202X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+037654Y-016446X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+032142Y-021958X0236Y0000R000S3
-317GND              VIA        MD0118PA00X+065213Y-027470X0236Y0000R000S3
+317GND              VIA        MD0118PA00X+065236Y-027146X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+037654Y-044005X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+034898Y-049517X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+048678Y-052273X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+050079Y-046693X0236Y0000R000S3
+317GND              VIA        MD0118PA00X+041437Y-038780X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+032142Y-035737X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+059701Y-049517X0236Y0000R000S3
+317GND              VIA        MD0118PA00X+070886Y-018780X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+048678Y-030226X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+032142Y-049517X0236Y0000R000S3
 317GND              VIA        MD0118PA00X+040020Y-033661X0236Y0000R000S3
@@ -115,7 +120,7 @@ P  arrayDim   N
 317IGN_SENSE        VIA        MD0118PA00X+038645Y-030736X0236Y0000R000S3
 317IGN_SENSE        VIA        MD0118PA00X+038524Y-032600X0236Y0000R000S3
 317IGN_SENSE        VIA        MD0118PA00X+039512Y-033200X0236Y0000R000S3
-317IGN_SENSE        VIA        MD0118PA00X+047520Y-026634X0236Y0000R000S3
+317IGN_SENSE        VIA        MD0118PA00X+047835Y-026811X0236Y0000R000S3
 317SW_FAN           VIA        MD0118PA00X+065624Y-025127X0236Y0000R000S3
 317SW_FAN           VIA        MD0118PA00X+067052Y-021796X0236Y0000R000S3
 317/5V_FAN          VIA        MD0118PA00X+070710Y-019620X0236Y0000R000S3
@@ -156,7 +161,7 @@ P  arrayDim   N
 317EXT_LED          VIA        MD0118PA00X+035865Y-040968X0236Y0000R000S3
 317/NTC_TEMP        VIA        MD0118PA00X+064724Y-042815X0236Y0000R000S3
 317/NTC_TEMP        VIA        MD0118PA00X+066826Y-044916X0236Y0000R000S3
-317FAN_TACH         VIA        MD0118PA00X+058134Y-027183X0236Y0000R000S3
+317FAN_TACH         VIA        MD0118PA00X+058366Y-027185X0236Y0000R000S3
 317FAN_TACH         VIA        MD0118PA00X+038044Y-030973X0236Y0000R000S3
 317FAN_TACH         VIA        MD0118PA00X+038730Y-039849X0236Y0000R000S3
 3173V3              VIA        MD0118PA00X+052950Y-038906X0236Y0000R000S3
@@ -171,10 +176,10 @@ P  arrayDim   N
 317/MAIN5V          VIA        MD0118PA00X+049468Y-036206X0236Y0000R000S3
 317/MAIN5V          VIA        MD0118PA00X+046466Y-036145X0236Y0000R000S3
 317/MAIN5V          VIA        MD0118PA00X+039967Y-030386X0236Y0000R000S3
-317/SW_IN           VIA        MD0118PA00X+060472Y-025276X0236Y0000R000S3
+317/SW_IN           VIA        MD0118PA00X+060472Y-025276X0315Y0000R000S3
-317/SW_IN           VIA        MD0118PA00X+053346Y-024114X0236Y0000R000S3
+317/SW_IN           VIA        MD0118PA00X+053346Y-024114X0315Y0000R000S3
-317/SW_IN           VIA        MD0118PA00X+059928Y-020295X0236Y0000R000S3
+317/SW_IN           VIA        MD0118PA00X+059928Y-020295X0315Y0000R000S3
-317/SW_IN           VIA        MD0118PA00X+055965Y-023996X0236Y0000R000S3
+317/SW_IN           VIA        MD0118PA00X+055866Y-024114X0315Y0000R000S3
 317FAN_GATE         VIA        MD0118PA00X+039166Y-036753X0236Y0000R000S3
 317FAN_GATE         VIA        MD0118PA00X+040520Y-037584X0236Y0000R000S3
 317/IGATE           VIA        MD0118PA00X+049272Y-037399X0236Y0000R000S3
@@ -205,14 +210,14 @@ P  arrayDim   N
 317/LED_A           VIA        MD0118PA00X+039287Y-042294X0236Y0000R000S3
 317/24V_IN          VIA        MD0118PA00X+035855Y-024425X0236Y0000R000S3
 317/BASE_LS         VIA        MD0118PA00X+064764Y-023750X0236Y0000R000S3
-317/BASE_LS         VIA        MD0118PA00X+061245Y-024079X0236Y0000R000S3
+317/BASE_LS         VIA        MD0118PA00X+061319Y-023780X0236Y0000R000S3
 317/FB_FAN          VIA        MD0118PA00X+069900Y-018229X0236Y0000R000S3
 317/FB_FAN          VIA        MD0118PA00X+068257Y-019603X0236Y0000R000S3
 317BST_FAN          VIA        MD0118PA00X+066297Y-018140X0236Y0000R000S3
 317BST_FAN          VIA        MD0118PA00X+065646Y-021827X0236Y0000R000S3
 317/SW_BAT          VIA        MD0118PA00X+064488Y-036161X0236Y0000R000S3
 317/SW_BAT          VIA        MD0118PA00X+051701Y-032891X0236Y0000R000S3
-317/BATLED3         VIA        MD0118PA00X+065562Y-029630X0236Y0000R000S3
+317/BATLED3         VIA        MD0118PA00X+065610Y-029528X0236Y0000R000S3
 317/BATLED3         VIA        MD0118PA00X+078743Y-019092X0236Y0000R000S3
 317/CLPROG_TP       VIA        MD0118PA00X+045136Y-037087X0236Y0000R000S3
 317/CLPROG_TP       VIA        MD0118PA00X+044564Y-041750X0236Y0000R000S3
@@ -225,7 +230,7 @@ P  arrayDim   N
 317/BATLED2         VIA        MD0118PA00X+077172Y-019224X0236Y0000R000S3
 317/BATLED2         VIA        MD0118PA00X+071533Y-024001X0236Y0000R000S3
 317/USB_CC2         VIA        MD0118PA00X+065945Y-049449X0236Y0000R000S3
-317IGN_IN           VIA        MD0118PA00X+041081Y-028018X0236Y0000R000S3
+317IGN_IN           VIA        MD0118PA00X+041201Y-028287X0236Y0000R000S3
 317/PFI             VIA        MD0118PA00X+048840Y-035956X0236Y0000R000S3
 317/PFI             VIA        MD0118PA00X+040680Y-033158X0236Y0000R000S3
 317/PFI             VIA        MD0118PA00X+041931Y-038282X0236Y0000R000S3
@@ -254,10 +259,10 @@ P  arrayDim   N
 317USART1_RX        P13   -1    D0374PA00X+045745Y-018237X0669Y0768R000S0
 317/DIN_4G          P13   -2    D0374PA00X+046729Y-018237X0669Y0768R000S0
 317GND              P13   -3    D0374PA00X+047713Y-018237X0669Y0768R000S0
-327IGN_SENSE        Rigb  -1          A01X+040233Y-029261X0315Y0374R180S2
+327IGN_SENSE        Rigb1 -1          A01X+040233Y-029261X0315Y0374R180S2
-327GND              Rigb  -2          A01X+039583Y-029261X0315Y0374R180S2
+327GND              Rigb1 -2          A01X+039583Y-029261X0315Y0374R180S2
-327SW_FAN           Dbk   -1          A01X+066217Y-025127X0984Y0709R090S2
+327SW_FAN           Dbk1  -1          A01X+066217Y-025127X0984Y0709R090S2
-327GND              Dbk   -2          A01X+066217Y-026702X0984Y0709R090S2
+327GND              Dbk1  -2          A01X+066217Y-026702X0984Y0709R090S2
 317/5V_FAN          P6    -1    D0374PA00X+082753Y-024340X0669Y0768R090S0
 317/FAN_RET         P6    -2    D0374PA00X+082753Y-023356X0669Y0768R090S0
 317GND              P6    -3    D0374PA00X+082753Y-022371X0669Y0768R090S0
@@ -271,8 +276,8 @@ P  arrayDim   N
 317/NTC             P4    -3    D0374PA00X+082753Y-040678X0669Y0768R270S0
 317/NRST            P10   -1    D0394PA00X+082743Y-031525X0669Y0787R090S0
 317GND              P10   -2    D0394PA00X+082743Y-030541X0669Y0787R090S0
-327CC_FAN           Ccomp -1          A01X+069229Y-020747X0354Y0374R090S2
+327CC_FAN           Ccomp1-1          A01X+069229Y-020747X0354Y0374R090S2
-327GND              Ccomp -2          A01X+069229Y-021358X0354Y0374R090S2
+327GND              Ccomp1-2          A01X+069229Y-021358X0354Y0374R090S2
 327/SW3_NODE        U7    -1          A01X+078778Y-045070X0768Y0236R180S2
 327/SW_5V           U7    -2          A01X+078778Y-044570X0768Y0236R180S2
 327/COMP3           U7    -3          A01X+078778Y-044070X0768Y0236R180S2
@@ -313,24 +318,24 @@ P  arrayDim   N
 327/GATE_LS         Q1    -1          A01X+054218Y-023602X0581Y0236R000S2
 327/SW_IN           Q1    -2          A01X+054218Y-024350X0581Y0236R000S2
 327/SW_5V           Q1    -3          A01X+054956Y-023976X0581Y0236R000S2
-327FAN_PWM          Rg    -1          A01X+036759Y-037135X0315Y0374R000S2
+327FAN_PWM          Rg1   -1          A01X+036759Y-037135X0315Y0374R000S2
-327FAN_GATE         Rg    -2          A01X+037408Y-037135X0315Y0374R000S2
+327FAN_GATE         Rg1   -2          A01X+037408Y-037135X0315Y0374R000S2
-327/MAIN5V          Q7    -1          A01X+043402Y-033592X0768Y0236R000S2
+327/VIN_SW          Q7    -1          A01X+043402Y-033592X0768Y0236R000S2
-327/MAIN5V          Q7    -2          A01X+043402Y-034092X0768Y0236R000S2
+327/VIN_SW          Q7    -2          A01X+043402Y-034092X0768Y0236R000S2
-327/MAIN5V          Q7    -3          A01X+043402Y-034592X0768Y0236R000S2
+327/VIN_SW          Q7    -3          A01X+043402Y-034592X0768Y0236R000S2
 327/IGATE           Q7    -4          A01X+043402Y-035092X0768Y0236R000S2
-327/VIN_SW          Q7    -5          A01X+045351Y-035092X0768Y0236R000S2
+327/MAIN5V          Q7    -5          A01X+045351Y-035092X0768Y0236R000S2
-327/VIN_SW          Q7    -6          A01X+045351Y-034592X0768Y0236R000S2
+327/MAIN5V          Q7    -6          A01X+045351Y-034592X0768Y0236R000S2
-327/VIN_SW          Q7    -7          A01X+045351Y-034092X0768Y0236R000S2
+327/MAIN5V          Q7    -7          A01X+045351Y-034092X0768Y0236R000S2
-327/VIN_SW          Q7    -8          A01X+045351Y-033592X0768Y0236R000S2
+327/MAIN5V          Q7    -8          A01X+045351Y-033592X0768Y0236R000S2
 327/MAIN5V          C34   -1          A01X+051198Y-041072X0394Y0571R000S2
 327GND              C34   -2          A01X+051946Y-041072X0394Y0571R000S2
 3273V3              R31   -1          A01X+050430Y-044222X0315Y0374R000S2
 327/I2C_SDA         R31   -2          A01X+051079Y-044222X0315Y0374R000S2
 327/FREQ3           Rfreq2-1          A01X+070351Y-044025X0315Y0374R000S2
 327GND              Rfreq2-2          A01X+071001Y-044025X0315Y0374R000S2
-327/MODEM_LED       Rmled -1          A01X+079616Y-033248X0315Y0374R000S2
+327/MODEM_LED       Rmled1-1          A01X+079616Y-033248X0315Y0374R000S2
-327/MODEM_LED_A     Rmled -2          A01X+080266Y-033248X0315Y0374R000S2
+327/MODEM_LED_A     Rmled1-2          A01X+080266Y-033248X0315Y0374R000S2
 327/I2C_SDA         U3    -1          A01X+048619Y-046426X0197Y0118R000S2
 327/I2C_SCL         U3    -2          A01X+048619Y-046741X0197Y0118R000S2
 3273V3              U3    -3          A01X+049170Y-046741X0197Y0118R000S2
@@ -357,15 +362,15 @@ P  arrayDim   N
 327/LED_A           R3    -2          A01X+038855Y-042253X0315Y0374R000S2
 327/3V3_MODEM       R60   -1          A01X+070351Y-040285X0315Y0374R000S2
 327/FB3             R60   -2          A01X+071001Y-040285X0315Y0374R000S2
-327USART1_RX        Rdfu  -1          A01X+043343Y-044222X0315Y0374R000S2
+327USART1_RX        Rdfu1 -1          A01X+043343Y-044222X0315Y0374R000S2
-3273V3              Rdfu  -2          A01X+043993Y-044222X0315Y0374R000S2
+3273V3              Rdfu1 -2          A01X+043993Y-044222X0315Y0374R000S2
 327/24V_IN          D10   -1          A01X+035056Y-024340X0984Y0906R000S2
 327GND              D10   -2          A01X+036749Y-024340X0984Y0906R000S2
-327COMP_FAN         Rcomp -1          A01X+069229Y-018818X0315Y0374R090S2
+327COMP_FAN         Rcomp1-1          A01X+069229Y-018818X0315Y0374R090S2
-327CC_FAN           Rcomp -2          A01X+069229Y-019468X0315Y0374R090S2
+327CC_FAN           Rcomp1-2          A01X+069229Y-019468X0315Y0374R090S2
 327/BASE_LS         Q5    -1          A01X+056895Y-023327X0581Y0236R000S2
-327/GATE_LS         Q5    -2          A01X+056895Y-024075X0581Y0236R000S2
+327GND              Q5    -2          A01X+056895Y-024075X0581Y0236R000S2
-327GND              Q5    -3          A01X+057633Y-023701X0581Y0236R000S2
+327/GATE_LS         Q5    -3          A01X+057633Y-023701X0581Y0236R000S2
 327/5V_SENSE        C7    -1          A01X+037566Y-045796X0354Y0374R000S2
 327GND              C7    -2          A01X+038176Y-045796X0354Y0374R000S2
 317/VEH5V           P2    -1    D0394PA00X+050075Y-018237X0669Y0787R000S0
@@ -374,13 +379,13 @@ P  arrayDim   N
 327/FB_FAN          R20   -2          A01X+068776Y-017844X0315Y0374R000S2
 327/BST3            Cbst2 -1          A01X+073678Y-043237X0354Y0374R000S2
 327/SW3_NODE        Cbst2 -2          A01X+074288Y-043237X0354Y0374R000S2
-327FAN_TACH_RAW     Rts   -1          A01X+037812Y-040285X0315Y0374R000S2
+327FAN_TACH_RAW     Rts1  -1          A01X+037812Y-040285X0315Y0374R000S2
-327FAN_TACH         Rts   -2          A01X+038461Y-040285X0315Y0374R000S2
+327FAN_TACH         Rts1  -2          A01X+038461Y-040285X0315Y0374R000S2
 327FAN_GATE         Q2    -1          A01X+041439Y-037548X0581Y0236R000S2
 327GND              Q2    -2          A01X+041439Y-038296X0581Y0236R000S2
 327/FAN_RET         Q2    -3          A01X+042177Y-037922X0581Y0236R000S2
-327BST_FAN          Cbst  -1          A01X+066001Y-017844X0354Y0374R000S2
+327BST_FAN          Cbst1 -1          A01X+066001Y-017844X0354Y0374R000S2
-327SW_FAN           Cbst  -2          A01X+066611Y-017844X0354Y0374R000S2
+327SW_FAN           Cbst1 -2          A01X+066611Y-017844X0354Y0374R000S2
 317/USART1_TX       H3    -1    D0394PA00X+043776Y-018237X0669Y0669R000S0
 317USART1_RX        H3    -2    D0394PA00X+043776Y-019237X0669Y0000R000S0
 317GND              H3    -3    D0394PA00X+043776Y-020237X0669Y0000R000S0
@@ -401,8 +406,8 @@ P  arrayDim   N
 327/5V_FAN          L2    -2          A01X+075272Y-018828X0787Y1260R000S2
 327IGN_SENSE        C9    -1          A01X+039692Y-032804X0354Y0374R000S2
 327GND              C9    -2          A01X+040302Y-032804X0354Y0374R000S2
-327/MODEM_RST       SW4G  -1          A01X+056811Y-053386X0492Y0394R000S2
+327/MODEM_RST       SW4G1 -1          A01X+056811Y-053386X0492Y0394R000S2
-327GND              SW4G  -2          A01X+059862Y-053386X0492Y0394R000S2
+327GND              SW4G1 -2          A01X+059862Y-053386X0492Y0394R000S2
 317GND              J8    -1    D0315PA00X+077379Y-029458X0531Y0531R000S0
 317J8-PIN_2-PAD2)   J8    -2    D0315PA00X+077379Y-030245X0531Y0000R000S0
 317J8-PIN_3-PAD3)   J8    -3    D0315PA00X+077379Y-031033X0531Y0000R000S0
@@ -442,13 +447,13 @@ P  arrayDim   N
 327GND              C41   -2          A01X+078225Y-041033X0394Y0571R090S2
 327/VEH5V           R55   -1          A01X+039780Y-042253X0315Y0374R000S2
 327/NTC             R55   -2          A01X+040430Y-042253X0315Y0374R000S2
-327EXT_LED          Rled  -1          A01X+037241Y-044222X0315Y0374R000S2
+327EXT_LED          Rled1 -1          A01X+037241Y-044222X0315Y0374R000S2
-327GND              Rled  -2          A01X+037890Y-044222X0315Y0374R000S2
+327GND              Rled1 -2          A01X+037890Y-044222X0315Y0374R000S2
 327/MAIN5V          JP4   -1          A01X+055154Y-039300X0394Y0197R000S2
 327/F0_SEL          JP4   -2          A01X+055666Y-039300X0394Y0591R000S2
 327GND              JP4   -3          A01X+056178Y-039300X0394Y0197R000S2
-327FAN_GATE         Rgs   -1          A01X+038727Y-037135X0315Y0374R000S2
+327FAN_GATE         Rgs1  -1          A01X+038727Y-037135X0315Y0374R000S2
-327GND              Rgs   -2          A01X+039377Y-037135X0315Y0374R000S2
+327GND              Rgs1  -2          A01X+039377Y-037135X0315Y0374R000S2
 317/LED_A           P8    -1    D0394PA00X+082743Y-027883X0669Y0787R090S0
 317/LED_K           P8    -2    D0394PA00X+082743Y-026899X0669Y0787R090S0
 327/Q6_BASE         R41   -1          A01X+069829Y-025521X0315Y0374R000S2
@@ -461,8 +466,8 @@ P  arrayDim   N
 327GND              Rcc2  -2          A01X+065118Y-048789X0315Y0374R270S2
 327/LED_K           D1    -1          A01X+039076Y-045796X0384Y0551R000S2
 327/LED_A           D1    -2          A01X+039815Y-045796X0384Y0551R000S2
-3273V3              Rtp   -1          A01X+039386Y-040285X0315Y0374R000S2
+3273V3              Rtp1  -1          A01X+039386Y-040285X0315Y0374R000S2
-327FAN_TACH         Rtp   -2          A01X+040036Y-040285X0315Y0374R000S2
+327FAN_TACH         Rtp1  -2          A01X+040036Y-040285X0315Y0374R000S2
 327/5V_FAN          JP1   -1          A01X+064918Y-031623X0394Y0197R000S2
 327/VEH5V           JP1   -2          A01X+065430Y-031623X0394Y0197R000S2
 3273V3              R30   -1          A01X+048855Y-044222X0315Y0374R000S2
@@ -511,35 +516,35 @@ P  arrayDim   N
 317/DIN_4G          K1    -6    D0394PA00X+076521Y-025994X0787Y0000R000S0
 317/KCOIL           K1    -9    D0394PA00X+076521Y-022994X0787Y0000R000S0
 317/USART1_TX       K1    -10   D0394PA00X+076521Y-021994X0787Y0000R000S0
-317/BATLED1         J2    -1    D0394PA00X+042201Y-029174X0669Y0669R270S0
+317/BATLED1         J2    -1    D0394PA00X+042205Y-028091X0669Y0669R270S0
-317/BATLED2         J2    -2    D0394PA00X+043201Y-029174X0669Y0000R270S0
+317/BATLED2         J2    -2    D0394PA00X+043205Y-028091X0669Y0000R270S0
-317/BATLED3         J2    -3    D0394PA00X+044201Y-029174X0669Y0000R270S0
+317/BATLED3         J2    -3    D0394PA00X+044205Y-028091X0669Y0000R270S0
-317/BATLED4         J2    -4    D0394PA00X+045201Y-029174X0669Y0000R270S0
+317/BATLED4         J2    -4    D0394PA00X+045205Y-028091X0669Y0000R270S0
-317/CHRG_EN         J2    -5    D0394PA00X+046201Y-029174X0669Y0000R270S0
+317/CHRG_EN         J2    -5    D0394PA00X+046205Y-028091X0669Y0000R270S0
-317/USART1_TX       J2    -6    D0394PA00X+047201Y-029174X0669Y0000R270S0
+317/USART1_TX       J2    -6    D0394PA00X+047205Y-028091X0669Y0000R270S0
-317USART1_RX        J2    -7    D0394PA00X+048201Y-029174X0669Y0000R270S0
+317USART1_RX        J2    -7    D0394PA00X+048205Y-028091X0669Y0000R270S0
-317J2-PIN_8-PAD8)   J2    -8    D0394PA00X+049201Y-029174X0669Y0000R270S0
+317J2-PIN_8-PAD8)   J2    -8    D0394PA00X+049205Y-028091X0669Y0000R270S0
-317J2-PIN_9-PAD9)   J2    -9    D0394PA00X+050201Y-029174X0669Y0000R270S0
+317J2-PIN_9-PAD9)   J2    -9    D0394PA00X+050205Y-028091X0669Y0000R270S0
-317-PIN_10-PAD10)   J2    -10   D0394PA00X+051201Y-029174X0669Y0000R270S0
+317-PIN_10-PAD10)   J2    -10   D0394PA00X+051205Y-028091X0669Y0000R270S0
-317/CHRG_STAT       J2    -11   D0394PA00X+052201Y-029174X0669Y0000R270S0
+317/CHRG_STAT       J2    -11   D0394PA00X+052205Y-028091X0669Y0000R270S0
-317/CHRG_FAULT      J2    -12   D0394PA00X+053201Y-029174X0669Y0000R270S0
+317/CHRG_FAULT      J2    -12   D0394PA00X+053205Y-028091X0669Y0000R270S0
-317/BYP_CTRL        J2    -13   D0394PA00X+054201Y-029174X0669Y0000R270S0
+317/BYP_CTRL        J2    -13   D0394PA00X+054205Y-028091X0669Y0000R270S0
-317/I2C_SCL         J2    -14   D0394PA00X+055201Y-029174X0669Y0000R270S0
+317/I2C_SCL         J2    -14   D0394PA00X+055205Y-028091X0669Y0000R270S0
-317/I2C_SDA         J2    -15   D0394PA00X+056201Y-029174X0669Y0000R270S0
+317/I2C_SDA         J2    -15   D0394PA00X+056205Y-028091X0669Y0000R270S0
-317_16-PAD16)#1     J2    -16   D0394PA00X+057201Y-029174X0669Y0000R270S0
+317_16-PAD16)#1     J2    -16   D0394PA00X+057205Y-028091X0669Y0000R270S0
-317-PIN_17-PAD17)   J2    -17   D0394PA00X+058201Y-029174X0669Y0000R270S0
+317-PIN_17-PAD17)   J2    -17   D0394PA00X+058205Y-028091X0669Y0000R270S0
-317/SYS5V           J2    -18   D0394PA00X+059201Y-029174X0669Y0000R270S0
+317/SYS5V           J2    -18   D0394PA00X+059205Y-028091X0669Y0000R270S0
-317GND              J2    -19   D0394PA00X+060201Y-029174X0669Y0000R270S0
+317GND              J2    -19   D0394PA00X+060205Y-028091X0669Y0000R270S0
-3173V3              J2    -20   D0394PA00X+061201Y-029174X0669Y0000R270S0
+3173V3              J2    -20   D0394PA00X+061205Y-028091X0669Y0000R270S0
 327/CHRG_EN         R56   -1          A01X+041355Y-042253X0315Y0374R000S2
 327GND              R56   -2          A01X+042005Y-042253X0315Y0374R000S2
 32724V              C11   -1          A01X+063550Y-020167X0354Y0374R000S2
 327GND              C11   -2          A01X+064160Y-020167X0354Y0374R000S2
 327/3V3_MODEM       C43   -1          A01X+071847Y-048159X1378Y0630R000S2
 327GND              C43   -2          A01X+073973Y-048159X1378Y0630R000S2
-327Q10_GATE         DzG   -1          A01X+038683Y-023769X0581Y0236R000S2
+327Q10_GATE         DzG1  -1          A01X+038683Y-023769X0581Y0236R000S2
-327N/C              DzG   -2          A01X+038683Y-024517X0581Y0236R000S2
+327N/C              DzG1  -2          A01X+038683Y-024517X0581Y0236R000S2
-32724V              DzG   -3          A01X+039421Y-024143X0581Y0236R000S2
+32724V              DzG1  -3          A01X+039421Y-024143X0581Y0236R000S2
 327/BYP_CTRL        R40   -1          A01X+070223Y-026968X0315Y0374R090S2
 327/Q6_BASE         R40   -2          A01X+070223Y-027617X0315Y0374R090S2
 3273V3              R42   -1          A01X+044918Y-044222X0315Y0374R000S2
@@ -589,11 +594,11 @@ P  arrayDim   N
 317GND              SW1   -2    D0433PA00X+080981Y-054261X0787Y0000R270S0
 3273V3              R58   -1          A01X+052822Y-041072X0315Y0374R000S2
 327/CHRG_FAULT      R58   -2          A01X+053471Y-041072X0315Y0374R000S2
-327Q10_GATE         Rrp   -1          A01X+033215Y-024143X0315Y0374R000S2
+327Q10_GATE         Rrp1  -1          A01X+033215Y-024143X0315Y0374R000S2
-327GND              Rrp   -2          A01X+033865Y-024143X0315Y0374R000S2
+327GND              Rrp1  -2          A01X+033865Y-024143X0315Y0374R000S2
 327/Q6_BASE         Q6    -1          A01X+071754Y-024556X0581Y0236R000S2
-327/KCOIL           Q6    -2          A01X+071754Y-025304X0581Y0236R000S2
+327GND              Q6    -2          A01X+071754Y-025304X0581Y0236R000S2
-327GND              Q6    -3          A01X+072492Y-024930X0581Y0236R000S2
+327/KCOIL           Q6    -3          A01X+072492Y-024930X0581Y0236R000S2
 327/VEH5V           C31   -1          A01X+043953Y-038316X0354Y0374R000S2
 327GND              C31   -2          A01X+044564Y-038316X0354Y0374R000S2
 327/FB_FAN          R21   -1          A01X+069396Y-017844X0315Y0374R000S2
@@ -608,14 +613,14 @@ P  arrayDim   N
 327IGN_SENSE        D5    -2          A01X+038127Y-032804X0354Y0472R000S2
 327/MAIN5V          C33   -1          A01X+049091Y-041072X0453Y1063R000S2
 327GND              C33   -2          A01X+050253Y-041072X0453Y1063R000S2
-327FREQ_FAN         Rfreq -1          A01X+063439Y-022197X0315Y0374R270S2
+327FREQ_FAN         Rfreq1-1          A01X+063439Y-022197X0315Y0374R270S2
-327GND              Rfreq -2          A01X+063439Y-021547X0315Y0374R270S2
+327GND              Rfreq1-2          A01X+063439Y-021547X0315Y0374R270S2
 317/SW_5V           P3    -1    D0374PA00X+082753Y-037529X0669Y0768R270S0
 317GND              P3    -2    D0374PA00X+082753Y-036545X0669Y0768R270S0
 317/GNSS_TX         P3    -3    D0374PA00X+082753Y-035560X0669Y0768R270S0
 317/GNSS_RX         P3    -4    D0374PA00X+082753Y-034576X0669Y0768R270S0
-327IGN_IN           Rig   -1          A01X+040233Y-027293X0315Y0374R180S2
+327IGN_IN           Rig1  -1          A01X+040233Y-027293X0315Y0374R180S2
-327IGN_SENSE        Rig   -2          A01X+039583Y-027293X0315Y0374R180S2
+327IGN_SENSE        Rig1  -2          A01X+039583Y-027293X0315Y0374R180S2
 327/BATLED1         RB1   -1          A01X+076153Y-019025X0315Y0374R000S2
 327/BLED1           RB1   -2          A01X+076803Y-019025X0315Y0374R000S2
 32724V              Ren1  -1          A01X+068255Y-023356X0315Y0374R000S2
@@ -644,12 +649,12 @@ P  arrayDim   N
 327GND              JP2   -3          A01X+056178Y-035560X0394Y0197R000S2
 327/SYS5V           D6    -1          A01X+079268Y-024340X0354Y0472R180S2
 327/KCOIL           D6    -2          A01X+077969Y-024340X0354Y0472R180S2
-327GND              D4G   -1          A01X+079592Y-036260X0384Y0551R000S2
+327GND              D4G1  -1          A01X+079592Y-036260X0384Y0551R000S2
-327/MODEM_LED_A     D4G   -2          A01X+080330Y-036260X0384Y0551R000S2
+327/MODEM_LED_A     D4G1  -2          A01X+080330Y-036260X0384Y0551R000S2
 327/SW3_NODE        L7    -1          A01X+064485Y-046584X0787Y1260R000S2
 327/3V3_MODEM       L7    -2          A01X+067556Y-046584X0787Y1260R000S2
 317(MOD1-NC-PAD1)   MOD1  -1    D0394PA00X+045375Y-051017X0630Y0630R090S0
-3173V3              MOD1  -2    D0394PA00X+046375Y-051017X0630Y0630R090S0
+3173V3              MOD1  -2    D0394PA00X+046375Y-051017X0630Y0630R270S0
 317D1-RESET-PAD3)   MOD1  -3    D0394PA00X+047375Y-051017X0630Y0630R090S0
 317-3V3_OUT-PAD4)   MOD1  -4    D0394PA00X+048375Y-051017X0630Y0630R090S0
 317/SW_5V           MOD1  -5    D0394PA00X+049375Y-051017X0630Y0630R090S0
@@ -670,7 +675,7 @@ P  arrayDim   N
 317MOD1-D5-PAD20)   MOD1  -20   D0394PA00X+054375Y-032017X0630Y0630R090S0
 317MOD1-D6-PAD21)   MOD1  -21   D0394PA00X+053375Y-032017X0630Y0630R090S0
 317MOD1-D7-PAD22)   MOD1  -22   D0394PA00X+052375Y-032017X0630Y0630R090S0
-317USART1_RX        MOD1  -23   D0394PA00X+050776Y-032017X0630Y0630R090S0
+317USART1_RX        MOD1  -23   D0394PA00X+050776Y-032017X0630Y0630R270S0
 317MOD1-D9-PAD24)   MOD1  -24   D0394PA00X+049776Y-032017X0630Y0630R090S0
 317OD1-D10-PAD25)   MOD1  -25   D0394PA00X+048776Y-032017X0630Y0630R090S0
 317NCE_D11-PAD26)   MOD1  -26   D0394PA00X+047776Y-032017X0630Y0630R090S0

03-Architecture-Hardware/kicad/~hbox-watchdog-v3-PROD.kicad_pcb.lck

@@ -0,0 +1 @@
+{"hostname":"Leopoldos-MacBook-Pro","username":"leo"}

03-Architecture-Hardware/kicad/~hbox-watchdog-v3-PROD.kicad_pro.lck

@@ -0,0 +1 @@
+{"hostname":"Leopoldos-MacBook-Pro","username":"leo"}

CLAUDE.md

@@ -103,6 +103,26 @@ SYS (OR merge) → SPST → MAIN5V (= Block E/P11, kills vehicle AND battery). C
 100 nF/10 µF/100 µF; fan confirmed 2-wire. Docs synced: ledger xlsx · Guía **v2.2** ·
 circuitikz **v2.1** · both proto BOMs · design-state (canonical).
 
+**EinarBoard 1.0 Rev 1.1 — audit closed, order-prep pack (2026-07-07).** The PROD carrier is
+officially **Helgen EinarBoard 1.0** (title-block *EINARBoard HBOX 1.0*), **135.1×100.1 mm**
+(grew from 120×100 on Jul-3). Pre-fab audit (`03-Architecture-Hardware/2026-07-06_…PreFab-Audit_v1.0.md`)
+**CLOSED**: H1 Q7 S/D corrected (S=VIN_SW, D=MAIN5V) · H2 Q5/Q6 → Q_NPN_BEC · H3 **Rig 22k**
+(+ **DFR1015 removed** — raw 12–24 V → 22k/10k divider + BAT54 clamp → PA5) · H4 SW_IN → PWR_MID
+1.0 mm; ERC 0 / DRC 0; **M3 closed on a physical Pro** (switchless variants: XBee socket hardwired
+to UART2 — never plug the Pro's USB-XBee port in service) · **M4 HBOX fit verified** →
+**bare-board order RELEASED**; fleet PCBA still gated by **M2** (LTC4040 bench validation) + LCSC
+re-confirm at upload. Order-prep pack in `03-Architecture-Hardware/EinarBoard-Manual/`:
+`einarboard-manual.tex` → branded 21-pp PDF (embeds the **Rev 1.1 schematic full sheet + F/In1/In2/B
+layer plots + silk assembly view**, exported fresh from the Jul-7 saves into `assets/`; the Jul-6
+`…-PROD-schematic.pdf`/`-blueprints.pdf` at 03-AH root are **stale** — pre-H1/H2) ·
+`helgen_einarboard_1.0_production_bom.xlsx`
+(Summary + Internal PCBA w/ verified LCSC + External Integration, live formulas) ·
+`tools/generate_production_bom.py` + `tools/sync_bom.py` (Excel→`pcba_bom.tex` **+
+`external_bom.tex`** — both BOMs in the report; the workbook is
+the BOM source of truth) · `scripts/prep_order_release.sh` (safe cleanup + release commit;
+dry-run default). KiCad sch↔board sync is **manual** (F8 retired). Vault note:
+`EinarBoard 1.0 — System Overview & Toolchain`.
+
 ---
 
 ## 1. System architecture (corrected from the BOM, 2026-06-20)
@@ -131,9 +151,10 @@ circuitikz **v2.1** · both proto BOMs · design-state (canonical).
 - **Power into HBOX = clean 24 V** from the cabinet (via **GX16-5**). Internal
   **Mean Well SD-15B-05** makes 5 V; **PowerBoost 1000C + 18650** is battery
   backup; **DFR1015** conditions ignition to the Blackpill. *(This diagram is the field
-  as-built; the **v3 PCB design supersedes the battery + ignition path** — DFR1015 and an
+  as-built; the **EinarBoard 1.0 carrier supersedes the battery + ignition path** — LTC4040
-  **LTC4040** battery-backup charger fold on-board, GX16 pin 3 carries raw ignition. See
+  battery-backup on-board, **DFR1015 removed entirely** (Rev 1.1): GX16 pin 3 raw ignition →
-  `03-Architecture-Hardware/watchdog-electrical-design-state.md`.)*
+  22k/10k divider + BAT54 clamp → PA5. See
+  `03-Architecture-Hardware/watchdog-electrical-design-state.md` + the 2026-07-06 audit.)*
 - **Corrections arrive over the 4G modem** (RTCM3 via NTRIP), not the GNSS — so a
   GNSS reset can't fix a dead link; recover by power-cycling the stack (v2 does).
 - **Watchdog** = STM32F411; see [[03-Architecture-Hardware/watchdog-schematic|watchdog-schematic]].
@@ -177,7 +198,7 @@ these before presenting; if it breaks one, say so and propose the compliant fix.
 | `00-Project-Management` | plan, ethos, hackathon, **financials**, **handover**, client comms, Drive tooling | [[00-Project-Management/PLAN\|PLAN]] · [[00-Project-Management/Engineering-Handover\|Engineering-Handover]] · `ethos.md` · `hackathon-plan.md` · `Financials.md` · `Drive-Upload/` · `client-comms/` |
 | `01-Requirements` | what we build | `SRS.md` · `HBOX-product-spec.md` |
 | `02-Architecture-Software` | backend/software analysis, ADRs | `backend-review.md` |
-| `03-Architecture-Hardware` | HBOX/cabinet, wiring, BOM, **watchdog PCB v3** | `hardware-respec-and-pcb-brief.md` · `cabinet-electrical-bom.md` · `watchdog-schematic.md` · `watchdog-health-telemetry.md` · `firmware-review.md` · `BOM-master.md` (+§5 Block B/E/H/I parts) · **`watchdog-pcb-v3-design.md`** (schematic spec) · `watchdog-pcb-v3-bom.xlsx` · `watchdog-pcb-v3-kicad-guide.md` (KiCad→JLCPCB) · `watchdog-pcb-v3-blockdiagram.svg` · `watchdog-protoboard-bringup.md` + `watchdog-proto-bench-bringup-v3.md` · `watchdog-connections.xlsx` (PCB pin/net list; H1 DNP; +B/H/I rows) · `watchdog-connections-rationale.md` (+§7 additions 2026-07-02) · **`watchdog-electrical-design-state.md`** (CANONICAL — read first) · **`watchdog-production-schematic-delta.md`** (PROD build spec; LTC4040 §4 values) · `kicad/` — `hbox-watchdog-v3.kicad_sch` (**DEV/proto**) · `hbox-watchdog-v3-PROD.kicad_sch/.kicad_pcb` (**PRODUCTION**: ERC 0, layout started, DRC baseline) · `Drogheda-sym.kicad_sym` (MP1584EN · LTC4040EUFD · AO4406A) · `Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx` (**proto assumptions ledger**) · `Guia-Conexion-Protoboard/` (LaTeX source) → `Drogheda_Guia-Conexion-Protoboard_ES_v2.2.pdf` · `circuitikz-wiring/` (sheet + Beamer v2.1, blocks 1–11) · `watchdog-protoboard-BOM-3boards.xlsx` + `watchdog-LISTA-DE-COMPRAS-ES.xlsx` (proto BOMs) |
+| `03-Architecture-Hardware` | HBOX/cabinet, wiring, BOM, **watchdog PCB v3** | `hardware-respec-and-pcb-brief.md` · `cabinet-electrical-bom.md` · `watchdog-schematic.md` · `watchdog-health-telemetry.md` · `firmware-review.md` · `BOM-master.md` (+§5 Block B/E/H/I parts) · **`watchdog-pcb-v3-design.md`** (schematic spec) · `watchdog-pcb-v3-bom.xlsx` · `watchdog-pcb-v3-kicad-guide.md` (KiCad→JLCPCB) · `watchdog-pcb-v3-blockdiagram.svg` · `watchdog-protoboard-bringup.md` + `watchdog-proto-bench-bringup-v3.md` · `watchdog-connections.xlsx` (PCB pin/net list; H1 DNP; +B/H/I rows) · `watchdog-connections-rationale.md` (+§7 additions 2026-07-02) · **`watchdog-electrical-design-state.md`** (CANONICAL — read first) · **`watchdog-production-schematic-delta.md`** (PROD build spec; LTC4040 §4 values) · `kicad/` — `hbox-watchdog-v3.kicad_sch` (**DEV/proto**) · `hbox-watchdog-v3-PROD.kicad_sch/.kicad_pcb` (**PRODUCTION**: ERC 0, layout started, DRC baseline) · `Drogheda-sym.kicad_sym` (MP1584EN · LTC4040EUFD · AO4406A) · `Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx` (**proto assumptions ledger**) · `Guia-Conexion-Protoboard/` (LaTeX source) → `Drogheda_Guia-Conexion-Protoboard_ES_v2.2.pdf` · `circuitikz-wiring/` (sheet + Beamer v2.1, blocks 1–11) · `watchdog-protoboard-BOM-3boards.xlsx` + `watchdog-LISTA-DE-COMPRAS-ES.xlsx` (proto BOMs) · **`2026-07-06_Drogheda_EinarBoard-1.0-PreFab-Audit_v1.0.md`** (CLOSED — Rev 1.1 fixes) · `Assembly-BOM-Split.md` + `LCSC-search-list.md` (verified LCSC) + `JLCPCB-Order-Guide.md` (ordering runbook) · `harness-connector-pinout.md` + `Socket-Pinout-Silkscreen.md` · **`EinarBoard-Manual/`** (Rev 1.1 order-prep pack: `einarboard-manual.tex` → branded PDF · `helgen_einarboard_1.0_production_bom.xlsx` · `tools/generate_production_bom.py` + `tools/sync_bom.py` Excel→LaTeX BOM sync) — plus repo-root `scripts/prep_order_release.sh` (safe cleanup + release commit) |
 | `04-Source-Code` | firmware + backend repos | `firmware/` (**own git repo `hbox-firmware`**: `blackpillrtkcode_v2/` deploy · `legacy/` v1 · `docs/LOGGING-SPEC.md` v2.1) · `htracker/` · `notifications/` · `rtk-config/` |
 | `05-Analytics-Reports` | SQL views, dashboards (VERONICA/PowerBI), **observability** | `2026-06-22_Drogheda_Manual-Logs-Grafana_v1.0.pdf` (Grafana/Loki log-consultation manual) |
 | `06-Testing-Validation` | RCA, diagnostics, test evidence, **log analysis & tooling** | `RCA-2026-06-field-failures.md` · `remote-diagnostic-protocol.md` · `2026-06-20_Drogheda_Bench-Log-Analysis_v1.0.md` (rev-3) · `2026-06-20_Drogheda_GNSS-Findings-Summary.md` · `log-analysis/` (repo **`hbox-log-tools`**: `log-explorer.html` · `analyze_logs.py` · `build_dashboard.py` · `docs/manual.pdf`) |

scripts/prep_order_release.sh

@@ -0,0 +1,119 @@
+#!/usr/bin/env bash
+# =====================================================================
+# prep_order_release.sh — Project Drogheda workspace hygiene + release sync
+# Helgen EinarBoard 1.0 Rev 1.1 — order-prep housekeeping
+#
+# SAFE BY DEFAULT: dry-run unless RUN=1. Push only with PUSH=1.
+#   ./scripts/prep_order_release.sh              # preview (deletes nothing)
+#   RUN=1 ./scripts/prep_order_release.sh        # clean + stage + commit
+#   RUN=1 PUSH=1 ./scripts/prep_order_release.sh # ...and push to remote
+#
+# NEVER touches: .kicad_sch/.kicad_pcb/.kicad_pro/.kicad_prl, netlists
+# (.net/.ipc/.dsn/.ses), python modules, xlsx ledgers, PDFs, fab outputs
+# (production/), DRC/ERC baselines, raw field logs (nested repos are
+# pruned entirely). macOS bash 3.2 compatible.
+# =====================================================================
+set -euo pipefail
+
+ROOT="$(cd "$(dirname "$0")/.." && pwd)"
+cd "$ROOT"
+RUN="${RUN:-0}"; PUSH="${PUSH:-0}"
+COMMIT_MSG="build: helgen einarboard 1.0 rev 1.1 production release core"
+
+say()  { printf '%s\n' "$*"; }
+act()  { # act <path>  — delete (or preview) one filesystem entry
+  if [ "$RUN" = "1" ]; then rm -rf -- "$1"; say "  removed  $1"
+  else say "  [dry-run] would remove  $1"; fi
+}
+
+# Prune list: never descend (nested git repos hold raw field logs/evidence;
+# 99-Archive is read-only by convention).
+PRUNE=( -path './.git' -o -path './99-Archive' \
+        -o -path './04-Source-Code/htracker' \
+        -o -path './04-Source-Code/firmware' \
+        -o -path './06-Testing-Validation/log-analysis' \
+        -o -name 'production' -o -name 'node_modules' )
+
+say "== Drogheda order-prep cleanup (RUN=$RUN PUSH=$PUSH) =="
+say "root: $ROOT"
+
+# ---- 1. Compiler / build clutter (unambiguous junk extensions) --------
+say "-- [1/4] LaTeX aux + Python cache + OS litter + KiCad autosaves"
+find . \( \( "${PRUNE[@]}" \) -prune \) -o -type f \( \
+     -name '*.aux' -o -name '*.out' -o -name '*.toc' -o -name '*.lof' \
+  -o -name '*.lot' -o -name '*.fls' -o -name '*.fdb_latexmk' \
+  -o -name '*.synctex.gz' -o -name '*.nav' -o -name '*.snm' -o -name '*.vrb' \
+  -o -name '*.bbl' -o -name '*.blg' -o -name '*.pyc' -o -name '.DS_Store' \
+  -o -name '_autosave-*' -o -name '*.kicad_sch-bak' -o -name '*.kicad_pcb-bak' \
+  -o -name '*.lck' -o -name 'fp-info-cache' \) -print | while IFS= read -r f; do
+    act "$f"
+done
+find . \( \( "${PRUNE[@]}" \) -prune \) -o -type d -name '__pycache__' -print \
+  | while IFS= read -r d; do act "$d"; done
+
+# ---- 2. LaTeX .log files — ONLY when a sibling .tex proves provenance --
+# (raw field logs elsewhere in the tree are precious evidence — untouched)
+say "-- [2/4] LaTeX build logs (require sibling .tex with same stem)"
+find . \( \( "${PRUNE[@]}" \) -prune \) -o -type f -name '*.log' -print \
+  | while IFS= read -r f; do
+    stem="${f%.log}"
+    if [ -f "${stem}.tex" ]; then act "$f"; fi
+done
+
+# ---- 3. Stray text drafts — UNTRACKED only, draft-pattern only ---------
+# Tracked .txt (e.g. DRC baselines) are never candidates; among untracked
+# .txt/.log we delete only obvious scratch names and always protect
+# drc/erc/baseline/requirements/README files.
+say "-- [3/4] Untracked stray .txt drafts / scratch logs"
+git ls-files --others --exclude-standard -- '*.txt' '*.log' 2>/dev/null \
+  | while IFS= read -r f; do
+    base="$(basename "$f" | tr '[:upper:]' '[:lower:]')"
+    case "$base" in
+      *drc*|*erc*|*baseline*|*requirements*|readme*|leeme*|*netlist*)
+        say "  protected $f" ;;
+      *draft*|*scratch*|*tmp*|*temp*|*borrador*|*notes-old*|untitled*)
+        act "$f" ;;
+      *) say "  skipped (ambiguous — review manually)  $f" ;;
+    esac
+done
+
+# ---- 4. Git stage / commit / sync --------------------------------------
+say "-- [4/4] Git release sync"
+if ! git rev-parse --is-inside-work-tree >/dev/null 2>&1; then
+  say "  not a git work tree — skipping git phase."; exit 0
+fi
+
+if [ "$RUN" != "1" ]; then
+  say "  [dry-run] git status summary:"; git status --short | sed 's/^/    /' | head -40
+  say "  [dry-run] would: git add -A && git commit -m \"$COMMIT_MSG\"${PUSH:+ && push}"
+  exit 0
+fi
+
+git add -A
+
+# Secret pre-scan (invariant #6: no secrets in the repo — ever).
+# Blocks the commit if staged additions look like credentials.
+if git diff --cached -U0 | grep -E '^\+' | grep -Ei \
+    '(password|passwd|pwd)[[:space:]]*[:=][[:space:]]*[^[:space:]]{4,}|BEGIN (RSA|OPENSSH) PRIVATE KEY|api[_-]?key[[:space:]]*[:=]' \
+    >/dev/null 2>&1; then
+  say "  !! ABORT: staged content matches a credential pattern (invariant #6)."
+  say "     Inspect with: git diff --cached | grep -inE 'password|api[_-]?key|private key'"
+  exit 1
+fi
+
+if git diff --cached --quiet; then
+  say "  nothing to commit — tree already clean."
+else
+  git commit -m "$COMMIT_MSG"
+  say "  committed: $COMMIT_MSG"
+fi
+
+if [ "$PUSH" = "1" ]; then
+  BRANCH="$(git rev-parse --abbrev-ref HEAD)"
+  say "  pushing $BRANCH -> origin (git.helgen.dev pipeline)..."
+  git push origin "$BRANCH"
+  say "  push complete."
+else
+  say "  push skipped (set PUSH=1 to sync to the remote pipeline)."
+fi
+say "== done =="