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---
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tags: [project-drogheda, hardware, bom, cost, power]
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project: Project Drogheda
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author: Helgen CTO
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date: 2026-09-09
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status: Draft — first-pass estimate
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---
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# 5 V source: on-board (V6 / U25) vs external Mean Well SD-15B-05 (V5)
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> **Bottom line:** the on-board 24→5 V block already captured in V6 costs
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> **≈ US$2.2 / MX$37 per board** in parts. The external Mean Well it replaces costs
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> **≈ MX$330 per unit** all-in as currently purchased. **Net saving ≈ MX$290/unit**
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> (≈ MX$8,700 at 30 units, ≈ MX$29,000 at 100). The money is not the interesting part —
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> the isolation loss and the 3 A → 3.5 A headroom are.
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Prices: LCSC/JLCPCB live database (2026-09-09) · FX **USD 1 = MXN 16.91**.
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---
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## 1. What each version actually does
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| | **V5 (as built)** | **V6 (as captured in the schematic)** |
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|---|---|---|
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| 24→5 V | **External** Mean Well SD-15B-05 → `P2` (JST 2-pin) → `VEH5V` | **On-board** `U25` TPS54360B: `VIN_PROT` → `VEH5V` |
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| Rating | 5 V / **3 A** isolated (1.5 kVDC) | 5 V / **3.5 A**, non-isolated, 60 V input |
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| Entry chain | `Q10` (IRFR5305) + `D10` (SMBJ33A) → fan buck only | `F2 → Q23 → D32 (SMCJ33A) → C149/C150 → U25 → D34/L22 → C153/C154` |
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| Extra parts on board | `P2` connector | 15 fitted + 2 DNP (`R124`/`R125`) |
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V6 keeps the fan buck (`U2`) and the 3V3_ETH buck (`U12`); `U7` was deleted. Neither
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ever made the main rail — this comparison is only about the `VEH5V` source.
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---
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## 2. On-board block — BOM cost per board
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`U25` TPS54360B · `L22` SRP1265A-100M · `D34` B560C · `D32` SMCJ33A · `C149`/`C150`
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2.2 µF/100 V · `C151` 100 µF/50 V · `C152` 100 nF · `C153`/`C154` 47 µF/16 V ·
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`C155`/`C156` · `R120`–`R123` — plus the entry chain `F2` · `Q23` · `D33` · `R119`.
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| Line | 30 boards | 100 boards | 500 boards |
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|---|---:|---:|---:|
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| `U25` TPS54360BDDAR (C524806) | $0.487 | $0.428 | $0.419 |
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| `L22` SRP1265A-100M 10 µH/10 A (C840531) | $0.639 | $0.554 | $0.504 |
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| `D34` B560C 5 A/60 V (C85100) | $0.220 | $0.179 | $0.158 |
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| `D32` SMCJ33A TVS (C699039) | $0.114 | $0.091 | $0.079 |
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| `C149`/`C150` 2.2 µF/100 V 1210 ×2 † | $0.180 | $0.180 | $0.160 |
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| `C151` 100 µF/50 V elco (C134502) | $0.149 | $0.149 | $0.149 |
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| `C153`/`C154` 47 µF/16 V 1210 ×2 (C5440143) | $0.185 | $0.185 | $0.127 |
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| `C152`, `C155`, `C156`, `R120`–`R123` | $0.022 | $0.022 | $0.022 |
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| **Buck subtotal** | **$1.996** | **$1.788** | **$1.618** |
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| `Q23` IRFR5305 (C2624) | $0.262 | $0.227 | $0.193 |
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| `F2` 2 A/1812 fuse †, `D33` BZX84C15, `R119` | $0.144 | $0.144 | $0.144 |
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| **Entry subtotal** | **$0.406** | **$0.371** | **$0.337** |
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| **Parts / board** | **$2.40** | **$2.16** | **$1.96** |
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| JLC extended-part setup (7 new uniques × $3, amortised) | $0.70 | $0.21 | $0.04 |
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| SMT placement (~50 joints) | $0.10 | $0.09 | $0.09 |
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| **All-in / board** | **$3.20 · MX$54** | **$2.46 · MX$42** | **$2.09 · MX$35** |
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† `C149`/`C150` and `F2` have no LCSC part pinned yet — estimated at $0.09 and $0.12.
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Board outline stays 140×100, so **the block costs zero PCB area money**.
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---
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## 3. External Mean Well — cost per unit
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| Item | MXN | Source |
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|---|---:|---|
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| Mean Well SD-15B-05 | **300** | `BOM-master.md` §1 item 12 (as purchased locally) |
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| — same part, direct import | *189–200* | Mouser $11.15 / Arrow $11.85 @100 |
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| DC PSU bracket (ASA print) | 20 | `BOM-master.md` §1 item 3 |
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| `P2` JST-XH + housing + crimps + wire | ~12 | est. |
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| **Total** | **≈ 332** *(≈ 221 if imported direct)* | |
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Plus ~5 min/unit of mounting and wiring labour, and one more connector in the
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vibration path — `P2` is exactly the class of joint the RCA blamed.
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---
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## 4. Net
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| Volume | External (local price) | On-board | **Saving** |
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|---|---:|---:|---:|
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| per unit | MX$332 | MX$42 | **MX$290** |
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| 30 units | MX$9,960 | MX$1,260 | **MX$8,700** |
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| 100 units | MX$33,200 | MX$4,200 | **MX$29,000** |
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Against best-case direct import (MX$221) the saving is still **≈ MX$180/unit**.
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---
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## 5. What actually decides this (not the money)
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**For on-board:**
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- **3 A → 3.5 A.** The 10-Ago boot-loop was the SD-15B's 3 A ceiling. It also makes the
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standing `RS1` errata (3.12 A input limit sitting *above* a 3 A supply) go away by itself.
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- One fewer sub-assembly, one fewer connector, no import lead time on a PSU.
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**Against on-board:**
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- **Isolation is lost.** SD-15B-05 is 1.5 kVDC isolated; TPS54360B is not. HBOX ground
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becomes the cabinet 24 V return. The ignition already shares that return — worth a
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deliberate look at the ground topology before this is locked.
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- The EMC burden moves onto our board. The copper plan already calls `U25`'s input loop
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the loudest on the PCB; that stops being Mean Well's problem.
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- No field-replaceable part. Today a dead PSU is a 10-minute swap; after this it is a board.
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---
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## 6. 🔴 Side finding — the MP1584s cost more than this whole question
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Genuine `MP1584EN-LF-Z` (C15051) is **$2.21 @100** on LCSC. V6 carries two (`U2`, `U12`)
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= **$4.41 / MX$75 per board**, against **$0.43** for the TPS54360B or **$0.58** for the
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AP64350 already qualified as `U20`.
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Re-speccing those two rails onto a part already in the BOM saves **≈ $3.5 / MX$59 per
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board** — more than the entire 5 V-source saving — and it also retires EMC findings 3 and 4,
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which named the MP1584s directly. Worth a separate decision.
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---
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## 7. Battery — LiPo vs Li-ion, first pass
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| | Energy | Price | **MXN / Wh** |
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|---|---:|---:|---:|
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| **Li-ion** Hyvel 18650 1S4P (current pack) | ~43 Wh | MX$204 | **≈ 4.7** |
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| **LiPo** 2000 mAh 1S, SparkFun @ Sandorobotics | 7.4 Wh | MX$270 | **≈ 36** |
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| **LiPo** 2000 mAh 1S, generic (indicative) | 7.4 Wh | ~MX$90–160 | **≈ 12–22** |
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To reach today's 43 Wh with 2000 mAh pouches you need **6 in parallel**:
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MX$540–1,620 against MX$204. Li-ion 18650 is **3–8× cheaper per Wh**, and it is also the
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better cell for a box that runs hot — pouch cells swell, and heat is this product's
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standing failure mode.
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LiPo buys thickness and form factor, nothing else. Treat the 2000 mAh cells as bench
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hardware. ⚠ The generic LiPo row is indicative — MercadoLibre/Amazon MX would not serve
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prices to an automated fetch; get one real quote before this line is used in a decision.
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@ -0,0 +1,194 @@
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---
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tags: [project-drogheda, firmware, power, battery, thermal]
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project: Project Drogheda
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author: Helgen CTO
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date: 2026-09-09
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status: Draft — design proposal
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---
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# Backup mode: duty-cycled low power, and what it does to the charging problem
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> **Bottom line:** yes, do the duty-cycle. But **the wake interval barely matters — the
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> sleep floor is everything.** 10 min vs 60 min changes runtime by 2 %. Dropping the
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> sleeping draw from 150 mW to 20 mW changes it by **5.5×**. And the payoff is bigger than
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> runtime: at ~1.5 Wh/day the pack needs **~10 minutes of charging a day**, which the
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> narrow cool window we already have can supply. **The duty-cycle largely dissolves the
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> temperature problem** — that is the real reason to do it.
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---
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## 1. "Can't we just move the charge temperature?"
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The **threshold** is ours (`RNTB`). The **limit** is the cell's. Charging an NMC/LCO 18650
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at 55 °C is not a tuning choice — it is accelerated SEI growth, gas generation and a safety
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liability inside a sealed IP67 box in full sun. Not something to ship on 30 units.
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What you *can* legitimately buy, without changing the cell:
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- **Lower the float.** Damage rate is temperature × voltage × time. You are already at
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4.00 V rather than 4.20 V, which is most of the win. `JP3`/`JP4` → F1=0/F0=0 gives
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**3.95 V** and a little more margin. That justifies nudging the hot pause to maybe
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**48–50 °C** *if the cell's datasheet supports it*. A few degrees, not fifteen.
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- Anything beyond that needs a cell rated for it — see the high-temp LFP note.
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**But read §3 before deciding any of this.**
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---
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## 2. Duty-cycled backup — the numbers
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Pack ~43 Wh, 85 % usable = **36.5 Wh**. Boost efficiency 88 %.
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**Today, continuous:** ~2.5 W at the 5 V rail → **~13 h**; with the fan running, ~8 h.
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**Duty-cycled**, wake = 10 s at 1.5 W (modem held in PSM, no re-attach):
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| sleep floor | 10 min | 30 min | 60 min |
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|---|---:|---:|---:|
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| 150 mW | 7.7 d | 8.5 d | 8.7 d |
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| 100 mW | 10.7 d | 12.4 d | 12.9 d |
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| 50 mW | 17.9 d | **23.0 d** | 24.7 d |
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| 20 mW | 29.8 d | **47.3 d** | 55.5 d |
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| 10 mW | 38.3 d | 73.1 d | 94.6 d |
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If the carrier will not give us PSM and every wake is a full LTE re-attach (~35 s):
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| sleep floor | 10 min | 30 min | 60 min |
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|---|---:|---:|---:|
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| 150 mW | 5.6 d | 7.5 d | 8.1 d |
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| 50 mW | 9.7 d | 16.9 d | 20.8 d |
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| 20 mW | 12.5 d | 27.3 d | **38.8 d** |
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**Read the rows, not the columns.** Your 10-minute instinct costs 20–50 % against 30 min
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and buys the operator nothing they need. Go **30 min**, and spend the effort on the floor.
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---
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## 3. 🔴 The part that matters most — it also fixes the charging
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| Duty cycle | Daily energy | Charging needed at 2.42 A |
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|---|---:|---:|
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| 30 min wake, 50 mW sleep | 1.59 Wh/day | **~10 min/day** |
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| 30 min wake, 20 mW sleep | 0.77 Wh/day | **~5 min/day** |
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| 10 min wake, 100 mW sleep | 3.41 Wh/day | ~22 min/day |
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Today the pack must replace ~30 Wh after a long outage and we give it a charge window that
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closes at 42 °C. At **1.6 Wh/day** you need *ten minutes* of cool weather. Port nights drop
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well below 40 °C — the existing window is already enough.
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So the ordering changes: **do the firmware work first.** It is free, it ships to the
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installed fleet over the existing update path, and it may retire the cell question entirely.
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Keep the high-temp LFP option open — but stop treating it as the first move.
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It also means the 43 Wh pack is oversized. At 1.6 Wh/day a **single 12 Wh cell gives 6+
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days** — cheaper, cooler, smaller, easier to keep topped up.
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---
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## 4. What actually sets the sleep floor
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Ranked by what I expect to find on the bench. **All of these need measuring, not assuming.**
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| Suspect | Est. | Fix |
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|---|---:|---|
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| **`U17` AMS1117-3.3** — quiescent 5 mA typ / 11 mA max, and it burns 1.7 V × I as heat | **25–55 mW** | Swap for a low-Iq LDO. `U21` (AP2112K, 55 µA) is already in the BOM; a TPS7A02-class part is ~1 µA. **This is probably the single biggest item and it is a one-part change** |
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| **`K1` coil** — ~30 mA from SYS5V while the MCU is inserted | **150 mW** | See §5 |
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| **LTC4040 boost** at very light load — light-load efficiency and its own Iq | 10–40 mW? | Measure. If bad, this caps everything and needs a rethink |
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| Battery gauge LEDs `PB12–15`, `D17`, `D18`, `DB1–4`, `D4G1` | 50–150 mW | All off in backup, or one 50 ms blink per wake |
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| `U12` MP1584 → `/3V3_ETH` + `W5500` (~130 mA) | 400+ mW | Ethernet is useless on battery — disable `U12`, hold `W5500` in reset |
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| `MAX3232` charge pump, `SP3485`, `SC16IS752` | 5–15 mW | Shutdown pins / disable |
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| `U18` `V_BCKP` | **0.15 mW** | ✅ already right — see §6 |
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| MCU in STOP + LSE RTC | 0.1–0.2 mW | Achievable; today it is ~165 mW because `loop()` never stops |
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⚠ **Today's `SLEEP` state is not a low-power state.** It cuts `PWR_CTRL` and then keeps
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spinning `loop()` at 84 MHz with Serial, I²C polling and the gauge alive. Real STOP-mode
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+ RTC wake is the substantive firmware change here. `Y4` (32.768 kHz) is on the board, so
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LSE-driven RTC wake is available.
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---
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## 5. `K1` — reverse the earlier call
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The Firmware v3.1 brief said: *"bobina ~30 mA de SYS5V … se queda insertado; 30 mA contra
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12 Ah es ruido."* That was correct for a 13-hour continuous budget. **It is wrong for a
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duty-cycled one** — 150 mW against a 20–50 mW target is 3–7× the entire rest of the floor,
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and it alone would cap you at 8 days no matter what else you fix.
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**New rule: `BYP_CTRL` low between wakes, high only during the TX window.** 150 mW × 10 s
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per 30 min = 0.8 mW average — it disappears. The fail-safe semantics are unchanged
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(de-energised = F9P→modem direct), and between wakes there is nothing to inject anyway.
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Longer term, a **latching relay** (G6K-class, pulse to switch, zero hold) removes the
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question permanently. Worth pricing for the v6 BOM.
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---
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## 6. Don't chase position — you already have the right parts
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The machine is **parked**. Its position does not change during an outage, so re-acquiring
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a fix every wake is pure waste.
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- `V_BCKP` is already wired (`/3V3` via 1 kΩ + Schottky, 45 µA) and keeps ephemeris, so
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when you *do* want a fix it is a hot start (~2–5 s), not a 30 s cold start. Good design,
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already done.
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- Report the **stored** position with a `pwr=BATT` flag and a staleness marker. Take a real
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fix only every **N-th** wake (e.g. every 2 h) as an anti-theft check.
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- **`U26` (SC7A20 accelerometer) is on the v6 board.** Wire its interrupt to a wake-capable
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pin and you get motion-triggered wake for free: asleep while the machine is still, awake
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within a second if someone moves it. That is strictly better than polling GNSS.
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⚠ `U26` does not appear in any of the v6 briefs — confirm what it was placed for and that
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its INT line reaches an EXTI/wake pin before counting on this.
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---
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## 7. Modem: PSM before power-cycling
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Power-cycling the modem every 10 minutes means paying a full network attach every 10 minutes
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— 20–30 s at 100–300 mA with 2 A bursts. **3GPP PSM keeps the module registered while it
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sleeps at tens of µA**, with no re-attach cost; eDRX is the lighter variant.
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- The A7670SA (Cat-1bis) supports PSM. **Whether you get it is a Telcel question**, not a
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module question — it depends on the APN/plan and the network granting the requested TAU.
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**Verify this early; the whole table in §2 hinges on which column you land in.**
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- Fall back to `MODEM_PWR_EN` power-cycling only if PSM is refused — and then stretch the
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interval to 30–60 min so the attach cost amortises.
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⚠ **Inrush risk.** You already tripped the LTC4040 `PFI` at 4.60 V on LTE inrush with no
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pack connected. Duty-cycling means taking that 2 A / 7.6 W burst **repeatedly, at low SoC,
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on a hot or aged pack**. Hold the ≥ 470 µF modem bulk, and bench the worst case: coldest
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SoC × hottest pack × attach burst. This is the most likely way the design fails in the field.
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---
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## 8. Proposed state machine
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```
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RUNNING ──(5V_SENSE PA4 falls, debounced)──► BACKUP_ENTRY
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BACKUP_ENTRY: hot-start fix (or use last) → $PHLG{pwr=BATT, evt=POWER_LOSS} → TX now
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(operators care most in the first minute — do not make them wait 30)
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→ BACKUP_SLEEP: PWR_CTRL low · MODEM→PSM · BYP_CTRL low · U12/W5500 off
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transceivers shutdown · LEDs off · fan off · MCU STOP + RTC(T)
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→ wake on RTC(T) or accelerometer INT or PA4 rising:
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read vbat/tbat → if vbat < BAT_CRITICAL: TX final "shutting down" → deep off
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else: BYP_CTRL high → modem wake → TX heartbeat → back to BACKUP_SLEEP
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→ PA4 rising: full wake, resume RUNNING
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```
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**Adaptive cadence** (cheap, and better product behaviour): 15 min for the first hour,
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30 min to 24 h, 60 min after. Include the **drain rate** in `$PHLG` so ops can see how long
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the unit has left rather than guessing.
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**Fan: off in backup, full stop.** A 5 V fan is 0.75–1.25 W — it would consume the entire
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budget in hours. If the box is too hot to sit idle without a fan, that is a thermal problem,
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not a power-management one.
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---
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## 9. Do these three first
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1. **Measure the sleeping current** on a v5.5 board with `PWR_CTRL` low, MCU in STOP, and
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the loads in §4 disabled one at a time. That single number decides everything in §2.
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2. **Ask Telcel about PSM/eDRX** on the current APN and plan. It sets which table applies.
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3. **Pull the `tbat`/`tntc` fleet histogram** — with §3's 10 min/day figure in hand, the
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question is no longer "is it ever cool enough" but "is it cool enough for ten minutes",
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which is a much easier bar and may already be met.
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@ -0,0 +1,143 @@
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---
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tags: [project-drogheda, hardware, battery, thermal, power]
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||||
project: Project Drogheda
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author: Helgen CTO
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date: 2026-09-09
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status: Draft — decision input
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---
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# Backup cell at 45 °C: why Li-ion is failing, and what replaces it
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> **Bottom line:** LiPo is not an upgrade — a LiPo pouch *is* Li-ion, in a worse package.
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> And before changing any cell: **`RNTB` = 10 k makes the LTC4040 stop charging at
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> +40…+42 °C.** At a 45 °C port the pack essentially never charges. That is a resistor,
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> not a chemistry. The chemistry that then lets you *raise* that limit is
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> **high-temperature LiFePO4**, which the LTC4040 already supports — `JP2` re-strap, no respin.
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---
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## 1. LiPo is the wrong direction
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A "LiPo" pouch is lithium-ion (LCO or NMC) in a soft laminate bag. Same 0–45 °C charge
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window, same calendar aging, and **worse** in a hot sealed box: no vent, no CID, and it
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swells. The 2000 mAh cells are bench hardware. Keep them on the bench.
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---
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## 2. 🔴 The charger is refusing to charge — and it is our resistor
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`RNTB` (10 k 1 %) biases the pack NTC (`RT1`, 10 k, on the cell via `P4.3`). The LTC4040
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pauses charging when the NTC falls to **53.6 % of `RBIAS`** and resumes below **325 %**.
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With `RBIAS` = 10 k that puts the charge window at:
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| NTC β | Charge window today |
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|---|---|
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| B3380 | **−3.1 °C … +42.4 °C** |
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| B3950 | **+0.6 °C … +39.7 °C** |
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Port operating temperature is ~45 °C. **The pack sits above the hot-pause threshold
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for most of the working day**, so it never reaches full charge and the backup is not
|
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there when the power drops. The MCU's own `CHRG_EN` hot-cut sits on top of this.
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This is very likely most of the "poor performance" — and it is **not** the cell's fault.
|
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Note the earlier fleet finding blamed no-charge on the LTC4040 safety-timer latch; a
|
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pack that is repeatedly hot-paused mid-charge is exactly how you *reach* that latch.
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### Re-scaling `RNTB`
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|
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You cannot simply raise this on the current cell — an NMC/LCO 18650 **must not** be
|
||||
charged at 55 °C. Raise it *together with* the chemistry change:
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|
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| Target hot pause | β | New `RNTB` | Resulting window |
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|---|---|---|---|
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| +55 °C | B3380 | **6.62 k** | +6.1 … +55 °C |
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| +55 °C | B3950 | 5.56 k | +12.3 … +55 °C |
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| **+60 °C** | **B3380** | **5.67 k → 5.6 k E24** | **+9.7 … +60 °C** |
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| +60 °C | B3950 | 4.64 k | +16.0 … +60 °C |
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|
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`RBIAS` sets both ends, so raising the hot limit raises the cold one. **Specify the
|
||||
B3380 NTC** (the delta doc already calls B3380 "ideal", B3950 "acceptable") — with B3950
|
||||
you would refuse to charge below +16 °C, which is a real winter night in Ensenada.
|
||||
|
||||
⚠ Computed from the datasheet's 53.6 % / 325 % ratios and a β model with R25 = 10 k.
|
||||
Check against the actual NTC part's R/T table before cutting the BOM.
|
||||
|
||||
---
|
||||
|
||||
## 3. The cell: high-temperature LiFePO4 26650
|
||||
|
||||
| | Today — NMC/LCO 18650 | **High-temp LFP 26650** |
|
||||
|---|---|---|
|
||||
| Charge temp | 0…45 °C | **−20…60 °C** (Topwell 3600 mAh) · **0…75 °C** (JGNE 4000 mAh) |
|
||||
| Discharge temp | −20…60 °C | −50…80 °C · −30…75 °C |
|
||||
| Nominal | 3.6 V | 3.2 V |
|
||||
| Cell energy | ~11 Wh (3 Ah) | 11.5 Wh (3.6 Ah) · **12.8 Wh (4 Ah)** |
|
||||
| Cycle life | 300–500 | **≥ 2000** to 80 % |
|
||||
| Thermal runaway onset | ~150–200 °C | ~270 °C (olivine) — does not propagate |
|
||||
| Calendar aging at 45 °C | fast | far slower |
|
||||
|
||||
**4P of the 3.6 Ah cell = 46 Wh; 4P of the 4 Ah = 51 Wh** — both at or above today's
|
||||
~43 Wh. Even 3P clears 38 Wh.
|
||||
|
||||
### The board already supports it — one jumper
|
||||
|
||||
LTC4040 `F2` selects chemistry: **high = Li-Ion, low = LiFePO4**. Float table:
|
||||
|
||||
| F1 | F0 | F2 = 1 (Li-Ion) | F2 = 0 (LiFePO4) |
|
||||
|---|---|---|---|
|
||||
| 0 | 0 | 3.95 V | 3.45 V |
|
||||
| **0** | **1** | **4.00 V ← we are here** | **3.50 V ← we land here** |
|
||||
| 1 | 0 | 4.05 V | 3.55 V |
|
||||
| 1 | 1 | 4.10 V | 3.60 V |
|
||||
|
||||
Current straps are F2=1 / F1=0 / F0=1. **Flip `JP2` (F2) only** → 3.50 V LFP float.
|
||||
The 2026-07-06 pre-fab audit already recorded this path as preserved. No schematic
|
||||
change, no respin. 3.50 V on LFP is ~90 % SoC — deliberately shy of 3.65 V, which is
|
||||
exactly what you want for calendar life at temperature. `JP3` to F1=1 gives 3.60 V if
|
||||
you later want the last few percent.
|
||||
|
||||
### What else must change
|
||||
|
||||
1. **`RNTB` → 5.6 k** (§2) — without this the swap changes nothing; the charger still
|
||||
pauses at 42 °C.
|
||||
2. **Firmware `BAT_CRITICAL` / `BAT_RECOVERY`.** LFP's discharge curve is flat at ~3.2 V
|
||||
from 90 % to 15 % SoC. Voltage-based SoC stops working. Re-derive the thresholds
|
||||
against the knee (~2.9 V), and expect the gauge to be near-useless mid-band —
|
||||
coulomb-count or accept a three-state indicator. The firmware review already flagged
|
||||
these thresholds as bench-tune items for the 4.00 V pack; this makes it mandatory.
|
||||
3. **MCU `CHRG_EN` hot-cut threshold** — raise in step with `RNTB`, or it becomes the
|
||||
new binding limit.
|
||||
4. **LTC4040 boost current.** 3.2 V nominal instead of 3.6 V ⇒ ~12 % more pack current
|
||||
for the same backup watts. Re-check against the boost limit and the `RS1` errata fix.
|
||||
5. **Mechanical.** 26650 is 26.5 mm vs 18.5 mm and ~85 g/cell. New ASA battery-case
|
||||
print, and re-check the 4P footprint inside the HBOX.
|
||||
6. **Sourcing.** The high-temp grades are Chinese-supplier parts (JGNE, Topwell class),
|
||||
not a shelf item in MX. Check MOQ, lead time and whether they will give a real R/T
|
||||
and cycle-at-temperature spec before this goes on the 30-unit BOM.
|
||||
|
||||
---
|
||||
|
||||
## 4. Alternatives, briefly
|
||||
|
||||
| Option | Verdict |
|
||||
|---|---|
|
||||
| **High-temp LFP 26650** | ✅ **Recommended.** Solves charge-at-temperature, board already supports it, cost/Wh comparable |
|
||||
| **Supercap / LIC hold-up** | −40…+65/85 °C, no charge-temperature window at all, effectively infinite cycles — but ~1/20 the energy. **The right answer if the real requirement is "report a power-loss alarm and shut down cleanly" rather than "run for hours".** Pin the requirement before dismissing it again |
|
||||
| **Smaller pack, better cell** | Nobody has pulled this lever. 43 Wh is a lot for a parked machine. Halve the requirement and the thermal problem halves with it |
|
||||
| **LTO** | Best temperature range and cycle life, but 2.4 V nominal breaks the LTC4040's 1S window entirely — new charger. Low energy density, expensive, hard to source. **Out** |
|
||||
| **High-temp-rated NMC 18650** | Keeps the form factor, but you are still fighting the same chemistry for a few °C. Marginal |
|
||||
| **NiMH** | High self-discharge at temperature, and trickle-charging hot is its own failure mode. **Out** |
|
||||
|
||||
---
|
||||
|
||||
## 5. Do this first — you already have the data
|
||||
|
||||
Do **not** buy cells on an assumption. `tbat` (TMP102 on the pack) and `tntc` are already
|
||||
in `$PHLG` and already landing in `htracker`. Pull the fleet histogram and answer:
|
||||
|
||||
1. What is the **actual** pack temperature distribution, by unit and by hour?
|
||||
2. What **fraction of the day** does it sit above the current ~40–42 °C hot pause?
|
||||
3. Does `cflt` / charge-fault correlate with those windows?
|
||||
|
||||
Question 2 is the number that decides whether this is a resistor change, a chemistry
|
||||
change, or both. It is one query against data we are already collecting.
|
||||
@ -1 +1 @@
|
||||
Subproject commit 47d1a1e5a5c17fef7f1cbb131ccf67b674ac2149
|
||||
Subproject commit 63dfbaa351c645ba825674a7c668b29e92a8c2c3
|
||||
Loading…
Reference in New Issue
Block a user