Placement companion for the 140 × 100 re-layout — every capacitor's owner, what clusters together, and the EMC order of work. Cap ownership below is computed from the board netlist, not from memory.
Before placing anything: run Update PCB from Schematic once more. The NTC2 label was sitting on PA7 (TIMEPULSE) and merged the nets — it is fixed in the schematic (commit ba70f62), and the sync re-nets P18/R126/C157 to a clean /NTC2. Tick “delete footprints with no symbol” in that dialog.
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Known leftovers from the auto-clustering: ~54 small courtyard overlaps, nearly all against the legacy V5 regulator families that kept their old spots — L2/D2 (under U19's new outline), L6/DB2/DB3/Q2/Dbk1 near U25, C40, R40/R41 at Y3. Drag those few aside first and the board is clean.
§0Three laws that decide EMC at placement time
@@ -72,54 +73,47 @@ a{color:var(--plane)}
Aggressors far from victims
Four switchers, one LTE transmitter, one −167 dBm GNSS receiver on one board. Distance and an unbroken In1 ground plane are the only broadband shields you get for free.
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§1Suggested floorplan
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§1Floorplan as clustered (NW ETH · NE LTE · SW GNSS · SE power)
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§2Vehicle power entry — U25 TPS54360B hot loop
@@ -168,7 +162,7 @@ a{color:var(--plane)}
C143
100 nF RF
DC block
inline in the 50 Ω run between L21 tap and J12
D27
ESD9L (≤0.5 pF)
J12
at the connector, stub-less tap on the RF line
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This corner is the victim: no switcher, no inductor, no fast digital within ~25 mm; nothing but solid In1 ground under the module and the RF run. TIMEPULSE to the MCU is the one digital line that leaves — route it away from the RF path.
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This corner is the victim: no switcher, no inductor, no fast digital within ~25 mm (U25 sits ~95 mm away in the SE, the fan buck ~130 mm NE — keep it that way); nothing but solid In1 ground under the module and the RF run. TIMEPULSE to the MCU is the one digital line that leaves — route it away from the RF path.
§6MCU core — U16 analog care
@@ -206,12 +200,12 @@ a{color:var(--plane)}
§9Order of work from here
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Update PCB from Schematic (NTC2 re-net), then place by §1–§8. Field connectors on one edge — every cable is an antenna, and one entry edge keeps their common-mode currents off the board.
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Update PCB from Schematic (NTC2 re-net), then fine-tune inside the §1 regions. Field wiring now enters mostly along the north edge + P1 at the SE corner — keep each connector beside its block, and its TVS/filter parts right at the jack, so cable common-mode currents stay off the board core.
Say the word and I re-add the four zones — F.Cu GND pour, In1 GND (unbroken, especially under both RF runs and the crystals), In2 3V3, B.Cu GND — plus a stitching-via plan: 5 mm grid around RF, via fence along the board edge.
Route in this order: ① both 50 Ω RF runs (CPWG on F.Cu over In1, JLC7628 ≈ 0.35/0.25 mm — confirm in the JLC calculator and order controlled impedance) · ② the two hot loops and VBAT ≥ 3 mm · ③ /SW_BAT ≥ 2 mm + /BAT_PLUS ≥ 1.5 mm with via farms · ④ USB and ETH pairs · ⑤ sense lines · ⑥ everything else.
Refill zones, full DRC, then the G2 external review checkpoint before ordering.
Bench items carried forward: measure U21's 3V3_GNSS rise (F9P ramp window), verify U25's EP against the TI DDA drawing, and the DzG1 jumper check on the fabbed v5.5 boards.
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EinarBoard HBOX v6 · Helgen · generated 02-Sep-2026 from the live netlist (commit ba70f62).
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EinarBoard HBOX v6 · Helgen · updated 03-Sep-2026 to the clustered layout (commits ba70f62 · c7d2552).