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# EinarBoard V5.6 — Informe de cambios al esquemático (v1.0)
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**Fecha:** 2026-09-28 · **Base:** `hbox-watchdog-v5` (V5.5 as-fabbed, intacto) · **Nuevo proyecto:** `kicad/hbox-watchdog-v56.*` · **ECO implementada:** `2026-09-27_Drogheda_EinarBoard-V5.6_ECO_ES_v1.0.md` secciones A, B, C, D3, E5, F · **Autor:** Claude (edición por KiCad MCP + script con respaldo y verificación de UUID) · **Estado:** listo para revisión de Leo en KiCad; **no** se ha ejecutado *Update PCB from Schematic* ni se ha tocado el layout.
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## 0. Resumen
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| Ítem | Resultado |
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|---|---|
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| Proyecto V5.6 | `hbox-watchdog-v56.kicad_sch/.kicad_pro/.kicad_pcb/.kicad_prl/.kicad_dru` (copia de v5; `.kicad_pro/.kicad_prl` apuntan a los nombres v56). Librerías `sym-lib-table`/`fp-lib-table` sin cambio (ya incluían `Drogheda-v6`). |
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| V5.5 as-fabbed | **Byte-idéntico**: sha256 de los 5 archivos `hbox-watchdog-v5.*` iguales antes y después (tabla §7). |
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| ERC (kicad-cli) | **1 error, 27 warnings — todos preexistentes** en V5.5 (línea base: 1 error, 33 warnings). La ECO no introduce ninguna violación. Detalle en §5. |
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| Netlist | Exportada con kicad-cli (`_to_delete/v56-work-20260928/hbox-watchdog-v56-netlist.xml`). Diff pin-a-pin contra la netlist de V5.5: **58 diferencias, todas las previstas por la ECO, ninguna otra** (§4). |
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| Refs nuevas | C119 C120 C121 C122 C123 C124 · R105 R106 R107 R108 R109 R110 R111 R112 · U18 · D19 · JP6 (17 componentes). |
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| Refs con cambio de valor/símbolo | U7 · L7 · Cbst2 · Rcomp2 · Ccomp2 · Rfreq2 · C3 · C43 · RS1 · R50 · F1 · Dbk2 (DNP). |
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| PCB | `hbox-watchdog-v56.kicad_pcb` es copia byte-a-byte de v5; los footprints nuevos entran con *Update PCB* (§8). |
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| PDF | `03-Architecture-Hardware/hbox-watchdog-v56-schematic.pdf` (exportado con kicad-cli para revisión rápida). |
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Nombres del ECO → refdes reales asignados: `R_EN` → **R105** (10 k serie) + **R106** (100 k a GND) · `R_RSTM` → **R107** · `R_LEDM` → **R108** · `R_ONS` → **R109** (DNP) · `R_ASC` → **R110** (DNP) · `R_TAP` → **R111** · `R_ETHPD` → **R112** · `Cin U7` → **C119/C120** (22 µF 0805) + **C121** (10 µF 1206) · 22 µF extra en 3V3_MODEM → **C122** · `U4b` → **U18** · `D_J9` → **D19** · `JP_CUT` → **JP6** · 47 pF de COMP → **C123** · desacoplo de U18 → **C124**. (KiCad exige que la referencia termine en número, por eso no se usó «U4b».)
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## 1. Cambios en componentes existentes (antes → después)
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| Ref | V5.5 | V5.6 | LCSC | Nota |
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|---|---|---|---|---|
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| **U7** | MP1584EN, `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`, LCSC C15051 | **AP64350SP-13**, `Drogheda-v6:SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP` (mismo footprint que U20 de v6) | **C2071691** | Mismo UUID de símbolo que en v5 (`56a2435b-…`) → *Update PCB* sustituye el footprint en su sitio. Pinout nuevo: 1 BST, 2 VIN, 3 EN, 4 RT/CLK, 5 FB, 6 COMP, 7 GND, 8 SW, 9 EP. |
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| U7 VIN | `SW_5V` (pines 2 y 7) | **`SYS5V`** (pin 2) | | El módem ya no cuelga de Q1/F1. `SW_5V` queda solo con C3, C40, MOD1.5, Q1.3, PF5 (verificado §4). |
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| U7 EN | `SW_5V` | **`MODEM_EN_U7`** (R105 10 k desde `MODEM_EN`/PC3, R106 100 k a GND) | | Módem apagado con el MCU en reset/DFU. |
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| Cbst2 | 10 nF (BST3↔SW3_NODE) | **100 nF** | C14663 | Cap de bootstrap del AP64350 (v6 usa 100 nF). |
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| Rcomp2 | 40.2 k (COMP3→COMP3_C) | **14 k** | C22803 | Compensación copiada de U20 v6 (R116). |
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| Ccomp2 | 2.2 nF (COMP3_C→GND) | **3.3 nF** | C1613 | Copiada de U20 v6 (C141). |
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| Rfreq2 | 100 k (FREQ3→GND, pin FREQ del MP1584) | **200 k/1 %** (misma net `FREQ3`, ahora al pin 4 **RT/CLK**) | C25811 | Copiada de U20 v6 (R117). La net conserva el nombre `FREQ3`. |
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| Dbk2 | SS34 (SW3_NODE→GND, diodo de recirculación) | SS34 **DNP** (`dnp yes`) | C8678 | El AP64350 es síncrono; se deja el footprint por si se vuelve al MP1584. |
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| L7 | 10 µH/2 A, LCSC C17700171 | **4.7uH/4A** | **C17700167** | Sunlord MWSA0804S-4R7MT (misma familia 8.8×8.2 mm que la pieza actual; igual que L20 de v6). Footprint sin cambio. |
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| C43 | 100uF/6.3V elco 6.3×7.7 (3V3_MODEM) | **220uF/16V polymer** | **C881921** | Lelon OVZ221M1CTR-0608, mismo can. |
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| C3 | 47uF elco 6.3×7.7 (SW_5V) | **220uF/16V polymer** | **C881921** | |
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| RS1 | 8mR/1% 1206 | **10mR/1%/1W** | **C105362** | Límite de entrada 2.5 A. |
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| R50 | 825R/1% | **1.5k/1%** | **C22843** | I_chg 1.33 A. |
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| F1 | PPTC 3A 1812 (C20627123) | **PPTC 4A/1812 low-R** | **TBD** | Solo nota: elegir ≥ 4 A hold / ≤ 20 mΩ (o 0 Ω + protección en Q1). Footprint 1812 sin cambio. |
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| R53 | 499k | 499k (sin cambio) | | Decisión J3 del ECO. |
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| RNTB | 10k | 10k (sin cambio) | | Solo BOM; depende de la química (D1). |
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| R60/R61 | 100k / 31.6k | sin cambio | | FB 0.8 V → 3.33 V, igual en AP64350. |
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| C40, C41 | 22 µF (SW_5V / 3V3_MODEM) | sin cambio | | Ver §6 (decisión pendiente sobre C40). |
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Cada componente tocado lleva una propiedad `Note` que empieza por «V5.6:» y la propiedad `LCSC` actualizada (mismo campo que ya usaba la BOM del proyecto).
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## 2. Componentes nuevos
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Colocados en la zona libre inferior-izquierda de la hoja A1 (x 80–205 mm, y 380–520 mm), en cuatro filas con un texto de cabecera «V5.6 ECO (2026-09-28)». Todo va por etiquetas locales (net labels), igual que el resto del esquemático, así que Leo puede moverlos a su bloque sin rehacer conexiones.
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| Ref | Valor | Footprint | LCSC | Conexión (pin 1 / pin 2) | ECO |
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| C119 | 22uF | C_0805 | C86817 | SYS5V / GND — Cin de U7, < 3 mm de VIN | A |
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| C120 | 22uF | C_0805 | C86817 | SYS5V / GND — Cin de U7 | A |
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| C121 | 10uF/25V | C_1206 | C14860 | SYS5V / GND — Cin bulk de U7 | A |
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| C122 | 22uF | C_0805 | C86817 | 3V3_MODEM / GND — segundo 22 µF de salida | A |
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| C123 | 47pF | C_0603 | C1671 | COMP3 / GND — parte del lazo de compensación (v6 C142) | A |
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| R105 | 10k | R_0603 | C25804 | MODEM_EN (PC3) / MODEM_EN_U7 | A/B |
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| R106 | 100k | R_0603 | C103211 | MODEM_EN_U7 / GND | A/B |
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| R107 | 1k | R_0603 | C14676 | MODEM_RST_MCU (PC1) / MODEM_RST | B |
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| R108 | 10k | R_0603 | C25804 | MODEM_LED_MCU (PC2) / MODEM_LED | B |
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| R109 | 10k **DNP** | R_0603 | C25804 | MODEM_ON_SLEEP (PC4) / XBEE_ONSLP (J8.3) | B |
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| R110 | 10k **DNP** | R_0603 | C25804 | MODEM_ASSOC (PC5) / XBEE_ASSOC (J8.5) | B |
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| R111 | 1k | R_0603 | C14676 | RTCM_TAP (PC7 = USART6_RX) / DOUT_4G | B |
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| R112 | 100k | R_0603 | C103211 | ETH_RST / GND | F |
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| U18 | TMP102 (`Sensor_Temperature:TMP102xxDRL`) | SOT-563 | C99269 | 1 SCL→I2C_SCL, 2 GND, 3 ALERT n/c, 4 **ADD0→3V3 (0x49)**, 5 V+→3V3, 6 SDA→I2C_SDA | D3 («U4b») |
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| C124 | 100nF | C_0603 | C14663 | 3V3 / GND — desacoplo de U18 | D3 |
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| D19 | USBLC6-2SC6 (`Power_Protection:USBLC6-2SC6`) | `Package_TO_SOT_SMD:SOT-23-6` | C7519 | 1,6 I/O1→USB_DM · 3,4 I/O2→USB_DP · 5 VBUS→USB_VBUS · 2 GND | E5 («D_J9») |
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| JP6 | JP_CUT (`Jumper:SolderJumper_2_Open`) | `Jumper:SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm` | — | MAIN5V / SYS5V, en paralelo con P11, **abierto** | F («JP_CUT») |
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Nets nuevas de señal (J8.3 y J8.5 estaban sin conexión; se les quitó la bandera *no-connect*): `XBEE_ONSLP` (J8.3 = XBee pin 13) y `XBEE_ASSOC` (J8.5 = XBee pin 15).
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## 3. Líneas al MCU (U16 STM32F411RET6)
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Se retiraron las banderas *no-connect* de PC1/PC2/PC3/PC4/PC5/PC7 y se colocó la etiqueta en el extremo del pin.
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| Pad | Pin | Net nueva | A través de | Destino |
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| 9 | PC1 | `MODEM_RST_MCU` | R107 1 k | `MODEM_RST` (J7.5, SW4G1) |
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| 10 | PC2 | `MODEM_LED_MCU` | R108 10 k | `MODEM_LED` (J8.8, antes de Rmled1) |
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| 11 | PC3 | `MODEM_EN` | R105 10 k → `MODEM_EN_U7` (R106 100 k a GND) | U7 pin 3 EN |
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| 24 | PC4 | `MODEM_ON_SLEEP` | R109 10 k DNP | `XBEE_ONSLP` (J8.3) |
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| 25 | PC5 | `MODEM_ASSOC` | R110 10 k DNP | `XBEE_ASSOC` (J8.5) |
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| 38 | PC7 (USART6_RX) | `RTCM_TAP` | R111 1 k | `DOUT_4G` (J7.2 → MOD1.17) |
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| 50 | PA15 | `ETH_RST` (existente) | R112 100 k a GND | U11 W5500 pin 37 |
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## 4. Verificación por netlist (kicad-cli, `sch export netlist`)
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Diff pin-a-pin `v55-baseline.xml` → `hbox-watchdog-v56-netlist.xml`: **58 pines cambian, 0 cambios no previstos** (todos los demás ~1 300 nodos idénticos, incluido el resto de U16, MOD1, U6, U12, J7, J9…).
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| Net | Nodos en V5.6 |
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| `MODEM_EN` | U16.11 (PC3), R105.1 |
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| `MODEM_EN_U7` | U7.3 (EN), R105.2, R106.1 |
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| `MODEM_RST_MCU` | U16.9 (PC1), R107.1 |
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| `MODEM_RST` | J7.5, SW4G1.1, **R107.2** |
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| `MODEM_LED_MCU` | U16.10 (PC2), R108.1 |
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| `MODEM_LED` | J8.8, Rmled1.1, **R108.2** |
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| `MODEM_ON_SLEEP` | U16.24 (PC4), R109.1 |
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| `XBEE_ONSLP` | J8.3, R109.2 |
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| `MODEM_ASSOC` | U16.25 (PC5), R110.1 |
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| `XBEE_ASSOC` | J8.5, R110.2 |
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| `RTCM_TAP` | U16.38 (PC7), R111.1 |
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| `DOUT_4G` | J7.2, MOD1.17, **R111.2** |
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| `ETH_RST` | U11.37, U16.50, **R112.1** |
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| `SYS5V` | C101.1, D12.2, D6.1, F1.1, K1.2, P11.2, PF10.1, R2.2, U12.2, U12.7, **U7.2 (VIN)**, **C119.1, C120.1, C121.1**, **JP6.2** |
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| `SW_5V` | C3.1, C40.1, MOD1.5, PF5.1, Q1.3 — **U7 ya no está** |
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| `3V3_MODEM` | C41.1, C43.1, J7.1, J8.7, L7.2, R60.1, **C122.1** |
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| `SW3_NODE` | U7.8 (SW), L7.1, Cbst2.2, Dbk2.1 (DNP) |
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| `BST3` | U7.1 (BST), Cbst2.1 |
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| `FB3` | U7.5 (FB), R60.2, R61.1 |
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| `COMP3` | U7.6 (COMP), Rcomp2.1, **C123.1** |
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| `COMP3_C` | Rcomp2.2, Ccomp2.1 |
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| `FREQ3` | U7.4 (RT/CLK), Rfreq2.1 |
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| `MAIN5V` | … P11.1, **JP6.1** (resto sin cambio) |
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| `USB_DP` | J7.7, J9.A6, J9.B6, **D19.3, D19.4** |
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| `USB_DM` | J7.8, J9.A7, J9.B7, **D19.1, D19.6** |
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| `USB_VBUS` | J7.6, J9.A4/A9/B4/B9, **D19.5** |
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| `I2C_SCL` / `I2C_SDA` | … U4.1/U4.6, **U18.1 / U18.6** |
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| `3V3` | … **U18.4 (ADD0), U18.5, C124.1** |
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Volcado pad→net completo de todos los componentes nuevos y modificados: `kicad/_to_delete/v56-work-20260928/padnet-dump.txt`.
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## 5. ERC (kicad-cli, `hbox-watchdog-v56.kicad_sch`)
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**Resultado: 1 error, 27 warnings.** Línea base V5.5 (misma herramienta, antes de tocar nada): 1 error, 33 warnings.
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Preexistentes en V5.5 (no son de la ECO, se dejan tal cual):
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- **[error] Label not connected @ (50.8, 25.146)** — etiqueta `GND` suelta en la esquina superior izquierda. Existe igual en `hbox-watchdog-v5.kicad_sch`.
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- [warning] Unconnected wire endpoint @ (201.676, 216.408).
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- [warning] «Symbol … doesn't match copy in library» ×17 (SW_Push ×3, L ×4, Crystal ×4, AO4406A, STM32F411RETx, D, SP3485EN, AMS1117-3.3, RJ45_Hanrun…) y «not found in symbol library» ×6 (D_Zener_ANK, Q_PMOS_GDS, Q_NMOS_GSD ×2, Q_PMOS_GSD, PCF8574) — símbolos embebidos distintos de la librería global; sin efecto eléctrico.
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- [warning] Footprint PhoenixContact_MC_1,5_3-G-3.5… not found ×2; footprint library `Connector_RJ45` no configurada ×1.
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Warnings que desaparecieron respecto a la línea base (limpieza colateral, sin efecto en la netlist):
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- 8× «A pin with a "no connection" flag is connected»: J7/J8 tenían banderas *no-connect* encima de pines que sí están conectados por etiqueta (J7.1–.8, J8.1, .6, .7, .8, .10). Se quitaron esas 10 banderas (más las 8 de los pines PC1–PC7/J8.3/J8.5 que ahora se usan). Los pines siguen conectados exactamente igual (diff de netlist = 0 en ellos).
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- Los pines del símbolo `AP64350SP-13` en `Drogheda-v6.kicad_sym` son de tipo *unspecified*; en la copia embebida en `hbox-watchdog-v56.kicad_sch` se les asignó tipo (VIN/GND power_in, EN/FB input, SW power_out, resto passive) para que ERC no avise «Unspecified and Passive connected». La librería `Drogheda-v6.kicad_sym` no se tocó.
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## 6. Lo que no se hizo / decisiones abiertas
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1. **Compensación y frecuencia del AP64350 copiadas de v6 (U20)** — Rcomp2 14 k, Ccomp2 3.3 nF, C123 47 pF, Rfreq2 200 k, Cbst2 100 nF. En v6 esa red se diseñó para 3.8 V con Cout distinto; aquí la salida es 3.33 V con L = 4.7 µH y Cout ≈ 2×22 µF cerámico + 220 µF polímero (baja ESR). **Comprobar contra la tabla de aplicación del datasheet AP64350** (Diodes, «Typical Application» 3.3 V) antes de pedir; son 0603 y se cambian sin re-layout.
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2. **C40 sigue en `SW_5V`.** El ECO dice «C40 pasa a ser Cin»; el brief de ejecución pedía *añadir* 2×22 µF + 10 µF con refs nuevas en SYS5V. Se hizo lo segundo (C119/C120/C121) y C40 se dejó en SW_5V como cerámico del riel del F9P. Si Leo prefiere el texto del ECO: marcar C40 DNP o moverlo a SYS5V en layout (una sola etiqueta).
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3. **F1**: valor «PPTC 4A/1812 low-R», LCSC = `TBD`. Elegir la pieza (o 0 Ω) antes de la BOM.
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4. **L7 LCSC C17700167** = Sunlord MWSA0804S-4R7MT (8.8×8.2 mm, Extended). La pieza actual (C17700171) es de la misma familia sobre el footprint `L_Bourns-SRU8028_8.0x8.0mm`; confirmar que el 4R7 tiene la misma huella (o cambiar por SRU8028-4R7Y).
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5. **U12 (buck 3V3_ETH)** no se cambió (opcional J4 del ECO).
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6. **RNTB / JP2** sin cambio (decisión de química D1 pendiente).
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7. **Serigrafía** (SW4G1 = RESET MÓDEM, SW1 = RESET MCU, JP2 = F2) y toda la sección **E de EMC** son de PCB: no se tocaron.
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8. **Error ERC preexistente** (etiqueta GND suelta en 50.8, 25.146) se dejó tal cual por estar fuera de la ECO; borrar esa etiqueta en KiCad cuesta un clic si se quiere ERC = 0 errores.
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9. **Formato del archivo**: las herramientas KiCad-MCP reescriben `hbox-watchdog-v56.kicad_sch` en formato compacto (una línea por elemento, 657 kB frente a 813 kB). Es válido para KiCad 10 (kicad-cli lo lee para ERC/netlist/PDF) y al guardar desde eeschema vuelve al formato canónico; solo afecta a la legibilidad del diff en git. Las 238 instancias `(project …)` se renombraron de `hbox-watchdog-v5` a `hbox-watchdog-v56` (lo que haría *Save As*).
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10. Incidente detectado y corregido durante el trabajo: la herramienta MCP `replace_schematic_component` eliminó la unión (junction) en (39.37, 76.2) — Rig2.1 quedaba sin `IGN_SENSE`. Se detectó con el diff de netlist, se restauró la junction con su UUID original y el diff final es limpio. La misma herramienta añadió 5 junctions en cruces de cables ya conectados (722.63,130.81 · 722.63,69.85 · 699.77,240.03 · 446.786,301.498 · 509.524,287.02); se verificó que no alteran ninguna net.
|
||||||
|
|
||||||
|
## 7. Integridad de V5.5 (sha256 antes = después)
|
||||||
|
|
||||||
|
```
|
||||||
|
8e4d3a7ba7a209367c2dda2394ca7809b5b68078a388f74b8052ddda2aab518c hbox-watchdog-v5.kicad_dru
|
||||||
|
6f7ca0e414cc2af321c4909ac3491ee71300f6fa61507e179a46e945eb5c39b0 hbox-watchdog-v5.kicad_pcb
|
||||||
|
8f0158affbf93516649a1317572a687f330ad7f009cd4f4d8345324d8506c04c hbox-watchdog-v5.kicad_prl
|
||||||
|
8253ad14bea362c534bdb0895477899863bd3c843173751b0af3d253448a8fe3 hbox-watchdog-v5.kicad_pro
|
||||||
|
8926a7c0ec4785f9accaf6d005ae7a57b43099dd5d772b945782fdc3751c843f hbox-watchdog-v5.kicad_sch
|
||||||
|
```
|
||||||
|
`hbox-watchdog-v56.kicad_sch` final: `08219316517f636564fd0ae0804a30213d10fbc048b6446dd61216b312f81d2e`.
|
||||||
|
|
||||||
|
Respaldos de cada estado intermedio (nada se borró): `kicad/_to_delete/v56-work-20260928/` — `00-copied-from-v5`, `01-nc-removed-renamed`, `02-u7-replaced`, `03-values`, `04-new-parts`, `05-metadata`, `06-junction-nc-pintypes`, `07-final` (`.kicad_sch`), netlists `v55-baseline.xml`, `v6-reference.xml`, `step02/04/06.xml`, `hbox-watchdog-v56-netlist.xml`, y `padnet-dump.txt`. No se ejecutó `git` en la carpeta.
|
||||||
|
|
||||||
|
## 8. Siguientes pasos para Leo / Michelle
|
||||||
|
|
||||||
|
1. **Abrir `hbox-watchdog-v56.kicad_pro` en KiCad 10**, revisar el bloque U7 (x≈433–475, y≈185–210) y el bloque «V5.6 ECO» (x 70–210, y 362–530); mover los componentes nuevos junto a sus bloques si se quiere (todo es por etiquetas). Guardar → KiCad reescribe el archivo en formato canónico.
|
||||||
|
2. Opcional: borrar la etiqueta `GND` suelta en (50.8, 25.146) para ERC = 0 errores.
|
||||||
|
3. Revisar punto 6.1 (compensación AP64350) y 6.2 (C40); fijar F1 (6.3).
|
||||||
|
4. **Update PCB from Schematic** (F8) sobre `hbox-watchdog-v56.kicad_pcb`: sustituye U7 (mismo UUID, footprint `Drogheda-v6:SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP`, pinout distinto → hay que re-rutear el bloque) y añade 17 footprints nuevos (C119–C124, R105–R112, U18 SOT-563, D19 SOT-23-6, JP6). Dbk2, R109, R110 quedan DNP.
|
||||||
|
5. Layout (sección E del ECO + notas de A/D):
|
||||||
|
- U7: lazo Cin (C119/C120/C121) < 3 mm de VIN; BST (Cbst2) pegado a pines 1/8; C123/Rcomp2/Ccomp2 y Rfreq2 junto a pines 4/6 con retorno a GND corto; EP con vías térmicas.
|
||||||
|
- `SW_BAT` polígono ≥ 2 mm; `BAT_PLUS` ≥ 1.5 mm + vías; EP de U6 ≥ 9 vías térmicas.
|
||||||
|
- Divisor FB del ventilador (R20/R21) junto al pin 4 de U2; ESD DFU (D14/D15/D16) junto a J11; **D19 en J9**, en la salida de las líneas D+/D− del conector.
|
||||||
|
- Cristales ≤ 5 mm de sus ICs; costura de vías bajo MOD1.
|
||||||
|
- **U18** entre J7/J8 y el módem (fuente de calor); C124 al lado.
|
||||||
|
- JP6 junto a P11; R112 junto a U11 (pin 37); R107/R108 cerca de J7/J8; R111 cerca de J7.2.
|
||||||
|
- Serigrafía: `SW4G1 = RESET MÓDEM`, `SW1 = RESET MCU`, `JP2 = F2 (Li-ion / LFP)`, `JP6 = CUTOFF BYPASS (abierto)`.
|
||||||
|
6. DRC = 0 → auditoría pad-a-pad contra `board_v56.h` (PC1/PC2/PC3/PC4/PC5/PC7 según §3) → BOM/CPL → JLC.
|
||||||
|
|
||||||
|
## 9. Addendum 28-sep (tarde) — decisiones cerradas y fusión en `hbox-watchdog-v5.*`
|
||||||
|
|
||||||
|
Por decisión de Leo ya **no existe una copia `hbox-watchdog-v56.*`**: el esquemático de la ECO se fusionó en `hbox-watchdog-v5.kicad_sch` (255 instancias `(project …)` renombradas de vuelta a `hbox-watchdog-v5`; `.kicad_pcb/.kicad_pro` eran copias idénticas). El estado as-fabbed V5.5 queda en git (`git tag v5.5-as-fabbed` antes del commit) y una copia en `kicad/_to_delete/v56-work-20260928/hbox-watchdog-v5_as-fabbed-before-v56-merge.kicad_sch`. Los archivos `-v56` se movieron a la misma carpeta `_to_delete/`.
|
||||||
|
|
||||||
|
Decisiones §6 cerradas y aplicadas en el esquemático (script por referencia, respaldos `08-merged-into-v5` y `09-before-chemistry`):
|
||||||
|
|
||||||
|
| Ref | Antes | Ahora | LCSC | Razón |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| Rcomp2 | 14k (fila 5 V del datasheet, copiada de v6) | **9.1k** | C23260 (básica) | Fila 3.3 V del AP64350 (9.31k); fc ≈ 2.4 kHz con Cout ≈ 250 µF (2×22 µF + 220 µF polímero) |
|
||||||
|
| Ccomp2 | 3.3nF | **10nF** | C57112 (básica) | Con Cout 250 µF el cero a 5.3 kHz quedaba por encima del cruce → MF 25–40°; a 1.75 kHz → MF 55–70° |
|
||||||
|
| C123 | 47pF | **68pF** | C1680 | Fila 3.3 V; polo ≈ 260 kHz contra el rizado de 500 kHz |
|
||||||
|
| F1 | PPTC 3 A (C20627123) / «TBD» | **BSMD1812-400-12V** 4 A hold / 8 A trip, 25 mΩ máx | C18164540 | ≤ 60 mV a 2.5 A; hold ≈ 3 A a 45 °C; mismo 1812 |
|
||||||
|
| C40 | 22 µF en SW_5V | sin cambio | — | U7 ya tiene C119–C121 como Cin; C40 sigue desacoplando el F9P |
|
||||||
|
| L7 | — | C17700167 confirmado | — | Misma familia MWSA0804S, mismo encapsulado 8.8×8.2 → misma huella |
|
||||||
|
| **R55 (= RNTB)** | 10k/1% (C25804) | **5.6k/1%** | C23189 (básica) | Química **LFP-HT 26650**: ventana de carga +10…+60 °C con NTC B3380 en el paquete (P4.3) |
|
||||||
|
| **JP2** | `SolderJumper_3_Bridged12` «F2:Li-ion» | **`SolderJumper_3_Bridged23`** «F2:LFP (2-3)», huella `…_Bridged23_…` | — | F2 = bajo → flotación LiFePO4 del LTC4040. Símbolo Bridged23 añadido a `lib_symbols` (derivado del Bridged12: puente entre pads 2-3) |
|
||||||
|
|
||||||
|
Pendiente de Leo: tamaño del lote; el paquete 26650 LFP-HT con NTC **B3380** (caja/BOM mecánica). Validación de banco en la primera tarjeta: escalón de carga 0→2 A en 3V3_MODEM (< 150 mV, sin oscilación); carga LFP a 45 °C en horno sin pausa NTC.
|
||||||
|
|
||||||
|
## 10. Addendum 28-sep (noche) — hallazgos de la auditoría v6 aplicados a V5.6 + chequeo de stock JLC
|
||||||
|
|
||||||
|
Fuente: `2026-09-28_EinarBoard-v6_Full-Audit` (E-02, H-01, A-03, H-02, H-02b, A-08, A-09) y un chequeo de stock de las 94 LCSC de la BOM V5.6 para 30 tarjetas (2 problemas, 92 OK). Respaldo previo: `_to_delete/v56-work-20260928/10-before-v6audit-fixes.kicad_sch`.
|
||||||
|
|
||||||
|
| Ref | Antes | Ahora | LCSC | Razón |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| **R112** (ETH_RST → GND) | 100k | **4.7k** | C23162 (básica) | E-02: el W5500 tiene pull-up interno de 62–112 k en RSTn y PA15 arranca como JTDI con pull-up de 30–50 k → con 100 k el nodo queda en 2.75 V (ALTO). Con 4.7 k: 0.62 V peor caso (BAJO). 0.7 mA cuando el firmware lo pone en alto. |
|
||||||
|
| **U15** MAX3232ESE | huella `SOIC-16W_7.5x10.3mm` (campo obsoleto; la PCB V5.5 ya usa la angosta) | **`Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`** | C15846 | H-01: el ESE es SO-16 angosto. Corregido en el esquemático para que *Update PCB* no cambie la huella buena de la PCB. (U13 PCF8574T sí es ancho: correcto.) |
|
||||||
|
| **R50** | 1.5k | **1.43k/1%** | C22840 | A-03: I_chg = 2000/R ±5 % → 1.316–1.483 A (con 1.5 k el mínimo es 1.254 A < 1.3 A). Mismo valor en v6 (comunalidad). |
|
||||||
|
| **U10** | C729142 (SC16IS762, **15 en stock**) | mismo valor SC16IS752IPW | **C57156** (2 670) | H-02: por debajo del mínimo de 20 de JLC. Pin-compatible, modo I²C idéntico, mitad de precio. |
|
||||||
|
| **R53** 499k | C131054 (**6 en stock**) | mismo valor | **C177479** (26 862) | H-02: fija el voltaje del boost de respaldo; sin ella no hay respaldo. |
|
||||||
|
| 100k ×9 (Rgs1, R87, R20, R56, Ren1, Rfreq1, R85…) y 100k/1% ×3 (R60, R52, R54) | C103211 (5 %, 702 en stock) / C14675 | mismos valores | **C25803** (1 %, básica, 10.8 M) | H-02b: 2.3× de cobertura para 30 tarjetas y una bobina Extended menos. |
|
||||||
|
| **U17** | AMS1117-3.3 (C6186) | **TLV1117LV33DCYR** (mismo SOT-223, pin 1 GND / 2 OUT / 3 IN) | C15578 | A-08: en batería LDO_IN = VSYS 4.60–4.99 V − D12 ≈ 4.25–4.65 V y el AMS1117 necesita ≈ 4.3 V (dropout 1.0–1.3 V) → 3V3 marginal justo en respaldo; Iq 5–11 mA vs 0.1 mA. Vin máx 5.5 V ≥ SD-15B 5.57 − D12. Comprobar ≥ 10 µF cerámico en 3V3 (C23 22 µF). |
|
||||||
|
| **C78** (VEH5V bulk) | 220uF/10V electrolítico 85 °C (C2827940) | **220 µF/16 V polímero** | C881921 | A-09: 2 000 h @ 85 °C ≈ 1 año en gabinete de puerto; mismo can 6.3×7.7. |
|
||||||
|
|
||||||
|
No aplicados a V5.6 (decisión de Leo, o v6.1): A-11 (R56 a 3V3 → cargador OFF por defecto sin MCU; es un cambio de red), D-09 (100 k en la base de Q5), crystales Y1/Y3 HC-49 (E-03/D-02, V5.5 funciona en campo), A-13 (PFO al MCU: no hay pin libre en V5).
|
||||||
|
|
||||||
|
Añadido (Ethernet, E-04, respaldo `11-before-eth-caps`): **C90** (TOCAP, U11.20) 10 µF → **4.7 µF** (C1779) y **C91** (1V2O, U11.22) 4.7 µF → **10 nF** (C1710, básica), ambos 0805 sin cambio de huella — valores que exige el datasheet W5500 v1.0.2 («must be connected to a 4.7uF / 10nF capacitor»). Y1/C95/C96 (E-03) se dejan: el diseño de referencia de WIZnet usa las mismas cargas de 18 pF; sólo verificar con frecuencímetro si el enlace falla.
|
||||||
@ -0,0 +1,101 @@
|
|||||||
|
# Agent brief — Full audit of EinarBoard v6 (with V5.5/V5.6 lessons learned)
|
||||||
|
|
||||||
|
**Owner:** Leo (Helgen Technologies) · **Date:** 2026-09-28 · **For:** a fresh Claude session/agent with the Drogheda folder mounted (`$HOME/mnt/Projects/Drogheda`) and the KiCad MCP tools available on Leo's Mac.
|
||||||
|
**Language:** write the report in English with a Spanish executive summary (same convention as `2026-09-28_Drogheda_EinarBoard-v6_Review-vs-V5.5-Lessons_v1.0.md`).
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 1. Goal
|
||||||
|
|
||||||
|
Audit the EinarBoard **v6** design (`03-Architecture-Hardware/kicad/hbox-watchdog-v6.kicad_sch` + `.kicad_pcb`, current state on disk) **completely**, not only against the nine V5.5 lessons: power tree, modem, GNSS, MCU pin map vs. firmware, Ethernet, thermal/EMC, connectors, BOM/JLC, identity/telemetry, DRC/ERC. Output a single ranked report with evidence and concrete fixes so Leo can decide what to change **before ordering v6**. Read-only by default; apply fixes only on a copy and only if Leo asks (§7).
|
||||||
|
|
||||||
|
## 2. Inputs (read all before starting)
|
||||||
|
|
||||||
|
Design files (do not modify in place):
|
||||||
|
- `03-Architecture-Hardware/kicad/hbox-watchdog-v6.{kicad_sch,kicad_pcb,kicad_pro}` — the target. `hbox-watchdog-v6 respaldo.*` is an older backup, ignore unless comparing.
|
||||||
|
- `03-Architecture-Hardware/kicad/hbox-watchdog-v5.*` — V5.5 **as fabbed** (frozen; never touch). `hbox-watchdog-v56.*` — V5.6 ECO copy (reference for what was fixed on V5).
|
||||||
|
- Libraries: `Drogheda-v6.kicad_sym`, `Drogheda.pretty` in the kicad folder.
|
||||||
|
|
||||||
|
Lessons and prior reviews (the audit must cite these):
|
||||||
|
- `03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Review-vs-V5.5-Lessons_v1.0.md` — lesson-by-lesson review F1–F9 (✅ F1 F2 F3 · ⚠ F4 F6 F8 F9 · ❌ F5 F7). Start from its §4 risk checklist; **re-verify every item against the current files** (it was written on the 25-Sep state).
|
||||||
|
- `03-Architecture-Hardware/2026-09-27_Drogheda_EinarBoard-V5.6_ECO_ES_v1.0.md` — the V5.6 ECO: sections A (modem power), B (MCU lines), C (charger RS1/R50), D (temperature), E (EMC list), F (misc), H (firmware 0.7.0 needs), I (validation).
|
||||||
|
- `03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-V5.6_Schematic-Change-Report_v1.0.md` — how V5.6 was implemented, open items §6.
|
||||||
|
- `03-Architecture-Hardware/2026-08-24_Drogheda_EinarBoard-v6_GNSS-4G-Integration_Design-Brief_v1.0.md`, `..._Phase-2_Schematic-Delta_v1.0.md`, `2026-09-02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html`, `2026-08-27_Drogheda_v6-Antenna-Chain_Diagram.html`.
|
||||||
|
- Project docs (claude.ai project "Drogheda"): `2026-09-25_HBox-v6_Pre-Fab-Audit_EN.md`, `2026-09-26_HBOX-V4-V5_Pinmap-Audit-FW-0.5.4.md`, `2026-09-27_HBOX-V5.5-V4_Modem-on-battery_Diagnosis-and-0.5.8-Field-Strategy.md`, `2026-09-28_Drogheda_Status-and-Next-Steps.md`.
|
||||||
|
- Obsidian vault `Second Brain/03 Projects/Helgen/Project-Drogheda/`: "EinarBoard — Lecciones aprendidas V5.5 (sep 2026)", "EinarBoard v6 — Revisión contra lecciones V5.5", "Drogheda — Decision Log", "Drogheda — Risk Register".
|
||||||
|
- Test evidence: `06-Testing-Validation/2026-09-28_H0008_charging-overnight-log.md` (charger works; average charge current ≈ 1.3 A vs 2.4 A programmed; 8.5 h to full; rail 5.25 V; MODEM watch threshold flapping).
|
||||||
|
- Firmware: `04-Source-Code/firmware/hbox_v5_bringup/hbox_v5_bringup.ino` (0.6.0) and `CHANGELOG.md` — the pin map and every GPIO/ADC/UART/SPI/I²C the firmware expects. v6 will need a new pin map; the audit must produce it.
|
||||||
|
- Memory files in this project (read: `drogheda-einarboard-v6-brief`, `drogheda-v6-zed-f9p-integration`, `drogheda-v6-lte-island`, `drogheda-v6-resync-protocol`, `drogheda-einarboard-v5-audit`, `drogheda-battery-hightemp`, `drogheda-backup-lowpower`, `drogheda-einarboard-harness`, `drogheda-einarboard-modem-rail`, `drogheda-einarboard-short-incident`, `drogheda-mff2-footprint`, `drogheda-power-cost`, `preferences`).
|
||||||
|
|
||||||
|
## 3. Ground rules (Leo's standing rules — non-negotiable)
|
||||||
|
|
||||||
|
1. **Never edit the v6 files in place.** Work read-only; if a fix phase is requested, copy to `hbox-watchdog-v6-audit.*`, keep backups of every intermediate state under `kicad/_to_delete/v6-audit-<date>/`, preserve UUIDs, and prove every change with a **netlist diff** (`kicad-cli sch export netlist`) before and after.
|
||||||
|
2. **Never run bare numeric regex over KiCad files** (values like `0.3`, `825` appear everywhere). Parse S-expressions (python `sexpdata`/kiutils or the KiCad MCP tools) and match by ref/UUID/net.
|
||||||
|
3. **No git from the mounted folder** — give Leo the commands. The mount cannot delete (use `_to_delete/`).
|
||||||
|
4. Hardware bodges on existing boards are rejected — every fix is a design change for the next fab.
|
||||||
|
5. Look things up yourself (netlist, datasheets, JLC parts DB via the KiCad MCP `search_jlcpcb_parts`/`get_jlcpcb_part`) — do not ask Leo for values you can derive from the files.
|
||||||
|
6. Verify with tools, not by reading: `kicad-cli sch erc`, `kicad-cli pcb drc`, netlist export, pad→net dump, track width/length per net, courtyard overlaps (`check_courtyard_overlaps`), clearance (`check_clearance`).
|
||||||
|
|
||||||
|
## 4. Audit scope — do every block, in this order
|
||||||
|
|
||||||
|
**A. Power tree (24 V → 5 V → rails), incl. lessons F5/F7/F4**
|
||||||
|
- U25 TPS54360B: output set-point (R121/R122) vs. the 0.6.0 charge governor (CHG_RAIL_ON 5.05 / CHG_RAIL_OFF 4.90 V) and LTC4040 PFI (4.44 V on V5). Required: ≥ 5.30 V nominal (R121 57.6k proposal) — confirm with the datasheet formula, check FB divider tolerance, output ripple, Cout, and that the 5 V rail can source F9P + modem peak + 2 A charge with margin. Input protection on 24 V (TVS, reverse, inrush) and the 24V/5V inner-layer clearance lesson from the 23-Jul short incident (`drogheda-einarboard-short-incident`): report every 24 V-to-other-net clearance < 0.5 mm on inner layers.
|
||||||
|
- LTC4040 U6 block: RS1 (input limit 25 mV/RS vs. what U25 can supply), R50 (825 Ω = 2.42 A → 1.5 k = 1.33 A per ECO C; justify with the H0008 finding), PROG/NTC/RNTB/JP2 chemistry (Li-ion vs LFP-HT — `drogheda-battery-hightemp`), BSTFB divider (backup V), PFI divider, safety timer, CHRG/FAULT pull-ups to the MCU. **Thermal:** SW_BAT/BAT_PLUS track widths (target ≥ 2 mm / 1.5 mm), U6 EP thermal vias (≥ 9), L6 distance, copper area, a temperature sensor within 10 mm of U6 (TMP102 or NTC) so the firmware can see charger die heating.
|
||||||
|
- Every buck/LDO on the board: input/output caps location (< 3 mm), BST cap, compensation network vs datasheet application table for the actual Vout/L/Cout, EN pull-downs (default OFF where the firmware expects OFF), UVLO vs the minimum battery voltage in backup (3.5 V boost floor).
|
||||||
|
- Backup path: what runs on battery, what the boost can deliver (VSYS backup 4.79 V on V5) and whether F9P + modem + W5500 cold-start on battery is within the LTC4040 boost limit — this is the root cause of the V5.5 "modem dark on battery" failure (`2026-09-27_..._Modem-on-battery_Diagnosis`). Produce a worst-case current budget table (per rail, cold start and steady state).
|
||||||
|
|
||||||
|
**B. Modem (A7670SA) — lessons F1/F2/F3, ECO A/B**
|
||||||
|
- U20 AP64350 3.80 V: source (D21/MAIN5V vs D20/24 V), EN = MODEM_PWR_EN (PC10) with 100k pull-down (R113), compensation/frequency network vs datasheet for 3.8 V, Cout, bulk ≥ 220 µF polymer within 10–20 mm of VBAT_MODEM pins, track width ≥ 0.25 mm (2 A bursts), ground return.
|
||||||
|
- Control lines: PWRKEY (PC8), STATUS (PC9), RST (PC11), level shifting to 1.8 V logic where the module requires it, series resistors, pull-ups/downs at power-up (module must not be back-powered through UART/GPIO while its rail is off).
|
||||||
|
- UART USART6 PC6/PC7 with the R106 100 Ω RTCM tap: confirm direction, no contention with the ArduSimple/F9P path, and that the firmware can read RTCM age (`$GxGGA` field 13) or raw RTCM.
|
||||||
|
- SIM/eSIM (U22 MFF2 footprint — `drogheda-mff2-footprint`), SIM ESD, antenna path (matching, DC block, ESD), LTE island copper rules (`drogheda-v6-lte-island`).
|
||||||
|
- Cold-start on battery test case: state explicitly whether v6 can bring the modem up from the LTC4040 boost alone; if not, which sequencing the firmware must enforce (this is requirement R1 of the ECO: "10 minutes off, come back to life, report, while on battery").
|
||||||
|
|
||||||
|
**C. GNSS (ZED-F9P) — `drogheda-v6-zed-f9p-integration`**
|
||||||
|
- VCC ramp window (20–8000 µs/V), RTK_STAT, TIMEPULSE, SAFEBOOT/RESET_N handling, backup battery/V_BCKP, antenna chain (LNA bias, DC block, ESD, 50 Ω trace geometry on the stack-up), UART/I²C/SPI to MCU, u-center passthrough via J11 (P17 removed).
|
||||||
|
- Confirm no `$GPTXT H00xx` source exists on v6 → identity must be `$PHID` from the MCU (lesson F9); check the MCU has a UID-based ID path and the monitor/firmware plan (`2026-09-25_HBox-v6_Pre-Fab-Audit_EN.md`).
|
||||||
|
|
||||||
|
**D. MCU pin map vs firmware 0.6.0 (STM32F411RET6)**
|
||||||
|
- Build the full table: every net on U16 (or whatever the MCU ref is on v6) → function → firmware macro in `hbox_v5_bringup.ino` (PIN_*). Flag: pins used by firmware that are unconnected on v6; v6 nets with no firmware counterpart; ADC pins on non-ADC-capable pads; UART/SPI/I²C alternate-function conflicts; PWM (fan) timer availability; 5 V-tolerant requirement on any 5 V signal; BOOT0/BOOT1/DFU trap (`drogheda-einarboard-30-mcu-integration`); NRST routing (SW1, P10, C104); SWD header; the CHRG_STAT/FAULT/PFO inputs; IGN_SENSE divider (Rig 22k) and its junction (the V5.6 tool bug removed a junction there — check v6 too).
|
||||||
|
- Deliverable: `pinmap-v6.md` table ready to become `#ifdef HBOX_BOARD_V6` in firmware.
|
||||||
|
|
||||||
|
**E. Ethernet W5500 — lesson F8**
|
||||||
|
- SPI2 wiring, CS/INT/RST, RST pull-down (100k), 3V3_ETH source and whether it should be switchable (always-on on V5 wastes battery), magnetics/HR911105A, ESD on J9 (USBLC6-2SC6 or equivalent), no PoE (state it), 25 MHz crystal placement ≤ 5 mm.
|
||||||
|
|
||||||
|
**F. Thermal and EMC (ECO section E, copper plan) — lesson F5/F6**
|
||||||
|
- Fan driver/FB divider location, fan tach, temperature sensors: count and placement (near modem, near U6, board ambient, P12 NTC for the battery pack), and whether the firmware's thermal inhibit (CHG_CELL_HOT 45 °C) has a real cell temperature source.
|
||||||
|
- Crystals ≤ 5 mm; via stitching under the modem; DFU ESD (D14/D15/D16) at J11; return paths across splits; 24 V in inner layers; courtyard overlaps; DRC clean.
|
||||||
|
|
||||||
|
**G. Connectors and harness — `drogheda-einarboard-harness`, `drogheda-einarboard-j1-mirror`**
|
||||||
|
- P1/P2 power entry, ignition GND return, JP_CUT across the P11 equivalent, pin-1 marking and mirrored-socket check on every header (the J1 mirror errata), silkscreen names (RESET MÓDEM / RESET MCU / F2), mounting holes and case fit.
|
||||||
|
|
||||||
|
**H. BOM / JLC manufacturability**
|
||||||
|
- Every part with an `LCSC` property: exists, in stock, Basic vs Extended, footprint matches the JLC part (e.g. the L7 SRU8028 vs MWSA0804S question), polarity marks, DNP list explicit, no `TBD`. Export BOM + CPL with `kicad-cli` and check with `get_jlcpcb_part`. Estimate the unit BOM cost delta vs V5.6.
|
||||||
|
|
||||||
|
**I. Requirements traceability (from the ECO §0 R1–R5)**
|
||||||
|
- R1 10-min off/on on battery with report; R2 modem never left dark (MCU can power-cycle it); R3 report while on battery; R4 temperature management (sensors + fan + charger inhibit); R5 charge at ≥ 1.3 A without thermal cycling. For each: satisfied by v6 as-is / needs change X / needs firmware only.
|
||||||
|
|
||||||
|
**J. ERC/DRC** — run both with `kicad-cli`; list every error and warning, classify pre-existing vs real.
|
||||||
|
|
||||||
|
## 5. Method and evidence standard
|
||||||
|
|
||||||
|
- Every finding: **ID, severity (Blocker / Major / Minor / Note), block, evidence (ref, net, coordinates, measured width/length/distance, datasheet page), consequence, concrete fix (part value + LCSC, or layout instruction with numbers), effort (schematic-only / layout / both)**.
|
||||||
|
- "Pass" items need evidence too (one line each) — the report must show what was checked, not only what failed.
|
||||||
|
- Compute, don't eyeball: track widths via pcb parsing, distances from footprint positions, divider outputs from resistor values, current budgets from datasheets.
|
||||||
|
- If a fact is not derivable from the files (e.g. enclosure dimensions), list it under "Inputs needed from Leo" at the end — do not stop the audit for it.
|
||||||
|
|
||||||
|
## 6. Deliverables
|
||||||
|
|
||||||
|
1. `03-Architecture-Hardware/2026-MM-DD_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md` — sections in the order of §4, then §4-I traceability table, §4-D pin map, a **ranked change list** (Blockers first) and a "ready to order? YES/NO + conditions" verdict.
|
||||||
|
2. `03-Architecture-Hardware/pinmap-v6.md` (or inside the report) — the MCU pin table.
|
||||||
|
3. Same report as a project doc `claude/…_EinarBoard-v6_Full-Audit.md` (claude.ai project "Drogheda") and a vault note `EinarBoard v6 — Auditoría completa (fecha).md` in `Second Brain/03 Projects/Helgen/Project-Drogheda/`, linked from `Project Drogheda MOC.md`; append decisions to `Drogheda — Decision Log.md` and new risks to `Drogheda — Risk Register.md`.
|
||||||
|
4. Update `2026-09-28_Drogheda_Status-and-Next-Steps.md` (project) with a v6 line.
|
||||||
|
5. Git commands for Leo (two-step: kicad submodule first, then the parent gitlink — `drogheda-kicad-submodule`).
|
||||||
|
|
||||||
|
## 7. Optional phase 2 (only if Leo says "apply")
|
||||||
|
|
||||||
|
Apply the Blocker/Major schematic fixes on a copy `hbox-watchdog-v6-audit.*` following the V5.6 method (`2026-09-28_..._Schematic-Change-Report`): copy → backups per step → KiCad MCP edits by ref/UUID → ERC → netlist diff = only the intended pins → PDF export → change report. Layout changes are listed for Michelle, not executed, unless explicitly requested.
|
||||||
|
|
||||||
|
## 8. Acceptance
|
||||||
|
|
||||||
|
The audit is done when: every §4 block has a pass/fail table with evidence; ERC/DRC outputs are attached; the R1–R5 traceability table is complete; the pin map covers 100 % of MCU pins; every proposed part has an LCSC number; the verdict states what blocks the order and what can follow in v6.1.
|
||||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,218 @@
|
|||||||
|
# EinarBoard v6 — Review against the V5.5 lessons of 26–27 Sep 2026 (v1.0)
|
||||||
|
|
||||||
|
**Date:** 2026-09-28 · **Design reviewed:** `kicad/hbox-watchdog-v6.kicad_sch` / `.kicad_pcb` (state of 25-Sep, after T15) · **Reference documents:** `2026-09-27_Drogheda_EinarBoard-V5.6_ECO_ES_v1.0.md`, `2026-09-28_Drogheda_EinarBoard-V5.6_Schematic-Change-Report_v1.0.md`, project doc `2026-09-25_HBox-v6_Pre-Fab-Audit_EN.md`, firmware `CHANGELOG.md` 0.5.8 → 0.6.0 · **Author:** Claude for Leo · **Scope:** read-only review; no KiCad file was modified.
|
||||||
|
|
||||||
|
## Resumen ejecutivo (ES)
|
||||||
|
|
||||||
|
1. La v6 ya resuelve por arquitectura el hallazgo más grave de la semana (F1): el módem A7670SA tiene su propio buck AP64350 (U20) con `MODEM_PWR_EN` en PC10, `PWRKEY` en PC8, `STATUS` en PC9 y `RST` en PC11, y su UART llega al MCU por USART6 (PC6/PC7). El módem se puede arrancar solo, sobre riel asentado, y se sabe si está vivo.
|
||||||
|
2. Con eso, el ciclo de 10 min en batería (F2) y la recuperación de enlace sin matar el módem (F3) son posibles en v6: falta solo el firmware (`ENABLE_DUTY 1` con la secuencia `PWR_CTRL` → 4 s → `MODEM_PWR_EN`).
|
||||||
|
3. Cargador (F4): `RS1` ya es 10 mΩ (C105362, límite 2.5 A) ✅, pero **`R50` sigue en 825 Ω (2.4 A)** ❌ → 1.5 kΩ (C22843).
|
||||||
|
4. Térmico del LTC4040 (F5): **`/SW_BAT` es una pista de 0.25 mm** (peor que los 0.3 mm de la V5.5), `/BAT_PLUS` 0.25–0.5 mm, el EP de U6 **no tiene vías térmicas**, L6 está a 15 mm de U6 y no hay ningún sensor de temperatura junto a U6/L6 (el TMP102 se eliminó; el SHT40 U3 está a 71 mm). ❌ — es el cambio nº 1.
|
||||||
|
5. Ventana NTC (F6): `R55` (RNTB) 10 k y `JP2` puenteado a Li-ion, igual que la V5.5; la pausa a ~40–42 °C se repite en v6 hasta decidir la química (LFP-HT + JP2 2-3 + 5.6 k). `CHRG_FAULT` sí llega al MCU (PB4) para mostrar «pausa NTC».
|
||||||
|
6. Fuente de 5 V (F7): **U25 TPS54360B está fijada a 5.00 V** (R121 53.6 k / R122 10.2 k) → solo 0.56 V sobre el PFI (4.44 V) y **0.10 V sobre la línea de corte del gobernador (4.90 V)**: el cargador se cortaría en cada ráfaga LTE. ❌ → R121 57.6 k (5.32 V).
|
||||||
|
7. Robustez (F8): ESD del DFU ya está junto a J11 (3–7 mm) ✅ y `ETH_INT` va a PC0 (sin trampa BOOT1) ✅; pero **J9 (USB del módem) no tiene ESD**, **`ETH_RST` (PA15) no tiene pull-down** y no hay puente en paralelo a P5 (corte). F1 PPTC 3 A queda solo en el riel del F9P (inocuo, sobredimensionado). Sin PoE en J10 por diseño.
|
||||||
|
8. Software (F9): la v6 pierde el `$GPTXT H00xx` del NTRIP Master de ArduSimple (el módem ahora es nuestro) → la identidad debe generarla el MCU (`$PHID` por UID, ya existe en 0.6.0-eth) también por 4G.
|
||||||
|
9. Veredicto: **3 ✅ (F1, F2, F3) · 4 ⚠ (F4, F6, F8, F9) · 2 ❌ (F5, F7)**. Todos los ❌ y ⚠ son cambios de valor de BOM o de layout; ninguno cambia la arquitectura.
|
||||||
|
10. Los cinco cambios por riesgo: (1) cobre + vías + sensor en U6/L6; (2) U25 a 5.3 V; (3) R50 1.5 k; (4) condensadores de VBAT_MODEM pegados a U19 y pistas del módem ≥ 0.8 mm; (5) pull-down en `ETH_RST` + USBLC6 en J9 + decidir RNTB/JP2.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 0. Method
|
||||||
|
|
||||||
|
- Board: pad→net dump of every footprint (`padnets2.py`), track widths/lengths per net, via positions, footprint positions and pad-to-pad distances computed from `hbox-watchdog-v6.kicad_pcb`.
|
||||||
|
- Schematic: symbol values, `LCSC` and `Note` properties and block texts from `hbox-watchdog-v6.kicad_sch`.
|
||||||
|
- STM32F411RET6 LQFP-64 pad → pin mapping used throughout (pad 15 = PA1, 24 = PC4, 25 = PC5, 37 = PC6, 38 = PC7, 39 = PC8, 40 = PC9, 41 = PA8, 43 = PA10, 50 = PA15, 51 = PC10, 52 = PC11, 55 = PB3, 56 = PB4, 57 = PB5, 8 = PC0, 28 = PB2).
|
||||||
|
- Ground truth for the lessons: the bench findings of 26–27 Sep on V5.5 with firmware 0.5.7–0.6.0 (F1–F9 below).
|
||||||
|
|
||||||
|
Where a fact could not be found in the v6 files, it is stated as such.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 1. Lesson-by-lesson review
|
||||||
|
|
||||||
|
### F1 — Modem never cold-starts on battery (shared Q1 switch, MP1584 UVLO, no MCU visibility)
|
||||||
|
|
||||||
|
**What v6 does today (found in the files):**
|
||||||
|
|
||||||
|
| Item | v6 |
|
||||||
|
|---|---|
|
||||||
|
| Modem power path | `U20` AP64350SP-13 (C2071691), `L20` 4.7 µH/5 A (C17700167), output `/VBAT_MODEM` = 0.8 V × (1 + R110 75 k / R111 20 k) = **3.80 V**. Input `/VIN_MODEM` fed by **`D20` SS34 from `/24V`** (vehicle side, via Q10) **or `D21` PMEG3050EP from `/MAIN5V`** (LTC4040 boost output on battery). The modem no longer hangs from Q1, F1 or `/SW_5V`. |
|
||||||
|
| Modem enable | `U20.3 EN` = `/MODEM_PWR_EN` = **U16 pad 51 = PC10**, with `R113` 100 k to GND (modem OFF while the MCU is in reset/DFU). No series resistor (direct drive; fine for the AP64350 EN pin). |
|
||||||
|
| PWRKEY / RST / STATUS | `/MODEM_PWRKEY` = **PC8** (pad 39) → `Q20` 2N7002 open-drain → `U19.1 PWRKEY`, `R114` 100 k pull-down on the gate. `/MODEM_RST` = **PC11** (pad 52) → `Q21` 2N7002 → `U19.16 RESET`, `R115` 100 k. `U19.66 STATUS` (1.8 V) → `U24` 74LVC2T45 → `/MODEM_STATUS` = **PC9** (pad 40). `U19.52 NETLIGHT` only drives `D4G1` via `R109`/`Q22` — not read by the MCU (STATUS covers the need). |
|
||||||
|
| Modem UART visibility | `U19.9 TXD` → `U24` → `/DOUT_4G` → **`U18.26` (ZED-F9P UART2 RXD, RTCM in)** *and* `R106` 100 Ω → **`/USART6_RX` = PC7 (pad 38)**. `U19.10 RXD` ← `U23` ← `/DIN_4G` ← `K1` relay common: NC = `/USART1_RX` (ZED-F9P `U18.27` TXD2 → also MCU PA10), NO = **`/USART6_TX` = PC6 (pad 37)**. So the MCU always hears the modem's TX (RTCM byte count = "modem registered and NTRIP flowing"), and talks to it on USART6 when K1 is in Mode B. This is the RTCM_TAP of V5.6 built in. |
|
||||||
|
| F9P power | `Q1` AO3401A (gate via `Q5`/`R1` from `/PWR_CTRL` = **PA1**, pad 15) → `/SW_5V` → `U21` AP2112K-3.3 → `/3V3_GNSS` → `U18`. Independent of the modem. |
|
||||||
|
| UVLO margin on battery | `/MAIN5V` (boost, R53 499 k / R54 100 k → 4.79 V nominal, 4.6 V measured under load on V5.5) − `D21` forward drop (≈0.3–0.45 V at 1–2 A) ≈ **4.2–4.5 V at U20 VIN** vs AP64350 VIN(min) 3.8 V → ≈ **0.4–0.7 V margin** (V5.5 had ≈ 0.1 V). Adequate but not generous: the buck runs at ~90 % duty (3.8 V out of 4.3 V in) during a 2 A burst. |
|
||||||
|
| Input capacitance at U20 | `C127` 10 µF (5.4 mm from U20.2) + `C128` 1 µF (2.0 mm). The V5.6 ECO specifies 2 × 22 µF + 10 µF at VIN (< 3 mm). |
|
||||||
|
| Output bulk at U19 | `C130` 220 µF, `C131` 220 µF, `C132` 22 µF, `C133` 1 µF, `C134` 100 nF, `C135` 33 pF, `C136` 10 pF, `D22` SMAJ5.0A. Distances from the VBAT pads (U19.55/56/57): **C130 17.8–19.7 mm, C131 10.5–12.4 mm**, C132 5.6–7.3 mm, C133 4.1–5.5 mm, D22 23–25 mm. The 440 µF sits 10–20 mm away, behind `/VBAT_MODEM` tracks of 0.25–3.0 mm (58.9 mm total, 6.3 mm on In1 at 0.5 mm). |
|
||||||
|
|
||||||
|
**Verdict: ✅ covered (architecture) — 4 layout/value follow-ups.**
|
||||||
|
|
||||||
|
**Changes:**
|
||||||
|
1. Move `C131` (and ideally `C130`) to ≤ 5 mm of U19 pads 55–57; pour `/VBAT_MODEM` on F.Cu from L20 to U19 (≥ 1.5 mm, no 0.25/0.5 mm necks; the T15 DRC rule already flags ≥ 0.8 mm).
|
||||||
|
2. Add 2 × 22 µF 0805 (C86817) at `U20.2 VIN` (< 3 mm), keep `C127`/`C128`; widen `/VIN_MODEM` (0.25/0.5 mm today) and `/SW_MODEM` (0.25 mm, 23 mm long) to ≥ 0.8 mm.
|
||||||
|
3. Battery-mode headroom (choose one, bench-decided): (a) `R53` 499 k → 511 k (C188257) → boost 4.89 V (+0.1 V at U20 VIN); (b) replace `D21` with a low-Vf Schottky in a bigger package or a P-FET ideal-diode; (c) lower `/VBAT_MODEM` to 3.6 V (`R110` 75 k → 70 k) — A7670SA VBAT range is 3.4–4.2 V, 3.8 V typical; 3.6 V keeps the buck out of dropout. Not required to order; required before the 20-cycle battery test.
|
||||||
|
4. Firmware (v6 `board_v6.h`): `PIN_MODEM_PWR_EN PC10`, `PIN_MODEM_PWRKEY PC8`, `PIN_MODEM_STATUS PC9`, `PIN_MODEM_RST PC11`, modem UART = **USART6 (PC6 TX / PC7 RX)**; K1 Mode B via `BYP_CTRL` = PB5 (pad 57, `R40` → `Q6` → `K1` coil).
|
||||||
|
|
||||||
|
Note on behaviour: because `R113` is a pull-down, **any MCU reset (DFU, IWDG, `NVIC_SystemReset`) drops `MODEM_PWR_EN` and power-cycles the modem**. That is the intended V5.6 policy (modem OFF while the MCU is not in control), but firmware must re-run the settled-rail sequence after every reset, and a watchdog reset costs a ~30 s re-registration.
|
||||||
|
|
||||||
|
### F2 — 10-min duty cycle on battery impossible on V5.5
|
||||||
|
|
||||||
|
**What v6 does today:** `/PWR_CTRL` (PA1) switches only the F9P rail (`Q1` → `/SW_5V` → `U21`); `/MODEM_PWR_EN` (PC10) switches only the modem buck. `/MODEM_STATUS` (PC9) and the RTCM tap on PC7 give a real "modem up" signal. `NRST` reaches only the MCU (`SW1`, `P6` RESET-EXT, `TP5`, `C104`), as on V5.5.
|
||||||
|
|
||||||
|
**Verdict: ✅ covered (hardware).** Firmware: `ENABLE_DUTY 1` on the v6 build with the V5.6 window — `PWR_CTRL` high → ≥ 4 s → `MODEM_PWR_EN` high → PWRKEY pulse → wait `STATUS` high / first RTCM bytes on PC7 → ≥ 2 `$PHLG` with `pwr=BATT` and fresh fix → `MODEM_PWR_EN` low → `PWR_CTRL` low → sleep 10 min. End of window decided by STATUS/RTCM, not by a timer. Note `K1` (G5V-1, coil on `/SYS5V` via `Q6`) draws its 0.15 W whenever Mode B is held on battery.
|
||||||
|
|
||||||
|
### F3 — Link-recovery stack cycles on battery kill the modem
|
||||||
|
|
||||||
|
**What v6 does today:** the modem can be reset (`MODEM_RST` PC11), PWRKEY-cycled (PC8) or power-cycled alone (`MODEM_PWR_EN` PC10) without touching the F9P, and `MODEM_STATUS` (PC9) confirms the result.
|
||||||
|
|
||||||
|
**Verdict: ✅ covered (hardware).** Firmware rule for v6 stays as 0.5.9: no stack cycle on battery, ever; recovery escalates modem-only — `MODEM_RST` 500 ms → PWRKEY off/on → `MODEM_PWR_EN` OFF 5 s / ON — and only after `PWR_CTRL` has been high ≥ 4 s. Never cycle `PWR_CTRL` for a link problem.
|
||||||
|
|
||||||
|
### F4 — Charger input limit above the supply (RS1 8 mΩ), charge current 2.4 A (R50 825 Ω)
|
||||||
|
|
||||||
|
**What v6 does today:** `RS1` = **10 mΩ/1 % 1206 (C105362)** between `/VEH5V` and `/VIN_SW` → LTC4040 input limit 25 mV / 10 mΩ = **2.5 A** ✅, below U25's 3 A. **`R50` = 825 Ω/1 % (C50214)** on `PROG` → 2000/825 = **2.42 A** charge ❌. `CHRG_EN` = PA8 (pad 41) with `R56` 100 k pull-down — the 0.6.0 governor works unchanged. `CHRG_STAT` = PB3, `CHRG_FAULT` = PB4 (pull-ups `R57`/`R58` 100 k).
|
||||||
|
|
||||||
|
**Verdict: ⚠ partial.** Change: **`R50` 825 Ω → 1.5 kΩ 0603 1 % (C22843)** → 1.33 A (12 Ah in ~9 h). Governor 0.6.0 stays as the second layer. On v6 the supply is U25 (3 A rated, 3.5 A switch) — same reasoning as the SD-15B.
|
||||||
|
|
||||||
|
### F5 — Slow charge on H0008: LTC4040 die-temperature cycling from thin copper / no thermal vias
|
||||||
|
|
||||||
|
**What v6 does today (measured on the board file):**
|
||||||
|
|
||||||
|
| Item | v6 | Target (ECO D2 / Copper Plan) |
|
||||||
|
|---|---|---|
|
||||||
|
| `/SW_BAT` (U6.21/22 → L6.1) | **4 segments, 0.25 mm, 12.3 mm total, F.Cu, no pour** | ≥ 2 mm polygon |
|
||||||
|
| `/BAT_PLUS` (P3.1 → L6.2 → U6.23, C35, R5) | 0.25 mm (5.4 mm) + 0.5 mm (42 mm F.Cu + 70.5 mm In2) + 1.0 mm (4.9 mm); 2 vias; no pour | ≥ 1.5 mm + via farm |
|
||||||
|
| U6 exposed pad (pad 25, 2.65 × 3.65 mm) | footprint `QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm` (no ThermalVias variant); **0 vias inside the EP**; nearest GND via 4.4 mm away | ≥ 9 thermal vias to In1 GND |
|
||||||
|
| `L6` 2.2 µH/8 A distance to U6 | 15.2 mm (pad-to-pad 10.2–11.1 mm) | ≤ 5 mm |
|
||||||
|
| Input cap `C30` 10 µF / `C31` 2.2 µF to U6 | 11.2 mm / 10.0 mm | ≤ 3 mm |
|
||||||
|
| Temperature sensor at U6/L6 | **None.** `U4` TMP102 was deleted in v6 (schematic note); `U3` SHT40 is at (122.4, 77.3), **71 mm** from U6; `P7` NTC-HOTSPOT / `P8` NTC-PROBE-2 are JST jacks for external probes (PB1 / PC4) at 100 mm. | On-board sensor at U6/L6 |
|
||||||
|
|
||||||
|
**Verdict: ❌ missing.** This is the highest-risk item: v6 repeats the V5.5 boost copper and makes it slightly worse (0.25 vs 0.3 mm), and the charger will run its ~2.5 A input / 1.3–2.4 A charge through it at 45 °C ambient.
|
||||||
|
|
||||||
|
**Changes:**
|
||||||
|
1. Re-cluster U6: `L6` ≤ 5 mm from pads 21/22, `C30`/`C31` ≤ 3 mm from pads 6/16, `C35` at pad 23 (pre-fab audit B5).
|
||||||
|
2. `/SW_BAT` as an F.Cu polygon ≥ 2 mm wide; `/BAT_PLUS` ≥ 1.5 mm F.Cu from P3 to L6/U6 with a via farm to an In2 copper area (drop the 70 mm 0.5 mm inner run).
|
||||||
|
3. Replace the U6 footprint with the `…_ThermalVias` variant or add ≥ 9 × 0.3 mm vias in the EP to the In1 GND plane; keep the In1 plane solid under U6 (it is split into islands today — pre-fab audit §7).
|
||||||
|
4. Add a temperature sensor at U6/L6: **TMP102 SOT-563 (C99269, address 0x48 — free on v6; SC16IS752 is 0x4D, SHT40 0x44, SC7A20 0x18) placed between U6 and L6**, or an on-board 10 k NTC to **PC5 (pad 25, ADC1_IN15, free)** with the same 10 k/100 nF network as `R42`/`C24`. Firmware: `tchg` append field in `$PHLG`; governor uses it instead of the V5 `U4` cell sensor. Also log `tmax`.
|
||||||
|
5. Bench: thermal camera on U6/L6 during 1 h of charge at 1.3 A and 1 h of backup at 2.5 A; the 60 mV/30 s pulsing seen on H0008 must not appear.
|
||||||
|
|
||||||
|
### F6 — NTC pause invisible; charge window with RNTB 10 k pauses above ~40–42 °C
|
||||||
|
|
||||||
|
**What v6 does today:** `R55` (= RNTB) **10 k/1 % (C25804)** from `/VEH5V` to `/NTC` (`U6.17`, `P3.3`). `JP2` value `F2:Li-ion`, bridged 1-2 → `/F2_SEL` = `/MAIN5V` (high) = Li-ion 4.0/4.1 V float. `JP3` F1:0, `JP4` F0:1 as on V5.5. `CHRG_FAULT` → PB4 with pull-up: the firmware can show `cflt=1` as "pausa NTC" (LTC4040 keeps CHRG low during an NTC pause; only FAULT goes low).
|
||||||
|
|
||||||
|
**Verdict: ⚠ partial** (visibility ✅, window ❌ until the chemistry decision).
|
||||||
|
|
||||||
|
**Changes (BOM/solder-jumper only, PCB unchanged):** if LFP-HT 26650 is chosen (ECO D1a): `JP2` 2-3 (F2 low, 3.50 V float) + `R55` **5.6 k** with a B3380 NTC (window +10…+60 °C). If Li-ion stays: keep 10 k and accept the pause (or 6.6 k = pause at 55 °C, hard on the cell). Firmware/monitor: `ltc=PAUSA NTC` when `CHRG_EN` allowed ∧ `CHRG_STAT` idle ∧ `CHRG_FAULT` low; cell-temperature inhibit threshold per chemistry (Li-ion 45 °C / LFP 55–60 °C). Silkscreen `JP2 = F2 (Li-ion / LFP)`.
|
||||||
|
|
||||||
|
### F7 — Power-supply margin: 5.25–5.57 V trimmed units vs PFI 4.44 V / warning 4.60 V / shed 4.90 V
|
||||||
|
|
||||||
|
**What v6 does today:** `U25` TPS54360B (C524806), feedback `R121` **53.6 k/1 %** / `R122` **10.2 k/1 %** → V_out = 0.8 V × (1 + 53.6/10.2) = **5.00 V** (pre-fab audit: "5.00 V, ~620 kHz"; `R120` 162 k). `R124` 523 k / `R125` 84.5 k (EN UVLO divider) are DNP → EN floats high (internal pull-up), U25 runs from ≈ 4.5 V input. LTC4040: PFI `R51` 270 k / `R52` 100 k → 1.2 V × 3.7 = **4.44 V**; boost `R53` 499 k / `R54` 100 k → 0.8 V × 5.99 = **4.79 V**. `5V_SENSE` = `/VEH5V` × 10 k/(10 k + 10 k) (`R7`/`R8`) → PA4, so the ADC scale is fine up to 6.6 V. `P2` (bench SD-15B) is in parallel on `/VEH5V` ("one source at a time").
|
||||||
|
|
||||||
|
Margins with 5.00 V: to PFI **0.56 V**; to the 0.6.0 governor shed line (4.90 V) **0.10 V**; to the governor start line (5.05 V) **−0.05 V** — the charger would never be enabled, and a 100–200 mV LTE sag (V5.5 measured) would hit the shed line on every burst.
|
||||||
|
|
||||||
|
**Verdict: ❌ missing.**
|
||||||
|
|
||||||
|
**Changes:** `R121` 53.6 k → **57.6 k/1 % 0603** → 0.8 × (1 + 57.6/10.2) = **5.32 V** (56.2 k → 5.21 V is the minimum acceptable). Within LTC4040 VIN range (3.5–5.5 V) and U25 rating; `5V_SENSE` unchanged. Pick the LCSC number in the sourcing pass (basic 0603 1 %). Governor thresholds (5.05 start / 4.90 shed / 4.60 warn / 4.44 PFI) then have the same 0.3–0.9 V ladder as the field units. Also re-cluster U25 (`L22` 25.9 mm, `D34` 18–23 mm, `C149`/`C150` 5.4–8.8 mm from pins today) — pre-fab audit B5.
|
||||||
|
|
||||||
|
### F8 — Robustness items (F1 PPTC, ETH_RST float, J9 ESD, DFU ESD placement, BOOT1 trap, PoE)
|
||||||
|
|
||||||
|
| Item | v6 today | Verdict | Change |
|
||||||
|
|---|---|---|---|
|
||||||
|
| F1 PPTC 3 A (C20627123) | `F1` between `/SYS5V` and `/SW_IN` → `Q1` → `/SW_5V` → `U21` LDO → F9P only (`/SW_5V` nodes: Q1.3, C3, C40, C119, U21). The modem is not behind it. | ⚠ | Harmless (≈ 15 mV at 150 mA) but pointless at 3 A; resize to 1–1.5 A hold so it actually protects the F9P/LDO, or keep and note. Not a blocker. |
|
||||||
|
| `ETH_RST` (PA15, pad 50 → `U11.37`) | Only two nodes; **no pull resistor**. `U12` (3V3_ETH buck) has EN tied to VIN (`U12.2` = `/SYS5V`) → `/3V3_ETH` is always up, on battery too. During an MCU reset PA15 floats, the W5500 leaves reset and draws ~130 mA for the ~4 s. | ❌ | Add 100 k 0603 (C103211) `ETH_RST` → GND (= V5.6 `R112`). Optional: drive `U12` EN from a free MCU pin (PD2 pad 54 or PB10 pad 29) with a 100 k pull-down so `/3V3_ETH` is fully off on battery and in reset. |
|
||||||
|
| J9 modem USB-C ESD | `/USB_DP`, `/USB_DM`, `/USB_VBUS` nodes: J9 and U19 only. **No ESD device.** `Rcc1`/`Rcc2` 5.1 k present. | ❌ | Add USBLC6-2SC6 SOT-23-6 (C7519) at J9 (= V5.6 `D19`): I/O1 → USB_DM, I/O2 → USB_DP, VBUS → USB_VBUS. |
|
||||||
|
| DFU ESD at J11 | `D14` (DFU_DP) 3.0 mm, `D15` (DFU_DM) 3.7 mm, `D16` (DFU_VBUS) 6.6 mm from J11 centre. | ✅ | — |
|
||||||
|
| BOOT1 trap | `ETH_INT` = **PC0** (pad 8); PB2 (pad 28) = `/BOOT1_STRAP` with `R99` 10 k to GND; schematic note "never repurpose PB2". | ✅ | — |
|
||||||
|
| PoE on J10 | `J10` HR911105A pins 7/8 unconnected; no PoE PD circuit. Firmware 0.6.0-eth documents "sin PoE". | ⚠ (decision) | Keep no PoE (external splitter). Record the decision; if PoE is ever wanted it is a v6.1 feature (PD controller + isolated DC-DC), not a patch. |
|
||||||
|
| Cutoff bypass | `P5` CUTOFF-SW between `/MAIN5V` and `/SYS5V`; no solder-jumper in parallel (JP1 = fan, JP5 = RS-485 term). | ⚠ | Add `JP_CUT` (SolderJumper_2_Open) across P5, open by default (= V5.6 `JP6`). |
|
||||||
|
| Silkscreen | Not checked here (pre-fab audit: all labels 0.5 mm/0.1 mm). | — | `SW1 = RESET MCU`, `JP2 = F2 (Li-ion / LFP)`, `P5 = CUTOFF`, labels ≥ 0.8/0.15 mm. |
|
||||||
|
|
||||||
|
**Verdict: ⚠ partial.**
|
||||||
|
|
||||||
|
### F9 — Software/process lessons
|
||||||
|
|
||||||
|
| Lesson | v6 implication | Verdict |
|
||||||
|
|---|---|---|
|
||||||
|
| Unit identity = modem `$GPTXT H00xx` | **v6 has no ArduSimple NTRIP Master**: the A7670SA is driven by the MCU, so nobody emits `$GPTXT H00xx`. The MCU must generate the identity on every path (4G and Ethernet) — `$PHID,<uid>,<fw>,<board>,<mac>,<up_s>` from 0.6.0-eth is the right vehicle; the server (`retranslator`) needs to accept `$PHID` as the primary ID before v6 ships. | ⚠ |
|
||||||
|
| `$PHLG` append-only fields | New v6 fields (`tchg`, `rtcm_bps`, `modem_status`, `tmodem` if read from the module) go at the end. | ✅ (rule) |
|
||||||
|
| Deploy with conflict markers broke the dashboard | Process: pre-deploy syntax check (`node --check` / `python -m py_compile`) in the deploy script; never `git stash pop` on the production tree. Not a board item. | ⚠ (process) |
|
||||||
|
| Monitor shows power source and charger state explicitly; history stores `pwr`, `v5min`, `vbat_min` | v6 adds `MODEM_STATUS` and `CHRG_FAULT` (PB4) → columns "Módem" and "pausa NTC". | ✅ (rule) |
|
||||||
|
| Modem temperature | v6 can read it from the module over USART6 (`AT+CPMUTEMP` on SIMCom A76xx, to be confirmed on the A7670SA firmware) — no extra sensor needed for the modem; the charger sensor (F5) is still needed. | — |
|
||||||
|
|
||||||
|
**Verdict: ⚠ partial** (identity path must change for v6).
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 2. Specific v6 checks requested
|
||||||
|
|
||||||
|
| Check | Found in v6 | Assessment |
|
||||||
|
|---|---|---|
|
||||||
|
| U25 output divider and margin to PFI / VSYS | `R121` 53.6 k / `R122` 10.2 k → 5.00 V; PFI 4.44 V (`R51` 270 k / `R52` 100 k); boost 4.79 V (`R53` 499 k / `R54` 100 k) | ❌ 0.56 V to PFI, 0.10 V to the 4.90 V shed line → `R121` 57.6 k (5.32 V) |
|
||||||
|
| Modem buck input on battery and UVLO margin | `/VIN_MODEM` ← `D21` PMEG3050EP ← `/MAIN5V` (boost) on battery; ← `D20` SS34 ← `/24V` on vehicle power | ⚠ ≈ 4.2–4.5 V at U20 VIN vs 3.8 V min → 0.4–0.7 V; improve with R53 511 k, lower-Vf D21 or VBAT_MODEM 3.6 V |
|
||||||
|
| MODEM_PWR_EN / PWRKEY / STATUS / RST to MCU | PC10 (pad 51) / PC8 (39, via Q20) / PC9 (40, via U24) / PC11 (52, via Q21); pull-downs R113/R114/R115 100 k | ✅ |
|
||||||
|
| Modem UART to MCU | USART6: PC7 RX ← `R106` 100 Ω ← `/DOUT_4G` (always); PC6 TX → `K1` NO → `/DIN_4G` (Mode B) | ✅ |
|
||||||
|
| Modem VBAT bulk near U19 | 440 µF (`C130`/`C131`) at 10.5–19.7 mm from pads 55–57; `C132` 22 µF at 5.6–7.3 mm | ⚠ move to ≤ 5 mm, pour VBAT_MODEM |
|
||||||
|
| `/SW_BAT` and `/BAT_PLUS` copper | 0.25 mm × 12.3 mm; 0.25–0.5 mm (+70 mm on In2); no pours | ❌ |
|
||||||
|
| LTC4040 EP thermal vias | 0 in the EP; footprint has no ThermalVias variant | ❌ |
|
||||||
|
| RNTB and JP2 default | `R55` 10 k; `JP2` 1-2 = Li-ion | ⚠ pending D1 |
|
||||||
|
| F1 / F2 fuses | `F1` PPTC 3 A on the F9P rail only; `F2` 2 A/125 V nano fuse in holder on `/24V_IN` (LCSC still TBD per pre-fab audit) | ⚠ resize F1 (optional); pick F2 part |
|
||||||
|
| ETH_RST pull | none | ❌ 100 k to GND |
|
||||||
|
| J9 / J11 ESD | J11 ✅ (D14/D15/D16 at 3–7 mm); J9 ❌ none | add USBLC6-2SC6 at J9 |
|
||||||
|
| W5500 PoE | none (J10 pins 7/8 open) | decision: stay without PoE |
|
||||||
|
| Switcher EP vias (U20, U25) | 0 vias within 3 mm of either EP | add thermal vias (secondary to U6) |
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 3. What to carry from V5.6 into v6
|
||||||
|
|
||||||
|
| V5.6 item | Already in v6? | Action for v6 |
|
||||||
|
|---|---|---|
|
||||||
|
| `MODEM_EN` sequencing (F9P first, modem 4 s later on a settled rail) | Hardware ✅ (`MODEM_PWR_EN` PC10 + `PWR_CTRL` PA1) | Firmware `board_v6.h` + `ENABLE_DUTY 1`; identical window logic to V5.6 0.7.0, plus PWRKEY pulse and `STATUS` wait. |
|
||||||
|
| RTCM / modem-UART visibility (`RTCM_TAP` PC7 = USART6_RX) | ✅ built in (`R106` → PC7; `K1` → PC6) | Byte counter on USART6 RX = "NTRIP flowing"; `rtcm_bps` field. |
|
||||||
|
| Thermal copper for U6 (ECO D2 / EMC #1 #2) | ❌ | `/SW_BAT` ≥ 2 mm pour, `/BAT_PLUS` ≥ 1.5 mm + vias, EP ≥ 9 vias, L6/C30 re-clustered. |
|
||||||
|
| `RS1` 10 mΩ (C105362) | ✅ | — |
|
||||||
|
| `R50` 1.5 k (C22843) | ❌ (825 Ω) | Change value. |
|
||||||
|
| `RNTB` 5.6 k + `JP2` 2-3 (if LFP) | ❌ (10 k, Li-ion) | Decide chemistry (D1); BOM/jumper only. |
|
||||||
|
| PSU set-point ≥ 5.2 V | ❌ (5.00 V) | `R121` 57.6 k → 5.32 V. |
|
||||||
|
| ESD at connectors | J11 ✅ / J9 ❌ | USBLC6-2SC6 (C7519) at J9. |
|
||||||
|
| Fuse in the F9P rail | ⚠ (3 A PPTC) | Resize to 1–1.5 A or leave; document. |
|
||||||
|
| `ETH_RST` pull-down 100 k | ❌ | Add (C103211). |
|
||||||
|
| PoE decision | none by design | Keep; write it in the schematic block-N note. |
|
||||||
|
| Second TMP102 / NTC at U6 | ❌ (no sensor near U6; TMP102 deleted in v6) | TMP102 SOT-563 (C99269, 0x48) between U6 and L6, or NTC → PC5. |
|
||||||
|
| `JP_CUT` across the cutoff connector | ❌ | Solder jumper across `P5`. |
|
||||||
|
| 220 µF polymer on the F9P rail (`C3`) | `C3` 47 µF elco on `/SW_5V` | Optional on v6: `/SW_5V` only feeds the AP2112K LDO now. |
|
||||||
|
| 2 × 22 µF + 10 µF at the modem buck input | `C127` 10 µF + `C128` 1 µF | Add 2 × 22 µF (C86817) at `U20.2`. |
|
||||||
|
| AP64350 compensation (Rcomp 14 k, Ccomp 3.3 nF, 47 pF, RT 200 k, BST 100 nF) | v6 is the source (`R116` 14 k, `C141` 3.3 nF, `C142` 47 pF, `R117` 200 k, `C129` 100 nF) | Verify against the AP64350 datasheet application table for 3.8 V / 4.7 µH / 2 × 220 µF + 22 µF (same open point as V5.6 §6.1). |
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 4. Checklist ordered by risk
|
||||||
|
|
||||||
|
| # | Risk | Lesson | Item | Refdes / value / net | Owner |
|
||||||
|
|---|---|---|---|---|---|
|
||||||
|
| 1 | 🔴 | F5 | LTC4040 copper + thermal vias + re-cluster | `/SW_BAT` 0.25 → ≥ 2 mm pour; `/BAT_PLUS` ≥ 1.5 mm + via farm; `U6` EP ≥ 9 × 0.3 mm vias; `L6` ≤ 5 mm; `C30`/`C31` ≤ 3 mm | Michelle |
|
||||||
|
| 2 | 🔴 | F7 | Vehicle PSU set-point | `R121` 53.6 k → **57.6 k/1 %** (5.32 V); re-cluster `L22`/`D34`/`C149`/`C150` | Leo (value) / Michelle (layout) |
|
||||||
|
| 3 | 🔴 | F4 | Charge current | `R50` 825 Ω → **1.5 k/1 %** (C22843) | Leo |
|
||||||
|
| 4 | 🟠 | F1 | Modem rail integrity on battery | `C130`/`C131` ≤ 5 mm from U19.55–57; pour `/VBAT_MODEM`; `/VIN_MODEM`, `/SW_MODEM` ≥ 0.8 mm; + 2 × 22 µF at `U20.2`; optional `R53` 511 k / D21 low-Vf / VBAT 3.6 V | Michelle / Leo |
|
||||||
|
| 5 | 🟠 | F5 | Temperature sensor at the charger | TMP102 SOT-563 (C99269, 0x48) between U6 and L6 + 100 nF, or NTC → PC5 | Leo |
|
||||||
|
| 6 | 🟠 | F8 | W5500 in reset while MCU resets | 100 k (C103211) `/ETH_RST` → GND; optional `U12` EN from PD2/PB10 | Leo |
|
||||||
|
| 7 | 🟠 | F8 | Modem USB ESD | USBLC6-2SC6 (C7519) at `J9` | Leo |
|
||||||
|
| 8 | 🟠 | F6 | NTC window / chemistry | `R55` 10 k → 5.6 k + `JP2` 2-3 if LFP-HT; else keep and display "pausa NTC" | Leo (decision D1) |
|
||||||
|
| 9 | 🟡 | F8 | Cutoff bypass | `JP_CUT` solder jumper across `P5` | Michelle |
|
||||||
|
| 10 | 🟡 | F8 | F9P rail fuse | `F1` 3 A PPTC → 1–1.5 A hold (or document) ; `F2` part number (TBD) | Leo |
|
||||||
|
| 11 | 🟡 | F9 | Identity without `$GPTXT` | `$PHID` from MCU UID on 4G too; server accepts it | Firmware / backend |
|
||||||
|
| 12 | 🟡 | F1/F2/F3 | Firmware v6 | `board_v6.h` pins (PC10/PC8/PC9/PC11, USART6, PB5 K1), duty window, modem-only recovery, no stack cycle on battery | Firmware |
|
||||||
|
| 13 | 🟡 | F8 | PoE | Record "no PoE, external splitter" in block N | Leo |
|
||||||
|
| 14 | ⚪ | F1 | AP64350 compensation vs datasheet table | `R116`/`C141`/`C142`/`R117`/`C129` | Leo |
|
||||||
|
| 15 | ⚪ | F5 | Bench validation | Thermal camera U6/L6 at 1.3 A charge and 2.5 A backup, 1 h each; 20 battery duty cycles; U20 VIN scope at 3.5 V cell | Jesús / Leo |
|
||||||
|
|
||||||
|
**Tally: ✅ 3 (F1, F2, F3) · ⚠ 4 (F4, F6, F8, F9) · ❌ 2 (F5, F7).**
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 5. Notes and non-findings
|
||||||
|
|
||||||
|
- The v5.5 `DzG1` gate-clamp fix, the `R51` 270 k PFI choice (E-PFI 24-Jul) and the `RS1` 10 mΩ are already in v6.
|
||||||
|
- `U12` (3V3_ETH, MP1584EN from `/SYS5V`) keeps the MP1584 UVLO issue but Ethernet is not used on battery; firmware 0.6.0-eth holds the W5500 in reset without 5 V. Combined with the `ETH_RST` pull-down that is acceptable for v6.
|
||||||
|
- `C3` 47 µF and `C40` 22 µF on `/SW_5V` now only buffer the AP2112K LDO input; the V5.6 polymer upgrade is optional here.
|
||||||
|
- Free MCU pins after this review: PC5 (25, ADC), PB10 (29), PA9 (42), PD2 (54). PC5 is the natural home for an on-board charger NTC; PD2/PB10 for a `U12` EN.
|
||||||
|
- Nothing in this review changes the v6 architecture; every item is a value, a footprint or a layout change, so the pre-fab audit's B5/B6 pass (Michelle) can absorb items 1, 2 (layout part), 4 and 9 in one go.
|
||||||
@ -0,0 +1,533 @@
|
|||||||
|
# A (Power tree) + F-5x (temperature sensors / fan) — v6 audit findings
|
||||||
|
Snapshot: sch ecee9fed… / pcb 6ddec80d… (evidence pack 2026-09-28)
|
||||||
|
|
||||||
|
Auditor: POWER (block §4-A plus the temperature-sensor and fan parts of §4-F). All values come from the evidence pack (`nets.json`, `ref_pins.json`, `components.csv`, `pcb_pads.csv`, `pcb_tracks.csv`, `vias.csv`, zone fills parsed from `src/hbox-watchdog-v6.kicad_pcb`) and from datasheets fetched this session. Scratch scripts and results are in `/home/claude/v6audit/work/A_power/` (`q.py` net/ref dump, `segs.py` segment lists, `path.py` widest-path bottleneck and resistance per current path, `pdist.py` pad edge-to-edge distances, `islands.py`/`island_of.py` GND-pour island map, `under.py` copper under parts).
|
||||||
|
|
||||||
|
Conventions: "edge" = pad-copper to pad-copper distance (shapely, true pad shapes); "ctr" = pad centre distance. Track resistance assumes 1 oz (35 µm) copper, ρ = 1.72e-8 Ω·m. Trace temperature rise uses IPC-2221 (k = 0.048 external, 0.024 internal). IPC-2221 is known to be pessimistic for inner layers next to planes, and IPC-2152 gives roughly half the internal rise. Both are quoted where it matters. The GND-island analysis uses the **zone fills stored in the file**. Refill before fab and re-run `islands.py`.
|
||||||
|
|
||||||
|
## Sources read
|
||||||
|
- `findings/_COMMON_BRIEF.md`, `INDEX.md`, `evidence/MANIFEST.md`, master brief §3–§5, §4-A, §4-F (temperature/fan).
|
||||||
|
- `docs/2026-09-28_Drogheda_EinarBoard-v6_Review-vs-V5.5-Lessons_v1.0.md` (§1 F1/F4/F5/F6/F7/F8, §2, §3, §4 checklist).
|
||||||
|
- `docs/2026-09-27_Drogheda_EinarBoard-V5.6_ECO_ES_v1.0.md` (§0 R1–R5, §A, §C, §D, §E, §F, §H, §I).
|
||||||
|
- `docs/2026-09-28_Drogheda_EinarBoard-V5.6_Schematic-Change-Report_v1.0.md` (§1, §2, §6).
|
||||||
|
- `docs/2026-09-28_H0008_charging-overnight-log.md`.
|
||||||
|
- `docs/project/claude__2026-09-27_HBOX-V5.5-V4_Modem-on-battery_Diagnosis-and-0.5.8-Field-Strategy.md`.
|
||||||
|
- Memory copies in `docs/memory/`: `drogheda-battery-hightemp`, `drogheda-einarboard-modem-rail`, `drogheda-backup-lowpower`, `drogheda-power-cost`, `drogheda-fan-policy`, `drogheda-einarboard-v5-audit`, `drogheda-einarboard-harness`, `drogheda-einarboard-short-incident`, `drogheda-einarboard-v6-brief`, `preferences`.
|
||||||
|
- Evidence: `components.csv`, `nets.json`, `ref_pins.json`, `ic_pins_U6/U25/U20/U2/U12/U17/U21.csv`, `mcu_pins.csv`, `pcb_footprints.csv`, `pcb_pads.csv`, `pcb_tracks.csv`, `vias.csv`, `zones.csv`, `net_routing_summary.csv`, `drc_summary.md`, `clearance_24v.md`, `diff_v56_v6.md`, `sch_pcb_sync.md`, `bom.csv`, `firmware_constants.csv`; firmware `src/fw/hbox_v5_bringup.ino`, `board_v5.h`.
|
||||||
|
- Datasheets (fetched this session):
|
||||||
|
- **LTC4040** Rev B (ADI `4040fb.pdf`): pin functions p.10–11; EC p.3–5 (ICHG 950/1000/1050 mA at RPROG 2k, VCLN 23.5/25/26.5 mV, VBSTFB 0.78/0.80/0.82 V, PFI 1.17/1.19/1.21 V falling with 30 mV hysteresis, RSTFB 0.74 V, NTC hot 34.9 %VIN / cold 76.5 %VIN, safety timer 4.25 h Li-ion, ILIMBST 5.5/6.5/7.5 A, IBATQ 40 µA, IINQ 570 µA); "2.5 A from a battery as low as 3.2 V" p.15; "external load prioritized … charge current drops to zero" p.13/16; RPROG = 2000 V/ICHG p.18; CSYS "at least 100 µF low-ESR ceramic" p.10, "≥75 µF transient" p.21; θJA 43 °C/W; overtemperature protection only (no charge-current thermal regulation), p.5 Note 2; layout p.22–23; abs max VIN 6 V steady / 7 V transient, VSYS/BAT/SW 6 V p.2; OVSNS "6.2 k to the connector if OVP used, else short to VIN" p.11.
|
||||||
|
- **TPS54360B** (TI `tps54360b.pdf`): Vref 0.792/0.800/0.808 V; fSW = 92417·RT^-0.991 (162 k → 600 kHz); tON,min 135 ns; peak switch limit 4.5/5.5/6.8 A; EN 1.2 V, Ip 1.2 µA, Ih 3.4 µA, VIN UVLO 4.1–4.3 V; gmps 12 A/V, gmea 350 µS; compensation equations; 5 V/3.5 A example design (53.6k/10.2k, 13k/6.8 nF/39 pF, 8.2 µH, 2×47 µF ceramic, B560C, 2×2.2 µF/100 V); soft start 1024 cycles; θJA 42 °C/W; abs max VIN 65 V.
|
||||||
|
- **AP64350** (Diodes DS41976 Rev 5-2): abs max VIN 42 V DC / 45 V 400 ms, EN 42 V; VIN 3.8–40 V; UVLO rising 3.5–3.7 V, hysteresis 400 mV; EN high 1.18–1.25 V / low 1.03–1.09 V, EN pull-up 5.5 µA; FB 792–808 mV; RT = 100000/fSW (200 k → 500 kHz); HS limit 4.25/5/5.75 A; tON,min 100 ns; Table 1 (5 V: 14.0 k/3.3 nF/47 pF, 5.5 µH, 2×22 µF); R5 = 4.67e3·fc·VOUT·COUT; θJA 45 °C/W.
|
||||||
|
- **MP1584** (MPS Rev 1.0): abs max VIN 30 V, all other pins (EN, FB, COMP, FREQ) 6 V; VIN 4.5–28 V; EN rising 1.5 V/hysteresis 0.3 V; UVLO 3.0/2.6 V; FB 0.776/0.8/0.824 V; switch limit 4.0–4.7 A.
|
||||||
|
- **AMS1117** (AMS `ds1117.pdf`): dropout 1.1 V typ/1.3 V max at 0.8 A; ground current 5/11 mA; output cap 22 µF tantalum; VOUT 3.251–3.399 V.
|
||||||
|
- **A7670X series Hardware Design V1.03** (SIMCom, Table 8 p.26–27): VBAT 3.4/3.8/4.2 V; 2 A peak (GSM max-power TX); supply ≥ 2 A for < 300 mV drop; ≥ 300 µF bulk (≥ 600 µF if the supply cannot give 2 A); VBAT trace ≥ 3 mm; off leakage 20 µA; PWRKEY ≥ 50 ms, STATUS ~7 s; A7670SA includes GSM 850/900/1800/1900.
|
||||||
|
- JLC DB (`get_jlcpcb_part` / `search_jlcpcb_parts`): C524806, C2071691, C15051, C6186, C51118, C15578, C840531, C5440143, C2827940, C165527, C88734, C88744, C116241, C881921, C206910, C206912, C206914, C20627123, C699039, C224019, C152082, C50603, C85100, C8678, C2624, C35349, C105362, C687163, C17700165, C17700167, C17700171, C153036, C440198, C86817, C15849, C138687, C28695, C22843, C22840, C25957, C23082, C23080, C99269.
|
||||||
|
|
||||||
|
## Findings
|
||||||
|
|
||||||
|
### A-01 24 V front end: the `/24V` branch is unfused and outside the D32 clamp, and it feeds parts rated 30 V / 42 V
|
||||||
|
- **Severity:** Blocker
|
||||||
|
- **Block / refs:** §4-A (input protection; lead "F2 only protects the U25 branch"); lesson F8; memory `drogheda-einarboard-v6-brief` (T9 "9–36 V in"), `drogheda-einarboard-short-incident`, `drogheda-power-cost` (MP1584 finding).
|
||||||
|
- **Evidence:**
|
||||||
|
- Topology (netlist): `P1.1 /24V_IN` splits into two branches.
|
||||||
|
- Branch 1: `F2 (0154002.DR, 2 A fast) → /VIN_FUSED → Q23 IRFR5305 → /VIN_PROT` (D32 SMCJ33A, C149/C150/C151) → U25.
|
||||||
|
- Branch 2: `Q10 IRFR5305 → /24V` = {C10 47 µF/50 V, C11, C22, Ren1, **U2.7 (MP1584EN VIN)**, **D20 → /VIN_MODEM → U20.2 (AP64350 VIN)**}. It has **no fuse**, and its only clamp is **D10 SMBJ33A** on `/24V_IN` (600 W, VC 53.3 V @ 11.3 A, C224019). D32 (1.5 kW) sits on branch 1 only.
|
||||||
|
- Ratings on branch 2:
|
||||||
|
- U2 MP1584EN: VIN operating 4.5–28 V, **abs max 30 V**. EN = /24V·20k/120k = 6.0 V at 36 V vs **EN abs max 6 V**.
|
||||||
|
- U20 AP64350: **abs max 42 V** (45 V for 400 ms).
|
||||||
|
- D21 PMEG3050EP (VRRM 30 V, leakage 8 mA @ 30 V per JLC) is reverse-biased by VIN_MODEM − MAIN5V = 36 − 0.45 − 4.79 ≈ **30.8 V at the 36 V spec limit** and ≈ 48 V during a D10 clamp event.
|
||||||
|
- Standards: 24 V truck systems see 28–28.8 V charging, ISO 16750-2 overvoltage 36 V/60 min, and ISO 7637-2 pulse 2a (+112 V, 2 Ω, 50 µs). Pulse 2a through D10 gives ≈ (112 − 45)/2 ≈ 33 A, above its 11.3 A 10/1000 µs rating, with a clamp ≥ 53 V. U2 dies at the 36 V overvoltage test and U20 is over its 42 V abs max during pulse clamping.
|
||||||
|
- Layout: the `/24V` branch is 1.5 mm on In1 at **0.15 mm** from the In1 GND pour and has a via **0.15 mm** from the B.Cu `/3V3` pour (`clearance_24v.md`). An inner-layer breakdown there is an unfused vehicle-battery short, or 24 V straight onto 3V3.
|
||||||
|
- F2 sizing today: U25 input at 2.5 A/5 V is 0.60 A @ 24 V, 1.25 A @ 12 V and 1.67 A @ 9 V. The Littelfuse 154 continuous-current derating (~75 %, lower when hot) puts a 2 A fuse at its limit on a 12 V machine.
|
||||||
|
- **Consequence:** (1) A short of C10/C22, U2, U20 or D22 (a U20 high-side short puts 24 V on VBAT_MODEM and SMAJ5.0A D22 crowbars it) draws vehicle-fuse current through 0.3–1.5 mm board copper. That is a fire and harness risk. (2) U2, and in pulses U20 and D21, are over their absolute maximum ratings on the v6 target supply (9–36 V, 24 V trucks). (3) This design also carries the V5.5 U2 exposure forward.
|
||||||
|
- **Fix:** Make U25 the only consumer of vehicle voltage. Everything else then runs from protected 5 V.
|
||||||
|
1. **Fan from VEH5V, delete the 24 V fan buck.** DNP U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21, and close JP1 (`/5V_FAN` = `/VEH5V`, upstream of RS1, so fan current is outside the LTC4040 limit). JP1 today is an *open* solder jumper: change the footprint to `Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`, or fit a 0 Ω 0805. Fan current (assumed 0.2–0.3 A) adds to U25: ≤ 2.68 + 0.3 = 2.98 A vs 3.5 A rating and 4.5 A minimum current limit. Fan stays dark on battery, as today (ECO D4). This also retires the MP1584 cost item ($2.21 @100, C15051) and EMC items E3/E4 for U2.
|
||||||
|
2. **Modem buck input from MAIN5V only ("Option A").** Delete D20 and its 48 mm `/VIN_MODEM` run, and replace D21 with a copper bridge or 0 Ω link. U20 then never sees vehicle voltage. On battery its input rises from ~4.4 V to ~4.74 V (no 0.30 V diode drop; see A-05). On vehicle power the modem load (≤ 1.8 A peak at 5 V) becomes LTC4040 system load. The LTC4040 prioritises system load over charge current (datasheet p.13), and U25 is stiff: estimated 0.16 V dip for a 1.8 A step, against PFI rising max 4.66 V and U25 min 5.18 V with A-04. **Needs the modem auditor's agreement.** Option B, if the 24 V modem feed must stay: fuse and clamp as below and replace U20 with a ≥ 60 V synchronous buck, because the 42 V AP64350 cannot live behind a 53 V clamp.
|
||||||
|
3. **Q10 branch.** With (1) and (2) done, `/24V` has no loads. DNP Q10, DzG1, Rrp1, C10, C11, C22, and keep Q23 as the single reverse-polarity FET.
|
||||||
|
4. **F2.** Keep it on the (now only) branch. Rate it **3 A (0154003.DR, C206912, 2217 in stock)** for 24 V-only fleets, or **4 A (0154004.DR, C206914, 778 in stock)** if 12 V machines are in scope. Same holder footprint. Optional layout: put F2 ahead of D10 so a shorted TVS opens the board fuse.
|
||||||
|
- Effort check: every item is a schematic change (DNP/value) plus one short re-route (D21 bridge). No new parts.
|
||||||
|
- **Effort:** both (mostly schematic/BOM; D21 → bridge and removal of the D20 run are layout)
|
||||||
|
- **Confidence:** high on topology and ratings (netlist plus datasheets). Medium on the Option A system impact until the modem auditor reviews it and a bench test runs U25 with a 2 A modem step.
|
||||||
|
|
||||||
|
### A-02 LTC4040 (U6) thermal copper and placement repeat lesson F5 (the H0008 slow-charge mechanism)
|
||||||
|
- **Severity:** Blocker
|
||||||
|
- **Block / refs:** §4-A (LTC4040 thermal); lesson F5; ECO §D2 / §E1–E2; memory `drogheda-einarboard-v5-audit` (SW_BAT 0.3 mm critical); H0008 log.
|
||||||
|
- **Evidence (measured):**
|
||||||
|
|
||||||
|
| Item | v6 now | Target | Result |
|
||||||
|
|---|---|---|---|
|
||||||
|
| `/SW_BAT` U6.21/22 → L6.1 | F.Cu **0.50 mm × 11.9 mm** plus 0.25/0.30 mm necks at the pins; R ≈ 12.2 mΩ | ≥ 2 mm polygon | ❌ (V5.5 was 0.3 mm; improved but 4× short) |
|
||||||
|
| `/BAT_PLUS` P3.1 → L6.2 (battery current) | F.Cu **1.0 mm × 21.3 mm**, 10.4 mΩ | ≥ 1.5 mm + via farm | ❌ |
|
||||||
|
| `/BAT_PLUS` L6.2 → U6.23 (BAT pin, sense-class) | 1.0/0.5/0.25 mm, 18.8 mm | Kelvin from L6.2/CBAT | ⚠ acceptable electrically |
|
||||||
|
| U6 VSYS pins 1/24 → CSYS | 0.30 mm necks (1.5 mm) + 0.5 mm × 6.7 mm; C32/C33/C34 **3.9–5.3 mm** edge | pour, CSYS ≤ 2 mm | ❌ |
|
||||||
|
| CSYS GND return | C32.2 on F.Cu island 16 (the U6 EP island); **C33.2 on island 3**; C34.2 on its own 2.2 mm² island with 1 via | same island as EP, via array | ❌ |
|
||||||
|
| U6 EP (pad 25, 2.65 × 3.65 mm, solid zone connect) | **0 vias in EP**; nearest GND via **5.21 mm** (188.6, 102.7) | ≥ 9 vias to In1/In2 | ❌ |
|
||||||
|
| EP copper | F.Cu GND island 16 = **252 mm²** with 5 GND vias. Within 6 mm of U6: F.Cu GND 33.7 mm², In1 GND split between islands 0/1 (cut by 7 `/VFB_BST` + `/IGATE` + `/CHRG_*` In1 segments), In2 GND 99 mm², B.Cu = /3V3 pour | solid planes under U6 | ❌ |
|
||||||
|
| L6 distance | L6.1 ↔ U6.21/22 **8.65–9.10 mm** edge (10.7–11.1 ctr; footprints 15.25 mm) | ≤ 5 mm | ❌ |
|
||||||
|
| VIN caps C30 10 µF / C31 2.2 µF → U6.6 | **7.2 / 6.2 mm** edge | < 3 mm | ❌ |
|
||||||
|
| CBAT C35 22 µF | at P3 (192.0, 112.7): 5.2 mm from U6.23 but **21.9 mm** from L6.2 | at L6.2/BAT pin | ⚠ |
|
||||||
|
| Temperature sensor ≤ 10 mm of U6 | **none**; nearest is U3 SHT40 at **71.4 mm** | ≤ 10 mm | ❌ (F-51) |
|
||||||
|
|
||||||
|
- Trace temperature rise (IPC-2221 external, `/SW_BAT` 0.5 mm): charging at 2.42 A (R50 825 Ω) **+32 °C**; at 1.40 A (A-03) +9 °C; sustained backup at 3.6 A battery current (2.3 A at VSYS) **+79 °C**. The same current at 2.0 mm gives +8 °C.
|
||||||
|
- IC dissipation estimate (assumption: charger efficiency ≈ 90 % at 2.4 A, IC share ≈ 75 %):
|
||||||
|
- At 2.42 A: ≈ 0.75 W. As-built θJA ≈ 60–70 °C/W (the datasheet's 43 °C/W assumes a via array), so ΔTj ≈ 45–53 °C, before the 45 °C port ambient and enclosure rise.
|
||||||
|
- At 1.4 A: ≈ 0.25–0.3 W, so ΔTj ≈ 18–21 °C.
|
||||||
|
- The LTC4040 has **overtemperature shutdown only, with no charge-current thermal regulation** (datasheet p.5 Note 2). The H0008 pulsing (60–70 mV at 30 s) and the ~1.3 A average versus 2.42 A programmed are what on/off thermal cycling would produce. This is not yet proven: the clamp-meter and IR checks in the H0008 "Pendientes" 1–2 are still open.
|
||||||
|
- **Consequence:** R5 (≥ 1.3 A without thermal cycling) is not met by layout. In continuous backup the boost node and the VSYS necks run hot. This repeats the V5.5 lesson.
|
||||||
|
- **Fix (layout instructions, for Michelle):**
|
||||||
|
1. Re-cluster: L6 pad 1 ≤ 5 mm from U6.21/22. C32/C33/C34 ≤ 2 mm from VSYS pins 1/24, with GND pads on the EP island. C30/C31 ≤ 3 mm from pin 6. C35 (or an extra 22 µF 0805, C86817) at L6.2 next to BAT pin 23.
|
||||||
|
2. `/SW_BAT`: F.Cu polygon ≥ 2 mm wide covering pins 21–22 to L6.1, kept compact (it is the switch node).
|
||||||
|
3. `/BAT_PLUS` P3 → L6.2: ≥ 1.5 mm F.Cu (or a pour), plus ≥ 4 vias to an In2 copper area if routed inner.
|
||||||
|
4. `/MAIN5V`: pour from pins 1/24 over C32–C34 to the Q7 drain pads, ≥ 2 mm, with no 0.3/0.5 mm necks.
|
||||||
|
5. EP: 12 vias (3 × 4 at 0.9 mm pitch, 0.3 mm drill / 0.6 mm pad), plugged or capped (JLC via-in-pad). Or use the `QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm_ThermalVias` footprint and add vias to reach ≥ 9.
|
||||||
|
6. Keep In1 and In2 GND solid for ≥ 5 mm around U6/L6: move the `/VFB_BST` and `/IGATE` In1 runs (see A-14).
|
||||||
|
7. Put the TMP102 from F-51 between U6 and L6.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high (measured from the board file). The OT-cycling causality stays medium until the H0008 clamp/IR test.
|
||||||
|
|
||||||
|
### A-03 R50 = 825 Ω programs 2.42 A. Set 1.43 kΩ to meet R5 at worst case
|
||||||
|
- **Severity:** Blocker
|
||||||
|
- **Block / refs:** §4-A (R50); lesson F4; ECO §C; R5; H0008 log; memory `drogheda-battery-hightemp`.
|
||||||
|
- **Evidence:**
|
||||||
|
- Datasheet: ICHG = 2000 V/RPROG (p.18), accuracy ±5 % (950–1050 mA at 2 k, p.3).
|
||||||
|
- R50 825 Ω/1 % (C50214): **2.42 A** nominal (2.28–2.57 A).
|
||||||
|
- V5.6 value 1.5 kΩ: 1.333 A nominal, **1.254–1.414 A** worst case, so the low corner is **below the R5 floor of 1.3 A**.
|
||||||
|
- **1.43 kΩ: 1.399 A nominal, 1.316–1.483 A** worst case, which is ≥ 1.3 A at every corner.
|
||||||
|
- H0008 (V5.5, same R50): ≈ 1.3 A average delivered, 8.5 h to C/8, pulsing charge (A-02). At 1.4 A the IC loss drops by (2.42/1.4)² ≈ 3×, and delivered current is about what H0008 actually got, without the cycling mechanism. Charge time for the ~11.6 Ah pack from ~3.5 V is ≈ 6–7 h (CC plus CV taper). The Li-ion safety timer (4.25 h, 3.7–5 h) only runs in CV (p.14), so it does not cut CC.
|
||||||
|
- Input side: 1.4 A × 4.0 V/(0.9 × 5.3 V) ≈ 1.17 A plus ≈ 0.35 A logic gives 1.52 A, against the RS1 limit of 2.14–2.41 A effective (A-07). The charger stops being input-limited.
|
||||||
|
- **Consequence:** At 825 Ω, v6 repeats the H0008 behaviour. U25 also sits at the RS1 limit (≈ 2.5 A continuous) whenever charging, which drives the A-06/A-07 thermal problems.
|
||||||
|
- **Fix:** R50 → **1.43 kΩ 1 % 0603, LCSC C22840** (Extended; 4965 in stock in the DB snapshot). If Leo prefers V5.6 BOM commonality, use 1.5 kΩ (C22843, Basic), but R5 is then met only nominally.
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** high for the numbers. Medium that thermal cycling is the whole H0008 story (pending the clamp test).
|
||||||
|
|
||||||
|
### A-04 U25 set-point 5.00 V (4.87–5.14 V) is incompatible with the charge governor. Set R121 = 57.6 k
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-A (U25 set-point); lesson F7; ECO §A/§C ("≥ 5.30 V"); `firmware_constants.csv` (CHG_RAIL_ON 5.05, CHG_RAIL_OFF 4.90, V5_PFI 4.60).
|
||||||
|
- **Evidence (Vout = Vref·(1 + R121/R122), Vref 0.792/0.800/0.808 V, resistors 1 %):**
|
||||||
|
|
||||||
|
| R121 / R122 | min | nom | max | vs CHG_RAIL_ON 5.05 | vs LTC4040 VIN max 5.5 |
|
||||||
|
|---|---|---|---|---|---|
|
||||||
|
| 53.6 k / 10.2 k (as-is) | **4.871** | **5.004** | 5.140 | nominal below the start line: charger never (or randomly) enabled | ok |
|
||||||
|
| 56.2 k / 10.2 k | 5.069 | 5.208 | 5.350 | low corner 0.02 V above | ok |
|
||||||
|
| **57.6 k / 10.2 k** | **5.176** | **5.318** | **5.463** | ≥ 0.13 V above | 37 mV margin |
|
||||||
|
| 57.6 k / 10.2 k, 0.1 % resistors | 5.256 | 5.318 | 5.380 | ok | 120 mV margin |
|
||||||
|
|
||||||
|
- LTC4040 PFI from v6's R51 270 k / R52 100 k at 1.19 V: **falling 4.27/4.40/4.54 V, rising 4.38/4.51/4.66 V**. The firmware constant V5_PFI 4.60 V is stale (it comes from the old 287 k).
|
||||||
|
- As-is margin U25 min → PFI rising max = 0.21 V. With 57.6 k: 0.52 V.
|
||||||
|
- The ADC measures 5V_SENSE (R7/R8 10 k/10 k) against VDDA = the 3V3 LDO (±1.5 %, and lower on battery, A-08). Firmware thresholds carry ±2–3 % error unless calibrated with VREFINT.
|
||||||
|
- With the as-is topology the modem does not load VEH5V (it runs from /24V), so the V5.5 LTE-sag argument is gone on vehicle power. It comes back if A-01 Option A is adopted.
|
||||||
|
- **Consequence:** With FW 0.6.0 thresholds, v6 as-is will not start charging on most units, so R5 fails. The margins are thin under modem bursts if the modem moves to MAIN5V.
|
||||||
|
- **Fix:** R121 → **57.6 k 1 % 0603, LCSC C23082** (Extended; 3673 in stock in the DB snapshot). Optionally specify R121/R122 at 0.1 % to take the upper corner to 5.38 V. In firmware v6 (FW 0.7.x), calibrate the ADC against VREFINT and set V5_PFI = 4.40 V.
|
||||||
|
- **Effort:** schematic-only (plus firmware constants)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### A-05 Backup mode: worst-case load reaches 93–97 % of the LTC4040 boost capability during a 2 A modem burst; W5500 always powered; U20 input weakly bypassed
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-A (backup path, budget); lessons F1/F2; ECO §A, §I-1; R1, R3; memory `drogheda-einarboard-modem-rail`, `drogheda-backup-lowpower`; modem-on-battery diagnosis.
|
||||||
|
- **Evidence:**
|
||||||
|
- **What stays alive on battery (netlist):**
|
||||||
|
- `BAT → L6 → U6 boost → /MAIN5V`. Backup VSYS = 0.8·(1 + 499k/100k): **4.60/4.79/4.99 V** (VBSTFB 0.78–0.82 V). R53 must stay at 499 k because the 5.0 V limit sits at the top corner.
|
||||||
|
- From MAIN5V: (a) **D21 → /VIN_MODEM → U20 → modem** (D21 anode is *before* P5, so the cutoff switch does not cut this path; EN is held low by R113 when the MCU is unpowered). (b) **P5 (cutoff) → /SYS5V** → D12 → U17 (3V3: MCU and all logic), **U12 (3V3_ETH, EN tied to VIN → always on)**, F1 → Q1 (PWR_CTRL) → U21 → F9P, K1 coil (BYP_CTRL).
|
||||||
|
- `/VIN_MODEM` falls to MAIN5V − Vf(D21) once 24 V is gone. There is no separate "D21/MAIN5V" rail.
|
||||||
|
- **LTC4040 boost:** 2.5 A load from battery ≥ 3.2 V; switch limit 5.5 A min (p.4, p.15). It runs only when PFI < threshold (p.13). BAT quiescent 40 µA.
|
||||||
|
- **CSYS:** C32/C33 47 µF/16 V X7R 1210 plus C34 10 µF/50 V 0805 = 104 µF nominal, which meets the 100 µF text. Effective at 4.8 V ≈ 59 µF (assumed DC-bias loss −40 % / −40 %), below the 75 µF transient guidance (p.21).
|
||||||
|
- **U20 input (A7670 needs a 2 A-capable supply, HD Table 8):** C127 10 µF/50 V 0805 + C128 1 µF only. The V5.6 ECO specified 2×22 µF + 10 µF.
|
||||||
|
- **U20 UVLO:** falling ≈ 3.1–3.3 V against VIN_MODEM ≥ 4.2 V on battery, so ≈ 1 V margin (V5.5 had 0.1 V). **The V5.5 failure mechanism is fixed**, and the residual risk is boost current limit.
|
||||||
|
- **Worst-case current budget.** Assumptions:
|
||||||
|
- Logic (3V3): 90 mA typ, 120 mA worst including 4 gauge LEDs, plus AMS1117 Iq 5 mA.
|
||||||
|
- F9P (3V3_GNSS): 100 mA cold, 85 mA steady, including LNA (u-blox ~68 mA typ).
|
||||||
|
- W5500: 132 mA at 3.3 V (100BASE-TX), through U12 at η 0.85.
|
||||||
|
- K1 coil: 30 mA (G5V-1 5 VDC, 167 Ω).
|
||||||
|
- Modem VBAT: 2.0 A GSM peak (HD Table 8). LTE TX average assumed 0.7 A (HD table is TBD). Idle 20 mA. R112 bleeder 3.8 mA.
|
||||||
|
- Efficiencies: U20 0.88, U25 0.87, boost 0.88. Battery 3.5 V.
|
||||||
|
|
||||||
|
**On 24 V (as-is topology, charging with R50 825 Ω / with 1.43 k):**
|
||||||
|
|
||||||
|
| Rail | Cold start | Steady | Modem TX burst |
|
||||||
|
|---|---|---|---|
|
||||||
|
| /3V3 (U17 out) | 0.120 A | 0.090 A | 0.090 A |
|
||||||
|
| /3V3_GNSS | 0.100 A | 0.085 A | 0.085 A |
|
||||||
|
| /3V3_ETH | 0.132 A | 0.132 A | 0.132 A |
|
||||||
|
| /VBAT_MODEM | 2.0 A pk (0.3 A avg) | 0.024 A | 2.0 A pk |
|
||||||
|
| /VIN_MODEM @ 23.5 V (from /24V) | 0.37 A pk | 0.005 A | 0.37 A pk |
|
||||||
|
| /24V (+ fan 0.2 A @ 5 V via U2) | 0.42 A | 0.05 A | 0.42 A |
|
||||||
|
| /SYS5V | 0.35 A | 0.31 A | 0.31 A |
|
||||||
|
| /VEH5V (U25 out; charger held off 120 s at boot) | 0.36 A | **2.50 A (RS1-limited) / 1.48 A** | 2.50 / 1.48 A |
|
||||||
|
| /VIN_PROT @ 24 V | 0.09 A | 0.60 / 0.38 A | 0.60 / 0.38 A |
|
||||||
|
| P1 total @ 24 V | 0.50 A | 0.65 / 0.43 A | **1.02 / 0.80 A** |
|
||||||
|
| P1 total @ 9 V (12 V vehicle low) | — | 1.73 / 1.1 A | **2.8 / 2.2 A** |
|
||||||
|
|
||||||
|
**On battery (as-is topology; VSYS 4.79 V; VIN_MODEM ≈ 4.4 V after D21):**
|
||||||
|
|
||||||
|
| Rail | Cold start (all on, modem registering) | Steady (registered, idle) | GSM TX burst | LTE TX |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| /VIN_MODEM | 1.96 A pk | 0.024 A | 1.96 A pk | 0.69 A |
|
||||||
|
| /SYS5V (logic + F9P + W5500 via U12 + K1) | 0.36 A | 0.32 A | 0.32 A | 0.32 A |
|
||||||
|
| **/MAIN5V = boost load** | **2.33 A (93 % of 2.5 A)** | 0.34 A | **2.28 A (91 %)** | 1.01 A (40 %) |
|
||||||
|
| same at the VSYS low corner 4.60 V (VIN_MODEM 4.2 V) | **2.43 A (97 %)** | 0.34 A | 2.38 A (95 %) | 1.04 A |
|
||||||
|
| Battery current (VSYS·I/(3.5 V·0.88)) | 3.62 A | 0.53 A | 3.55 A | 1.57 A |
|
||||||
|
| with fixes below + FW sequencing (W5500 off, K1 off, F9P deferred, D21 bridged) | **1.95 A (78 %)** | 0.15 A | 1.95 A | 0.85 A |
|
||||||
|
| with fixes + LTE-only on battery (peak ≈ 1 A assumed) | ≈ 1.2 A (48 %) | 0.15 A | — | 0.85 A |
|
||||||
|
|
||||||
|
- **Consequence:** As-is, a cold modem registration (or a GSM burst) with everything else on uses 93–97 % of the boost rating, with no allowance for bursts above 2.0 A or a hot, aged pack. Hitting the limit droops VSYS: U17 drops out first (A-08), then U20 → VBAT_MODEM < 3.4 V. That is the V5.5 "modem dark on battery" symptom through a different mechanism. **R1/R3 are not robust on hardware as-is. They are achievable with firmware sequencing (mandatory) plus the fixes below.** Without U12 gating, W5500 alone costs ≈ 0.5 W continuous on battery, against a 20–50 mW duty-cycle sleep target.
|
||||||
|
- **Fix:**
|
||||||
|
1. **U12 EN (pin 2)** off `/SYS5V` onto a new net `/ETH_PWR_EN` from **PD2 (pad 54, free)**, with **100 k to GND** (C25803). MP1584 EN threshold 1.5 V and abs max 6 V are compatible with 3.3 V drive. Default OFF. (E auditor: W5500 reset/strap implications.)
|
||||||
|
2. **CSYS:** add 2 × 47 µF 16 V X7R 1210 (**C5440143**) at U6 VSYS pins 1/24 (≈ 113 µF effective).
|
||||||
|
3. **U20 input:** with A-01 Option A (5 V input), add 2 × 22 µF 16 V 0805 (**C86817**) ≤ 3 mm from U20.2, GND to U20.7/EP, plus 1 × 220 µF 16 V polymer (**C881921**) at `/VIN_MODEM`. If the 24 V feed stays (Option B), use 50 V parts (e.g. 2 × 10 µF 50 V 1210 **C138687**).
|
||||||
|
4. **D21:** replace with a bridge (Option A), which removes 0.30 V and lowers U20 input current by ≈ 7 %.
|
||||||
|
5. **MAIN5V from U6 to U20:** ≥ 1.5–2 mm the whole way (today 0.3/0.5 mm necks and 60 mm; A-07).
|
||||||
|
6. **Firmware sequencing** (see firmware section): mandatory.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** medium. Datasheet limits are firm. Load currents for the modem (LTE average), F9P and fan are assumptions. Raise confidence with the ECO §I-1 bench test: MAIN5V and VIN_MODEM scope during a battery-only cold start at VBAT 3.5 V, plus a current probe on `/BAT_PLUS`.
|
||||||
|
|
||||||
|
### A-06 Switcher hot loops and exposed-pad grounding: loops close through inner planes via distant vias; no EP vias on any regulator
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-A ("input/output cap distance < 3 mm", compensation/BST); ECO §E4; Review §2 "Switcher EP vias"; datasheets TPS54360B/AP64350 layout sections.
|
||||||
|
- **Evidence:**
|
||||||
|
- Board-wide there are **69 GND vias** (8 in the SE power quadrant x > 150, y > 85). The F.Cu GND pour is split into **71 islands** (stored fill). The EP-pad zone connection defaults to *thermal* (0.5 mm spokes) except U6.25 and U2.9, which are solid.
|
||||||
|
|
||||||
|
| Reg | Cin → VIN pin (edge) | Cin GND ↔ return (diode anode / GND pin) | EP vias / nearest GND via | Other |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| **U25** TPS54360B | C150 **2.88 mm** ✅, C149 6.37 mm | C149.2/C150.2 on **island 16**, D34.2 + U25 EP on **island 3** (3006 mm², only 3 vias at (145.7, 129.9), (148.1, 135.3), (198.8, 78.1): **≥ 30 mm** from U25). The input loop closes through In1/In2 via ≥ 11 mm and ≥ 30 mm detours. | **0 / 14.4 mm**; EP thermal-relief | D34 4.28 mm from SW; **L22 17.0 mm** from SW (`/SW_PWRIN` 20.4 mm at 1 mm); BST C152 1.49 mm ✅; FB/COMP/RT 1.0–2.9 mm ✅ |
|
||||||
|
| **U20** AP64350 | C128 0.72 mm, C127 2.38 mm ✅ | C127.2/C128.2 → U20.7 **6.9/8.5 mm**; EP on a different island (3) from pin 7 (island 20) | **0 / 5.15 mm**; EP thermal-relief | L20 2.24 mm ✅; BST 1.8 mm ✅; COMP 0.7/2.2 mm ✅; FB 3.2/4.1 mm |
|
||||||
|
| **U2** MP1584 (fan) | C22/C10/C11 **17.0–20.8 mm** ❌ | C22.2 ↔ Dbk1.2 11.7 mm | **0 / 19.7 mm** | Dbk1 6.5 mm, L2 11.9 mm from SW; FB divider R20/R21 **0.67/1.48 mm** ✅ (ECO E3 fixed) |
|
||||||
|
| **U12** MP1584 (3V3_ETH) | C101 6.40 mm | C101.2 (island 41, 0 vias) ↔ D11.2 (island 40) 14.9 mm; U12.5/U12.9 on island 39 (21 mm², **0 vias**) tied by **0.2 mm** GND tracks | **0 / 6.4 mm** | D11 11.9 mm, L8 15.1 mm from SW; Cout C102/C103 28–36 mm; FB top R87 24 mm |
|
||||||
|
|
||||||
|
- **D34 (B560C) thermal:** average current (1 − D)·Io ≈ 0.78 × 2.5 = 1.95 A → ≈ 1.0 W at 24 V. The GND pad has thermal-relief spokes and the cathode sits on a 1 mm SW trace. Estimated +75–100 °C over local ambient at full load, which approaches Tj max 150 °C in a 45 °C box. It drops to ≈ 0.55 W with A-03.
|
||||||
|
- U25 IC loss ≈ 0.5–0.75 W (24–36 V) with no EP vias.
|
||||||
|
- **Consequence:** For U25, SW-node and VIN-pin ringing and conducted/radiated EMI from a non-sync buck switching 2.5 A at 24–36 V. Ringing adds on top of the 53 V TVS clamp relative to the 65 V SW/VIN abs max. Poor regulator and diode thermals. For U12, a broken hot loop next to the Ethernet magnetics. U2 loses its local input bypass (MP1584 VIN abs max 30 V). U2 disappears if A-01 fix 1 is taken.
|
||||||
|
- **Fix:**
|
||||||
|
- **U25:** place C149/C150 ≤ 2 mm from pins 2/7 with their GND on the same F.Cu copper as D34.2 and the EP. D34 ≤ 3 mm from pin 8. L22 ≤ 5 mm from pin 8, SW copper ≤ 1.5× pad area. EP: 8 vias (4 × 2, 0.3/0.6 mm) and `zone_connect` solid on pad 9. D34 GND pad solid to ≥ 150 mm² F.Cu GND with ≥ 6 vias.
|
||||||
|
- **U20:** C127/C128 GND ≤ 2 mm to pin 7/EP. EP 8 vias, solid zone connect.
|
||||||
|
- **U12:** Cin C101 ≤ 3 mm with GND next to pin 5. D11 and L8 ≤ 4 mm from pin 1. EP ≥ 6 vias. Replace the 0.2 mm GND ties with pour.
|
||||||
|
- **Stitching:** GND vias every ≤ 5 mm around each regulator and on both sides of each hot loop. (Layout auditor F owns board-wide stitching.)
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high on the geometry. Medium on the island picture because it depends on stored fills: refill, then re-run `islands.py`.
|
||||||
|
|
||||||
|
### A-07 5 V power-path bottlenecks: VEH5V and VIN_SW run the full LTC4040 input current on inner 0.5/0.8 mm tracks
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-A; DRC `track_width` (183 warnings, T15 rules); lead "netclass patterns match no net". (A separate issue: the `24V`/`IGN_IN`/`Q10_GATE` patterns resolve nothing. Layout auditor owns clearance.)
|
||||||
|
- **Evidence (widest path, `path.py`):**
|
||||||
|
|
||||||
|
| Path | Bottleneck | Length / R | Current | IPC-2221 ΔT | Action |
|
||||||
|
|---|---|---|---|---|---|
|
||||||
|
| `/VEH5V` L22.2 → RS1.1 | **In1 0.5 mm × 13.6 mm** | 24.8 mm / 18.9 mΩ | 2.5 A (charging, as-is) / 1.5 A | **+168 °C / +52 °C** (internal; IPC-2152 ≈ half) | ❌ widen |
|
||||||
|
| `/VIN_SW` RS1.2 → Q7.1–3 | **In2 0.8 mm × 23.6 mm** | 26.0 mm / 15.9 mΩ | 2.5 A | +77 °C internal | ❌ |
|
||||||
|
| `/MAIN5V` Q7 → U6.24 / C32 | F.Cu 0.5 mm × 13.3 / 6.6 mm | 23 / 15 mΩ | 2.2 A (charger in) / 2.4 A (backup) | +26 / +32 °C | ❌ |
|
||||||
|
| `/MAIN5V` U6.1 → C32 | **0.30 mm** neck 1.5 mm | 12 mΩ | 2.4 A | +73 °C (short neck) | ❌ (A-02) |
|
||||||
|
| `/MAIN5V` Q7 → D21 (modem, battery) | 1.0 mm (In2 6.8 mm) | 40 mm / 20 mΩ | 2.0 A | +12 °C | ⚠ widen to ≥ 1.5 mm |
|
||||||
|
| `/VIN_MODEM` D21 → U20.2 | 0.5 mm × 5.8 mm | 5.7 mΩ | 2.0 A | short | ⚠ ≥ 1 mm |
|
||||||
|
| `/BAT_PLUS` P3 → L6 | 1.0 mm × 21.3 mm | 10.4 mΩ | 3.6 A backup peak / 2.42 A | +25 / +10 °C | (A-02) |
|
||||||
|
| `/VIN_PROT` Q23 → U25.2 | 0.5 mm × 9.8 mm | 13.5 mΩ | 0.6 A @ 24 V, 1.7 A @ 9 V | +14 °C @ 9 V | ok for 24 V |
|
||||||
|
| `/24V_IN` P1 → Q10 | In1 1.5 mm | 12.4 mΩ | ≤ 1.0 A (24 V) | small | ok |
|
||||||
|
| `/SW_BAT` | see A-02 | | | | |
|
||||||
|
| `/3V3_ETH`, `/SW_5V`, `/SW_IN`, `/SYS5V`, `/5V_FAN`, `/FAN_RET`, `/SW_FAN` | 0.25–0.5 mm (DRC-flagged) | | ≤ 0.4 A | < 5 °C | ok (DRC hygiene only) |
|
||||||
|
|
||||||
|
- **RS1 Kelvin:** the CLN sense (U6.7) taps at the via (183.91, 104.21), **1.66 mm down the 0.8 mm trace** from the RS1.2 pad (+1.0 mΩ in the sense loop). The effective input limit is 25 mV/11 mΩ = 2.27 A typ (**2.14–2.41 A**) instead of 2.35–2.65 A. That is harmless (more conservative) but unintended.
|
||||||
|
- **Consequence:** Hot inner copper under U6/Q7 at charge current, extra drop, and the 2.5 A input path sharing heat with the U6 area.
|
||||||
|
- **Fix:** Put `/VEH5V` from L22.2 to RS1.1 on F.Cu ≥ 2 mm (or a pour) and move L22/C153/C154 toward RS1, or use ≥ 2 mm inner with ≥ 4 vias per transition. Put `/VIN_SW` on F.Cu ≥ 2 mm and move Q7 within 5 mm of RS1/U6. For `/MAIN5V`, see A-02, and run ≥ 1.5 mm to D21/U20. Route the U6.7 CLN and U6.6 VIN sense traces from the inner edges of the RS1 pads (Kelvin). Fix the netclass patterns (prefix `/`) so the T15 widths become rules instead of warnings.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### A-08 U17 AMS1117-3.3 drops out on battery and sets a 25–55 mW sleep floor
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-A ("dropout for the LDOs at the backup voltage"); memory `drogheda-backup-lowpower` (AMS1117 = #1 sleep-floor suspect); R1.
|
||||||
|
- **Evidence:**
|
||||||
|
- `LDO_IN = SYS5V − Vf(D12 SS34 ≈ 0.30–0.35 V at 0.1 A)`. On battery SYS5V ≈ VSYS 4.60–4.99 V minus ≈ 0.02 V, so **LDO_IN ≈ 4.25–4.65 V**.
|
||||||
|
- AMS1117 dropout: 1.1 V typ / 1.3 V max at 0.8 A, ≈ 1.0 V at 0.1 A, so it needs ≈ 4.3–4.4 V. At the low boost corner, and during every boost-limited dip (A-05), 3V3 sags by ≈ 50–150 mV.
|
||||||
|
- VDDA = 3V3 via R104 10 Ω. The firmware assumes ADC_REF = 3.3 V, so BAT_SENSE/5V_SENSE read up to +4 % high. The 3.40 V low-battery cut then trips at ≈ 3.27 V real. The NTC channels (R42/R126 from 3V3) are ratiometric and unaffected.
|
||||||
|
- Ground current is **5 mA typ / 11 mA max** (25–55 mW at 5 V).
|
||||||
|
- The datasheet asks for a 22 µF tantalum output cap. The /3V3 rail is all ceramic (C118 22 µF 0805 plus many 100 nF), which is a stability question for genuine AMS1117 parts.
|
||||||
|
- **Consequence:** Degraded 3V3 exactly when running on battery, wrong battery-voltage telemetry, and a duty-cycle sleep floor already as large as the whole 20–50 mW target.
|
||||||
|
- **Fix:** U17 → **TI TLV1117LV33DCYR, LCSC C15578** (SOT-223, same 1-GND/2-OUT/3-IN pinout and footprint; 1 A; dropout 455 mV at 1 A, ≈ 0.1 V at 0.15 A; IQ ≈ 100 µA; ceramic-stable; VIN max 5.5 V vs LDO_IN max ≈ 5.3 V with A-04). **Do not use** C48937499: it is listed under the same MPN but its spec (1.2 V dropout, 12 V) is the wrong die. Firmware: VREFINT calibration anyway.
|
||||||
|
- **Effort:** schematic-only (value/LCSC; same footprint)
|
||||||
|
- **Confidence:** high (AMS1117 numbers). Medium for TLV1117LV at 0.1–0.15 A: check the TI dropout curve during sourcing.
|
||||||
|
|
||||||
|
### A-09 Aluminium electrolytics: 85 °C/2000 h parts on the 5 V and modem rails (≈ 1-year life in a port box); modem bulk also over its ripple rating
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-A (Cout type/ESR); ECO §A (220 µF polymer); cross-ref modem auditor (C130/C131).
|
||||||
|
- **Evidence:**
|
||||||
|
- C78 (VEH5V bulk), **C130, C131** (VBAT_MODEM bulk) = C2827940 SamYoung MVG 16 V 220 µF, **−40…+85 °C, 2000 h @ 85 °C, 130 mA @ 120 Hz ripple**.
|
||||||
|
- C10 (/24V) = C165527 MVK 50 V 47 µF, **105 °C/1000 h**.
|
||||||
|
- C3 = C88734 and C103 = C88744: Rubycon TZV, 105 °C/2000 h.
|
||||||
|
- C151 = C116241: Nichicon UUD, 105 °C/5000 h ✅.
|
||||||
|
- 10 °C-rule life at 65 °C local (45 °C ambient plus enclosure/board rise, assumption): MVG ≈ 8,000 h (**0.9 y** of 24/7). MVK ≈ 16,000 h. TZV ≈ 32,000 h. UUD ≈ 80,000 h.
|
||||||
|
- C130/C131 take the modem's GSM/LTE burst edges (2 A, 577 µs, 217 Hz). Ripple current exceeds the 130 mA rating, so self-heating shortens life further.
|
||||||
|
- **Consequence:** Bulk capacitance and ESR drift within the first year. That affects the U20 loop (A-17), modem brown-out margin (HD: ≥ 300 µF) and U25 transient response.
|
||||||
|
- **Fix:** C78, C130, C131 → **Lelon OVZ221M1CTR-0608 220 µF 16 V polymer, C881921** (same 6.3 × 7.7 can; 105 °C/2000 h, polymer ≈ ×10 per −20 °C, so > 100,000 h at 65 °C). C10 is removed by A-01; otherwise use a 105 °C ≥ 5000 h part. After the swap, re-check U20 compensation (A-17), because polymer ESR moves the ESR zero from ≈ 2.4 kHz to > 15 kHz.
|
||||||
|
- **Effort:** schematic-only (same footprints)
|
||||||
|
- **Confidence:** medium (lifetime model plus assumed local temperature). High on the part ratings.
|
||||||
|
|
||||||
|
### F-51 No charger-die or cell temperature reaches the MCU; the firmware thermal inhibit has no source on v6 (R4)
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-F (temperature sensors), §4-A (sensor ≤ 10 mm of U6); ECO §D2/§D3/§D5; lesson F5/F6; firmware `CHG_CELL_HOT_C 45 / CHG_CELL_COOL_C 40` ("TMP102 on the cell"); memory `drogheda-fan-policy` (thermalCtlTemp ignores the NTC), `drogheda-battery-hightemp`.
|
||||||
|
- **Evidence — every temperature source on v6:**
|
||||||
|
|
||||||
|
| Sensor | Ref / net | Position (mm) | MCU pin / ADC | Distance to U6 (187.0, 107.7) | Notes |
|
||||||
|
|---|---|---|---|---|---|
|
||||||
|
| Board air + RH | U3 SHT40-AD1B (I²C 0x44) | (122.4, 77.3) | PB6/PB7 I²C1 | **71.4 mm** | 52 mm from U19, 28.8 mm from U20 |
|
||||||
|
| MCU die | U16 internal | (120.7, 67.4) | ADC1_IN16 (TS_CAL1/2 used) | 77 mm | |
|
||||||
|
| External probe 1 | P7 NTC-HOTSPOT → `/NTC_TEMP`, R42 10 k to 3V3, C24 100 nF | (109.75, 44.0) | **PB1 = ADC1_IN9** | ~100 mm | jack only |
|
||||||
|
| External probe 2 | P8 NTC-PROBE-2 → `/NTC2`, R126 10 k to 3V3, C157 | (133.0, 44.0) | **PC4 = ADC1_IN14** | ~83 mm | jack only |
|
||||||
|
| Pack NTC | P3.3 → `/NTC` → **U6.17 only** (R55 10 k from VEH5V) | (196.0, 110.5) | **none** | — | LTC4040 window: hot pause **42.4 °C**, resume 40.1 °C, cold −3.1 °C (B3380); 39.7/37.9/0.6 °C (B3950) |
|
||||||
|
| Modem die | A7670SA internal (AT) | (174.3, 72.0) | USART6 (AT) | — | firmware-only (F-53) |
|
||||||
|
| Accelerometer | U26 SC7A20 (has a temperature output, low accuracy) | — | I²C | — | not a thermal sensor |
|
||||||
|
| TMP102 | **absent** (V5.x U4 and the V5.6 U18 TMP102 were deleted in v6 T10) | — | — | — | |
|
||||||
|
|
||||||
|
- Free MCU ADC pin: only **PC5 (pad 25, ADC1_IN15)**. Free digital pins: PB10, PA9, PD2.
|
||||||
|
- **Consequence:** CHG_CELL_HOT/COOL (45/40 °C) have no cell sensor unless an installer tapes P7 to the pack. There is no charger-die visibility, so the A-02/H0008 cycling is invisible in telemetry. R4 is not met in firmware. (The cell is still protected in hardware by the LTC4040 NTC pause.)
|
||||||
|
- **Fix:**
|
||||||
|
1. **Charger temperature:** TMP102AIDRLR **C99269** (SOT-563) placed between U6 and L6, ≤ 5 mm from the U6 EP, on I²C1 at **0x48** (ADD0 → GND; confirm the U10 SC16IS752 strap stays at 0x4D), with 100 nF C14663.
|
||||||
|
2. **Cell temperature to the MCU:** tap `/NTC` into **PC5** through 100 k (top, C25803) / 120 k (bottom) + 10 nF. PC5 ≤ 0.545·5.46 V = 2.98 V. The 220 k load shifts the LTC4040 hot threshold by < 0.6 °C. Firmware computes Rntc = R55·Vntc/(VEH5V − Vntc), using PA4 for VEH5V; it is valid whenever VEH5V is present, which is when charging is possible.
|
||||||
|
3. Firmware: `tchg`, `tcell` appended to `$PHLG`. The governor inhibits on tcell (Li-ion 45 °C / LFP 55–60 °C) and on tchg (e.g. > 85 °C shed).
|
||||||
|
- **Effort:** both (2 parts plus 3 passives; place the TMP102 in the A-02 re-cluster)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### A-10 No over-voltage protection on VEH5V now that the 5 V source is a non-isolated on-board buck
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-A (input protection); LTC4040 p.11 (OVSNS); memory `drogheda-power-cost` ("galvanic isolation lost").
|
||||||
|
- **Evidence:**
|
||||||
|
- U6.16 OVSNS is tied straight to `/VEH5V`, so the OVP feature is not used (datasheet: short OVSNS to VIN when OVP is not used).
|
||||||
|
- A TPS54360B high-side short puts `/VIN_PROT` (24–36 V) on VEH5V. LTC4040 VIN abs max is 6 V steady / 7 V transient, and Q7 then passes it to MAIN5V → SYS5V → U17/U21/U12/U20.
|
||||||
|
- V5 used the isolated SD-15B, so v6 adds this failure mode.
|
||||||
|
- **Consequence:** A low-probability single-point failure destroys the whole board (F9P $85, modem, MCU).
|
||||||
|
- **Fix (pick one):** (a) use the LTC4040 OVP arrangement per the datasheet OVP application: OVSNS through 6.2 kΩ from the U25 output node, plus the series N-FET (≥ 40 V V_DS) the application shows. Verify the topology against the datasheet figure before committing. (b) Minimum: a 1.5 kW 5 V TVS (SMCJ5.0A class) on VEH5V as a crowbar that forces F2 open. This is imperfect, because VEH5V can exceed 7 V for the fuse's melt time.
|
||||||
|
- **Effort:** schematic + small layout
|
||||||
|
- **Confidence:** medium (topology of the datasheet OVP figure not fully extracted)
|
||||||
|
|
||||||
|
### A-11 CHGOFF (PA8) has a pull-DOWN: the charger runs at full programmed current whenever the MCU is not driving the pin
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-A (EN default states); LTC4040 p.10 ("CHGOFF: GND = enable, > 1.2 V = disable"); firmware line 356 ("HIGH = charge OFF").
|
||||||
|
- **Evidence:** R56 100 k from `/CHRG_EN` to GND. During MCU reset, DFU, boot and unflashed boards, CHGOFF = 0, so the charger is enabled with no governor or thermal inhibit (2.42 A with R50 as-is). This contradicts the board's own policy that MODEM_EN (R113) and PWR_CTRL default OFF while the MCU is not in control.
|
||||||
|
- **Consequence:** An uncontrolled charge during DFU or boot loops. It is bounded by the LTC4040 input limit and NTC window, so there is no damage.
|
||||||
|
- **Fix:** R56 → 100 k from `/CHRG_EN` to **/3V3** (C25803, same footprint re-netted), so the default is charge OFF. On battery the charger is inactive anyway.
|
||||||
|
- **Effort:** schematic + one-track layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### A-12 Q5 base floats during MCU reset: the F9P rail (Q1/U21) is not guaranteed OFF
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-A (EN defaults); firmware "PWR_CTRL LOW = stack OFF".
|
||||||
|
- **Evidence:** `/BASE_LS` = {R1.2, Q5.1} only; `/PWR_CTRL` = {U16.15, R1.1}. The STM32 pins are floating inputs during reset. Datasheet-max pin leakage (1 µA) × hFE ≈ 100–300 µA into R2 10 k gives 1–3 V Vgs on the AO3401A, so partial turn-on is possible (typical leakage is nA, so it is benign in practice).
|
||||||
|
- **Fix:** add 47 k 0603 from `/BASE_LS` to GND (Basic 0603 1 %).
|
||||||
|
- **Effort:** schematic + small layout
|
||||||
|
- **Confidence:** medium
|
||||||
|
|
||||||
|
### A-13 PFO goes only to TP2 (and CLPROG only to TP1): no hardware power-fail interrupt to the MCU
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-A (CHRG/FAULT/PFO); LTC4040 p.11.
|
||||||
|
- **Evidence:** `/PFO_TP` = {U6.20, TP2}. Firmware detects backup by polling 5V_SENSE (V5_OFF 3.80 V), but the LTC4040 has already switched to backup at PFI 4.40 V. `/CLPROG_TP` = {U6.3, TP1}: this is the VSYS current monitor, V = 32·(VIN − CLN), i.e. 0.8 V at the 2.5 A limit.
|
||||||
|
- **Consequence:** Tens of ms late on backup entry, and the firmware cannot shed the modem/K1/W5500 before the boost takes the full load. Input current is not measurable in telemetry.
|
||||||
|
- **Fix:** route `/PFO` to **PB10 (pad 29, EXTI10)** with 100 k to /3V3 (3V3 stays up on battery). Optional: CLPROG → an ADC pin through 1 MΩ (datasheet recommends isolation, PROG-side ≤ 40 pF). No ADC pin is left if F-51 takes PC5, so CLPROG is a Note.
|
||||||
|
- **Effort:** schematic + layout (two tracks)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### A-14 BSTFB divider 21–24 mm from U6 (feedback net 41 mm, 5 vias, cutting In1 under U6); IGATE 43 mm unguarded
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-A (BSTFB); LTC4040 layout p.22–23 (guard IGATE with VSYS copper).
|
||||||
|
- **Evidence:** R53.2 → U6.18 **21.4 mm** edge, R54.1 **24.0 mm**. `/VFB_BST` is F.Cu 16.8 mm + In1 24.4 mm with 5 vias; 7 of its In1 segments lie inside a 6 mm radius of U6, splitting In1. `/IGATE` is F.Cu 6.0 mm + In1 37.0 mm, with Q7.4 ↔ U6.15 at 23.2 mm. The IGATE charge pump has µA-class drive, so leakage in a humid port box can partially enhance Q7. Its body diode at 2.5 A dissipates ≈ 1.2 W.
|
||||||
|
- **Fix:** R53/R54 ≤ 3 mm from pins 18/10, with the top leg Kelvin-tapped at the CSYS pads and the net on F.Cu. Q7 ≤ 5 mm from U6.15 with IGATE ≤ 8 mm on F.Cu, flanked by MAIN5V copper.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high (geometry). Medium (consequence).
|
||||||
|
|
||||||
|
### A-15 U25 footprint carries a second property `LCSC Part` = C2071691 (AP64350, pin-compatible)
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-H cross-ref; `sch_pcb_sync.md`; INDEX gotcha 7.
|
||||||
|
- **Evidence:** U25 `LCSC` = C524806 (TPS54360B), `LCSC Part` = C2071691. The TPS54360B pinout (1 BOOT, 2 VIN, 3 EN, 4 RT/CLK, 5 FB, 6 COMP, 7 GND, 8 SW) is **identical** to the AP64350 pinout. If a BOM tool picks `LCSC Part`, the boards assemble and run, but with a **42 V-rated** part behind a 53 V clamp and the wrong compensation. That is a latent field failure nobody would notice at test.
|
||||||
|
- **Fix:** delete the `LCSC Part` property from U25 (PCB and schematic).
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-52 Modem temperature: no on-board sensor near U19 (ECO D3 dropped)
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-F; ECO §D3 (TMP102 #2 at the modem); R4.
|
||||||
|
- **Evidence:** The nearest board sensor to U19 is U3 at 52.1 mm. The only modem temperature path is AT over USART6. SIMCom A76xx has `AT+CPMUTEMP`; availability on A7670SA firmware is not verified. That path also works only while the modem is powered and responsive.
|
||||||
|
- **Fix:** either firmware-only (poll `AT+CPMUTEMP` into a `$PHLG` `tmodem` field) or a second TMP102 C99269 at **0x49** (ADD0 → 3V3) between U19 and U20. The latter is cheap and independent of modem state.
|
||||||
|
- **Effort:** firmware-only, or schematic + layout
|
||||||
|
- **Confidence:** medium
|
||||||
|
|
||||||
|
### A-16 U25 EN/UVLO divider DNP: U25 runs from 4.1–4.3 V
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:** R124 523 k / R125 84.5 k DNP. EN floats (1.2 µA pull-up), so the internal UVLO is 4.1–4.3 V rising with 325 mV hysteresis. Populating them gives a start of ≈ 8.0 V and a stop of ≈ 5.5 V (TI equations with Ip 1.2 µA, Ih 3.4 µA). Between ≈ 4.3 V and 5.8 V input, VEH5V sits in dropout inside the PFI band (4.27–4.66 V), so the LTC4040 toggles backup (hysteresis 0.11 V). This only matters for 12 V vehicles under crank.
|
||||||
|
- **Fix (optional):** populate R124 523 k/1 % and R125 84.5 k/1 % (Basic 0603, pick LCSC in sourcing) if 12 V machines are in scope.
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** medium
|
||||||
|
|
||||||
|
### A-17 U20 compensation is the AP64350 5 V table set (14 k / 3.3 nF / 47 pF, 500 kHz) applied at 3.8 V
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Block / refs:** §4-A; V5.6 change report §6.1; Review §4 #14.
|
||||||
|
- **Evidence:**
|
||||||
|
- Output network: L20 4.7 µH, C132 22 µF/16 V 0805 (≈ 10–12 µF effective at 3.8 V), C133 1 µF, plus C130/C131 2 × 220 µF aluminium at 13–21 mm (ESR ≈ 0.15 Ω pair, assumed).
|
||||||
|
- Datasheet: fc = R5/(4.67e3·VOUT·COUT).
|
||||||
|
- Bulk-dominated (455 µF): fc ≈ 1.7 kHz. Phase is about −90° (integrator) −84° (fp ≈ 184 Hz) +27° (zero at 3.44 kHz) +36° (electrolytic ESR zero ≈ 2.4 kHz), so **PM ≈ 69°**.
|
||||||
|
- Ceramic-only: fc ≈ 50 kHz ≈ fSW/10 (the guideline edge).
|
||||||
|
- With polymer bulk (A-09) the ESR zero moves above 15 kHz and PM falls to ≈ 40°.
|
||||||
|
- **Fix:** if A-09 goes ahead, set R116 = 10 k (keep C141 3.3 nF, C142 47 pF) and verify with a 0.1 → 2 A load step at VIN 4.4 V and 5.3 V. Otherwise bench-verify the current values.
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** low-medium (estimate). Raise it with a Bode plot or load step.
|
||||||
|
|
||||||
|
### A-18 U25 compensation is the TPS54360B datasheet example (13 k / 6.8 nF / 39 pF), designed for 8.2 µH + 58 µF
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:**
|
||||||
|
- v6 has 10 µH, C153/C154 2 × 47 µF X7R (≈ 56 µF effective), C78 220 µF aluminium, and ≈ 70 µF effective downstream (C30/C31, C32–C34 through RS1 + Q7, ≈ 20 mΩ).
|
||||||
|
- fco = R4·gmps·Vref·gmea/(2π·Cout·Vout) ≈ 43.7/(2π·Cout·5.3): ≈ 4–6 kHz with the bulk counted, ≈ 22 kHz ceramic-only. The compensation zero is at 1.8 kHz, and PM estimates > 60° in both cases.
|
||||||
|
- Stable, but a slower load step: ≈ 0.16 V dip for 1.8 A, relevant if A-01 Option A moves the modem onto VEH5V.
|
||||||
|
- **Fix:** none required. Optionally raise R123 to 24 k after A-01/A-09 to restore ≈ 10 kHz. Bench-verify with a 0.3 → 2.5 A step.
|
||||||
|
- **Effort:** schematic-only (optional)
|
||||||
|
- **Confidence:** medium
|
||||||
|
|
||||||
|
### A-19 Load-dump survivability of D10 SMBJ33A / D32 SMCJ33A depends on vehicle-level suppression
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:**
|
||||||
|
- SMCJ33A: VBR 36.7 V min, VC 53.3 V @ 28.1 A. SMBJ33A: VC 53.3 V @ 11.3 A.
|
||||||
|
- Adequate for continuous 24 V systems (≤ 32 V), for the ISO 16750-2 36 V/60 min overvoltage test (below VBR min), and for ISO 7637-2 fast pulses behind the U25 65 V rating.
|
||||||
|
- Not adequate for an ISO 16750-2 Test B suppressed load dump (24 V: Us* ≤ 58 V, 100–350 ms, Ri 1–8 Ω, i.e. ≈ 10 A for 350 ms, hundreds of J): the TVS would fail short. After A-01, F2 then opens. The alternative is a surge stopper, which is out of scope.
|
||||||
|
- **Fix:** confirm the fleet has alternator load-dump suppression (Inputs needed). Keep SMCJ33A. Do not raise the TVS voltage, because U25 has 65 V abs max.
|
||||||
|
- **Effort:** none / decision
|
||||||
|
- **Confidence:** medium
|
||||||
|
|
||||||
|
### A-20 Other power items
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence / fix:**
|
||||||
|
- (a) **U12 MP1584EN** (C15051, $2.21 @100, TA −20…+85 °C): if not replaced, gate EN (A-05). Optional swap to AP64350 C2071691 ($0.58, VIN 3.8 V min, synchronous, better battery margin; needs a re-layout for pinout).
|
||||||
|
- (b) **F1 PPTC 3 A** (C20627123, 10–60 mΩ, trip 5 A) now protects only the F9P LDO branch (≈ 0.1 A). It is harmless (≤ 6 mV) and not protective. The V5.6 "≥ 4 A low-R" requirement was for the modem, which is no longer behind it. Keep it.
|
||||||
|
- (c) **P2 bench jack** has no reverse protection (VEH5V −0.3 V abs max). A bench-only risk, which the silkscreen should state.
|
||||||
|
- (d) **JP_CUT across P5 (V5.6 JP6) is absent.** Harness auditor G owns it.
|
||||||
|
- (e) **C22 value mismatch:** the schematic says "22uF/50V" but LCSC C138687 is 10 µF/50 V (moot if U2 is removed; BOM auditor H).
|
||||||
|
- (f) **K1 G5V-1:** operating range −40…+70 °C, which is close to the enclosure worst case.
|
||||||
|
- (g) **R112 1 k VBAT_MODEM bleeder:** 3.8 mA / 14 mW while the modem is on. Fine.
|
||||||
|
- **Effort:** —
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-53 Fan block
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:**
|
||||||
|
- Driver: U2 MP1584 from /24V, 5V_FAN = 0.8·(1 + 100/19.1) = **4.99 V** (4.76–5.23 V).
|
||||||
|
- FB divider R20/R21 at **0.67/1.48 mm** from U2.4 and `/FB_FAN` 4.1 mm, so ECO E3 is fixed.
|
||||||
|
- PWM: PA6 (TIM3_CH1) → Rg1 100 Ω → Q2 AO3400A low side, with Rgs1 100 k gate pull-down (**default OFF** ✅) and D2 SS34 flyback ✅.
|
||||||
|
- 2-wire fan, no tach (`ENABLE_FAN_TACH 0`, a decision). Fan dark on battery by design (ECO D4).
|
||||||
|
- U2 is out-of-rating on the 24 V bus (A-01) and its Cin is 17–21 mm away (A-06).
|
||||||
|
- **Fix:** take A-01 fix 1 (fan from VEH5V via a bridged JP1, U2 block DNP). Firmware policy `vehiclePower && ignitionOn` is unchanged, and the fan supply then equals `vehiclePower` exactly. Add `tNtcC` to `thermalCtlTemp()` (memory `drogheda-fan-policy`).
|
||||||
|
- **Effort:** schematic-only (with A-01)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
## Pass checks
|
||||||
|
| Check | Evidence (one line) | Result |
|
||||||
|
|---|---|---|
|
||||||
|
| U25 output formula / tolerance | 0.8·(1 + 53.6/10.2) = 5.004 V; Vref 0.792–0.808 → 4.87–5.14 V | ✅ math / ❌ set-point (A-04) |
|
||||||
|
| U25 RT / fsw / min on-time | 162 k → 600 kHz (TI eq.); tON at 36 V = 0.147/600 k = 244 ns ≥ 135 ns | ✅ |
|
||||||
|
| U25 inductor | 10 µH ≥ Lmin 7.2 µH (36 V) / 7.7 µH (60 V), KIND 0.3; SRP1265A Isat 15.5 A, Irms 10 A vs peak 3.1–3.4 A | ✅ |
|
||||||
|
| U25 current capability | load ≤ RS1 limit 2.14–2.41 A (+0.3 A fan with A-01) vs 3.5 A rating, 4.5 A min switch limit | ✅ |
|
||||||
|
| U25 Cout / ripple | 2 × 47 µF X7R 1210 (≈ 56 µF eff) + 220 µF; ΔI 0.69 A @ 24 V, ΔV ≈ 3 mV | ✅ (life ❌ A-09) |
|
||||||
|
| U25 compensation | datasheet example; fco ≈ 4–6 kHz, PM > 60° (estimate) | ✅ (A-18 Note) |
|
||||||
|
| U25 BOOT cap | C152 100 nF, 1.49 mm edge to pins 1/8 | ✅ |
|
||||||
|
| U25 Cin value | 2 × 2.2 µF/100 V X7R 1210 ≈ 3.4–3.8 µF eff at 24–36 V ≥ TI 3 µF | ✅ (placement A-06) |
|
||||||
|
| U25 soft start / inrush | 1024/600 kHz = 1.7 ms; ≈ 0.9 A into ≈ 280 µF | ✅ |
|
||||||
|
| U25 EN / UVLO | EN floats → on; internal UVLO 4.1–4.3 V | ✅ (A-16 Note) |
|
||||||
|
| Reverse polarity Q23 (and Q10) | P-FET D→input, S→load, gate R119 100 k + D33 15 V clamp (Rrp1 10 k + DzG1); IRFR5305 −55 V/65 mΩ | ✅ |
|
||||||
|
| DzG1 netlisted (V5 corruption) | DzG1.1 /Q10_GATE, .3 /24V | ✅ |
|
||||||
|
| TVS standoff | D32 SMCJ33A / D10 SMBJ33A VRWM 33 V ≥ 32 V max 24 V system; polarity pad 1 = K on the + rail | ✅ (A-19) |
|
||||||
|
| F2 part assigned | C206910 0154002.DR 2 A/125 V, 50 A breaking | ✅ part / ❌ coverage (A-01) |
|
||||||
|
| RS1 input limit | 10 mΩ 1 W 1206 (C105362): 23.5–26.5 mV → 2.35–2.65 A (2.14–2.41 A with the CLN tap, A-07) < U25 3.5 A | ✅ |
|
||||||
|
| LTC4040 PROG node | R50 1.26 mm from pin 2; `/PROG` 2.6 mm (≤ 40 pF) | ✅ |
|
||||||
|
| LTC4040 BSTFB (backup VSYS) | 499 k/100 k → 4.60/4.79/4.99 V within 3.5–5.0 V; keep 499 k | ✅ (placement A-14) |
|
||||||
|
| LTC4040 PFI | 270 k/100 k, 1.19 V: fall 4.27/4.40/4.54, rise 4.38/4.51/4.66 V | ✅ (FW V5_PFI stale) |
|
||||||
|
| LTC4040 RSTFB / RST | RSTFB tied to BSTFB (datasheet allows), RST NC | ✅ |
|
||||||
|
| LTC4040 OVSNS | tied to VIN → OVP unused | ⚠ (A-10) |
|
||||||
|
| NTC window RNTB | R55 10 k: hot 42.4 °C / resume 40.1 °C / cold −3.1 °C (B3380) | ⚠ (chemistry D1 pending) |
|
||||||
|
| Chemistry straps | JP2 1-2 (F2 = MAIN5V = Li-ion), JP3 F1 = 0, JP4 F0 = 1 → 4.00 V; LFP by JP2 2-3 (+ RNTB 5.6 k → +10.0…+60.4 °C) | ✅ |
|
||||||
|
| Safety timer | Li-ion 4.25 h (3.7–5 h), counts in CV only | ✅ |
|
||||||
|
| CHRG / FAULT | R57/R58 100 k to 3V3 → PB3/PB4 | ✅ |
|
||||||
|
| CHGOFF default | R56 100 k pull-down → charger ON without MCU | ⚠ (A-11) |
|
||||||
|
| BSTOFF | tied to GND → boost always armed (no FW shutdown; BAT UVLO 2.45 V is the only floor) | ✅ / Note |
|
||||||
|
| Q7 ideal-diode orientation | AO4406A N-ch: S = VIN_SW (CLN), D = MAIN5V → body diode blocks VSYS→VIN | ✅ |
|
||||||
|
| L6 | 2.2 µH (datasheet 1–2.2 µH), rated 8 A ≥ ILIMBST max 7.5 A | ✅ (placement ❌ A-02) |
|
||||||
|
| CSYS | 104 µF nominal ≥ 100 µF; ≈ 59 µF effective | ⚠ (A-05) |
|
||||||
|
| CBAT | C35 22 µF ≥ 10 µF | ✅ value / ⚠ placement |
|
||||||
|
| U20 FB | 75 k/20 k → 3.70/3.80/3.90 V within A7670 3.4–4.2 V | ✅ |
|
||||||
|
| U20 RT / min on-time | 200 k → 500 kHz (450–550); tON at 36 V = 211 ns ≥ 100 ns | ✅ |
|
||||||
|
| U20 UVLO on battery | falling ≈ 3.1–3.3 V vs VIN_MODEM ≥ 4.2 V (≈ 1 V margin; V5.5 had 0.1 V) | ✅ |
|
||||||
|
| U20 EN default | R113 100 k vs 5.5 µA pull-up → 0.55 V < 1.03 V → OFF; PC10 3.3 V > 1.25 V | ✅ |
|
||||||
|
| U20 BST | C129 100 nF, 1.8 mm | ✅ |
|
||||||
|
| L20 | 4.7 µH (MWSA0804S-4R7), rated 5 A vs peak 2.2 A (batt) / 2.7 A (24 V) | ✅ |
|
||||||
|
| U2 FB / placement | 4.99 V; divider at pin (0.67/1.48 mm) | ✅ (rating ❌ A-01, Cin ❌ A-06) |
|
||||||
|
| U12 FB | 100 k/31.6 k → 3.18/3.33/3.48 V | ✅ (EN ❌ A-05, loop ❌ A-06) |
|
||||||
|
| U21 AP2112K | dropout 250 mV @ 600 mA; F9P ≈ 0.1 A; SW_5V ≥ 4.5 V on battery; EN = VIN follows Q1 | ✅ |
|
||||||
|
| U17 AMS1117 on 24 V | LDO_IN ≈ 4.6 V ≥ 4.4 V | ✅ (battery ❌ A-08) |
|
||||||
|
| DFU-only power | DFU_VBUS → D13 → LDO_IN; D12 blocks back-feed into SYS5V | ✅ |
|
||||||
|
| K1 flyback | D6 1N4148W across the coil | ✅ |
|
||||||
|
| Temperature sensor ≤ 10 mm of U6 | none (U3 at 71.4 mm) | ❌ (F-51) |
|
||||||
|
| Fan PWM default | Rgs1 100 k → Q2 OFF at reset | ✅ |
|
||||||
|
|
||||||
|
## Review-vs-Lessons §4 checklist items re-verified
|
||||||
|
- **#1 LTC4040 copper + thermal vias + re-cluster (F5):** still ❌. `/SW_BAT` is now 0.5 mm (was 0.25 mm on 25-Sep) × 11.9 mm with 0.25/0.30 mm necks. `/BAT_PLUS` main path 1.0 mm. EP 0 vias (nearest 5.21 mm). L6 8.65–9.10 mm edge. C30/C31 6.2–7.2 mm. CSYS GND on three F.Cu islands. → A-02.
|
||||||
|
- **#2 U25 set-point (F7):** still ❌. R121 53.6 k → 5.00 V (4.87–5.14 V). Re-cluster status: C150 2.88 mm (improved), C149 6.37 mm, D34 4.28 mm, L22 17.0 mm (edge), Cin/diode GND on different islands. → A-04, A-06.
|
||||||
|
- **#3 R50 (F4):** still ❌ 825 Ω. Also, 1.5 k only meets R5 nominally; 1.43 k is recommended. → A-03.
|
||||||
|
- **#4 Modem rail integrity on battery (power parts):** U20 Cin is still C127 10 µF + C128 1 µF (no 2 × 22 µF) ⚠. `/VIN_MODEM` 0.5/0.8 mm (D21 → U20 5.8 mm at 0.5 mm) ⚠. VBAT_MODEM bulk C130/C131 at 13.2/20.9 mm from L20 on 2 mm copper (improved from 0.25/0.5 mm; modem auditor owns U19-side distances). D21 drop and boost budget → A-05. Topology → A-01.
|
||||||
|
- **#5 Temperature sensor at the charger:** still ❌. → F-51.
|
||||||
|
- **#6 W5500 in reset / U12 EN:** U12 EN still tied to VIN (always on, including on battery) ❌. → A-05 fix 1. (ETH_RST pull-down belongs to E.)
|
||||||
|
- **#8 NTC window / chemistry:** unchanged ⚠ (R55 10 k, JP2 Li-ion). Decision D1 pending; BOM-only change.
|
||||||
|
- **#10 F1 / F2:** F2 LCSC now assigned (C206910) ✅, but it protects only the U25 branch ❌ (A-01). F1 3 A PPTC is harmless (A-20b).
|
||||||
|
- **#14 AP64350 compensation vs datasheet:** evaluated. It is the 5 V table set; the estimate is stable with electrolytic bulk and marginal with polymer. → A-17.
|
||||||
|
- **"Switcher EP vias (U20, U25): 0"** (Review §2): still 0 on U20, U25, U2, U12 and U6. → A-06, A-02.
|
||||||
|
- **#15 Bench validation (power parts):** still required: U6/L6 IR at 1.4 A charge and 2.3 A backup; U20 VIN scope during a battery cold start at VBAT 3.5 V; D34/U25 IR at full load.
|
||||||
|
|
||||||
|
### V5.6 power / charger / temperature fixes vs v6
|
||||||
|
| V5.6 fix (ECO / change report) | v6 status |
|
||||||
|
|---|---|
|
||||||
|
| A: modem buck AP64350 with MCU EN + 100 k pull-down | **equivalent** (U20, PC10, R113); fed from /24V + MAIN5V instead of SYS5V → A-01 |
|
||||||
|
| A: Cin 2 × 22 µF + 10 µF at the modem buck | **missing** (10 µF + 1 µF) → A-05 |
|
||||||
|
| A: 220 µF polymer output | **missing** (2 × 220 µF 85 °C aluminium) → A-09 |
|
||||||
|
| A: L 4.7 µH ≥ 4 A | **has** (L20 4.7 µH/5 A, C17700167) |
|
||||||
|
| A: C3 → 220 µF polymer (F9P rail) | **equivalent / not needed** (F9P behind the U21 LDO; C3 47 µF 105 °C + C40 + C119) |
|
||||||
|
| A: R53 stays 499 k | **has** |
|
||||||
|
| A (opt): U12 → AP64350 | **missing** (optional) → A-20a; U12 EN gating → A-05 |
|
||||||
|
| C: RS1 10 mΩ | **has** (C105362) |
|
||||||
|
| C: R50 1.5 k | **missing** (825 Ω) → A-03 (1.43 k) |
|
||||||
|
| D1: RNTB / JP2 per chemistry | **unchanged**, pending decision |
|
||||||
|
| D2 / E1 / E2: SW_BAT ≥ 2 mm, BAT_PLUS ≥ 1.5 mm, EP ≥ 9 vias | **missing** → A-02 |
|
||||||
|
| D3: TMP102 near the modem | **missing** → F-52 (AT alternative) |
|
||||||
|
| (V5.x U4 TMP102 "cell") | **removed in v6**, no replacement → F-51 |
|
||||||
|
| D4: fan unchanged | **has**; E3 FB divider at pin **fixed** |
|
||||||
|
| D5: NTC probe to PB1 | **has** (P7 → PB1) + second probe P8 → PC4 |
|
||||||
|
| E4: buck Cin loops < 3 mm | **missing / worse** (U2 17–21 mm; U12 6.4 mm; U25 GND islands) → A-06 |
|
||||||
|
| F: F1 ≥ 4 A low-R | **equivalent / not needed** (modem not behind F1) |
|
||||||
|
| F: JP_CUT across the cutoff | **missing** (owner G) |
|
||||||
|
|
||||||
|
## Requirements input R1–R5
|
||||||
|
- **R1 (10 min off → wake → report on battery):** **needs change A-05 (+ A-08) plus firmware.** The hardware structure is right (independent PWR_CTRL / MODEM_PWR_EN, U20 UVLO margin ≈ 1 V). As-is, the boost reaches 93–97 % at a GSM burst with all loads on, W5500 cannot be powered off, and the AMS1117 floor eats the sleep budget.
|
||||||
|
- **R2 (modem never dark; MCU can power-cycle it):** **satisfied as-is** for the power side (U20 EN on PC10 with pull-down, UVLO margin, the modem can be power-cycled alone). A-01 changes the U20 input source but not the control.
|
||||||
|
- **R3 (report while on battery):** **needs change A-05 plus firmware** (same budget as R1). Also A-13 (PFO interrupt) for fast load shedding.
|
||||||
|
- **R4 (temperature management):** **needs change F-51** (charger TMP102 plus pack NTC to PC5), plus firmware. Fan: satisfied, and simplified by A-01 fix 1 (F-53).
|
||||||
|
- **R5 (charge ≥ 1.3 A without thermal cycling):** **needs A-03 (R50 1.43 k) + A-02 (copper/vias) + A-04 (R121 57.6 k or firmware retune).** A-07 is recommended.
|
||||||
|
|
||||||
|
## Firmware implications (things board_v6.h / FW 0.7.x must do)
|
||||||
|
1. **Pins (power-related):**
|
||||||
|
- Unchanged: `PIN_CHRG_EN PA8` (HIGH = charge OFF; polarity unchanged by A-11, only the reset default becomes OFF), `PIN_CHRG_STAT PB3`, `PIN_CHRG_FAULT PB4`, `5V_SENSE PA4` (÷2), `BAT_SENSE PA0` (÷2), `NTC_TEMP PB1`, `NTC2 PC4`, `PWR_CTRL PA1`, `MODEM_PWR_EN PC10`, `BYP_CTRL PB5`.
|
||||||
|
- New, if the fixes are taken: `PIN_ETH_PWR_EN PD2` (A-05), `PIN_PFO PB10` EXTI falling (A-13), `NTC_CELL PC5` ADC1_IN15, ratio 120/220 (F-51), TMP102 charger sensor at 0x48 (F-51), optional modem TMP102 at 0x49 (F-52).
|
||||||
|
2. **Constants:**
|
||||||
|
- `V5_PFI` 4.60 → **4.40 V** (falling; rising 4.51 V).
|
||||||
|
- With R121 57.6 k, keep `CHG_RAIL_ON 5.05` / `CHG_RAIL_OFF 4.90`. If R121 stays 53.6 k, the governor must be retuned (ON ≤ 4.80 V is not possible with PFI rising max 4.66 V and ADC error), so the hardware change is preferred.
|
||||||
|
- The v6 supply cannot fold (RS1 2.14–2.41 A < U25 4.5 A min limit): the governor is a safety net only.
|
||||||
|
3. **ADC:** compute VDDA every window from VREFINT (`VREFINT_CAL` @ 0x1FFF7A2A). Never assume 3.30 V, especially on battery (A-08).
|
||||||
|
4. **Thermal inhibit:** CHG_CELL_HOT/COOL on `tcell` from PC5 (Li-ion 45/40 °C; LFP 55–60 °C). Shed on `tchg` > 85 °C from the new TMP102. Append `tchg`, `tcell`, `tmodem` to `$PHLG`. Include the NTC in `thermalCtlTemp()`.
|
||||||
|
5. **Backup entry (PFO EXTI or 5V_SENSE < V5_OFF):**
|
||||||
|
- Immediately `ETH_PWR_EN` = 0 (or hold ETH_RST low if not fitted).
|
||||||
|
- `BYP_CTRL` = 0 except inside the TX window.
|
||||||
|
- Modem to **LTE-only on battery** (`AT+CNMP=38`) to avoid 2 A GSM bursts.
|
||||||
|
6. **Duty window (R1/R3):**
|
||||||
|
- Never start the modem with W5500, K1 and the F9P acquiring simultaneously.
|
||||||
|
- Order: modem EN → PWRKEY → wait STATUS (~7 s) and first RTCM on PC7, with the F9P OFF or already settled ≥ 4 s. Then the F9P for a hot fix. Then ≥ 2 `$PHLG` → modem OFF → F9P OFF → MCU STOP (LSE RTC).
|
||||||
|
- Refuse a modem cold start below VBAT ≈ 3.4 V: the boost's 2.5 A rating holds only down to 3.2 V.
|
||||||
|
7. **Low battery:** BSTOFF is hard-wired to GND, so firmware cannot switch the boost off. At `VBAT_BACKUP_MIN` go to STOP with every load off. The hardware floor is only LTC4040 BAT UVLO 2.45 V plus the pack PCM.
|
||||||
|
8. **Fan:** if the fan moves to VEH5V (A-01), the fan exists exactly when `vehiclePower`. The policy stays as is, and the ignition proxy becomes optional.
|
||||||
|
9. **Charger status:** "pausa NTC" = CHRG low ∧ FAULT low (datasheet table p.14). Bad battery = CHRG high ∧ FAULT low.
|
||||||
|
|
||||||
|
## Inputs needed from Leo
|
||||||
|
1. Supply systems in the fleet: 24 V only, or 12 V machines too? This sets F2 at 3 A vs 4 A, the U25 UVLO (A-16), and whether 9 V operation matters. Do the machines have alternator load-dump suppression (A-19)?
|
||||||
|
2. The fan part (5 V, 2-wire) and its current. Assumed 0.2–0.3 A for the VEH5V feed (A-01).
|
||||||
|
3. **Decision on A-01 Option A** (modem buck from MAIN5V only, D20 removed, D21 bridged) versus Option B (keep the 24 V feed with a ≥ 60 V buck). Coordinate with the modem auditor.
|
||||||
|
4. Pack details: capacity (Ah), PCM cut-off voltage, NTC β (B3380 vs B3950), and the chemistry decision D1.
|
||||||
|
5. Is GSM/2G fallback required on battery, or is LTE-only acceptable? This sets the backup peak (A-05).
|
||||||
|
6. Must Ethernet work on battery? Assumed no, so U12 is gated.
|
||||||
|
7. Enclosure internal temperature at 45 °C ambient. Assumed 60–65 °C local near the regulators, for electrolytic life (A-09) and U6/D34 thermals.
|
||||||
|
8. Bench data from the H0008 "Pendientes": clamp-meter charge current and U6/L6 temperature. This confirms or refutes OT cycling (A-02/A-03).
|
||||||
@ -0,0 +1,408 @@
|
|||||||
|
# B/C/E (Modem A7670SA · GNSS ZED-F9P · Ethernet W5500) — v6 audit findings
|
||||||
|
Snapshot: sch ecee9fed… / pcb 6ddec80d… (evidence pack 2026-09-28)
|
||||||
|
|
||||||
|
Auditor: RF/COMMS block agent. Read-only; no design file touched. Scratch scripts and numbers: `/home/claude/v6audit/work/BCE/` (`dist.py` pad distances, `tracks.py` segments, `pathr.py` path resistance/IR drop, `rfgeo.py` RF gaps/reference planes/crossings, `islands.py` F.Cu GND clusters and plane vias, `z0.py`/`fdrun*.py` impedance (analytic + 2-D finite-difference solver), `budget.py` battery budget).
|
||||||
|
|
||||||
|
**Stackup assumption (stated once, used everywhere):** the board file carries KiCad's generic stack (3 × 0.48 mm FR4, εr 4.5). JLC will build its standard **JLC04161H-7628**: L1–L2 prepreg 0.2104 mm (7628, εr ≈ 4.4), core 1.065 mm, L3–L4 prepreg 0.2104 mm, outer Cu 35 µm, inner Cu 15–17.5 µm (0.5 oz default). All impedance and inner-layer IR numbers below use that; the file's own stack is shown for comparison.
|
||||||
|
|
||||||
|
## Sources read
|
||||||
|
- Common brief `findings/_COMMON_BRIEF.md`; master brief §3–§5 incl. §4-B/C/E; `INDEX.md`; `evidence/MANIFEST.md`; `evidence/stackup.md`.
|
||||||
|
- Prior review `docs/2026-09-28_…_Review-vs-V5.5-Lessons_v1.0.md` (§1 F1/F2/F3/F8/F9, §2, §3, §4 checklist); ECO `docs/2026-09-27_…_V5.6_ECO_ES_v1.0.md` §0 (R1–R5), §A, §B, §E, §F, §H; project docs `claude__2026-09-25_HBox-v6_Pre-Fab-Audit_EN.md`, `claude__2026-09-27_…Modem-on-battery_Diagnosis…md`, `claude__2026-09-28_…Status-and-Next-Steps.md`.
|
||||||
|
- Design docs: `2026-08-24_…GNSS-4G-Integration_Design-Brief_v1.0.md` (§3, §4), `…Phase-2_Schematic-Delta_v1.0.md` (Blocks N–T), `…Phase-1_NTRIP-Firmware-Spec_v1.0.md` (§1.4, §2, §4), `2026-08-27_…Antenna-Chain_Diagram.html`, `2026-09-02_…Copper-Plan_Placement-EMC-Guide.html` (§4, §5, §7, §8).
|
||||||
|
- Memory (`docs/memory/`): `drogheda-einarboard-v6-brief`, `drogheda-v6-zed-f9p-integration`, `drogheda-v6-lte-island`, `drogheda-mff2-footprint`, `drogheda-einarboard-v6-phase12`, `drogheda-einarboard-modem-rail`, `drogheda-epct-telemetria`.
|
||||||
|
- Evidence: `ic_pins_U19/U18/U11/U20/U22/U23/U24.csv`, `mcu_pins.csv`, `components.csv`, `nets.json`, `ref_pins.json`, `pcb_footprints.csv`, `pcb_pads.csv`, `pcb_tracks.csv`, `vias.csv`, `zones.csv`, `net_routing_summary.csv`, `erc_summary.md`, `drc_summary.md`, `sch_pcb_sync.md`, `firmware_pins.md`, `firmware_constants.csv`; staged `src/hbox-watchdog-v6.kicad_pcb` (parsed with `scripts/parse_pcb.py`), `src/Drogheda-v6.kicad_sym`, `src/Drogheda-v6.pretty/*`, `src/fw/hbox_v5_bringup.ino`, `board_v5.h`.
|
||||||
|
- Datasheets / app docs (manufacturer or vendor copies):
|
||||||
|
- SIMCom **A7672X/A7670X Series Hardware Design V1.03** (124-pin LCC+LGA; covers A7670SA): Table 8 (VBAT 3.4–4.2 V, peak 2 A, PWRKEY 50 kΩ pull-up), p.27 (≥300 µF / 600 µF, ≤300 mV drop, VBAT ≥3 mm), Tables 10–12 (PWRKEY ≥50 ms on / ≥2.5 s off, RESET 2.5 s, STATUS), Table 28 (VDD_1V8 50 mA), Table 41 (digital pins abs max −0.3…2.0 V), Fig. 33 (antenna D1 = **bidirectional** ESD, R1/R2 0 Ω, C1/C2 NM) — https://files.waveshare.com/wiki/A7670E-Cat-1-GNSS-HAT/A7672X_A7670X_Series_Hardware_Design_V1.03.pdf
|
||||||
|
- SIMCom **A7670 Series Hardware Design V1.00**: Table 7 (peak 2.8 A), Table 9 (STATUS 11.2 s), Fig. 19 (USIM: 22 Ω series, 22 pF NM, ESDA6V1W5/SMF15C), Fig. 25 / Table 28 (antenna), Table 35 (LTE 23 dBm 490–670 mA) — https://nostris.ee/pdf/A7670%20Series%20Hardware%20Design_V1.00.pdf
|
||||||
|
- u-blox **ZED-F9P-04B Data sheet UBX-21044850**: Table 14 (Vin abs max −0.5…VCC+0.5 V when VCC ≤ 3.1 V; VCC_RF 300 mA abs), Table 15 (VCC ramp 20–8000 µs/V, VCC_RF ≤ 50 mA, RESET_N pull-up 7–13 kΩ, I_BCKP 45 µA), Table 16, Table 23 (UART defaults) — https://content.u-blox.com/sites/default/files/ZED-F9P-04B_DataSheet_UBX-21044850.pdf
|
||||||
|
- u-blox **ZED-F9P Integration Manual UBX-18010802**, antenna bias section: "a 10 Ω current limiting resistor is **required** to prevent against short circuits destroying the BIAS-T inductor"; bias-T 120 nH recommended; supervisor via ANT_OFF/ANT_SHORT_N/ANT_DETECT — https://www.manualslib.com/manual/1927649/U-Blox-Zed-F9p.html?page=92
|
||||||
|
- Diodes **AP64350 DS41976 Rev 5-2**: VIN abs max 42 V DC / 45 V 400 ms, operating 3.8–40 V, UVLO rising 3.5–3.7 V (hyst 400 mV), EN pull-up 1.5 µA, EN low ≤ 1.03 V, RDS 75/45 mΩ, t_on,min 100 ns, SS 2 ms, RT = 100000/f, Table 1, R5 = 4.67·10³·fc·VOUT·COUT — https://www.diodes.com/datasheet/download/AP64350.pdf
|
||||||
|
- Diodes **AP2112 DS39724**: start-up time 20 µs, foldback short-circuit 50 mA — https://www.mouser.com/datasheet/2/115/AP2112-271550.pdf
|
||||||
|
- TI **TPS7A20**: t_STR 750–1150 µs with internal soft-start, DBV pinout IN/GND/EN/NC/OUT — https://www.ti.com/lit/ds/symlink/tps7a20.pdf
|
||||||
|
- TI **TPS2552/53**: IOS = 22980/R_ILIM(kΩ), ILIM tied to IN = 75 mA typ, DBV pinout — https://www.ti.com/lit/ds/symlink/tps2552.pdf
|
||||||
|
- Nexperia **PMEG3050EP**: VR 30 V, VF 240 mV@1 A / 285 mV@3 A typ, **IR 2.6 mA typ / 8 mA max @ 30 V, 25 °C**, Rth(j-a) 120 K/W — https://assets.nexperia.com/documents/data-sheet/PMEG3050EP.pdf
|
||||||
|
- ADI **LTC4040 (4040fb)**: 2.5 A backup from VBAT ≥ 3.2 V, ILIM(BST) 5.5–7.5 A, VSYS 3.5–5 V, VSYS abs max 6 V, system load not limited by input limit — https://www.analog.com/media/en/technical-documentation/data-sheets/4040fb.pdf
|
||||||
|
- WIZnet **W5500 datasheet v1.0.2**: TOCAP 4.7 µF, 1V2O 10 nF, EXRES1 12.4 kΩ 1 %, VBG floating, RSVD23 → GND, RSTn ≥ 500 µs, crystal 25 MHz CL 18 pF ±30 ppm, 128/75/13 mA — https://cdn.sparkfun.com/datasheets/Dev/Arduino/Shields/W5500_datasheet_v1.0.2_1.pdf
|
||||||
|
- SamYoung **MVG** series catalogue (general purpose, 85 °C 2000 h, tanδ 0.20 @16 V) — https://www.samyoung.co.kr/download/surface/MVG.pdf
|
||||||
|
- STM32F411 RM0383 §8.3.1 (debug pins after reset: PA15 = JTDI with pull-up; R_PU 30–50 kΩ from the F411 datasheet) — from ST documentation, not re-fetched this session.
|
||||||
|
- JLC parts DB (`get_jlcpcb_part`) for every LCSC number quoted below.
|
||||||
|
|
||||||
|
## Findings
|
||||||
|
|
||||||
|
### B-01 Modem buck input hangs on the unfused, weakly clamped /24V branch; D21 (30 V Schottky) is over-stressed and leaks into MAIN5V
|
||||||
|
- **Severity:** Blocker
|
||||||
|
- **Block / refs:** §4-B (U20 source); lesson F1; ECO §A; memory `drogheda-einarboard-v6-brief` (T9 "9–36 V in"), `drogheda-einarboard-v6-phase12` (Block P); INDEX gotcha #4.
|
||||||
|
- **Evidence:**
|
||||||
|
- Netlist: `/VIN_MODEM` = D20.1 (SS34 K) + D21.1 (PMEG3050EP K) + C127/C128 + U20.2. D20.2 = `/24V` = Q10.3 (IRFR5305 reverse-polarity FET from `/24V_IN`), **not behind F2** (F2 is only on `/24V_IN → F2 → Q23 → /VIN_PROT`). D21.2 = `/MAIN5V` (LTC4040 VSYS).
|
||||||
|
- When 24 V is absent (battery/backup) VIN_MODEM is fed only through D21 from the LTC4040 boost (4.79 V) → the modem **can** run on battery (numbers in B-16). When 24 V is present D21 is reverse-biased by VIN_MODEM − MAIN5V.
|
||||||
|
- **D21 reverse stress:** VR = V24 − VF(D20 ≈ 0.45 V) − MAIN5V (5.0–5.3 V). At the declared 36 V input max: **30.3–30.6 V > 30 V VRRM**. At 32 V (24 V-system max steady): 26.3 V (88 % of rating). PMEG3050EP IR = **2.6 mA typ / 8 mA max at 30 V, 25 °C**; Schottky leakage roughly doubles per ~10 °C, so at a 60 °C board it is tens of mA × 26 V = 0.5–1 W into a 120 K/W package → thermal runaway risk, and that current is injected from the vehicle supply into MAIN5V (6 V abs max, LTC4040 DS p.2).
|
||||||
|
- **Transients:** /24V is clamped only by D10 SMBJ33A (VBR 36.7–40.6 V, VC 53.3 V @ 11.3 A). AP64350 abs max = **42 V DC / 45 V for 400 ms**. An ISO 7637-2 pulse 2a-class event that pushes D10 to ≈ 45–51 V exceeds U20's rating and puts ≈ 40–46 V reverse on D21 → avalanche into MAIN5V.
|
||||||
|
- No fuse on the D20 path: a failed C127/C128/U20/D20 short draws unlimited current from the vehicle battery through Q10 and 0.8 mm × 48 mm of track (`/VIN_MODEM` F.Cu, D20 at (136.5,113.8) → U20 at (147.5,63.2)).
|
||||||
|
- Positives: C127 = GRM21BR61H106 10 µF **50 V** and C128 = 1 µF 50 V (voltage rating OK).
|
||||||
|
- **Consequence:** On 24–28 V vehicles in a hot cabinet D21 can run away and short 24 V into the 5 V domain (LTC4040, MCU, F9P); transients can destroy U20; no overcurrent protection on that branch. The original reason for the 24 V feed (keep 1.6 A of modem off the SD-15B's 3 A) no longer exists: v6 has its own U25 TPS54360B and RS1 = 10 mΩ (2.5 A input limit < U25 capability).
|
||||||
|
- **Fix (pick one; B recommended):**
|
||||||
|
- **Option B (recommended, schematic + small layout):** delete D20 and the /24V→VIN_MODEM trace; feed U20 only from `/MAIN5V`. Either keep D21 as a plain forward diode (no reverse stress any more) or replace it by a copper link (+0.27 V battery headroom, see B-16). U20 then never sees > 5.5 V, the unfused-branch question disappears for the modem, and the modem sits behind the LTC4040 PowerPath (seamless 24 V↔battery). Budget on vehicle power: modem LTE ≈ 0.6–1.0 A, GSM burst ≈ 1.8 A from MAIN5V + ≈ 0.4 A system = 2.2 A peak; LTC4040 system load has priority over charge (DS p.13/16), U25 rated 3.5 A. Needs the power auditor to confirm U25 transient droop stays above PFI (4.44 V) with R121 = 57.6 k (5.32 V).
|
||||||
|
- **Option A (keep 24 V feed):** D21 → **PMEG6045ETPX, LCSC C552943** (Nexperia, 60 V/4.5 A, IR 400 µA @ 60 V, SOD-128 = same land as PMEG3050EP; 2722 in stock, Extended); move D20's anode from `/24V` to `/VIN_PROT` (behind F2 + Q23 + D32 SMCJ33A 1500 W, whose clamp at ≈ 9.5 A is ≈ 43.5 V, inside U20's 45 V/400 ms rating); F2 (currently Littelfuse 0154002.DR, 2 A, C206910) must then be re-rated for U25 + U20 at the 9 V minimum input (≈ 2.4 A at 12 V) → 4 A class (power auditor).
|
||||||
|
- **Effort:** both (schematic + ~50 mm of copper removed/added)
|
||||||
|
- **Confidence:** high on ratings (datasheet numbers); medium on the runaway temperature (Fig. 5 of the PMEG3050EP DS not tabulated). Raise by measuring D21 leakage at 26 V on a hot plate (60/85 °C).
|
||||||
|
|
||||||
|
### B-02 VBAT_MODEM bulk is a general-purpose aluminium electrolytic, not polymer; U20 compensation not designed for the actual output bank
|
||||||
|
- **Severity:** Blocker
|
||||||
|
- **Block / refs:** §4-B (Cout, bulk ≥ 220 µF polymer); lesson F1 (modem brown-out on burst); ECO §A (C43 → 220 µF polymer C881921); memory `drogheda-einarboard-v6-brief` ("≥300 µF VBAT bank").
|
||||||
|
- **Evidence:**
|
||||||
|
- C130, C131 = **C2827940 = SamYoung MVG 16 V 220 µF 6.3×7.7**, general purpose, **85 °C / 2000 h**, tanδ 0.20 → ESR(120 Hz) = 0.20/(2π·120·220 µF) = **1.2 Ω**, rated ripple 40 mA (catalogue) / 130 mA (LCSC) rms. Value field says "220uF/10V".
|
||||||
|
- Placement: C131 **8.7 mm**, C130 **16.3 mm** edge from the nearest VBAT pad (U19.55/56/57) → meets the 10–20 mm position criterion, fails the polymer/low-ESR criterion.
|
||||||
|
- Effective low-ESR output capacitance is therefore only the ceramics: C132 22 µF/16 V X5R 0805 (≈ 60 % at 3.8 V) + C133 1 µF + C134 100 nF ≈ **14 µF**, vs SIMCom ≥ 300 µF (≥ 600 µF if the source cannot deliver the peak), HD V1.03 p.27.
|
||||||
|
- No capacitor at the L20 output: nearest is C130 12 mm away. Inductor ripple ΔIL = 3.8·(24−3.8)/(24·4.7 µH·500 kHz) = **1.36 A p-p** (24 V input) or 0.39 A p-p (5 V input) flows through that e-cap's ESR. AP64350 DS: "22 µF to 68 µF ceramic" at the output.
|
||||||
|
- Compensation (R116 14 k, C141 3.3 nF, C142 47 pF) = the AP64350 **5 V** Table 1 row. With DS eq. R5 = 4.67·10³·fc·VOUT·COUT: ceramics only → fc = 14k/(4.67k·3.8·14 µF) = **56 kHz** (> fsw/10 = 50 kHz, low phase margin); with a real 454 µF low-ESR bank → fc = **1.7 kHz** (too slow). Load-step droop estimate for a 2 A step: ceramic-loop ≈ 2/(2π·56 kHz·14 µF) = **0.41 V**, plus 2 A × ESR(e-caps ≈ 0.15–0.3 Ω pair) ≈ 0.3–0.6 V → VBAT can dip to ≈ 3.2–3.4 V (A7670 min 3.4 V, max droop 300 mV).
|
||||||
|
- Life: 2000 h × 2^((85−T)/10) → **8000 h at 65 °C, 5660 h at 70 °C** (≈ 8–11 months), before any burst ripple heating.
|
||||||
|
- FB: R110 75 k / R111 20 k → 0.8·(1+75/20) = **3.80 V**; worst case (±1 % R, VFB ±2 % assumed) **3.67–3.94 V** — inside 3.4–4.2 V ✅.
|
||||||
|
- **Consequence:** Modem brown-out/reset during registration bursts (the exact V5.5 "modem dark" failure mechanism, now from the output side), worse on battery where the boost is near its 2.5 A limit (B-16); electrolytic wear-out within the first year in a 45 °C port cabinet.
|
||||||
|
- **Fix:** C130, C131 → **Lelon OVZ221M1CTR-0608 220 µF/16 V polymer, 105 °C, LCSC C881921** (same CP_Elec_6.3x7.7 land; 2442 in stock) — the part already chosen in ECO §A. Move C131 to ≤ 5 mm of U19.55–57 (see B-08). Add **2 × 22 µF 0805 (C86817, Murata GRM21BR61C226)** at L20.2 within 3 mm. Re-compensate for COUT ≈ 454 µF, fc ≈ 14 kHz (≈ the Table 1 bandwidth): **R116 → 113 kΩ 1 % (C22862), C141 → 6.8 nF 0402 X7R (C1542), C142 → 56 pF 0402 C0G (C1572)** (R5 = 4.67k·14k·3.8·454 µ = 112.8 kΩ; C5 = 3.8·454 µ/(2 A·113 k) = 7.6 nF; C6 = ESR·Co/R5 ≈ 60 pF with ≈ 15 mΩ bank ESR). Verify on the bench: 0.1 → 2 A load step on VBAT_MODEM, droop ≤ 150 mV, no ringing.
|
||||||
|
- **Effort:** both (BOM values + 2 caps + C131 move)
|
||||||
|
- **Confidence:** high on part type/life/ESR class; medium on the exact compensation (polymer ESR taken from class, C881921 datasheet host is robots-blocked). Raise with the bench load step.
|
||||||
|
|
||||||
|
### B-03 LTE antenna ESD D28 is a unidirectional 5 V TVS on an RF line without DC bias
|
||||||
|
- **Severity:** Blocker
|
||||||
|
- **Block / refs:** §4-B (antenna path: ESD); memory `drogheda-v6-lte-island` (Block S chose ESD9L for both antennas); SIMCom HD V1.03 Fig. 33 ("D1 is a **Bidirectional** ESD protection device").
|
||||||
|
- **Evidence:** D28 = ESD9L5.0ST5G, **C82326 (JLC: "Unidirectional", 0.9 pF, VRWM 5 V, VBR 5.4 V, VC 9.8 V)**; symbol pin 1 = C on `/RF_ANT_LTE`, pin 2 = A on GND; footprint pad 1 = cathode (silk band at x = −1.2 mm side verified). The LTE line has no DC. RF peak voltage at the connector: +23 dBm → 4.47 V pk (6.7 V at VSWR 3:1); A7670SA also transmits GSM 850/900 at +33 dBm → **14.1 V pk (21.2 V at VSWR 3:1)**. A unidirectional diode forward-conducts at ≈ −0.6 V on every negative half-cycle and avalanches at +5.4 V on GSM positive peaks.
|
||||||
|
- **Consequence:** Hard clipping of every TX cycle: harmonics/spurious emissions (homologation IFT/CRT fail), lost TX power, PA stress, and likely destruction of D28 under GSM bursts (then possibly a short across the antenna port). Placement is fine (in-line, 1.8 mm from J13.1); the part is wrong.
|
||||||
|
- **Fix:** D28 → **Littelfuse PGB1010402KR, LCSC C10676** (polymer ESD, bidirectional, 0.04 pF, 0402; 59 948 in stock) with a 0402 land in the same in-line spot; or DNP D28 (SIMCom marks it optional). Keep D27 (GNSS) as is: its line carries +3.2 V bias, so a unidirectional 5 V part is correct there.
|
||||||
|
- **Effort:** both (part + 0402 land)
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### B-04 Modem ground: one via under the A7670SA, none in U20's EP, none at J13; the whole LTE island reaches the inner GND planes through 5 vias
|
||||||
|
- **Severity:** Blocker
|
||||||
|
- **Block / refs:** §4-B (ground return/vias); lesson F5 (U6 EP without thermal vias, same class of omission); ECO §E6 (stitching); Phase-2 Block O ("full via field"); memory `drogheda-v6-lte-island`.
|
||||||
|
- **Evidence (`islands.py`, `gndvias.py`):** board has 69 GND vias in total. **U19 courtyard (162.2…186.2 × 60.0…84.0) contains 1 GND via.** 34 of U19's 39 GND pads (incl. the 20 inner 2.1 × 2.1 mm LGA GND pads on a 3.8 mm grid) sit in one F.Cu GND cluster of 3611 mm² whose only connections to In1/In2 are **5 vias** (at (152.6,62.5), (153.5,77.0), (198.8,78.1), (145.7,129.9), (148.1,135.3); nearest 21.3 mm from U19 centre) plus THT pads of J9, P1, P11. The other 5 U19 GND pads sit in three tiny islands with 1 via each. U20 EP (pad 9, 3.2 × 2.5 mm): **0 vias in pad, 0 within 2 mm**; C127/C128/C130–C136/D22 GND pads: 0 vias within 3 mm. J13 GND pads: 0 vias within 3 mm. RF_LTE path (32 mm): 1 GND via within 1.5 mm of the centreline.
|
||||||
|
- **Consequence:** The PA's 2 A return current and the RF return of the antenna feed flow through a chopped 1 oz F.Cu pour to vias ≥ 21 mm away → large current loops (radiated emission, GNSS desense = the brief's #1 risk), no RF reference continuity at the In1 transitions of RF_LTE (B-05), and the module's main heat path (GND pads → planes) is missing (A7670SA normal range −30…+80 °C in a 45 °C cabinet).
|
||||||
|
- **Fix (layout):** tented 0.6/0.3 mm GND vias: (a) U19 — one in each of the 1.7 mm gaps between adjacent inner GND pads (≥ 16) plus a ring on the outer GND pads (58, 59, 61–65, 69–89 groups), target ≥ 40 vias; keep vias out of signal-pad areas; (b) U20 EP — ≥ 6 vias (2 × 3 array, 0.3 mm drill) in the EP land; (c) C127/C128 and every VBAT cap GND pad — 2 vias each ≤ 0.5 mm from the pad; (d) J13 and J12 GND pads — 2 vias per pad; (e) via fence along both RF lines (B-05/C-05). Re-run the cluster check: every GND pad of U19/U20/J13 in a cluster with ≥ 1 plane via within 2 mm.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high (geometry); impact magnitude medium (no field solver run for emissions).
|
||||||
|
|
||||||
|
### C-01 GNSS antenna bias has no current limit and no supervisor; ANT_DETECT / ANT_SHORT_N are undriven
|
||||||
|
- **Severity:** Blocker
|
||||||
|
- **Block / refs:** §4-C (ANT supply current limit/short detection); memory `drogheda-v6-zed-f9p-integration`, `drogheda-einarboard-v6-brief` (H0005/H0014 antenna faults); u-blox ZED-F9P Integration Manual (antenna bias: "a 10 Ω current limiting resistor is **required**"); ZED-F9P DS Table 14/15 (VCC_RF ≤ 50 mA operating, 300 mA abs max).
|
||||||
|
- **Evidence:** `/VCC_RF_GNSS` = U18.7 (VCC_RF) + L21 + C144/C145 only — L21 (68 nH, LQG18HN68NJ00D, C162555: 0.8 Ω DCR, 400 mA) connects VCC_RF straight to the antenna line; no series resistor, no switch. `/GNSS_ANT_DETECT` = U18.4 + U16.9 (PC1) and `/GNSS_ANT_SHORT_N` = U18.6 + U16.10 (PC2): both ends are **inputs** (these F9P pins are supervisor *inputs*), nothing drives them; with the F9P powered they sit at its internal pull-ups → MCU always reads "antenna present, no short". U18.5 ANT_OFF is NC.
|
||||||
|
- **Consequence:** A crushed/wet coax (the H0005/H0014 class of fault) shorts 3V3_GNSS through L21: current limited only by U21 → exceeds VCC_RF 300 mA abs max and L21's 400 mA rating ("destroying the BIAS-T inductor"), collapses 3V3_GNSS (F9P brown-out loop), and the PC1/PC2 "antenna telemetry" never reports it.
|
||||||
|
- **Fix:** add a current-limited antenna feed: **TPS2552DBVR, LCSC C46506** (SOT-23-6, EN active-low): IN (1) = `/3V3_GNSS`; OUT (6) = net to L21.2/C144/C145 (rename `/ANT_BIAS`); ILIM (5) tied to IN → **75 mA typ** (DS; above the 50 mA VCC_RF/antenna budget, below 300 mA); EN (3) ← U18.5 ANT_OFF with **100 kΩ to GND (C25803)** so the antenna is ON by default; FAULT (4, open-drain) → `/GNSS_ANT_SHORT_N` (U18.6 + PC2) with **10 kΩ to /3V3_GNSS (C25804)**; leave U18.7 VCC_RF NC. U21 then supplies F9P 130 mA + antenna ≤ 75 mA = 205 mA (TPS7A2033 300 mA, see C-02). Minimum fallback if no new IC: **10 Ω 0805 in series between VCC_RF and L21.2** (u-blox minimum; short → 3.2 V/10.8 Ω ≈ 0.3 A, 0.95 W in the resistor → use a 1206 ≥ 0.5 W). Open-antenna detect (ANT_DETECT) can stay unimplemented; firmware infers it from C/N0.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### B-05 RF_LTE runs 22.1 mm inside In1 (the GND reference plane) with two via transitions, 32–47 Ω, under power and LED tracks
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-B (50 Ω trace geometry, keepouts, LTE island rules); Phase-2 Block S ("referenced to unbroken In1… nothing crossing on any layer"); pre-fab audit §7 (flagged "v6.1"); memory `drogheda-v6-lte-island`.
|
||||||
|
- **Evidence (`tracks.py`, `rfgeo.py`, `fdrun2.py`):** U19.60 (174.25,60.00) → F.Cu 1.75 mm → via (174.25,58.25) → **In1 22.14 mm (w 0.50)** → via (194.27,53.72) → F.Cu 2.3 mm → R118 (0 Ω) → `/RF_ANT_LTE` F.Cu 5.6 mm → D28 → J13.1. Total 31.8 mm. In1 section: same-layer GND fill at 0.15 mm both sides; F.Cu above is GND for only 45–55 % of the length; In2 below 65–89 %. Crossing copper: F.Cu `/SYS5V`, `/SW_IN` (Q1 = F9P rail switch), `/VBAT_MODEM`, `/MODEM_LED_A/K`; In2 `/DIN_4G`; B.Cu `/5V_FAN`. FD-solver impedance of the In1 trace: **32.5 Ω** where F.Cu above is GND, **47.1 Ω** where it is not → |Γ| up to 0.21 (RL 13.5 dB) with two via discontinuities and no adjacent GND vias (B-04).
|
||||||
|
- **Consequence:** Uncontrolled LTE match; +23/+33 dBm TX energy coupled 0.21 mm into SYS5V/SW_IN (the F9P supply chain, see C-04) and VBAT; the In1 plane is slotted for 22 mm under F.Cu signals.
|
||||||
|
- **Fix (layout):** route U19.60 → J13 entirely on F.Cu as CPWG over solid In1: **w = 0.30 mm, gap = 0.20 mm** (FD: 53.3 Ω bare / 48.4 Ω with 20 µm mask on JLC04161H-7628; alternative 0.35/0.25 → 51.3/47.1 Ω); confirm in JLC's impedance calculator and order impedance control. GND via fence both sides at ≤ **3.3 mm** pitch (λg/20 at 2.69 GHz, εeff 2.8), vias ≤ 0.5 mm from the gap edge; two GND vias at each J13 ground pad; nothing on In1/In2/B.Cu under the line; keep the π-pad (C146/R118/C147) as is at J13. Add a KiCad netclass `RF` (0.30 mm track, 0.20 mm clearance, excluded from autoroute) and a custom rule for zone clearance 0.20 mm to RF nets.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high (geometry and solver agree with analytic within 2–3 Ω).
|
||||||
|
|
||||||
|
### B-06 U20 AP64350 hot loop and thermal: input-cap ground returns 4.9–8.5 mm, EP without vias, FB node next to SW
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-B (compensation/frequency network, Cin), §4-A/F (Cin ≤ 3 mm); pre-fab B5; ECO §E3/§E4; Copper Plan §4.
|
||||||
|
- **Evidence (`dist.py`):** VIN side is good: C128.1 → U20.2 **0.72 mm**, C127.1 → U20.2 **2.38 mm**; but GND side: C128.2 → U20.7 **6.86 mm**, C127.2 → U20.7 **8.48 mm** / → EP **4.94 mm**, no vias (B-04). L20.1 → U20.8 2.24 mm ✅, C129 (BST) 1.8–1.9 mm ✅, R117 (RT) 1.44 mm ✅, R116/C142 (COMP) 0.72/2.15 mm ✅. FB: R111.1/R110.2 junction at (152.5–154.25, 61.4) is ≈ 2 mm from U20.8/SW copper; `/FB_MODEM` is 13.9 mm long (0.5 mm) running around U20; R110 top taps VBAT via a 5.6 mm In1 detour (vias (154.00,58.90)/(154.47,52.83)). Only C127 10 µF (≈ 4 µF at 24 V DC bias) + C128 1 µF at VIN; ECO §A asked 2 × 22 µF + 10 µF.
|
||||||
|
- **Consequence:** A synchronous-buck input loop closed through several mm of pour around pin 1 (EMI at 500 kHz harmonics, SW ringing), EP θJA far above the DS 45 °C/W, FB noise pickup.
|
||||||
|
- **Fix (layout + 1 part):** turn C127/C128 so their GND pads face U20's EP/pin 7 side and drop 2 vias each ≤ 0.5 mm; 6 EP vias (B-04); place R110/R111 at U20.5 (≤ 2 mm) on the side away from pin 8, take the VBAT sense from a dedicated trace at C131, delete the In1 detour; add **1 × 22 µF 0805 (C86817)** at U20.2 ≤ 3 mm (with option B of B-01 the input is ≤ 5.5 V, so the 16 V part is fine; with option A use a 50 V 1206).
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** high (geometry).
|
||||||
|
|
||||||
|
### B-07 Modem USB-C J9 has no ESD protection (lesson F8), and the USB pair is split across layers
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-E/F (ESD at connectors); lesson F8; ECO §E5 (USBLC6 at J9); Review §4 item 7.
|
||||||
|
- **Evidence:** `/USB_DP` = J9.A6/B6 + U19.27; `/USB_DM` = J9.A7/B7 + U19.28; `/USB_VBUS` = J9.A4/A9/B4/B9 + U19.24 → **no protection device** (unchanged since the 25-Sep review). J9 at (147.95,130.98) is 59 mm from U19; pair: DP F.Cu 49.9 + In1 9.6 mm, DM F.Cu 50.0 + In1 8.0 + In2 1.7 mm; coupled (≤ 0.6 mm) only 34.7 mm; J9 is the modem's firmware-update/USB_BOOT recovery port.
|
||||||
|
- **Consequence:** A field-service ESD hit on J9 goes straight into the A7670SA USB PHY/VBUS (module = the only link); HS signal integrity marginal for FOTA/recovery.
|
||||||
|
- **Fix:** add **USBLC6-2SC6, LCSC C7519** (SOT-23-6) ≤ 5 mm from J9: I/O1 = USB_DM, I/O2 = USB_DP, VBUS pin = USB_VBUS, GND with 2 vias. Route DP/DM as a coupled pair on F.Cu only (w/gap for 90 Ω diff, e.g. 0.20/0.15 on JLC7628 — confirm in JLC calculator), one layer, ≤ 1 via pair.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### C-02 U21 AP2112K start-up is 20 µs — the ZED-F9P VCC ramp window (20–8000 µs/V) is not guaranteed
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-C (VCC ramp); memory `drogheda-v6-zed-f9p-integration` ("20–8000 µs/V window, measure before fab"); ZED-F9P DS Table 15.
|
||||||
|
- **Evidence:** U21 = AP2112K-3.3 (C51118), EN (pin 3) tied to VIN (`/SW_5V`), so it starts when Q1 switches `/SW_5V` on. Q1 gate: R2 10 k to SYS5V, pulled down directly by Q5 collector — no gate RC → `/SW_5V` steps in µs. AP2112 DS: **t_S = 20 µs** (no load) → 3.3 V/20 µs = **6 µs/V** unloaded; with the actual ≈ 16–20 µF on `/3V3_GNSS` (C120, C124 10 µF + 3 × 100 nF) the ramp is bounded by the foldback current limit (50 mA at 0 V rising to ≈ 0.6–0.8 A) → ≈ 400 µs/V at the start falling to ≈ **20–25 µs/V** near regulation, i.e. at/over the fast limit. The F9P is power-cycled on every 10-min duty window (R1: ≈ 52 000 starts/year).
|
||||||
|
- **Consequence:** Out-of-spec VCC ramp → occasional failed F9P start (dark receiver until the next cycle) in exactly the duty-cycled mode R1 requires.
|
||||||
|
- **Fix:** U21 → **TPS7A2033PDBVR, LCSC C2862740** (TI, 300 mA, SOT-23-5 with the **same pinout** IN/GND/EN/NC/OUT, internal soft-start **t_STR 750–1150 µs** → 237–367 µs/V, inside the window with > 10× margin; inrush 20 µF·4.2 V/ms ≈ 84 mA + load < 360 mA limit; 95 dB PSRR @ 1 kHz; COUT ≤ 200 µF OK). Load: F9P 130 mA pk + antenna ≤ 75 mA (C-01) = 205 mA. Bench: scope `/3V3_GNSS` rise (target 100–1000 µs/V).
|
||||||
|
- **Effort:** schematic-only (drop-in footprint)
|
||||||
|
- **Confidence:** medium-high (AP2112 behaviour into 20 µF is derived from DS limits, not measured).
|
||||||
|
|
||||||
|
### C-03 ZED-F9P: 0 vias under the module; 56 GND pads reach the planes through 5 vias
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-C (decoupling/GND per u-blox integration manual); Phase-2 Block N ("full pad-under-module via field").
|
||||||
|
- **Evidence:** U18 courtyard (65.0…82.0 × 102.2…124.2): **0 vias**. Its 56 GND pads (48-pad array of 1.1 mm pads on a 2.1 mm grid + 8 ring pads) are in one 946 mm² F.Cu cluster with 5 GND vias + 1 THT pad. J12 GND pads: 0 vias ≤ 3 mm.
|
||||||
|
- **Consequence:** Poor RF/digital ground reference for the receiver and the RF input, shared return with the long digital lines leaving the island; higher susceptibility to the LTE aggressor.
|
||||||
|
- **Fix (layout):** tented vias between the 1.1 mm GND array pads (gap 1.0 mm → 0.45/0.2 mm vias, or via-in-pad filled/capped if JLC option chosen): ≥ 24 vias; 2 vias at each J12 GND pad and at C121/C122/C120/C124/U21 GND pads.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### C-04 The GNSS supply switch Q1 sits 9 mm from the LTE antenna feed; /SW_5V crosses the whole board on In1
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-C (distance from LTE feed; desense); brief §4.3 ("#1 risk GNSS desense"); Copper Plan §5 ("no switcher/fast digital within 25 mm of the GNSS corner"); cross-block with power (F1/Q1 placement).
|
||||||
|
- **Evidence:** Q1 (AO3401A, `/SW_IN` → `/SW_5V`) at (197.28,59.81) = **9.0 mm from J13**; F1 at (171.4,44.3) in the LTE corner; Q5/R1/R2 at 192–196 mm. `/SW_5V` path Q1.3 → U21.1 = **167 mm** (F.Cu 19.7 + **In1 181.3 mm**, 95 mΩ at 35 µm / 184 mΩ at 17.5 µm inner Cu). RF_LTE's In1 section passes 0.21 mm under `/SW_IN` and `/SYS5V` (B-05).
|
||||||
|
- **Consequence:** The F9P's supply starts in the LTE transmitter's near field and travels 17 cm as a slot in the GND plane; LDO PSRR at LTE frequencies is ≈ 0 dB, so TX envelope/IMD products ride into the receiver rail (desense), and the In1 plane is cut end to end.
|
||||||
|
- **Fix (layout):** move Q1 + Q5 + R1 + R2 (and F1 if the power auditor agrees) into the GNSS island next to U21/C3/C40/C119; bring `/SYS5V` (or `/SW_IN`) to it instead; route the remaining feed on F.Cu or In2 away from the RF lines; keep `/PWR_CTRL` as the long signal. Target `/SW_5V` ≤ 15 mm, 0 mm on In1.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** medium (coupling level not simulated; geometry certain).
|
||||||
|
|
||||||
|
### E-01 3V3_ETH is not switchable: the W5500 is powered on battery and during MCU reset (lesson F8 repeated)
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-E ("On V5 it was always-on and wasted battery"); lesson F8; R1/R3.
|
||||||
|
- **Evidence:** U12 (MP1584EN) pin 2 EN = `/SYS5V` = pin 7 VIN → always on whenever SYS5V exists (vehicle **and** battery). W5500 DS: 128 mA (100M link), 75 mA (10M), 13 mA power-down; reset current not specified. J10 is DNP on the PCB, but U11/U12 are populated, so the draw exists even without a jack. Firmware 0.6.0-eth holds RST low without 5 V, but RST is floating/pulled-up during MCU reset (E-02).
|
||||||
|
- **Consequence:** A permanent ≈ 0.05–0.6 W battery load (depending on link/reset state) through a light-load MP1584 and the boost — comparable to the whole 10-min duty-cycle average; exactly the V5 lesson.
|
||||||
|
- **Fix:** new net `/ETH_PWR_EN`: U12.2 (EN) → **U16 pad 54 PD2** (free) with **100 kΩ to GND (C25803)** (MP1584 EN threshold ≈ 1.2–1.6 V; 3.3 V drive OK) — off in MCU reset/standby and on battery. PB10 (pad 29) is the alternative free pin. Coordinate with the MCU auditor (free pins: PC5, PB10, PA9, PD2).
|
||||||
|
- **Effort:** both (1 resistor, 1 track)
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### E-02 /ETH_RST has no pull-down — and the 100 kΩ fix proposed elsewhere would not work against PA15's JTDI pull-up
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-E (RST with 100k pull-down); lesson F8; Review §4 item 6; ECO §F (`ETH_RST` 100 k); **also affects V5.6 `R112` 100 k**.
|
||||||
|
- **Evidence:** `/ETH_RST` = U11.37 + U16.50 (PA15) only. PA15 resets to JTDI with an **internal pull-up (30–50 kΩ)** active during and after reset until firmware reconfigures it (RM0383 §8.3.1). A 100 kΩ pull-down gives 3.3·100/(100+30…50) = **2.2–2.5 V** → W5500 RSTn reads HIGH (VIL ≤ 0.8 V) → chip out of reset during every MCU reset/DFU/bootloader. With **4.7 kΩ**: 3.3·4.7/(4.7+30…50) = **0.28–0.45 V** ✅; cost when driven high 0.7 mA.
|
||||||
|
- **Consequence:** W5500 active (up to 128 mA) whenever the MCU is in reset/DFU/bootloader — on battery that is the lesson-F8 drain; a V5.6 built with R112 = 100 k keeps the bug.
|
||||||
|
- **Fix:** add **4.7 kΩ 0603 (C23162, Basic) from /ETH_RST to GND** at U11.37. Tell V5.6: R112 100 k → 4.7 k. (With E-01 in place this becomes belt-and-braces, but keep it for vehicle-power resets.)
|
||||||
|
- **Effort:** schematic-only (+1 small footprint)
|
||||||
|
- **Confidence:** high on the mechanism; medium on the exact pull-up value range (ST datasheet 30/40/50 kΩ).
|
||||||
|
|
||||||
|
### E-03 W5500 crystal Y1: 10.8/13.7 mm from XO/XI, 22 mm crystal traces, load-cap mismatch
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-E (25 MHz crystal ≤ 5 mm, load caps vs CL); ECO §E6 (crystals ≤ 5 mm, R5); Phase-2 §5 row 6.
|
||||||
|
- **Evidence:** Y1 (C14872 = YXC X49SM25MSD2SC, HC-49S, **CL 20 pF, ±20 ppm**) at (91.5,65.5); pad edge → U11.31 XO **10.79 mm**, → U11.30 XI **13.74 mm**; `/ETH_XI` 22.98 mm, `/ETH_XO` 22.03 mm (0.25–0.5 mm, F.Cu); C95 1.0 mm from Y1, C96 **6.4 mm** from Y1; C95/C96 = **18 pF**. Effective CL ≈ (18 + ≈ 5 pF stray)/2 ≈ 11.6 pF vs 20 pF → frequency pulled high by ≈ **+70…110 ppm** (C1 7–10 fF, C0 4–5 pF assumed for HC-49S), plus ±20 ppm tolerance — W5500 requires ±30 ppm (DS), 100BASE-TX ±50 ppm. Also 63 × 25 MHz = 1575.000 MHz, 0.42 MHz from GPS L1 (inside the C/A main lobe); long crystal traces radiate that harmonic family (MCU HSE Y3 is also 25 MHz — MCU/EMC auditor).
|
||||||
|
- **Consequence:** Link errors/negotiation failures at temperature extremes; slow or marginal oscillator start; an avoidable radiator near L1.
|
||||||
|
- **Fix:** place Y1 ≤ 5 mm from U11.30/31 with C95/C96 at the crystal pads, ground guard; set **C95/C96 → 33 pF C0G 0603 (C1663, Basic)** → CL ≈ (33 + 4)/2 ≈ 18.5–19 pF for the 20 pF crystal (or use a 3225 25 MHz CL 18 pF part with 27 pF caps). Verify with a frequency counter (target ±10 ppm).
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** medium on the ppm number (crystal motional parameters assumed); high on geometry and CL mismatch.
|
||||||
|
|
||||||
|
### B-08 VBAT_MODEM feed: 0.5 mm neck into pins 55–57; 1 mm over 7 mm; no pour
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-B (track width/length per layer, drop at 2 A); SIMCom HD ("VBAT ≥ 3 mm" V1.03 / "≥ 2 mm" V1.00); DRC T15 rule (7 segments < 0.8 mm).
|
||||||
|
- **Evidence (`tracks.py`, `pathr.py`):** F.Cu 48.9 mm (0.25/0.5/1/1.5/2 mm) + In1 6.3 mm (0.5 mm, FB tap), 2 vias. Final feed: 0.5 mm × 2.5 mm into U19.55 then 0.5 mm × 2.0 mm along the pads to 56/57; 1.0 mm for ≈ 7 mm from C132 to C136. Resistance L20.2 → U19.55 = **12.5 mΩ** (→ U19.57 14.4 mΩ); C131 → U19.55 7.3 mΩ; drop at 2 A = **25–29 mV** (static, fine); SW_MODEM now 1.0 mm × 6.6 mm (was 0.25 mm on 25-Sep ✅).
|
||||||
|
- **Consequence:** Electrically acceptable DC drop; violates the vendor width rule and adds loop inductance between the bulk and the pins.
|
||||||
|
- **Fix (layout):** F.Cu pour ≥ 3 mm wide from L20.2 → C130 → C131 → C132–C136 → U19.55/56/57 (fan out to all three pads); C131 (polymer, B-02) within 5 mm of the pads.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### B-09 SIM interface details (J14 primary): 0 Ω instead of 22 Ω, ESD 22–25 mm from the holder, VDD cap 13.5 mm away, no ESD on VDD
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-B (SIM/eSIM); memory `drogheda-mff2-footprint` (Telcel will not supply MFF2 → J14 primary, U22 DNP); SIMCom A7670 HD Fig. 19.
|
||||||
|
- **Evidence:** J14 (JAE SF72S006, C2977286, populated) + R131–R134 0 Ω populated; U22 + R127–R130 DNP ✅. D23/D24/D25 (PESD5V0S1BA TECH PUBLIC clone, C2827694, bidirectional, capacitance not stated; Nexperia original 35 pF) sit 1.3–5.7 mm from U19 but **21.7–24.8 mm** from the J14 contacts; C126 (100 nF) 13.5 mm from J14.C1; `/SIM_VDD` has no clamp; total SIM trace lengths VDD 37.5 / DATA 46.9 / CLK 38.5 / RST 45.4 mm; USIM1_DET NC (intentional, hot-plug stays off) ✅; U22 die-pad zone crossed by `/SIMB_CLK` and `/SIMA_RST` on F.Cu (harmless while U22 is DNP).
|
||||||
|
- **Consequence:** Less ESD protection at the card (handled at assembly/service), more EMI/ringing on CLK than the reference.
|
||||||
|
- **Fix:** R132/R133/R134 (RST/CLK/DATA holder branch) → **22 Ω 0603 (C23345, Basic)**; add 100 nF 0402 (C1525) at J14.C1; move D23–D25 (or add an ESDA6V1W5-class array covering VDD) next to J14; keep F.Cu clear under U22's die-pad zone if MFF2 is ever fitted.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### B-10 Undefined idle levels on the modem interface; RTCM-tap series resistor too small
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-B (STATUS readback, back-powering, R106 tap).
|
||||||
|
- **Evidence:** U24 (74LVC2T45, VCCA = `/1V8_MODEM`) is in suspend (both ports Hi-Z) whenever the modem is off → `/MODEM_STATUS` (PC9) and `/DOUT_4G` float; `/DIN_4G` floats during the K1 transfer and when the F9P is off. R106 = 100 Ω between `/DOUT_4G` (U24 1B output) and PC7: if PC7 is ever mis-configured as an output, contention current ≈ 3.3 V/100 Ω = 33 mA (> STM32 25 mA pin limit).
|
||||||
|
- **Consequence:** PC9 can read "modem on" with the modem off unless firmware remembers the pull-down; possible pin stress on a firmware slip.
|
||||||
|
- **Fix:** **100 kΩ (C25803) `/MODEM_STATUS` → GND**; **100 kΩ `/DIN_4G` → /3V3** (UART idle high); **R106 100 Ω → 1 kΩ (C14676)** (ECO §B value; 1 kΩ × ≈ 5 pF = 5 ns, fine to 921 600 Bd).
|
||||||
|
- **Effort:** schematic-only (+2 small footprints)
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### B-11 No-connect flags on connected MCU pins U16.37 (PC6) and U16.38 (PC7)
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-B (USART6); ERC; memory `drogheda-einarboard-v6-phase12` (T2 added labels, old NC flags stayed).
|
||||||
|
- **Evidence:** `mcu_pins.csv`: PC6 `/USART6_TX` → K1.10, PC7 `/USART6_RX` → R106.2 — status `CONNECTED +NC_FLAG_ON_CONNECTED_PIN`; ERC marker "A pin with a no-connection flag is connected" (erc_summary line 73). Netlist and PCB are correct (both nets routed: 73.3 mm / 42.3 mm).
|
||||||
|
- **Consequence:** Cosmetic today; a future script/netlist tool that honours NC flags could drop the modem UART.
|
||||||
|
- **Fix:** delete the two NC flags at U16 pin coordinates (482.6, 431.8) and (482.6, 434.34); ERC should lose the marker.
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### C-05 GNSS RF line: 38 Ω, a DC trace 0.46 mm alongside for 10 mm, sparse via fence, ESD on a stub
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-C (antenna chain, 50 Ω geometry, ESD, DC block).
|
||||||
|
- **Evidence:** `/RF_GNSS` C143.2 → U18.2 = 22.7 mm F.Cu, w 0.50 mm, gap 0.15 mm, 100 % In1 GND beneath; FD solver **38.4 Ω bare / 35.2 Ω masked** on JLC7628 (50.6/45.6 Ω on the file stack; Wadell CPWG 37.5–41 Ω); east side has no coplanar ground from y 113.45 to 123.25 because `/VCC_RF_GNSS` runs parallel at **0.46 mm** edge gap for 9.8 mm; 1 GND via within 1.5 mm over 27 mm (λg/20 at L1 = 5.7 mm). J12 → C143 0.56 mm ✅ (DC block at the connector), L21 bias tap 1.9 mm ✅, but D27 sits at the end of a 2.8 mm stub beyond C143 (≈ 1–1.2 pF with the stub → RL ≈ 11 dB, ≈ 0.4 dB) . L21 68 nH has SRF 1 GHz (C162555) → still a −j455 Ω shunt at L1 and −j1042 Ω at L2 (< 0.02 dB) ✅ (u-blox recommends 120 nH).
|
||||||
|
- **Consequence:** ≈ 0.1–0.4 dB loss after the antenna LNA (negligible for system NF with a ≥ 25 dB active antenna); the parallel VCC_RF trace is the more relevant coupling path.
|
||||||
|
- **Fix (layout):** w 0.30 / gap 0.20 mm (as B-05); move the bias feed (now `/ANT_BIAS` from C-01) away from the RF line with GND pour between; put D27 on the J12 pad (stub-less); GND vias both sides ≤ 5 mm; 2 vias per J12 GND pad. Optional: C143 → 47 pF C0G 0402 (series-resonant near L1) instead of 100 nF X7R.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### C-06 F9P back-powering through I/O when /3V3_GNSS is off
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-C; ZED-F9P DS Table 14 (Vin ≤ VCC + 0.5 V when VCC ≤ 3.1 V).
|
||||||
|
- **Evidence:** U18.26 RXD2 is driven directly by U24 1B (`/DOUT_4G`, 3.3 V, VCCB = always-on /3V3) whenever the modem is on; U18.43 RXD by PA2 (USART2 TX idles high); U18.49 RESET_N by PC12 (R105 pull-up goes to the switched rail); TIMEPULSE/RTK_STAT inputs on the MCU side could have pull-ups.
|
||||||
|
- **Consequence:** Any "F9P off, modem on" state (e.g. a PWR_CTRL cycle for GNSS recovery) injects current through the F9P's input clamps.
|
||||||
|
- **Fix:** firmware rule (below) + optional **1 kΩ (C14676) in series at U18.26** (split `/DOUT_4G`: U24.7 + R106 | 1 kΩ → U18.26) to cap injection at ≈ 2.8 mA.
|
||||||
|
- **Effort:** firmware-only (+ optional schematic)
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### C-07 No test pad on SAFEBOOT_N (F9P firmware recovery)
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-C (SAFEBOOT_N test pad?); memory `drogheda-v6-lte-island` (P17/F9P USB removed, u-center only via J11 passthrough).
|
||||||
|
- **Evidence:** U18.50 SAFEBOOT_N NC (no pad); V_USB/USB_DM/USB_DP NC; the only access is UART1 through the MCU bridge.
|
||||||
|
- **Consequence:** A failed F9P firmware update over the passthrough cannot be recovered (safeboot needs SAFEBOOT_N low at power-up).
|
||||||
|
- **Fix:** add a 1 mm test pad on U18.50 (and one on U18.49 RESET_N) next to a GND pad; no resistor.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### E-04 W5500 TOCAP and 1V2O capacitor values do not follow the datasheet
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-E (analog/digital supply decoupling); W5500 DS pin table.
|
||||||
|
- **Evidence:** C90 on `/ETH_TOCAP` (U11.20) = **10 µF** (DS: 4.7 µF; schematic note "VERIFY value vs ref"); C91 on `/ETH_1V2` (U11.22) = **4.7 µF** (DS: **10 nF**, 470× larger). C90 4.4 mm, C91 5.5 mm from their pins. AVDD pins 15/17/28 have 100 nF at 1.3–1.5 mm; pins 4/8/11/21 rely on C94 10 µF (7.1 mm) / C102 22 µF (5.8 mm).
|
||||||
|
- **Consequence:** Internal 1.2 V regulator operated outside its specified load capacitance (start-up/stability risk); weaker HF decoupling.
|
||||||
|
- **Fix:** C91 → **10 nF 0603 X7R (C1589)**; C90 → **4.7 µF 0805 (C1779, the part now on C91)**; both ≤ 2 mm from their pins; add 100 nF (C14663) at AVDD pins 4/8 and 11/21 pairs.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### E-05 J10 is DNP on the PCB but populated in the schematic, with a different footprint library nickname
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-E (magnetics/RJ45); `sch_pcb_sync.md`; pre-fab audit §7.
|
||||||
|
- **Evidence:** schematic footprint `Connector_RJ45:RJ45_Hanrun_HR911105A_Horizontal` (nickname not in fp-lib-table) vs PCB `Connector_RJ:…`; DNP no (sch) / yes (pcb). LCSC C12074 set. MAGJACK_NO_POUR keepout present ✅. LED pin mapping (9–12) still carries "VERIFY" in the schematic.
|
||||||
|
- **Consequence:** BOM from the board omits J10 (no Ethernet on the prototypes); BOM from the schematic includes it; Update-PCB either fails the footprint lookup or re-populates J10.
|
||||||
|
- **Fix:** Leo decides populate/DNP for the 5 prototypes; then set schematic footprint to `Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal` and the same DNP state in both; verify LED pins against the HR911105A drawing.
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### E-06 Ethernet pairs not coupled and split across layers; no line-side ESD; J10 pin 8 NC
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-E (TX/RX diff-pair routing; ESD).
|
||||||
|
- **Evidence:** TXP F.Cu 3.9 + In1 11.7 mm (1 via) vs TXN F.Cu 21.5 mm → coupled 0.3 mm; RXP F 5.0 + In1 11.2 vs RXN F 5.8 + In1 14.9 → coupled 1.2 mm; skew 5.9 mm (TX) / 4.4 mm (RX) ≈ 30–40 ps (irrelevant at 100BASE-TX); no ESD array on TX/RX; J10.8 NC (on common HR911105A drawings pin 8 is the shield/Bob-Smith node — verify). Terminations: TX 49.9 Ω to 3V3_ETH + TCT (J10.4) on 3V3_ETH; RX 49.9 Ω to RCT + 6.8 nF ✅ (W5500 reference topology). EXRES1 R83 12.4 k 1 % (C103261) 5.0 mm from pin 10 ✅; VBG open ✅; RSVD23 → GND, 38–42 open ✅; PMODE all high via R84 ✅.
|
||||||
|
- **Consequence:** Common-mode emission from the unbalanced pairs; slightly lower ESD robustness on cabled installations.
|
||||||
|
- **Fix (layout):** route each pair coupled on F.Cu only (100 Ω diff), ≤ 1 via pair, keep In1 unbroken; optional low-cap array (e.g. SRV05-4 class) between magjack and U11; tie J10.8 per the HR911105A drawing.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** medium (J10.8 function not confirmed from the Hanrun PDF).
|
||||||
|
|
||||||
|
### B-12 Stackup and netclasses: generic stack in the file; RF and PWR_MODEM netclasses missing
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Block / refs:** `evidence/stackup.md` §1, §4; memory `drogheda-v6-lte-island` ("RF 0.35 mm netclass + PWR_MODEM 1.5 mm") — both lost; INDEX gotcha #2.
|
||||||
|
- **Evidence:** file stack 3 × 0.48 mm εr 4.5; RF traces drawn 0.50 mm (≈ 50 Ω only on that fictitious stack: FD 50.6 Ω); `/VBAT_MODEM`, `/VIN_MODEM`, RF nets resolve to Default (0.15 mm rule).
|
||||||
|
- **Fix:** set the board stackup to JLC04161H-7628 values; recreate netclasses `RF` (0.30/0.20, no autoroute) and `PWR_MODEM` (1.5 mm) and assign by exact net names (`/RF_LTE`, `/RF_ANT_LTE`, `/RF_GNSS`, `/RF_ANT_GNSS`; `/VBAT_MODEM`, `/VIN_MODEM`, `/SW_MODEM`); order impedance control.
|
||||||
|
- **Effort:** layout (project settings)
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### B-13 K1 fail-safe premise is obsolete on v6
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Block / refs:** Phase-2 Block T; Phase-1 §1.4; memory `drogheda-epct-telemetria`.
|
||||||
|
- **Evidence:** K1 NC = F9P TXD2 → modem RXD, NO = PC6. The "MCU dead ⇒ receiver GGA reaches the caster ⇒ corrections keep flowing" logic assumed the ArduSimple NTRIP Master's own NTRIP client. The A7670SA has none (brief §2.5), and an MCU reset also switches the modem off (R113 pulls EN low) and releases K1 (R41). Coil 5 V × 30 mA = 150 mW whenever Mode B (now the normal mode) is held.
|
||||||
|
- **Fix:** none for v6 (no harm); firmware energises K1 only while the modem is on; consider replacing K1 by a direct PC6 → DIN_4G link in v6.1.
|
||||||
|
- **Effort:** firmware-only
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### B-14 Everything the modem prints reaches the F9P's UART2 (hard-wired RTCM path)
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Block / refs:** §4-B (RTCM tap, contention); Phase-1 §2/§4.
|
||||||
|
- **Evidence:** `/DOUT_4G` = U24 1B → U18.26 RXD2 **and** R106 → PC7. No contention (single driver U24) ✅. But AT responses/URCs and any non-transparent socket framing (`+RECEIVE…`/`+CIPRXGET` headers) are fed to the receiver; the MCU can read RTCM age from GGA field 13 (USART2) and raw RTCM3 frames on PC7 ✅.
|
||||||
|
- **Fix (firmware):** F9P UART2 in-protocol = RTCM3 only, baud = modem baud (115 200) saved to BBR+flash; caster socket in transparent mode (AT+CIPMODE=1) or, if multi-socket is needed for `$PHLG`, disable RTCM on UART2 and forward re-assembled RTCM from the MCU on USART2 TX → F9P UART1 (RTCM input enabled by default).
|
||||||
|
- **Effort:** firmware-only
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### B-15 R107/R108 "bypass the shifter" footprints cannot work
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:** DNP 0 Ω across U24 ch1 (`/DOUT_4G_M`↔`/DOUT_4G`) and U23 ch1. Fitted with the shifter removed they put 1.8 V on F9P RXD2 (VIH = 0.8·VCC = 2.64 V → no data) and 3.3 V on modem RXD (abs max 2.0 V, HD V1.03 Table 41).
|
||||||
|
- **Fix:** delete them (or add a schematic note "never fit").
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### B-16 Cold start on battery — modem-side numbers (the requested explicit statement)
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Block / refs:** §4-B cold-start test; ECO R1; `…Modem-on-battery_Diagnosis`; LTC4040 DS; AP64350 DS.
|
||||||
|
- **Evidence (`budget.py`; assumptions: VSYS 4.79 V, U6→D21 41.7 mΩ + D21→U20 5.7 mΩ measured, η(U20) 90 %, η(boost) 87 %, non-modem MAIN5V load 0.38 A incl. W5500 and K1):**
|
||||||
|
|
||||||
|
| D21 / option | Modem load | VIN(U20) | I(MAIN5V) | vs LTC4040 2.5 A | P_batt | I_batt @3.6 / 3.2 V | Vout max (98 % D) |
|
||||||
|
|---|---|---|---|---|---|---|---|
|
||||||
|
| PMEG3050EP (as is) | LTE 23 dBm 0.67 A | 4.54 V | 1.00 A | OK | 5.5 W | 1.53 / 1.73 A | 4.38 V |
|
||||||
|
| PMEG3050EP | GSM burst 2.0 A | 4.44 V | 2.28 A | OK (9 %) | 12.6 W | 3.49 / 3.93 A | 4.15 V |
|
||||||
|
| PMEG3050EP | 2.8 A (A7670 HD V1.00 peak) | 4.38 V | 3.08 A | **over** | 16.9 W | 4.71 / 5.29 A | 4.02 V |
|
||||||
|
| PMEG6045ETPX (B-01 A) | GSM 2.0 A | 4.27 V | 2.36 A | OK (6 %) | 13.0 W | 3.61 / 4.06 A | 3.98 V |
|
||||||
|
| link, no diode (B-01 B) | GSM 2.0 A | 4.70 V | 2.17 A | OK (13 %) | 12.0 W | 3.33 / 3.74 A | 4.41 V |
|
||||||
|
| link (B-01 B) | LTE 1.0 A | 4.75 V | 1.27 A | OK | 7.0 W | 1.94 / 2.18 A | 4.55 V |
|
||||||
|
|
||||||
|
AP64350 UVLO rising 3.5–3.7 V / falling ≈ 3.1–3.3 V vs VIN ≥ 4.2 V in every case (V5.5's MP1584 had ≈ 0.1 V margin). Boost ILIM(BST) 5.5–7.5 A vs ≤ 4.1 A battery current in the 2 A cases. AP64350 soft-start 2 ms → inrush 456 µF·3.8 V/2 ms = 0.87 A.
|
||||||
|
- **Statement:** **Yes — v6 can bring the modem up from the LTC4040 boost alone**, provided (1) the modem is enabled only after the F9P rail has settled, (2) the modem is LTE-only on battery (GSM 2.8 A peaks exceed the 2.5 A backup limit), (3) the W5500 is off (E-01), and (4) the VBAT bank is fixed (B-02); otherwise LTE-burst droop, not UVLO, is the failure mode. Option B of B-01 adds ≈ 0.27 V of headroom; option A removes ≈ 0.16 V. Max duty of the AP64350 is not stated in DS41976 — bench-check VBAT at MAIN5V = 4.6 V, 2 A load.
|
||||||
|
- **Hardware path to remove modem power (R2):** yes — EN low stops U20; VBAT decays through R112 1 kΩ with τ = 1 kΩ × 456 µF = 0.46 s → 47 mV after the 2 s HARD_CYCLE. PWRKEY (Q20) and RESET (Q21) are the soft steps above it.
|
||||||
|
- **Confidence:** medium (efficiencies and non-modem load assumed; power auditor owns the full budget).
|
||||||
|
|
||||||
|
### C-08 Identity: no `$GPTXT H00xx` source on v6; `$PHID` exists only on the Ethernet socket
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Block / refs:** §4-C (lesson F9); Review F9; pre-fab audit (does not cover identity).
|
||||||
|
- **Evidence:** H00xx came from the ArduSimple NTRIP Master firmware (retired). The A7670SA and the F9P (only `$GxTXT` banners) emit no unit ID. Firmware 0.6.0-eth builds `$PHID,<96-bit UID>,<fw>,<board>,<MAC>,<up_s>` from `HAL_GetUIDw0..2` (L718–724) but sends it **only** in `ethSendId()` on the TCP mirror.
|
||||||
|
- **Fix:** firmware 0.7.x sends `$PHID` on the modem uplink at every connect and every 5 min; backend `retranslator` maps UID → H-number before v6 ships.
|
||||||
|
- **Effort:** firmware-only (+ backend)
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### C-09 V_BCKP on the always-on /3V3
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:** U18.36 = `/3V3` (ungated) → hot start after each 10-min off (45 µA, DS Table 15) ✅; its decoupler Cu4 (100 nF, /3V3) is 4.06 mm from pin 36 (Copper Plan asked "at the pin").
|
||||||
|
- **Fix:** move Cu4 to ≤ 2 mm (optional).
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
### E-07 PoE
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:** no PoE PD/controller; J10.7/J10.8 NC; firmware prints "SIN PoE". Consistent with the recorded decision (external splitter if ever needed; v6.1 feature).
|
||||||
|
- **Effort:** —
|
||||||
|
- **Confidence:** high.
|
||||||
|
|
||||||
|
## Pass checks
|
||||||
|
| Check | Evidence (one line) | Result |
|
||||||
|
|---|---|---|
|
||||||
|
| A7670SA footprint/pin numbering | LGA-124 matches A7672X/A7670X HD V1.03 (VBAT 55–57, RF_ANT 60, STATUS 66, VDD_1V8 15, UART 9/10, USIM 30–34) | ✅ |
|
||||||
|
| U20 EN default OFF | EN 1.5 µA pull-up × R113 100 k = 0.15 V < 1.03 V EN-low | ✅ |
|
||||||
|
| U20 output set-point | 75 k/20 k → 3.80 V; worst 3.67–3.94 V (±1 % R, ±2 % VFB) inside 3.4–4.2 V | ✅ |
|
||||||
|
| U20 frequency | R117 200 k → 500 kHz (RT = 100000/f); t_on at 40 V = 190 ns > 100 ns min | ✅ |
|
||||||
|
| L20 saturation | MWSA0804S family: 8.2 µH part Isat 8.7 A → 4.7 µH ≥ 8.7 A vs peak 2.7 A and 5.75 A HS limit | ✅ (medium) |
|
||||||
|
| L20/C129/COMP/RT placement | L20 2.24 mm, BST 1.8 mm, COMP 0.72 mm, RT 1.44 mm from pins | ✅ |
|
||||||
|
| SW_MODEM copper | 1.0 mm × 6.6 mm, 2.2 mΩ (was 0.25 mm × 23 mm on 25-Sep) | ✅ |
|
||||||
|
| VBAT HF ceramics | C133–C136 1.7–2.7 mm, C132 4.1 mm from VBAT pads | ✅ |
|
||||||
|
| D22 polarity | SMAJ5.0A pad 1 = cathode (silk band) on /VBAT_MODEM | ✅ |
|
||||||
|
| VBAT bleed for HARD_CYCLE | τ = 0.46 s → 47 mV after 2 s EN-low | ✅ |
|
||||||
|
| PWRKEY / RESET drive | 2N7002 open-drain, 100 k gate pull-downs, no caps (≤ 100 nF rule) | ✅ |
|
||||||
|
| Level shifting | U23 DIR = GND (B→A, 3.3 → 1.8 V into modem RXD), U24 DIR = VCCA (A→B TXD + STATUS), unused 2B tied GND | ✅ |
|
||||||
|
| Back-powering of the modem | 74LVC2T45 suspend/Ioff when VCCA = 0 (both ports Hi-Z); PWRKEY/RESET open-drain; only 1.8 V on `_M` nets (abs max 2.0 V) | ✅ |
|
||||||
|
| STATUS readback | U24 2A→2B, VOH ≈ 3.3 V vs PC9 VIH 2.31 V | ✅ (float when off → B-10) |
|
||||||
|
| UART contention | /DOUT_4G single driver (U24); /DIN_4G via SPDT break-before-make K1 | ✅ |
|
||||||
|
| RTCM visibility | GGA field 13 on USART2 (PA3) + raw RTCM3 on USART6 RX (PC7) | ✅ |
|
||||||
|
| USART allocation | USART6 PC6/PC7 (AF8), USART2 PA2/PA3, USART1 RX PA10; PA9 free | ✅ |
|
||||||
|
| USB_BOOT | TP8 floating (not pulled low at power-up) | ✅ |
|
||||||
|
| SIM population | J14 + R131–R134 fitted, U22 + R127–R130 DNP; USIM1_DET NC (hot-plug off) | ✅ |
|
||||||
|
| LTE π-pad | R118 0 Ω + C146/C147 DNP at J13 (SIMCom Fig. 25) | ✅ |
|
||||||
|
| Island separation | J13↔J12 150.3 mm, U19↔U18 108.9 mm | ✅ |
|
||||||
|
| GNSS DC block / bias-T | C143 0.56 mm from J12; L21 −j455 Ω at L1 despite 1 GHz SRF | ✅ |
|
||||||
|
| D27 on GNSS line | unidirectional 5 V, cathode on line, bias 3.2 V < VRWM | ✅ |
|
||||||
|
| F9P decoupling | C121/C122 1.7 mm, C120/C124 2.4–2.5 mm, U21 4.4 mm from VCC pins | ✅ |
|
||||||
|
| F9P control/status wiring | RESET_N PC12 + R105 10 k; TIMEPULSE PA7 (TIM3_CH2); RTK_STAT PC3; D_SEL open = UART; UART1↔USART2; UART2 RX←modem, TX→PA10/K1 | ✅ |
|
||||||
|
| V_BCKP | on always-on /3V3, 45 µA | ✅ |
|
||||||
|
| No H00xx identity source | no ArduSimple module on v6 | ✅ (→ C-08) |
|
||||||
|
| W5500 SPI/INT | SPI2 PB12–15 (AF5), INT PC0 (BOOT1 trap avoided) | ✅ |
|
||||||
|
| W5500 straps/analog | PMODE all high; EXRES1 12.4 k 1 %; VBG open; RSVD23 GND; 38–42 open | ✅ |
|
||||||
|
| Ethernet termination | TX 49.9 Ω to 3V3_ETH + TCT; RX 49.9 Ω to RCT + 6.8 nF | ✅ |
|
||||||
|
| Magjack keepout | MAGJACK_NO_POUR rule area on all layers (vias/pour not allowed) | ✅ |
|
||||||
|
| PoE | none, documented | ✅ (note) |
|
||||||
|
|
||||||
|
## Review-vs-Lessons §4 checklist items re-verified
|
||||||
|
- **#4 F1 modem rail integrity** → partially improved, not closed. Now: SW_MODEM 1.0 mm ✅ (was 0.25), VIN_MODEM 0.3–0.8 mm (was 0.25/0.5), L20 2.24 mm from U20 ✅ (pre-fab: 9.5 mm); still C131 8.7 mm / C130 16.3 mm, VBAT neck 0.5 mm, no 2 × 22 µF at U20.2; **new: bulk is a GP electrolytic (B-02), input on unfused /24V with a 30 V OR-diode (B-01), 1 via under U19 (B-04)**.
|
||||||
|
- **#6 ETH_RST pull-down** → still missing; the proposed 100 k would not work (PA15 JTDI pull-up) → 4.7 k (E-02); plus 3V3_ETH gating (E-01).
|
||||||
|
- **#7 J9 ESD** → still missing (B-07).
|
||||||
|
- **#11 `$PHID` identity** → firmware sends it on Ethernet only (C-08).
|
||||||
|
- **#12 firmware v6 pins** → no `board_v6.h` yet; pin list below.
|
||||||
|
- **#13 PoE decision** → no PoE in hardware (E-07); record in the schematic block note if not done.
|
||||||
|
- **#14 AP64350 compensation** → evaluated: current values are the 5 V Table 1 row and do not fit either the ceramic-only or the polymer bank → new values in B-02.
|
||||||
|
- **#15 bench validation** → still pending; add: VBAT load step (B-02), /3V3_GNSS ramp (C-02), antenna short test (C-01), D21 leakage hot (B-01 A only).
|
||||||
|
- Review §2 "Switcher EP vias (U20)" → still 0 (B-04/B-06).
|
||||||
|
|
||||||
|
## Requirements input R1–R5
|
||||||
|
- **R1 (10 min off → wake → report, on battery):** hardware path exists (U20 on its own EN, D21 from the boost, STATUS on PC9, UVLO margin ≥ 0.9 V). **Needs change B-02** (VBAT bank + compensation) and **B-01** (option B preferred: +0.27 V headroom); **C-02** for reliable F9P restarts every cycle; **E-01** for battery energy; firmware sequencing (LTE-only on battery).
|
||||||
|
- **R2 (modem never left dark; MCU can power-cycle it):** **satisfied by hardware** (EN with R113 pull-down = full power removal, τ 0.46 s bleed; PWRKEY/RESET via Q20/Q21; STATUS); B-10 pull-down makes STATUS unambiguous; firmware ladder below.
|
||||||
|
- **R3 (report while on battery):** budget OK with LTE-only (≈ 1.0–1.3 A on MAIN5V); GSM bursts 2.2–2.4 A sit at the 2.5 A backup limit. Link robustness **needs B-02, B-03, B-04** (and B-05).
|
||||||
|
- **R4 (temperature management):** modem temperature via AT+CPMUTEMP (firmware); **B-04** is the modem's heat path; no board sensor near U19 (thermal auditor).
|
||||||
|
- **R5 (EMC list):** item 5 J9 ESD → **B-07**; item 6 crystals ≤ 5 mm → **E-03** (Y1); item 4 hot loops → **B-06** (U20); plus RF/plane items **B-05**, **C-04**.
|
||||||
|
|
||||||
|
## Firmware implications (things board_v6.h / FW 0.7.x must do)
|
||||||
|
- **Pins:** `PIN_MODEM_PWR_EN PC10` (high = on; R113 pulls off), `PIN_MODEM_PWRKEY PC8` (high = PWRKEY asserted low via Q20), `PIN_MODEM_RST PC11` (high = RESET asserted via Q21), `PIN_MODEM_STATUS PC9` (input, pull-down), modem UART = **USART6 PC6 TX / PC7 RX**, `PIN_BYP_CTRL PB5` (K1), F9P UART1 = USART2 PA2/PA3, F9P UART2 TX tap = USART1 RX PA10 (PA9 unused), `PIN_GNSS_RESET_N PC12` (**open-drain only**), `PIN_GNSS_TIMEPULSE PA7` (TIM3_CH2 capture), `PIN_GNSS_RTK_STAT PC3`, `PIN_GNSS_ANT_DETECT PC1` / `PIN_GNSS_ANT_SHORT_N PC2` (inputs, no pull-ups; meaningful only after C-01), W5500 as V5 (SPI2 PB12–15, INT PC0, RST PA15) + `PIN_ETH_PWR_EN PD2` if E-01 is adopted.
|
||||||
|
- **Modem power-up (duty window):** PWR_CTRL high → F9P settled (≥ 1–4 s) → check BAT_SENSE ≥ 3.4 V → W5500 off → MODEM_PWR_EN high → wait ≥ 100 ms (2 ms soft-start + bank charge) → PWRKEY asserted 100–500 ms (≥ 50 ms) → wait STATUS high (typ 7–11.2 s, timeout 20 s) → BYP_CTRL high (Mode B) → AT sync at 115 200 → **AT+CNMP=38 (LTE-only) on battery** → attach/NTRIP/report → ≥ 2 `$PHLG` with pwr=BATT → power-down.
|
||||||
|
- **Modem power-down:** AT+CPOF (or PWRKEY asserted ≥ 2.5 s) → wait STATUS low (≤ ≈ 2–3 s) → MODEM_PWR_EN low → hold ≥ 2 s → BYP_CTRL low → PWR_CTRL low. **Never** have PWR_CTRL low while MODEM_PWR_EN is high (C-06).
|
||||||
|
- **Recovery ladder (vehicle or battery, modem only):** AT timeout → RESET asserted ≈ 2.5 s (HD V1.03 Table 12) → PWRKEY off/on → HARD_CYCLE (EN low ≥ 2 s) → 3 strikes → log `MODEM_DARK`, retry next window; never cycle PWR_CTRL for a link problem. Every MCU reset power-cycles the modem (R113) → re-run the full sequence after reset.
|
||||||
|
- **Modem watch:** replace the V5 `sag5` heuristic (with the current D20 feed the modem draws from 24 V, not VEH5V) by STATUS + AT responses + RTCM byte count on PC7; VBAT via AT+CBC, temperature via AT+CPMUTEMP (no ADC on VBAT_MODEM).
|
||||||
|
- **I/O discipline:** modem off → disable USART6, PC7 analog, PC9 pull-down; F9P off → PA2 Hi-Z/analog, PC12 Hi-Z, no pull-ups on PA7/PC3/PC1/PC2; USIM hot-plug stays disabled (CSW/DSW NC).
|
||||||
|
- **F9P configuration (BBR + flash):** UART2 baud = modem baud (115 200), UART2 in-protocol RTCM3 only (UBX/NMEA/SPARTN off), UART2 out = NMEA GGA only if the K1-NC path is still wanted; UART1 NMEA/UBX for the MCU; after C-01: CFG-HW-ANT_CFG_VOLTCTRL/SHORTDET = 1; prefer UBX-CFG-RST over RESET_N; u-center passthrough must follow CDC line-coding → USART2 baud.
|
||||||
|
- **NTRIP transport:** transparent caster socket (AT+CIPMODE=1) or MCU re-assembly → USART2 → F9P UART1 (B-14); RTCM age from GGA field 13 and the RTCM3 frame walker on PC7.
|
||||||
|
- **Identity:** `$PHID` (96-bit UID) on the modem uplink at connect + every 5 min (C-08).
|
||||||
|
- **Ethernet:** ETH_PWR_EN low on battery and at boot until needed; RSTn low ≥ 500 µs before release; keep SPI2 pins low/Hi-Z while 3V3_ETH is off.
|
||||||
|
- **K1:** energise only while the modem is on (150 mW coil).
|
||||||
|
|
||||||
|
## Inputs needed from Leo
|
||||||
|
1. Vehicle classes in the fleet (12 V only, or 24 V trucks/RTGs?) and the max steady/transient voltage you want to survive → decides B-01 option A vs B (assumed: 9–36 V per T9, 24 V systems present).
|
||||||
|
2. Is 2G fallback required **on battery**? (assumed no → LTE-only on battery; GSM bursts exceed the backup limit.)
|
||||||
|
3. GNSS antenna model: bias voltage range and current (assumed 3.0–3.3 V accepted, ≤ 30 mA → 75 mA limit fits).
|
||||||
|
4. Ethernet on the 5 prototypes: populate J10 or not (E-05)?
|
||||||
|
5. Will technicians use J9 (modem USB) in the field? (sets how hard to push B-07; assumed yes, occasionally.)
|
||||||
|
6. Result of gate T1 (max cabinet `tntc`) — v6 has no heatsink clamp hole near U19 (MH11 of the brief is gone).
|
||||||
|
7. Fab order: JLC04161H-7628 with impedance control and ENIG (assumed; required for the RF numbers above).
|
||||||
@ -0,0 +1,280 @@
|
|||||||
|
# §4-D MCU pin map + §4-G Connectors and harness — v6 audit findings
|
||||||
|
Snapshot: sch ecee9fed… / pcb 6ddec80d… (evidence pack 2026-09-28)
|
||||||
|
|
||||||
|
Companion deliverable: `findings/pinmap-v6.md` (64/64 pins, conflicts, boot/debug, firmware delta, draft `board_v6.h`).
|
||||||
|
|
||||||
|
## Sources read
|
||||||
|
- Brief/rules: `findings/_COMMON_BRIEF.md`; master brief §3–§5, §4-D, §4-G; `INDEX.md`; `evidence/MANIFEST.md`.
|
||||||
|
- Evidence: `mcu_pins.csv`, `nets.json`, `ref_pins.json`, `components.csv`, `ic_pins_U6/U10/U13/U18/U23/U24/U26.csv`, `pcb_pads.csv`, `pcb_footprints.csv`, `pcb_tracks.csv`, `net_routing_summary.csv`, `clearance_24v_by_net_layer.csv`, `outline_and_holes.md`, `sch_pcb_sync.md`, `erc_summary.md`, `cpl.csv`, `firmware_pins.md/.csv`, `firmware_constants.csv`, `ref_versions/v5asfab_*`, `v56_*`.
|
||||||
|
- Source files: `src/hbox-watchdog-v6.kicad_pcb` (silk text, footprint pads, parsed with `kisexp.py`), `src/v5_current/hbox-watchdog-v5.kicad_pcb` (V5.5 as-fabbed PCB: holes, connectors, crystal distances), `src/Drogheda.pretty/JAE_SIM_Card_SF72S006.kicad_mod`, `src/fw/board_v5.h`, `board_v4.h`, `hbox_v5_bringup.ino` 0.6.0, `CHANGELOG.md`.
|
||||||
|
- Docs: Review-vs-V5.5-Lessons (§1 F8, §4), V5.6 ECO (§0, §B, §E, §F, §H), V5.6 Change Report (§6.10 junction incident), V4/V5 Pinmap Audit FW 0.5.4, Phase-1 NTRIP spec, Phase-2 Schematic Delta (§3 pin allocation, Block N/O), project doc 2026-09-25 Pre-Fab Audit.
|
||||||
|
- Memory: `drogheda-einarboard-30-mcu-integration`, `-harness`, `-j1-mirror`, `drogheda-firmware-por-tarjeta`, `drogheda-einarboard-v6-brief` (P-renumber map), `drogheda-fan-policy`, `drogheda-epct-telemetria`, `drogheda-v6-zed-f9p-integration`, `drogheda-backup-lowpower`, `preferences`.
|
||||||
|
- Datasheets: **ST DS10314 (DocID026289 Rev 7)**: Table 8 (pins, FT/TC), Table 11/12 (abs max, injection), Table 37/38 (HSE/LSE Gm_crit_max), Table 52 (injection susceptibility), Table 53 (VIL/VIH, RPU incl. PA10 7–14 kΩ). **ST STM32_open_pin_data** (CubeMX DB: `STM32F411R(C-E)Tx.xml`, `GPIO-STM32F411_gpio_v1_0_Modes.xml`) for every AF number. **LTC4040 DS (4040fb)** pin functions (CLPROG = 32 × (VIN − CLN), PFO/CHRG/FAULT open-drain 6 V). **ZED-F9P integration manual UBX-18010802**, pin table (ANT_DETECT = I, ANT_SHORT_N = I, ANT_OFF = O). JLC parts via `get_jlcpcb_part` (C14872, C32346, C48615, C2901684, C9006, C1679, C38523, C1644, C23162, C25803, C25804, C4190, C19726, C3040595, C14663, C1588, C7519, C2827694, C224019, C5160226, C144394, C424683, C12074, C2238, C125103).
|
||||||
|
|
||||||
|
## Findings
|
||||||
|
|
||||||
|
### D-01 Modem-side level shifter back-powers the unpowered ZED-F9P through RXD2
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-D, §4-C; lesson = FW 0.5.5/0.5.6 back-feed (PA2 kept the simpleRTK2B "alive and dead"); memory `drogheda-v6-zed-f9p-integration` (VCC ramp window); U24, U18, R106, Rdfu1, U16 PA10/PC7/PA2/PC12
|
||||||
|
- **Evidence:** U24 74LVC2T45: VCC(A) = /1V8_MODEM (modem VDD_EXT), **VCC(B) = /3V3 (always on)**, DIR = VCC(A), so A→B. 1B drives **/DOUT_4G = {U24.7, R106.1, R107.2 (DNP), U18.26 RXD2}**. The F9P rail is switched: /3V3_GNSS = U21 output from /SW_5V (PA1 → Q5 → Q1). When the modem is booted (VDD_EXT up) and PA1 is LOW, U24 holds /DOUT_4G at the modem UART idle level (HIGH ≈ 3.3 V, 74LVC push-pull, ±24 mA class) straight into the unpowered U18.26. The only limit is the F9P's input ESD diode to VCC. ZED-F9P abs max input = VCC + 0.5 V (UBX-21044850), so at VCC = 0 the limit is exceeded by ≈ 2.8 V. Smaller paths into the same receiver: Rdfu1 22 k → /3V3 on /USART1_RX (U18.27 TXD2) ≈ (3.3 − 0.6)/22 k = 0.12 mA; plus PA10's internal pull-up, which is **7–14 kΩ on PA10** (DS10314 Table 53, OTG_FS_ID), not 40 kΩ: 0.5 mA if USART1 RX is left pulled up; PC7 pull-up via R106 (≈ 70 µA); PA2 and PC12 if driven HIGH. Firmware can avoid the U24 path only by never having the modem on while the F9P is off. That rules out F9P-only recovery cycles with the modem registered (REC_NMEA → `PWR_CTRL` cycle) and any modem-only reporting window.
|
||||||
|
- **Consequence:** the F9P rail sits pre-biased (≈ 2–2.7 V). The receiver neither powers down nor gets a clean ramp inside the 20–8000 µs/V window, so F9P power-cycle recovery silently fails. This is the V5.5 failure mode, now in hardware, and it also stresses the RXD2 ESD structure.
|
||||||
|
- **Fix:** insert **U27 = 74LVC1G125 (C3040595, SOT-23-5, Ioff/partial-power-down) powered from /3V3_GNSS**: A = /DOUT_4G, Y = new net /DOUT_4G_F9P → U18.26, OE# = GND, 100 nF (C14663) at VCC. With the F9P off, Y is hi-Z and A tolerates 3.3 V. PC7 and R106 stay on /DOUT_4G. Minimum alternative (layout only, no new IC): split the net with **10 kΩ 0603 (C25804) in series at U18.26**. That caps injection at ≤ 0.2 mA; τ = 10 k × ≈ 5 pF = 50 ns, fine at 115 200–460 800 Bd. **Rdfu1 22 k → 100 k (C25803)**: back-feed ≤ 27 µA, and PA10 still sits at a defined idle-high for ROM-DFU noise immunity. Firmware rules in `pinmap-v6.md` §2.5.
|
||||||
|
- **Effort:** both (1 IC + 1 cap, or 1 resistor; small reroute at U18.26)
|
||||||
|
- **Confidence:** high on the path (netlist + 74LVC2T45 supply topology). Medium on the magnitude, because the F9P ESD/rail loading is not published. Scoping /3V3_GNSS with the modem on and PA1 LOW on the first article would confirm it.
|
||||||
|
|
||||||
|
### D-06 Raw ignition line crosses the board on In2; no TVS; no negative clamp
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-D, §4-A/§4-F (inner-layer clearance); lesson = 23-Jul inner-layer short (`drogheda-einarboard-short-incident`); memory `drogheda-einarboard-harness` (Rig 22 k); DS10314 Table 12, Table 52 and the note after it ("add a Schottky diode (pin to ground) to analog pins which may inject negative currents")
|
||||||
|
- **Evidence:** /IGN_IN = {P1.3, Rig1.1}. **Rig1 sits next to the MCU, 100.1 mm from P1.3** (Rig1.1 at 123.55/50.68, P1.3 at 177.5/135.0). The unlimited 9–36 V vehicle line is routed **110.6 mm: 4.1 mm F.Cu + 106.5 mm In2 at 0.5 mm**, 1 via. The pack's `clearance_24v` shows it 0.15 mm from the GND pour (F/In1/In2) and, per INDEX, 0.22 mm from /VEH5V, 0.29 mm from /FAN_PWM and 0.30 mm from /5V_FAN on In2. /IGN_IN has no TVS: D10 SMBJ33A protects only /24V_IN. D5 BAT54 clamps positive only. A negative ISO 7637-2 pulse through 22 k gives −600 V/22 k ≈ −27 mA into PA5 once C9 is discharged, against I_INJ(PIN) −5 mA (Table 12). At 58 V (suppressed load dump) Rig1 dissipates 0.135 W, more than the 0.1 W 0603 rating.
|
||||||
|
- **Consequence:** an inner-layer insulation defect or a harness transient lands 12–36 V (plus pulses) on the 5 V rail or the fan gate, the same geometry as the paid-for 23-Jul lesson. Negative injection on PA5 disturbs the ADC and adjacent pins (Table 52).
|
||||||
|
- **Fix (schematic + layout):** (1) **move Rig1 to ≤ 5 mm from P1.3**, so the long trace carries only the ≤ 3.6 V, 22 k-limited node, which removes /IGN_IN from In2 entirely. Keep Rig2/Rigb1/C9/D5 at the MCU. (2) Add **TVS SMBJ33A (C224019, already in BOM) /IGN_IN → GND at P1.3** (standoff 33 V covers 28.8 V charging on 24 V systems). (3) **D5 BAT54 → BAT54S (C19726, SOT-23)**: common = /IGN_SENSE, upper diode to /3V3, lower diode to GND. (4) Optional: Rig1 in 0805/1206 (150–200 V rating).
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** high (netlist, geometry, datasheet limits). The transient environment is Leo's call (Inputs).
|
||||||
|
|
||||||
|
### G-01 Mounting-hole pattern changed vs V5.5; the V5.5 right-side hole now lands on L6
|
||||||
|
- **Severity:** Major (Blocker if the HBOX backplate keeps the V5.5 standoffs)
|
||||||
|
- **Block / refs:** §4-G; `evidence/outline_and_holes.md`; V5.5 PCB `src/v5_current/…v5.kicad_pcb`; memory `drogheda-v6-zed-f9p-integration` ("MH4/5/6 (enclosure) and MH11 (heatsink clamp) survive")
|
||||||
|
- **Evidence:** outline identical to V5.5 (140.00 × 100.00, x 60.19–200.19, y 40.32–140.32) ✅. V5.5 holes: MH5 (65.2, 45.3), MH6 (65.2, 135.3), **MH4 (193.2, 90.3)**, plus MH7/9/10/11 (shield/heatsink). v6 holes: MH5 (65.2, 45.3), MH6 (65.2, 135.3), **MH7 (195.2, 45.3), MH8 (195.2, 135.3)**, a 130.0 × 90.0 mm corner pattern. At the V5.5 MH4 point, the v6 **L6 (2.2 µH/8 A) courtyard covers it (0.0 mm)** and L6.2 /BAT_PLUS pad centre is 2.44 mm away. R133 is 1.75 mm away, R130 2.73 mm, U22 3.13 mm. The MH6 edge: /3V3 F.Cu track 3.55 mm from the hole centre (an M3 washer Ø7 mm needs ≥ 3.5 mm plus tolerance).
|
||||||
|
- **Consequence:** in an enclosure drilled for V5.5, v6 cannot be screwed down on the right side, and a metal standoff at (193.2, 90.3) would press on L6 / /BAT_PLUS. If the backplate is re-drilled per board, this is only a documentation item.
|
||||||
|
- **Fix:** Leo confirms the enclosure/backplate pattern. If V5.5 standoffs must be reused: keep MH7/MH8 and **add MH at (193.2, 90.3)** by relocating L6. Block A already needs L6 ≤ 5 mm from U6. Otherwise publish the 130 × 90 mm corner pattern for the enclosure. Keep ≥ 4.0 mm copper-free radius on F.Cu/B.Cu around MH5–MH8 (move the /3V3 track at MH6 by ≥ 0.5 mm) or specify nylon washers.
|
||||||
|
- **Effort:** layout (+ enclosure drawing)
|
||||||
|
- **Confidence:** high on geometry. The enclosure fact is not derivable.
|
||||||
|
|
||||||
|
### G-02 Modem USB-C J9 still has no ESD protection
|
||||||
|
- **Severity:** Major (R5 line item "J9 sin ESD", ECO §0 / §E.5)
|
||||||
|
- **Block / refs:** §4-G, §4-B; ECO §E.5; Review §4 #7; V5.6 D19
|
||||||
|
- **Evidence:** /USB_DP = {J9.A6, J9.B6, U19.27}, /USB_DM = {J9.A7, J9.B7, U19.28}, /USB_VBUS = {J9.A4/A9/B4/B9, U19.24}. No ESD device. J11 has D14/D15/D16 at 3.19/6.74/6.83 mm.
|
||||||
|
- **Consequence:** ESD at the service connector goes straight into the A7670SA USB PHY. That port is the only recovery route for a bricked modem (TP8 USB_BOOT).
|
||||||
|
- **Fix:** add **USBLC6-2SC6 (C7519, SOT-23-6)** ≤ 3 mm from J9: pins 1/6 → /USB_DM, 3/4 → /USB_DP, 5 → /USB_VBUS, 2 → GND (same connection as V5.6 D19). Route D± through the device pads.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### D-02 HSE crystal far from the MCU; HC-49S 20 pF crystal outside ST's start-up gm criterion
|
||||||
|
- **Severity:** Minor (upgrade to Major if Leo counts ECO §E.6 as part of R5)
|
||||||
|
- **Block / refs:** §4-D, §4-F; ECO §E.6 (🟡 "cristales ≤ 5 mm"); memory `drogheda-einarboard-30-mcu-integration` (ROM DFU needs HSE, AN2606)
|
||||||
|
- **Evidence:** Y3 = C14872 YXC HC-49S 25 MHz, **CL 20 pF**. Pad distances: Y3.1 → U16.5 PH0 **10.30 mm**, Y3.2 → U16.6 PH1 **14.21 mm**, C113 13.72 mm, C114 17.02 mm (beyond the crystal). Tracks: /HSE_IN 14.5 mm, /HSE_OUT 20.7 mm (F.Cu). Load: 15 pF + 15 pF → 7.5 pF + 5…10 pF stray (DS10314 §6.3.8 "≈ 10 pF") = CL_eff 12.5–17.5 pF against the 20 pF spec, so the crystal runs +33…+130 ppm fast (harmless: USB FS allows ±2500 ppm). Start-up: gm_crit = 4·ESR·(2πf)²·(C0 + CL). With ESR 40 Ω and C0 5–7 pF (typical HC-49S values; the YXC PDF could not be fetched, LCSC blocked) this gives **1.2–2.4 mA/V, against Gm_crit_max = 1 mA/V** (DS10314 Table 37). For context, V5.5 as-fabbed has Y3 at 11.9–13.7 mm with the same parts and starts in the field, so this is margin, not a known failure.
|
||||||
|
- **Consequence:** thin oscillator margin, worst over temperature and ageing. The ROM DFU bootloader (the field flashing path) and the USB clock depend on it. The long HSE traces are an EMC radiator near the MCU.
|
||||||
|
- **Fix:** **Y3 → C2901684** (SCTF SX3B25.000F1010F30, 3225-4P, 25 MHz, **CL 10 pF, ESR 30 Ω**, 11 k stock), footprint `Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm`. **C113/C114 → 12 pF C0G (C38523, Basic)**: CL_eff = 6 + ≈ 3.5 = 9.5 pF. gm_crit = 4·30·(2π·25 MHz)²·(12.5 pF)² = **0.46 mA/V** (2.2× margin). Place the crystal ≤ 3 mm from PH0/PH1, caps between the crystal and a GND via, no signal under it on In1. Basic-part alternative: C9006 (YXC 3225, CL 12 pF) with C113/C114 kept at 15 pF (C1644); confirm its ESR ≤ 40 Ω first.
|
||||||
|
- **Effort:** both (footprint swap + layout)
|
||||||
|
- **Confidence:** high (geometry). Medium (ESR/C0 of C14872 assumed from HC-49S norms).
|
||||||
|
|
||||||
|
### D-03 LSE crystal load and gm do not suit the F411 low-drive LSE
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-D; memory `drogheda-backup-lowpower` (STOP + LSE RTC wake is the planned low-power path for R1)
|
||||||
|
- **Evidence:** Y4 = C32346 Epson FC-135, **CL 12.5 pF, ESR 70 kΩ max** (LCSC description), C0 ≈ 1 pF. C115/C116 12 pF → CL_eff ≈ 6 + 3 = 9 pF, so it runs ≈ +44 ppm fast (≈ 3.8 s/day). gm_crit = 4·70 kΩ·(2π·32 768)²·(13.5 pF)² = **2.16 µA/V** at max ESR, ≈ 1.1 µA/V at typical ESR. DS10314 Table 38: Gm_crit_max **0.56 µA/V (low-power, default)**, **1.50 µA/V (high-drive)**. Distances: Y4.1 5.54 mm, Y4.2 7.91 mm, C116 6.49 mm.
|
||||||
|
- **Consequence:** the LSE may fail to start, or start in tens of seconds, in the default low-drive mode. The 0.6.0 self-test `LSE_Y4` would flag it. An RTC wake from STOP would fall back to LSI (±5–10 %), acceptable for 10-minute timing but not for timestamps.
|
||||||
|
- **Fix:** **Y4 → C48615** (Epson FC-135 Q13FC13500002, **CL 7 pF**, 101 k stock) with **C115/C116 → 6.8 pF C0G (C1679)**: CL_eff ≈ 3.4 + 3.5 = 6.9 pF, gm_crit = 0.76 µA/V at max ESR (OK in high-drive) and ≈ 0.38 µA/V typical (OK in low-drive). Place ≤ 3 mm from PC14/PC15. Firmware: set `LSEMOD` (high-drive) before `LSEON`; LSI fallback.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** medium (C0/typical ESR from Epson family data, not the exact PDF)
|
||||||
|
|
||||||
|
### D-04 ETH_RST is on PA15 = JTDI: pulled HIGH by the MCU during reset; a 100 kΩ pull-down cannot hold the W5500
|
||||||
|
- **Severity:** Minor (corrects Review-vs-Lessons §4 #6 and V5.6 R112)
|
||||||
|
- **Block / refs:** §4-D, §4-E; ECO §F ("ETH_RST pull-down 100 k"); RM0383 debug-pin reset state (GPIOA_MODER reset 0xA800 0000, GPIOA_PUPDR reset 0x6400 0000: PA15 = JTDI AF0 **pull-up**); DS10314 Table 53 R_PU 30–50 kΩ
|
||||||
|
- **Evidence:** /ETH_RST = {U16.50 PA15, U11.37 RSTn}, no external pull. From reset until firmware reconfigures PA15, the internal 30–50 kΩ pull-up drives RSTn HIGH, so the W5500 runs through every MCU reset/boot (≈ 130 mA on /3V3_ETH, which is always on: U12 EN = VIN). The proposed 100 kΩ pull-down gives 3.3 × 100/(100 + 40) = **2.36 V** typical, 2.54 V with a 30 kΩ pull-up. That is still HIGH (W5500 VIH 2.0 V).
|
||||||
|
- **Consequence:** the V5.6/review fix does nothing on this pin, and the battery drain during resets stays.
|
||||||
|
- **Fix:** **4.7 kΩ 0603 (C23162, Basic) /ETH_RST → GND** at U11: 3.3 × 4.7/(4.7 + 30) = **0.45 V** worst case (< W5500 VIL 0.8 V). 0.70 mA while firmware drives HIGH. Or move ETH_RST to **PD2** (pad 54, spare, next to PA15 on the same LQFP edge) and use 100 k (C25803). Firmware: drive PA15 LOW as the first line of `setup()`.
|
||||||
|
- **Effort:** schematic-only (4.7 k option)
|
||||||
|
- **Confidence:** high (register reset values); medium that the pull-up is active while NRST is held low. It is certainly active from reset release until `setup()`.
|
||||||
|
|
||||||
|
### D-05 IGN_SENSE read digitally cannot detect a 12 V ignition; ADC saturates at 28.6 V
|
||||||
|
- **Severity:** Minor (firmware-only must-do + optional value change)
|
||||||
|
- **Block / refs:** §4-D; v6 brief T9 (9–36 V, 12 V and 24 V vehicles); V4/V5 audit §4.4; DS10314 Table 53
|
||||||
|
- **Evidence:** ratio 2.870 k/(22 k + 2.870 k) = 0.1154 (±1 % parts 0.1134–0.1174). PA5 voltage: 12 V → 1.385 V (1.30 V with the INPUT_PULLDOWN that `board_v5.h` uses), 14.4 V → 1.66 V, 24 V → 2.77 V, 28 V → 3.23 V. Production-tested VIL/VIH = 0.99/2.31 V, so a digital HIGH is guaranteed only above **20.0 V**. ADC full scale is at 28.6 V; the clamp starts at ≈ 30.3 V.
|
||||||
|
- **Consequence:** 12 V vehicles read ignition as undefined or OFF. The fan policy (`vehiclePower && ignitionOn`), AUTO and events misbehave. 24 V systems at 28–29 V saturate the ADC, so there is no vehicle-voltage telemetry.
|
||||||
|
- **Fix:** firmware: `analogRead(PA5)` with thresholds (ON > 0.60 V ≈ 5.2 V in, OFF < 0.35 V), no internal pull. Hardware (recommended): **Rigb1 3.3 k → 2.2 k (C4190, Basic)**: ratio 0.0833, so 12 V → 1.00 V, 24 V → 2.00 V, 36 V → 3.00 V, linear to 39.6 V, and the clamp stays idle below ≈ 42 V. New `$PHLG` field `vign`.
|
||||||
|
- **Effort:** firmware-only (+ schematic-only value)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### D-07 GNSS_ANT_DETECT / GNSS_ANT_SHORT_N are receiver inputs; the MCU cannot read antenna state
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-D, §4-C; Phase-2 delta §3 ("antenna-open/short telemetry — you have already lost H0005 and H0014 to antenna faults")
|
||||||
|
- **Evidence:** U18.4 ANT_DETECT and U18.6 ANT_SHORT_N have symbol pin type *input*, and the ZED-F9P integration manual pin table lists them as "I – Active antenna detect / short detect". Their only other node is U16 PC1/PC2. /VCC_RF_GNSS = {U18.7, L21 68 nH, C144, C145} has no current-sense or supervisor circuit. ANT_OFF (U18.5) is unconnected.
|
||||||
|
- **Consequence:** the intended antenna-fault telemetry does not exist. Firmware that reads PC1/PC2 gets meaningless levels, and driving them HIGH with the F9P off back-feeds it.
|
||||||
|
- **Fix:** either add the u-blox antenna supervisor (current-limit plus open/short comparators on VCC_RF, outputs to U18.4/.6 **and** to PC1/PC2 as MCU inputs; block C to size it), or leave the pins analog/hi-Z in firmware and rename the nets (`…_TO_F9P`). Firmware can still report UBX-MON-RF `antStatus` once a supervisor exists.
|
||||||
|
- **Effort:** both (supervisor) or firmware-only (accept)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### D-08 No hardware board-ID: a V5.6 binary on v6 drives PC3 against the F9P's RTK_STAT output
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-D; ECO §H `board_v56.h` (MODEM_EN PC3, MODEM_RST PC1, MODEM_LED PC2); memory `drogheda-firmware-por-tarjeta` (one binary per board, board in the file name)
|
||||||
|
- **Evidence:** V5.6 drives PC3 push-pull as MODEM_EN. v6 PC3 = U18.20 RTK_STAT, a push-pull output. PC1/PC2 (V5.6 MODEM_RST/LED) are F9P inputs on v6. There is no strap distinguishing the boards (PA9, PB10, PC5, PD2 are all unconnected on both).
|
||||||
|
- **Consequence:** a mis-flash contends two push-pull outputs (≈ 25 mA class) and leaves the modem uncontrolled. The naming rule is process-only protection.
|
||||||
|
- **Fix:** **PD2 → 10 kΩ (C25804) → GND** on v6 (pad 54). V5.x leaves PD2 floating. Firmware reads PD2 with INPUT_PULLUP at boot: v6 build requires 0, V5.6 build requires 1, else halt outputs and print `BOARD MISMATCH`.
|
||||||
|
- **Effort:** schematic + 1 short trace
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### D-09 PWR_CTRL has no default-off pull at Q5's base
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-D; `board_v5.h` "PWR_CTRL … Default OFF"
|
||||||
|
- **Evidence:** /PWR_CTRL = {U16.15, R1.1}; /BASE_LS = {R1.2, Q5.1 B}; no resistor to GND. PA1 floats in reset/DFU. Leakage: I_lkg ≤ ±1 µA (DS10314 Table 53) × h_FE ≈ 100 → up to 100 µA through R2 10 k gives ≈ 1 V of gate drive on Q1 AO3401A (V_GS(th) −0.5…−1.3 V). V5.5 is identical (fielded; typical leakage is nA).
|
||||||
|
- **Consequence:** worst-case partial turn-on of the F9P rail during reset/DFU, which fails "default off" and the clean-ramp requirement.
|
||||||
|
- **Fix:** **100 kΩ 0603 (C25803) /BASE_LS → GND** next to Q5.
|
||||||
|
- **Effort:** both (1 resistor)
|
||||||
|
- **Confidence:** medium (worst-case leakage argument)
|
||||||
|
|
||||||
|
### D-10 LTC4040 power-fail (PFO) and input-current monitor (CLPROG) are invisible to the MCU
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-D, §4-A; H0008 log (1.3 A actual vs 2.4 A programmed, only visible with a clamp meter); LTC4040 DS pins 3, 19, 20
|
||||||
|
- **Evidence:** U6.20 PFO → /PFO_TP = {TP2} only, no pull-up. U6.3 CLPROG → /CLPROG_TP = {TP1} only; V_CLPROG = 32 × (V_IN − V_CLN) = 0.32 V/A with RS1 10 mΩ (0.80 V at the 2.5 A limit). U6.11 RST unconnected. Firmware infers power fail from a 5V_SENSE ADC sample (`V5_PFI 4.60`) and cannot measure charge/load current at all.
|
||||||
|
- **Fix:** PFO → **PB10** (spare, FT, EXTI10) with **100 kΩ (C25803) pull-up to /3V3**, for an immediate IRQ on VEH5V < 4.40 V. CLPROG → **PC5 (ADC1_IN15)** via **100 kΩ (C25803) + 1 nF (C1588) at the MCU**. This keeps CLPROG unloaded; block A must confirm the pin accepts that load. Firmware field `iin`.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** medium (CLPROG loading rule not confirmed)
|
||||||
|
|
||||||
|
### D-11 No-connect flags on four connected pins (U16.37/38, U10.13/14)
|
||||||
|
- **Severity:** Minor (cosmetic, hygiene)
|
||||||
|
- **Block / refs:** §4-D, §4-J; `erc_summary.md`
|
||||||
|
- **Evidence:** netlist: U16.37 ∈ /USART6_TX {K1.10}, U16.38 ∈ /USART6_RX {R106.2}, U10.13 ∈ /I2C_SCL, U10.14 ∈ /I2C_SDA (6 nodes each). PCB pad nets are identical (IPC-356, 0 mismatches). All four nets are routed (1 group each). The connection is real, so there is no hidden wiring error.
|
||||||
|
- **Consequence:** the flags suppress future "unconnected pin" ERC on these pins. A later label break would go unreported (the V5.6 junction incident shows how such breaks happen).
|
||||||
|
- **Fix:** delete the four NC flags (by UUID) and re-run ERC. The count should drop by 2 markers.
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### D-12 No UART TX pad for a TX-only log / ROM USART bootloader; SWD pads scattered
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-D; Phase-2 delta §3 ("Leave PA9 as a test point", not done); memory 30-mcu-integration (ROM DFU requires HSE)
|
||||||
|
- **Evidence:** PA9 (USART1_TX, pad 42) carries an NC flag and no pad. USB DFU depends on HSE (D-02). The ROM USART1 bootloader runs on HSI but needs PA9 to answer. SWD = TP3 (109.0, 69.7), TP4 (112.5, 76.2), TP5 (110.0, 74.7), GND TP6 at (107.8, 52.1), 17.6 mm from TP3, 3V3 TP7 at (127.8, 42.6). No SWO (PB3 is CHRG_STAT).
|
||||||
|
- **Fix:** add **TP9 (TestPoint_Pad_D1.5mm) on PA9** next to TP3–TP5: TX-only debug log at 115 200 Bd plus the ROM-bootloader TX; PA10 RX is already the F9P TXD2 tap and the F9P is off in bootloader. Optionally add a DNP 1×5 2.54 mm footprint (3V3, SWDIO, SWCLK, NRST, GND) or a Tag-Connect TC2030-NL land (no BOM cost).
|
||||||
|
- **Effort:** layout (+ schematic pad)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### G-03 J10 / P11 / P12: DNP and footprint disagree between schematic and PCB
|
||||||
|
- **Severity:** Minor (must be settled before any Update-PCB or BOM/CPL export)
|
||||||
|
- **Block / refs:** §4-G, §4-H; `sch_pcb_sync.md` §2; pre-fab audit §7 (still open)
|
||||||
|
- **Evidence:** schematic: J10, P11, P12 populated. PCB: all three `dnp`. P11 (/RS485_A,B,GND) and P12 (/RS232_TX,RX,GND): schematic footprint `…MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical` **does not exist in the KiCad lib** (MC = right-angle series; vertical is MCV). The PCB uses `…_Horizontal`. **C5160226 = DEGSON 15EDGRC-3.5-03P, "Right-Angle", 7 A**, so the PCB footprint matches the part. V5.5 fabbed the same Horizontal footprint. J10: schematic library nickname `Connector_RJ45` (not configured) vs PCB `Connector_RJ`, same HR911105A footprint. The transceivers feeding P11/P12 (U14 SP3485, U15 MAX3232, U10) are populated in both. **P12 is the RS-232 terminal, not the battery NTC** (v6 renumber 03-Sep): the pack is P3 (BATT-1S4P+NTC).
|
||||||
|
- **Consequence:** the schematic BOM lists three parts the CPL flags as DNP (JLC order mismatch). An Update-PCB with "replace footprints" would try to load the non-existent Vertical footprint and flip DNP back. The Ethernet and RS-485/232 ports would be delivered without connectors while their ICs are fitted.
|
||||||
|
- **Fix:** schematic footprint fields: P11/P12 → `Connector_Phoenix_MC:PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal`; J10 → `Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal`. Then set DNP identically on both sides per Leo's intent (if they are hand-fitted THT, mark them DNP in the schematic too and list them on the hand-assembly sheet).
|
||||||
|
- **Effort:** schematic-only (+ Leo's decision)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### G-04 No solder-jumper bypass across the cut-off connector P5
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-G; ECO §F (JP_CUT); Review §4 #9; memory `drogheda-einarboard-harness` (old P11 → v6 P5)
|
||||||
|
- **Evidence:** P5 CUTOFF-SW = {1: /MAIN5V, 2: /SYS5V}; no other part bridges /MAIN5V ↔ /SYS5V (JP1 is the fan option, JP5 the RS-485 termination). Without a plug in P5, /SYS5V is dead, so the MCU runs only from USB. The modem buck is fed from /MAIN5V via D21, ahead of P5, but it stays off because R113 holds EN low while the MCU is unpowered.
|
||||||
|
- **Fix:** add **JP_CUT = `Jumper:SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm`** across P5 (/MAIN5V–/SYS5V), open by default, silk "CUTOFF BYPASS". The /SYS5V load is ≲ 0.8 A, within a 1.0 × 1.5 mm bridged pad pair.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### G-05 Silkscreen: stale modem-reset label, ECO names missing, 0.5/0.1 mm text, P-renumber collisions
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-G; ECO §F (RESET MÓDEM / RESET MCU / JP2 = F2); pre-fab audit §7 (text size); memory `drogheda-einarboard-v6-brief` (P-renumber map)
|
||||||
|
- **Evidence (parsed silk on F.SilkS):** 9 board texts. **"4G NTRIP RESET" at (187.0, 124.1)**: v6 has no modem-reset button (SW4G1 deleted); the label sits between D34 and L22 in the power island. SW1 is labelled "NRST" and SW2 "BOOT" (refdes hidden); the ECO asks for "RESET MCU". JP2 (chemistry F2, Li-ion/LFP) carries only its refdes, and "F2" is also the 24 V fuse refdes. P1 has one label, "IGN 24V" at (178.5, 129), with no per-pin legend, although v6 accepts 9–36 V. All labels are 0.5 mm / 0.1 mm stroke (JLC minimum stroke 0.15 mm; board rule 0.8 mm). **Renumber hazard:** V5-labelled plugs by number collide with same-type v6 headers. V5 "P6 FAN" (XH-2) fits v6 **P6 RESET-EXT** (XH-2): the fan motor across NRST–GND holds the MCU in reset. V5 "P8 PANEL_LED" fits v6 **P8 NTC2**.
|
||||||
|
- **Fix:** delete "4G NTRIP RESET". SW1 "RESET MCU", SW2 "BOOT0 (DFU)". JP2 "CHEM 1-2 Li-ion / 2-3 LFP". P1 pin legend "VIN 9-36V · GND · IGN · GND · NC". A **function name at every connector** (FAN, RESET, NTC1, NTC2, LED, BATT, CUTOFF, 5V BENCH). Text ≥ 0.8 mm / 0.15 mm (1.0/0.15 where space allows). Harness labels by function, not P-number.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### G-08 External-cable inputs P6 (NRST), P7/P8 (NTC ADC) have no ESD protection
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-G, §4-D; v6 brief "optional T12 adds offered: ESD at P7/P8" (not implemented); DS10314 Table 52
|
||||||
|
- **Evidence:** /NRST = {U16.7, C104, SW1, P6.1, TP5}: C104 100 nF sits at 3.26 mm from the MCU, 35.6 mm from P6, and NRST is routed 108.6 mm. /NTC_TEMP (PB1) and /NTC2 (PC4) go to P7.1/P8.1 with only 100 nF (C24 6.63 mm, C157 3.11 mm from the MCU; P7/P8 at 20.2/21.5 mm). All three connectors lead to cables outside the board (panel reset button, NTC probes). An IEC 8 kV/150 pF hit dumps 1.2 µC, i.e. ≈ 12 V step on 100 nF before the MCU's diodes conduct.
|
||||||
|
- **Fix:** **PESD5V0S1BA (C2827694, SOD-323, already in BOM as D14–D16)** at P6.1, P7.1 and P8.1, each ≤ 3 mm from its connector to GND. Optional 100 Ω series (C22775) on NRST between P6 and the net.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** medium (exposure depends on the harness)
|
||||||
|
|
||||||
|
### D-13 EXTI and timer allocation (firmware)
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:** EXTI3 is shared by PC3 RTK_STAT and PB3 CHRG_STAT; EXTI9 by PB9 ACC_INT1 and PC9 MODEM_STATUS. EXTI0 (ETH_INT), EXTI7 (PPS) and EXTI8 (SER_IRQ) are unique. PA6 fan = TIM3_CH1 and PA7 PPS = TIM3_CH2 share TIM3.
|
||||||
|
- **Fix:** EXTI9 → PB9 (motion wake); poll PC9 and PB3; fan stays GPIO ON/OFF (fan policy) so TIM3 is free for PPS capture.
|
||||||
|
- **Effort:** firmware-only · **Confidence:** high
|
||||||
|
|
||||||
|
### D-14 MODEM_STATUS and USART6_RX float whenever the modem is off
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:** U24 (74LVC2T45) outputs are hi-Z when VCC(A) (/1V8_MODEM) = 0. /MODEM_STATUS = {U24.6, U16.40} has no pull. /USART6_RX via R106 likewise.
|
||||||
|
- **Fix:** firmware PC9 INPUT_PULLDOWN (30–50 kΩ). Optional hardware 100 kΩ (C25803) /MODEM_STATUS → GND so DFU/reset states read "modem off". PC7: no pull-up while the F9P is off (D-01).
|
||||||
|
- **Effort:** firmware-only (optional resistor) · **Confidence:** high
|
||||||
|
|
||||||
|
### D-15 VDD decoupling slightly beyond the ≤ 2 mm rule
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence (nearest 100 nF, pad centre):** VDD19 C106 3.29 mm · VDD32 C105 3.65 mm · VDD48 C107 2.10 mm · VDD64 C110 3.90 mm (shared with VBAT pin 1 at 2.32 mm) · VDDA C109 3.13 mm · VCAP1 C111 3.19 mm.
|
||||||
|
- **Fix:** tighten to ≤ 2 mm in the layout pass if convenient (cap map 14-Aug).
|
||||||
|
- **Effort:** layout · **Confidence:** high
|
||||||
|
|
||||||
|
### D-16 Y2 value text says 1.8432 MHz but the LCSC part is 3.6864 MHz
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:** Y2 value "1.8432MHz", LCSC C2238 = YXC X49SM36864MSD2SC-1, **3.6864 MHz, CL 20 pF**. `board_v5.h`: `BOARD_SER_XTAL_HZ 3686400UL` "C2238". JLC assembles the 3.6864 MHz part, which matches firmware. Same in V5.5/V5.6.
|
||||||
|
- **Fix:** change the value field to "3.6864MHz" (block H/E).
|
||||||
|
- **Effort:** schematic-only · **Confidence:** high
|
||||||
|
|
||||||
|
### G-06 P2 bench input sits directly on U25's output; a P2-only bench back-feeds the 24 V domain
|
||||||
|
- **Severity:** Note (for block A)
|
||||||
|
- **Evidence:** /VEH5V = {L22.2 (U25 output), P2.1, RS1, …}; no OR-ing. The v6 brief says "P2 = bench backup, one source at a time". With SD-15B on P2 **and** 24 V on P1 the higher source wins; both are source-only, so this is benign. With **P2 only**, V_OUT > V_IN, so current flows through L22 → SW → TPS54360B high-side FET body diode → /VIN_PROT. Q23 (IRFR5305, gate R119 → GND, V_GS ≈ −4.5 V) then conducts to /24V_IN, and on through Q10 and its body diode to /24V. The result is ≈ 4 V on P1.1 and /24V; U2 (fan buck) may try to run.
|
||||||
|
- **Fix:** document it in the bench procedure ("P1.1 reads ≈ 4 V on P2-only power"), or add a Schottky in series with P2 if bench-only 5 V must not wake the 24 V side.
|
||||||
|
- **Effort:** documentation · **Confidence:** medium (body-diode path inferred from the TPS54360B topology)
|
||||||
|
|
||||||
|
### G-07 Battery connector P3 (JST-XH, 3 A per contact) at its rating
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:** P3 = C144394 JST B3B-XH-A, 3 A. Charge current 2000/825 = 2.42 A (81 %) with R50 825 Ω, 1.33 A after the R50 1.5 k fix. Backup: ≈ 10 W peak at MAIN5V (modem burst 7.6 W/0.9 + F9P 0.72 W + board ≈ 0.8 W) / (0.9 × 3.3–3.7 V) = **3.0–3.4 A peaks**, 0.6–1 A average. Two contacts × ≤ 10 mΩ → ≈ 70 mV at 3.4 A.
|
||||||
|
- **Fix:** keep XH-3 for compatibility with the existing 1S4P packs. If the pack harness is remade (LFP-HT decision, ECO D1), move to XH-5 (2 × BAT+, 2 × GND, NTC) or JST VH.
|
||||||
|
- **Effort:** — · **Confidence:** medium
|
||||||
|
|
||||||
|
## Pass checks
|
||||||
|
| Check | Evidence (one line) | Result |
|
||||||
|
|---|---|---|
|
||||||
|
| U16 symbol pin numbers vs ST LQFP64 | 64/64 names match ST open-pin-data XML | ✅ |
|
||||||
|
| Pin-map coverage | 64/64 rows in `pinmap-v6.md` | ✅ |
|
||||||
|
| ADC nets on ADC pads | PA0/IN0, PA4/IN4, PA5/IN5, PB1/IN9, PC4/IN14 | ✅ |
|
||||||
|
| AF conflicts | USART2 AF7, USART6 AF8, USART1_RX AF7, SPI2 AF5, I2C1 AF4, OTG AF10, SWD AF0: no overlaps | ✅ |
|
||||||
|
| 5 V on non-FT / any pin | none; TC pins PA0 ≤ 2.10 V, PB5 output | ✅ |
|
||||||
|
| 1.8 V modem signals reaching MCU | none (U23/U24, Q20/Q21) | ✅ |
|
||||||
|
| Modem control defaults in reset | R113/R114/R115 100 k pull-downs on PC10/PC8/PC11 | ✅ |
|
||||||
|
| BOOT0 / BOOT1 trap | R98 10 k PD + SW2; PB2 only R99 10 k PD; ETH_INT on PC0 | ✅ |
|
||||||
|
| NRST circuit | C104 100 nF at 3.26 mm; SW1 pad pairs correct (NRST 6.5 mm pair); P6, TP5 | ✅ |
|
||||||
|
| DFU ESD at J11 | D14/D15/D16 at 3.19/6.74/6.83 mm; CC 5.1 k ×2; VBUS diode-OR D12/D13 | ✅ |
|
||||||
|
| VCAP1 / VDDA | C111 4.7 µF 3.19 mm; R104 10 Ω + 1 µF + 100 nF | ✅ |
|
||||||
|
| IGN divider junction | Rig1.2/Rig2.1/Rigb1.1/C9/D5/U16.21 on one net, sch and PCB (6 pads, 1 group) | ✅ |
|
||||||
|
| IGN clamp orientation | D5 K (pad 1) → /3V3, A → /IGN_SENSE | ✅ |
|
||||||
|
| CHRG_STAT/FAULT pull-ups | R57/R58 100 k → /3V3 (always-on MCU rail) | ✅ |
|
||||||
|
| I2C address map | 0x18 SC7A20 (SDO→GND), 0x20 PCF8574 (A0–A2 GND), 0x44 SHT40, 0x4D SC16IS752 (A0/A1 GND, I2C mode pin 9 = 3V3): no clash | ✅ |
|
||||||
|
| NC flags on U16.37/38, U10.13/14 hide an error? | nets real in netlist + IPC-356, routed | ✅ (cosmetic, D-11) |
|
||||||
|
| Harness pinouts vs V5.5 (by function) | P1, P2, P3=P4, P4=P6, P5=P11, P6=P10, P7=P12, P9=P8, P10=P14, P11=P15, P12=P16 all identical | ✅ |
|
||||||
|
| Pin-1 / mirror | every connector is a KiCad-library footprint with a distinct pad-1 shape and silk marker; J12/J13 U.FL symmetric; J14 = stock KiCad JAE SF72S006 (C1–C3 / C5–C7 rows); no module sockets on v6 (J1-class risk gone) | ✅ |
|
||||||
|
| P1 ignition GND return | P1.2 and P1.4 = GND, P1.5 NC (as V5.5) | ✅ |
|
||||||
|
| External 5 V input | U25 is the primary; P2 retained as bench input on /VEH5V | ✅ (G-06 note) |
|
||||||
|
| Outline / case fit XY | 140.00 × 100.00 at the V5.5 coordinates; J10 (78.0, 53.825, −90) and J11 (69.975, 70.85) same as V5.5 (Δ ≤ 0.09 mm) | ✅ |
|
||||||
|
| Connector current (P1 16 A, P2 3 A at ≤ 2.5 A, P5 3 A at ≤ 0.8 A, P11/P12 7 A) | datasheet ratings vs loads | ✅ (P3 G-07) |
|
||||||
|
| HSE ≤ 5 mm | 10.30/14.21 mm | ❌ D-02 |
|
||||||
|
| LSE ≤ 5 mm | 5.54/7.91 mm | ⚠ D-03 |
|
||||||
|
| J9 ESD | none | ❌ G-02 |
|
||||||
|
| JP_CUT across P5 | none | ❌ G-04 |
|
||||||
|
| Silk names per ECO §F | stale "4G NTRIP RESET"; no "RESET MCU"/JP2 legend | ❌ G-05 |
|
||||||
|
| Sch/PCB parity J10/P11/P12 | DNP + footprint mismatch | ❌ G-03 |
|
||||||
|
|
||||||
|
## Review-vs-Lessons §4 checklist items re-verified
|
||||||
|
| Item | Status now | Evidence |
|
||||||
|
|---|---|---|
|
||||||
|
| #6 ETH_RST pull-down 100 k | **Still absent, and 100 k would not work** (PA15 JTDI pull-up) | D-04: use 4.7 k (C23162) or move to PD2 |
|
||||||
|
| #7 J9 USB ESD | Still absent | G-02 |
|
||||||
|
| #9 JP_CUT across P5 | Still absent | G-04 |
|
||||||
|
| #12 Firmware v6 pins (PC10/PC8/PC9/PC11, USART6 PC6/PC7, PB5 K1) | Confirmed on the netlist, plus PA7/PC1–PC4/PC12/PB9 | `pinmap-v6.md` |
|
||||||
|
| F8 BOOT1 trap | Holds | PB2 = R99 only; ETH_INT PC0 |
|
||||||
|
| F8 DFU ESD at J11 | Holds | 3.19–6.83 mm |
|
||||||
|
| §5 "free pins PC5, PB10, PA9, PD2" | Still free | NC flags; proposed uses in D-08/D-10/D-12 |
|
||||||
|
| #5 charger sensor via PC5 | PC5 still free (block A/F decides; D-10 competes for PC5 — use PB10 for PFO and choose between CLPROG and NTC on PC5) | mcu_pins.csv |
|
||||||
|
| #11 identity without `$GPTXT` | Firmware: 96-bit UID at 0x1FFF7A10 is available for `$PHID` | — |
|
||||||
|
|
||||||
|
## Requirements input R1–R5
|
||||||
|
- **R1** (10-min off/on on battery with report): MCU has independent F9P (PA1) and modem (PC10) power, PWRKEY/RST/STATUS. **Satisfied as-is for control.** Needs D-01 so an F9P-off/modem-on state never back-powers the receiver. LSE wake quality: D-03 (LSI fallback exists).
|
||||||
|
- **R2** (modem never dark; MCU can power-cycle it): **satisfied as-is** (PC10 + R113, PC11/Q21, PC8/Q20, PC9 STATUS). Firmware only.
|
||||||
|
- **R3** (report while on battery): firmware only. D-10 (PFO IRQ) is an improvement.
|
||||||
|
- **R4** (temperature management): NTC inputs PB1/PC4 on ADC pads ✅. There is no cell-temperature input to the MCU (P3 NTC goes to the LTC4040 only; TMP102 gone). This is block A/F's call; PC5 is available.
|
||||||
|
- **R5** (EMC list): DFU ESD at J11 ✅; **J9 ESD ❌ (G-02)**; crystals ≤ 5 mm ❌ (D-02, ECO §E.6 🟡).
|
||||||
|
|
||||||
|
## Firmware implications (board_v6.h / FW 0.7.x)
|
||||||
|
1. New `board_v6.h` (draft in `pinmap-v6.md` §5). A binary must never cross between V5.6 and v6 (PC1/PC3). Adopt the D-08 strap check.
|
||||||
|
2. First lines of `setup()`: drive LOW PC10, PC8, PC11, PA1, PB5, **PA15**, PA6, PB0.
|
||||||
|
3. Remove the PA9 RELAY TX; Mode-B TX = USART6 PC6 via K1 NO; USART6 RX PC7 always on (AT + RTCM byte counter, `rtcm_bps`); USART1 RX-only on PA10 with **no pull** (PA10 pull-up is 7–14 kΩ).
|
||||||
|
4. F9P back-feed rules (§2.5 of the pin map): PA2/PA10/PC7/PC12/PA7/PC3/PC1/PC2 inert while PA1 is LOW. Until D-01 is fixed, never hold PC10 HIGH with PA1 LOW.
|
||||||
|
5. PC12 open-drain only; PC1/PC2 analog (F9P inputs).
|
||||||
|
6. IGN on ADC (PA5/IN5) with thresholds, and `vign` if Rigb1 becomes 2.2 k (D-05).
|
||||||
|
7. New inputs: PPS (TIM3_CH2 or EXTI7), RTK_STAT (poll ≥ 10 Hz or EXTI3), ACC_INT1 (EXTI9, SC7A20 0x18), NTC2 (IN14, `tntc2`), MODEM_STATUS (poll, pull-down).
|
||||||
|
8. Drop TMP102 (0x48/0x49) and the PCF8574 P7 modem-reset code; re-source `CHG_CELL_HOT/COOL`.
|
||||||
|
9. LSE: `LSEMOD` high-drive, LSI fallback for the RTC wake.
|
||||||
|
10. Modem sequencing: PWRKEY ≥ 50 ms on / ≥ 2.5 s off; STATUS ≈ 11.2 s; any MCU reset = cold modem and cold F9P.
|
||||||
|
11. If D-10 is adopted: PB10 EXTI on PFO (falling), PC5 ADC on CLPROG (0.32 V/A).
|
||||||
|
|
||||||
|
## Inputs needed from Leo
|
||||||
|
1. **Enclosure/backplate hole pattern** for v6: are the V5.5 standoffs (incl. (193.2, 90.3)) reused? This decides whether G-01 is a Blocker. Assumed: backplate re-drilled.
|
||||||
|
2. **J10 / P11 / P12**: JLC-assembled or hand-fitted THT? (G-03.) Assumed: populated.
|
||||||
|
3. **Ignition environment**: 12 V vehicles in scope for v6? Unsuppressed ISO 7637/16750 transients on the ignition wire (terminal tractors, RTGs)? (D-05/D-06.) Assumed: yes to both.
|
||||||
|
4. Are field harness cables labelled by P-number (V5 names)? (G-05 collision.)
|
||||||
|
5. Is the v6 low-power plan STOP + RTC (LSE), or duty cycle with the MCU running? (D-03 severity.)
|
||||||
|
6. SWD header wanted on the fab board, or DFU plus pads only? (D-12.)
|
||||||
@ -0,0 +1,528 @@
|
|||||||
|
# F (Layout/EMC) + H (BOM/JLC) + J (ERC/DRC) — v6 audit findings
|
||||||
|
Snapshot: sch ecee9fed… / pcb 6ddec80d… (evidence pack 2026-09-28)
|
||||||
|
|
||||||
|
## Sources read
|
||||||
|
- Brief: `findings/_COMMON_BRIEF.md`; master brief §3–§5, §4-F/H/J; `INDEX.md`; `evidence/MANIFEST.md`; prior review `docs/2026-09-28_…Review-vs-V5.5-Lessons_v1.0.md` (§1–§4); pre-fab audit `docs/project/claude__2026-09-25_HBox-v6_Pre-Fab-Audit_EN.md`; ECO `docs/2026-09-27_…V5.6_ECO_ES_v1.0.md` (§0, §E, §G); Copper Plan `docs/2026-09-02_…v6-Copper-Plan_Placement-EMC-Guide.html` (§2–§9).
|
||||||
|
- Memory: `drogheda-einarboard-short-incident`, `drogheda-einarboard-v5-audit` (V5.5 EMC list; 165 GND vias), `drogheda-v6-lte-island` (RF/PWR_MODEM netclasses once existed; ESD9L on RF), `drogheda-v6-resync-protocol` (02-Sep copper wipe → hand layout; GUI saves wipe netclasses), `preferences`.
|
||||||
|
- Evidence: `stackup.md`, `zones.csv`, `clearance_24v.md/.csv`, `net_routing_summary.csv`, `pcb_footprints/pads/tracks.csv`, `vias.csv`, `drc_summary.md`, `drc_items.csv`, `erc_summary.md`, `erc_full.json`, `sch_pcb_sync.md`, `bom.csv`, `components.csv`, `cpl.csv`, `ref_versions/v56_components.csv`, `mcp/courtyard_overlaps_mcp.json`, `outline_and_holes.md`, `dangling_track_ends.csv`, `v6-pcb-layers.pdf` (viewed).
|
||||||
|
- Other block files read to avoid double counting: `findings/A_power.md` (A-01, A-02, A-06, A-09, A-14, A-15), `findings/DG_mcu_connectors.md` (D-02, D-03, D-06, D-11, D-16, G-02, G-03, G-05).
|
||||||
|
- Own computation (shapely, parsed from `src/hbox-watchdog-v6.kicad_pcb` with `scripts/parse_pcb.py`; scratch in `work/FHJ/`): `plane.py/voids.py/crossings2.py` (plane coverage under every track), `hv24.py` (0.5 mm re-check with corrected classes → `work/FHJ/hv24_violations_corrected_rule.csv`), `bucks.py/geodesic.py/islands.py` (loops, EP vias, F.Cu GND pieces), `stitch.py`, `xtal.py`, `esd.py`, `crt.py`, `classify.py`, `bomcheck.py`. Renders: `work/FHJ/in1_full.png`, `rf_lte.png`, `rf_gnss.png`, `u20.png`, `u25.png`, `fcu_gnd_pieces.png`.
|
||||||
|
- JLC: `get_jlcpcb_part` on all 121 BOM LCSC numbers + 10 alternates (local DB snapshot, 2026-09-28); `search_jlcpcb_parts` for MAX3232, SC16IS752, 499 k, PMEG6030EP. Web: KiCad forum (rule precedence, dev JeffYoung: "custom rules are appended after [netclass rules] so have higher priority"); JLCPCB capabilities page (4-layer: 0.09/0.09 mm track/space, via 0.15/0.25 mm, PTH ring ≥ 0.15 (0.20 rec.), hole-hole 0.45 mm, PTH-track 0.28 mm, silk ≥ 0.15 mm line / 1.0 mm text); Sunlord MWSA series spec (alfatec mirror) for MWSA0804S dimensions.
|
||||||
|
|
||||||
|
Deliverables alongside this file: `findings/bom_check.csv` (152 BOM lines), `findings/ercdrc_classified.csv` (166 ERC + 283 DRC items, each classified).
|
||||||
|
|
||||||
|
## Findings
|
||||||
|
|
||||||
|
### F-01 Netclass assignment is broken and one custom rule overrides every clearance: the DRC "0 errors" cannot see any 24 V spacing
|
||||||
|
- **Severity:** Blocker
|
||||||
|
- **Block / refs:** §4-F item 1, §4-J; lesson 23-Jul inner-layer short (`drogheda-einarboard-short-incident`, action "next rev: 24V-to-LV clearance rule ≥ 0.5–1 mm (netclass)"); `drogheda-v6-resync-protocol` §5 (GUI saves wiped RF/PWR_MODEM classes); pre-fab audit §6.
|
||||||
|
- **Evidence:**
|
||||||
|
- `.kicad_pro` patterns (stackup.md §4.1): HV24 = `/24V_IN`, `24V`, `IGN_IN`, `Q10_GATE`. KiCad matches the full name including the leading `/`, so only `/24V_IN` resolves (netlist `class` attribute). `/24V`, `/IGN_IN`, `/Q10_GATE`, `/VIN_FUSED`, `/VIN_PROT`, `/VIN_MODEM`, `/Q23_GATE` and the five 24 V switch/boot nodes are Default; `/SW_FAN` is PWR_MID. Dead patterns: `24V`, `IGN_IN`, `Q10_GATE`, all un-prefixed PWR_* duplicates, `/3V3_MODEM`, `3V3_MODEM`, `/SW3_NODE`, `SW3_NODE` (V5 nets). RF and PWR_MODEM classes are missing.
|
||||||
|
- `.kicad_dru` rule "Minimum clearance 1" = 0.15 mm, condition `A.NetClass != 'HV24' && B.NetClass != 'HV24'`, no layer or type qualifier. In KiCad 10 the netclass clearances and the zone "Clearance" field are implicit rules; custom rules are evaluated after them and a matching custom rule wins; only the board minimum (0.0 mm here) is a floor. So this rule overrides Default 0.2 mm, PWR_HI/PWR_MID 0.2 mm, the zone's own 0.3 mm, and would override any future RF class.
|
||||||
|
- Proof in the stored fills: in the same GND zones, the gap to `/24V_IN` (HV24) is 0.5005 mm, and to every other net 0.1505 mm (clearance_24v.md), although each zone's clearance field is 0.3 mm. DRC reports 0 clearance items.
|
||||||
|
- With the stale 0.15 mm rule deleted and Default left at 0.2 mm, 471 item pairs (209 net pairs) at 0.15–0.20 mm would fail (F.Cu 400, In1 33, In2 27, B.Cu 11). The layout was drawn to 0.15 mm, so the floor must stay 0.15 mm, set explicitly.
|
||||||
|
- **Justification of the number (IPC-2221B Table 6-1):** the vehicle rail peaks at the D10/D32 clamp, VC = 53.3 V @ 11.3 A (SMBJ33A/SMCJ33A, JLC C224019/C699039), and ISO 16750-2 suppressed load dump for 24 V systems is 58 V. That puts the design in the **51–100 V** row: B1 internal 0.10 mm, B4 external with permanent polymer coating (solder mask) 0.13 mm, A6 external uncoated component lead 0.13 mm (B2 bare external 0.6 mm does not apply under mask). So today's 0.15 mm already meets IPC dielectric spacing. **The 0.5 mm inner-layer value is a defect/CAF margin, chosen because Leo lost a board to a suspected inner-layer bridge at 0.20–0.25 mm.** Inner layers cannot be inspected or cleaned, and they sit under 24 V bias at 45 °C in humid ports. On outer layers under mask, 0.3 mm (2.3× IPC) is enough and fits the SO-8 pin rows.
|
||||||
|
- **Consequence:** DRC cannot flag a repeat of the 23-Jul geometry. F-02 is exactly that, and it passed DRC with 0 errors.
|
||||||
|
- **Fix (project + rules; no copper change by itself):**
|
||||||
|
|
||||||
|
| Class | Patterns (exact names, one per line) | Clearance | Track | Via | Notes |
|
||||||
|
|---|---|---|---|---|---|
|
||||||
|
| HV24 | `/24V_IN` `/VIN_FUSED` `/VIN_PROT` `/24V` `/VIN_MODEM` `/IGN_IN` `/Q10_GATE` `/Q23_GATE` `/SW_PWRIN` `/BOOT_PWRIN` `/SW_FAN` `/BST_FAN` `/SW_MODEM` `/BST_MODEM` | 0.5 (inner and outer set by DRU) | 1.0 | 0.8/0.4 | `/SW_FAN` leaves PWR_MID. `/EN_FAN` and `/EN_PWRIN` stay Default (≤ 10 V, high-impedance) |
|
||||||
|
| PWR_HI | `/BAT_PLUS` `/SW_BAT` `/MAIN5V` `/VEH5V` `/SYS5V` `/VIN_SW` | 0.15 | 1.5 | 0.8/0.4 | delete the un-prefixed duplicates |
|
||||||
|
| PWR_MID | `/SW_5V` `/SW_IN` `/5V_FAN` `/FAN_RET` | 0.15 | 0.6 | 0.8/0.4 | move `/3V3_ETH` to Default (0.15 A, see J-02) |
|
||||||
|
| PWR_MODEM | `/VBAT_MODEM` | 0.15 | 1.5 | 0.8/0.4 | re-create (was in T6) |
|
||||||
|
| RF | `/RF_GNSS` `/RF_ANT_GNSS` `/RF_LTE` `/RF_ANT_LTE` | CPWG gap from F-06 | CPWG width from F-06 | none | re-create |
|
||||||
|
| Default | everything else | **0.15** | 0.2 | 0.6/0.3 | set explicitly (today 0.2 in the class, 0.15 via the DRU) |
|
||||||
|
|
||||||
|
`.kicad_dru` (replace "Minimum clearance 1", "HV24 clearance" and "HV24 exception"; later rules win):
|
||||||
|
```
|
||||||
|
(rule "Floor 0.15 (non-HV24, non-RF)"
|
||||||
|
(condition "A.NetClass != 'HV24' && B.NetClass != 'HV24' && A.NetClass != 'RF' && B.NetClass != 'RF'")
|
||||||
|
(constraint clearance (min 0.15mm)))
|
||||||
|
(rule "HV24 outer"
|
||||||
|
(layer outer)
|
||||||
|
(condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
|
||||||
|
(constraint clearance (min 0.3mm)))
|
||||||
|
(rule "HV24 inner"
|
||||||
|
(layer inner)
|
||||||
|
(condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
|
||||||
|
(constraint clearance (min 0.5mm)))
|
||||||
|
(rule "HV24 IC land patterns"
|
||||||
|
(layer outer)
|
||||||
|
(condition "A.Type == 'Pad' && B.Type == 'Pad' && ((A.memberOfFootprint('U2') && B.memberOfFootprint('U2')) || (A.memberOfFootprint('U20') && B.memberOfFootprint('U20')) || (A.memberOfFootprint('U25') && B.memberOfFootprint('U25')))")
|
||||||
|
(constraint clearance (min 0.15mm)))
|
||||||
|
```
|
||||||
|
Then refill all zones and re-run DRC. Expected result: the 6 inner and 15 outer spots of F-02/F-15 (full list in `work/FHJ/hv24_violations_corrected_rule.csv`). The F.Cu pour will recede to 0.3/0.5 mm around 178 HV24 items; afterwards check `isolated_copper` and the U25/U20 GND islands (F-03/F-07). After every GUI project save, re-check that the classes survived (resync-protocol §5).
|
||||||
|
- **Effort:** both (rules now; the copper they flag is F-02/F-15)
|
||||||
|
- **Confidence:** high on the facts (fill geometry, 0 DRC items, pattern resolution from the netlist). Medium on the internal rule-precedence mechanism, which is confirmed by a KiCad developer's forum statement plus the fill evidence. A KiCad `Inspect → Clearance Resolution` on one `/24V`–GND pair would make it high.
|
||||||
|
|
||||||
|
### F-02 Raw ignition `/IGN_IN` crosses the board on In2 at 0.22 mm from `/VEH5V`: the 23-Jul inner-layer geometry repeated
|
||||||
|
- **Severity:** Blocker
|
||||||
|
- **Block / refs:** §4-F item 1; lesson `drogheda-einarboard-short-incident` (24 V on In2 at 0.20–0.25 mm from 5 V nets → board scrapped); Copper Plan §8 ("Rig1 22 k — 🔴 series element right at the jack"); same net as D-06 (rated Major there; I rate Blocker because it repeats a lesson already paid for).
|
||||||
|
- **Evidence:** `/IGN_IN` = {P1.3, Rig1.1}. P1.3 is at (177.5, 135.0) and Rig1 at (123.55, 50.68), 100 mm apart. The net runs 4 mm on F.Cu, **106.5 mm on In2** at 0.5 mm width, plus one via. With the corrected HV24 rule it is the **only** inner-layer violation set. All 6 inner spots are on `/IGN_IN`:
|
||||||
|
|
||||||
|
| layer | other net | gap | at |
|
||||||
|
|---|---|---|---|
|
||||||
|
| In2 | `/VEH5V` 1.0 mm track | **0.221 mm** | (147.34, 67.49) |
|
||||||
|
| In2 | GND via | 0.250 mm | (154.4, 83.15) |
|
||||||
|
| In2 | `/FAN_PWM` track | 0.291 mm | (152.63, 73.49) |
|
||||||
|
| In2 | `/5V_FAN` via | 0.300 mm | (157.5, 104.5) |
|
||||||
|
| In1 | `/NTC2` track (IGN via) | 0.305 mm | (127.32, 50.47) |
|
||||||
|
| In2 | `/VEH5V` via | 0.340 mm | (147.4, 67.4) |
|
||||||
|
|
||||||
|
Plus zone fills at 0.1505 mm on F/In1/In2/B.Cu (these re-pour automatically). The run is also one of the slots that split In2 (F-05).
|
||||||
|
- **Consequence:** a single inner-layer defect puts 9–36 V (and load-dump pulses) straight onto `/VEH5V`, which feeds LTC4040 VIN (abs max 6 V class) and the whole 5 V system, or onto the fan gate/5 V fan rail. This is the failure that scrapped the 23-Jul board, and it cannot be seen or reworked.
|
||||||
|
- **Fix:** move **Rig1 (22 k, 0603, C88614) to ≤ 3 mm from P1.3**, with `/IGN_IN` ≤ 3 mm long on F.Cu. The 106 mm run then becomes `/IGN_SENSE`: current-limited to 36 V/22 k = 1.6 mA (2.6 mA at 58 V) and clamped by D5/C9 at the MCU. A bridge to any 5 V net then injects ≤ 2.6 mA, which is harmless. Keep Rig2/Rigb1/C9/D5 at the MCU (Copper Plan §8). Optional (D-06): SMBJ33A (C224019) on `/IGN_IN` at P1.3; Rig1 in 1206 for pulse rating. Also move the In1 IGN via at (127.3, 50.5) ≥ 0.5 mm from `/NTC2`, or it disappears with the reroute.
|
||||||
|
- **Effort:** layout (one resistor moves, one net rerouted; no BOM change)
|
||||||
|
- **Confidence:** high (geometry measured on all layers; netlist membership)
|
||||||
|
|
||||||
|
### F-03 U25 (24 V buck) hot loop: the input capacitors' GND is on a different F.Cu island from U25/D34; the loop closes through vias 10–30 mm away (≈ 3.1 cm²)
|
||||||
|
- **Severity:** Major (same root item as A-06; not double-counted. It keeps pre-fab audit B5 open)
|
||||||
|
- **Block / refs:** §4-F item 5; Copper Plan §2 ("under 1 cm² or do it again"); ECO §E.4; pre-fab audit B5; TPS54360B layout guidance (Cin at VIN/GND pins, PowerPAD to GND with vias).
|
||||||
|
- **Evidence (pad edge-to-edge unless noted):**
|
||||||
|
|
||||||
|
| loop element | v6 | target |
|
||||||
|
|---|---|---|
|
||||||
|
| C150.1 → U25.2 VIN | 2.88 mm ✅ (C149: 6.37 mm) | ≤ 3 mm |
|
||||||
|
| C150.2 GND → U25 EP / pin 7 | 5.40 / 9.03 mm straight, **but on a different copper piece** | same copper, ≤ 3 mm |
|
||||||
|
| D34.1 → U25.8 PH | 4.28 mm | ≤ 3 mm |
|
||||||
|
| D34.2 (anode) → C150.2 | 8.63 mm straight; **no F.Cu path** | same island |
|
||||||
|
| L22.1 → U25.8 | 13.75 mm (17.0 ctr; was 25.9 on 25-Sep) | ≤ 5 mm |
|
||||||
|
| `/SW_PWRIN` copper | 45.8 mm² (tracks 20.9 mm², 20.4 mm × 1.0 mm) | minimal |
|
||||||
|
| U25 EP (3.2 × 2.5) | **0 vias**, nearest GND via 28 mm; pad joins the pour with 4 × 0.5 mm spokes (18 % perimeter contact) | via array, solid |
|
||||||
|
|
||||||
|
F.Cu GND copper pieces (pour + GND pads + GND tracks, `fcu_gnd_pieces.png`): C149.2/C150.2/C151.2 sit on the 270 mm² U6 piece (5 GND vias, nearest 10.2 mm from C150.2). D34.2 and U25.9 sit on the 3766 mm² east piece, whose nearest vias to U25 are (145.7, 129.9) and (148.1, 135.3), ≈ 30 mm away. The input loop C150+ → U25 → PowerPAD → F.Cu → via → In1/In2 → via → C150− encloses ≈ **311 mm²**. With C150.2 tied to the EP island it would be ≈ 51 mm².
|
||||||
|
- **Consequence:** non-synchronous buck, so the input loop carries the full switched current (3 A pulses at ~620 kHz). An estimated 15–25 nH of loop inductance × 3 A/5 ns gives ~9–15 V of ringing on VIN over the D32 clamp level (53.3 V). TPS54360B VIN abs max is 65 V, so margin disappears during a clamped load dump. Also conducted/radiated EMI into the GNSS/LTE receivers, and the IC dissipates through spokes.
|
||||||
|
- **Fix (layout):** (1) Rotate/re-cluster so C149/C150 (2.2 µF/100 V, C153036) sit ≤ 2 mm from pins 2/7 with their GND pads on the **same solid F.Cu copper as the PowerPAD and D34 anode** (Copper Plan §2 chain order). D34 cathode ≤ 2 mm from pin 8, anode tied to the Cin GND copper. (2) PowerPAD: 6–9 × 0.3/0.6 mm vias (3 × 3 at 1.0 mm pitch fits 3.2 × 2.5) to In1/In2, pad connection solid (F-13). (3) Four GND vias (0.3/0.6) around the Cin/D34 GND node within 2 mm. (4) L22 ≤ 5 mm from pin 8 with a ≤ 25 mm² `/SW_PWRIN` pour. Keep `/SW_PWRIN` off any area above In1 signal tracks (today it sits over In1 `/MAIN5V`, `/SW_5V`, `/VFB_BST`: F-10).
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high (island membership, distances). Medium on the ringing amplitude (inductance estimated, not simulated).
|
||||||
|
|
||||||
|
### F-04 East-half F.Cu GND pour (3766 mm²: U19 modem, U20, U25, U2, J13) is stitched to the inner planes by only 5 vias; modem and F9P have no GND vias under them
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-F item 4; `drogheda-einarboard-v5-audit` (V5.5: 165 GND vias, 4.6 mm median NN); Copper Plan §5 ("nothing but solid In1 ground under the module"), §10 (5 mm grid around RF); SIMCom/u-blox hardware-design guidance (module GND pads to the main ground with many vias).
|
||||||
|
- **Evidence:**
|
||||||
|
- 69 GND vias on the whole board (V5.5: 165). The largest F.Cu GND piece (3766 mm², x 115–200) touches 5 of them: (145.7, 129.9), (148.1, 135.3), (153.5, 77.0), (152.6, 62.5), (198.8, 78.1). The other GND vias in that area land on 2–22 mm² slivers (e.g. (175.2, 58.7) on 7.3 mm², (184.6, 81.8) on 7.9 mm², (192.8, 78.1) on 20.8 mm²).
|
||||||
|
- **U19 A7670SA**: 39 GND pads (109.5 mm², incl. 20 × 2.1 mm centre pads), **1 via under the 24 × 24 mm body**, 4 GND vias in a 5 mm ring. The GND pads join the pour through thermal spokes (pad 85: 24 % perimeter contact; pad 71: 18 %). **U18 ZED-F9P**: 56 GND pads, **0 vias under the body**, 5 in the ring, pads on spokes (pad 65: 45 %).
|
||||||
|
- J13 (LTE U.FL) GND pads: nearest GND via 28 mm. D28 (LTE ESD) GND: 30 mm. J12 GND: 4.1 mm.
|
||||||
|
- **Consequence:** the modem's return currents (23 dBm LTE, 2 A GSM bursts) and the F.Cu pour of the whole east half reach In1/In2 through 5 vias spread 30–70 mm apart. The pour behaves as a resonant patch (λ/2 at 1–2.7 GHz ≈ 26–75 mm in FR4) instead of a ground. Expect LTE self-desense of the F9P (−167 dBm sensitivity), antenna-port ESD returning through the pour, and poorer heat spreading from U19 (≈ 1–2 W at max TX) into the planes.
|
||||||
|
- **Fix (layout):** (1) Pad connection solid for SMD pads (F-13). (2) U19: one 0.3/0.6 mm via per centre GND pad (20) plus vias between perimeter GND pads (≥ 30 under the module in total, tented/plugged: JLC "epoxy filled & capped" or tented vias off-pad, so the LGA does not wick). (3) U18: ≥ 1 via per 2 centre GND pads (≥ 24 vias), same rule. (4) J13/J12: 2 GND vias per U.FL ground pad ≤ 1 mm from the pad. (5) Global stitching per F-12.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high (via/piece connectivity measured). Medium on the desense magnitude (needs the G3 bench test).
|
||||||
|
|
||||||
|
### F-05 In1, the "solid GND reference", carries 1572 mm of tracks from 49 nets and is 19 % void; almost every fast or sensitive interface crosses a slot
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-F item 2; Copper Plan §0 ("an unbroken In1 ground plane"), §10 ("In1 GND unbroken, especially under both RF runs and the crystals"); pre-fab audit §7; ECO §E.6.
|
||||||
|
- **Evidence:**
|
||||||
|
- In1 GND fill 11370.5 mm² in 8 islands (5553 / 4338 / 1289 / 94.5 / 37 / 34.6 / 14.5 / 9.7 mm²); void 2630 mm² (19 %). The voids form one connected slot network of 1276 mm² spanning 133 × 92 mm, plus a 605 mm² network in the Ethernet corner. Biggest In1 users: `/SW_5V` 181 mm, `/DOUT_4G` 95, `/KCOIL` 85, `/MAIN5V` 73, `/CHRG_FAULT` 72, `/CHRG_STAT` 69, `/USART6_TX` 68, `/BOOT0` 61, `/SER_TXB` 57, `/SER_RXB` 52, `/MODEM_STATUS` 45, `/ETH_LINKLED` 40 … `/24V_IN` 27, `/RF_LTE` 22.
|
||||||
|
- In2 GND (1 island) carries 1009 mm from 25 nets (`/IGN_IN` 106, `/PWR_CTRL` 98, `/SYS5V` 98, `/GNSS_ANT_*` 88 + 86, `/USART1_RX` 79, `/BAT_PLUS` 70 …); its voids form an 856 mm² network. B.Cu is the `/3V3` pour (1 island, 12610 mm²).
|
||||||
|
- Plane gaps under critical nets (reference = In1 for F.Cu tracks, In2 for In1 tracks, In1 for In2 tracks; "slot" = gap made by a foreign inner track; full list `work/FHJ/critical_crossings.csv`):
|
||||||
|
|
||||||
|
| group | net | slot crossings (worst) |
|
||||||
|
|---|---|---|
|
||||||
|
| SPI2 (W5500) | ETH_MISO/MOSI/SCK/CS | 1–3 each, 0.24–1.37 mm (In1 `/ETH_INT`, `/ETH_RST`) |
|
||||||
|
| USART6 (modem) | USART6_TX/RX (routed **on In1**, 68/37 mm) | 7 each; RX over In2 `/VEH5V` 4.61 mm, `/MODEM_PWR_EN` 3.18 mm |
|
||||||
|
| Modem UART 1V8 | DOUT_4G_M | 14 crossings (In1 `/CHRG_FAULT` 2.62 mm, `/KCOIL` 1.73, `/MAIN5V` 1.42) |
|
||||||
|
| Modem power | VBAT_MODEM | over In1 **`/RF_LTE`** (175.5, 57.0) and `/MAIN5V` 1.3 mm |
|
||||||
|
| Modem power | VIN_MODEM | 7 (In1 `/CHRG_FAULT` 1.8, `/DOUT_4G` 1.73) |
|
||||||
|
| Switch nodes | SW_PWRIN / SW_BAT | over In1 `/SW_5V` 1.83 mm, `/MAIN5V` 1.84, `/VFB_BST` 1.13 / `/SW_5V` ×5 |
|
||||||
|
| Crystals | HSE_IN/OUT | over In1 `/USART6_RX` 1.13 mm each (under Y3); ETH_XO over In1 `/ETH_RST` **6.28 mm** parallel |
|
||||||
|
| USB | USB_DP/DM (J9) | over In1 **`/24V_IN` 2.5 mm**, `/SW_5V` 2.47, `/CHRG_FAULT` 1.79; pair split In1/In2 |
|
||||||
|
| USB | DFU_DM | over In1 `/ETH_ACTLED` **5.98 mm** parallel |
|
||||||
|
| SIM | SIMB_CLK / SIMA_RST | over In1 `/SW_5V` 4.1 / 2.69 mm |
|
||||||
|
| Misc | I2C_SDA over In1 `/SER_TXB` **12.82 mm** parallel; NRST over `/USART6_RX` 6.45 mm | |
|
||||||
|
| RF | RF_LTE is **itself on In1** (F-06); RF_GNSS/RF_ANT_* have 0 slot crossings ✅ | |
|
||||||
|
- **Consequence:** return currents detour around slots (loop area → emissions and susceptibility). Parallel runs directly above/below foreign traces (12.8 mm I2C_SDA over SER_TXB, 6.3 mm ETH_XO over ETH_RST) are broadside crosstalk with no plane between. For the RF receiver this is the "unbroken In1" rule of the copper plan broken by design.
|
||||||
|
- **Fix (layout):** make In1 a plane again. Move all In1 tracks to In2/B.Cu, or to F.Cu where short. Priority: `/RF_LTE` (F-06), `/24V_IN` (F-16), `/SW_5V`, `/MAIN5V`, `/KCOIL`, `/USART6_TX/RX`, `/DOUT_4G`, `/CHRG_*`, `/SER_TXB/RXB`, `/ETH_*`, `/VFB_BST`, `/IGATE`. In2 then carries the signal layer with In1 GND above and the B.Cu 3V3 pour below. If In2 is kept as GND, accept In2 as the only plane and route everything else on B.Cu. Rule of thumb: no inner track under F.Cu fast nets, crystals, the RF runs, switch nodes or U18/U19. Target ≤ 3 In1 islands and no void longer than 5 mm under a critical net.
|
||||||
|
- **Effort:** layout (large)
|
||||||
|
- **Confidence:** high (geometry). Medium on the EMC consequence magnitude.
|
||||||
|
|
||||||
|
### F-06 RF feeds: LTE routed 22 mm on In1 under the modem power tracks with 2 via transitions and no fence; GNSS bias line runs 16.7 mm alongside the RF line at 0.27 mm; neither line is 50 Ω on either stackup
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-F items 2/4; Copper Plan §4/§5/§10 (① "both 50 Ω RF runs, CPWG on F.Cu over In1 … 0.35/0.25 mm, order controlled impedance"); `drogheda-v6-lte-island` (RF class 0.35 mm, "never autoroute"); pre-fab audit §7.
|
||||||
|
- **Evidence:**
|
||||||
|
- `/RF_LTE`: U19.60 → 1.75 mm F.Cu → via (174.25, 58.25) → **In1 22.1 mm** (4.95 + 15.49 + 1.46 + 0.24) → via (194.27, 53.72) → F.Cu → R118 → `/RF_ANT_LTE` → J13. Over the In1 run on F.Cu: `/VBAT_MODEM` (1.15 mm² overlap, the PA supply with 2 A bursts), `/SYS5V`, `/SW_IN`, `/MODEM_LED_A/K`; under it on In2: `/DIN_4G`. F.Cu GND above the run covers only 51 % of it; In2 GND below 85 %. GND vias within 2.5 mm of the whole 26 mm LTE path: 1 → fence pitch ≈ 52 mm.
|
||||||
|
- `/RF_GNSS` 22.7 mm F.Cu 0.5 mm; `/VCC_RF_GNSS` runs parallel for 9.8 + 3.2 + 3.75 = **16.7 mm at 0.27 mm edge gap** (no GND can fill a 0.27 mm gap). GND vias within 2.5 mm: 2 (fence ≈ 22.7 mm). F.Cu GND pour reaches only 24–41 % of a 0.5 mm band around each RF trace.
|
||||||
|
- Fence requirement: λ = c/(f·√εr) = 3e8/(2.7e9·√4.5) = 52.4 mm → λ/20 = 2.6 mm (3.0 mm with microstrip εeff ≈ 3.4). Actual 22–52 mm.
|
||||||
|
- Impedance, 0.5 mm microstrip (Hammerstad): file stackup (h = 0.48 mm, εr 4.5) → **68.9 Ω**. JLC04161H-7628 (L1–L2 prepreg 0.2104 mm, εr 4.4) → **43.9 Ω** (≈ 35 Ω with the intermittent 0.15 mm coplanar ground). The In1 LTE stripline with F.Cu at 0.21 mm and In2 at 1.065 mm is ≈ 30 Ω. The board file still carries the generic stackup (copper finish "None").
|
||||||
|
- **Consequence:** LTE: mismatch plus two unshielded via transitions, and the PA supply crossing the RF line (PA noise and burst ripple couple straight into the antenna feed); radiated desense of the adjacent F9P. GNSS: a coupled-line section between the LNA input and a bias line decoupled only at L21 (C144/C145); the line impedance is uncontrolled. The G3 desense bench test is likely to fail.
|
||||||
|
- **Fix (layout + stackup):** (1) Set the real stackup in Board Setup (JLC04161H-7628: 0.035/0.2104/0.035/1.065/0.035/0.2104/0.035, εr 4.4 prepreg / 4.6 core), and order impedance control. (2) Both RF runs on **F.Cu only**, as CPWG over **solid In1**: w ≈ 0.30–0.35 mm, gap ≈ 0.20–0.25 mm (verify in the JLC calculator for 50 Ω), RF netclass with clearance = that gap. (3) LTE: reroute U19.60 → R118/C146/C147 → D28 → J13 on F.Cu (rotate J13 or move U19's RF pad side toward it). Nothing crosses above or below; `/VBAT_MODEM` stays ≥ 3 mm away. (4) Via fence both sides at ≤ 2.5 mm pitch, ≤ 1 mm from the gap edge, and 2 vias per U.FL GND pad. (5) GNSS: route `/VCC_RF_GNSS` away (≥ 1 mm with a stitched GND strip between, or on In2 after a 100 pF + 100 nF decoupling at U18 pin 7), with L21 tapping the RF line stub-free at J12.
|
||||||
|
- **Effort:** both (stackup setting) / layout
|
||||||
|
- **Confidence:** high on geometry. Medium on impedance (closed-form estimates; the JLC calculator gives the final numbers).
|
||||||
|
|
||||||
|
### F-07 U20 (modem buck) input loop returns through a 0.25 mm GND track squeezed between pins 1 and 2; EP on thermal spokes, 0 vias
|
||||||
|
- **Severity:** Major (U20 part of A-06; the geometry details are new here)
|
||||||
|
- **Block / refs:** §4-F item 5; Copper Plan §4 ("C128 1 µF even closer … minimal SW pour"); AP64350 datasheet layout (Cin across VIN–GND/EP, EP vias).
|
||||||
|
- **Evidence:** C128.1 → U20.2: 0.72 mm ✅, C127.1: 2.38 mm ✅. Return: C128.2 → the 0.25 mm GND track routed **between U20.1 (BST) and U20.2 (VIN)** to the EP. The F.Cu path is 3.7 mm through that 0.25 mm neck; C127.2 → EP is 5.4 mm. Gaps: GND track to `/SW_MODEM` pad U20.8 0.150 mm, to `/VIN_MODEM` track 0.150 mm, to U20.2 0.195 mm. `/VIN_MODEM` 0.5 mm track 0.20 mm from the EP and 0.25 mm from U20.3/.4. EP: **0 vias** (nearest GND via 3.85 mm), 13 % perimeter contact (spokes). SW node 11.3 mm² (6.6 mm track) ✅; L20 2.24 mm ✅; BST 1.8 mm ✅. U20 VIN caps: 10 µF X5R 0805 50 V (C440198) keeps ≈ 30 % of its value at 24 V DC bias, and 1 µF (C15849).
|
||||||
|
- **Consequence:** the synchronous buck's hot loop includes ~3–4 nH of 0.25 mm neck, which gives SW-node ringing and input noise at the LTE PA supply. The HV24 outer rule (F-01) flags 15 spots here, because the GND neck sits at 0.15 mm from 24 V copper.
|
||||||
|
- **Fix (layout):** delete the GND neck. Put C128 (and a second 10 µF 50 V 1206, or 2 × 22 µF per ECO A if on 5 V only; see A-01 option A) with its GND pad on a solid F.Cu area bonded to the EP via ≥ 6 × 0.3/0.6 vias in the EP (2 × 3). Keep `/VIN_MODEM` ≥ 0.3 mm from EN/RT/EP pads.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-08 U2 (fan buck, 24 V) has no input capacitor within 17 mm; ground return 20–44 mm
|
||||||
|
- **Severity:** Major (moot if A-01 option 1, "delete the 24 V fan buck", is adopted)
|
||||||
|
- **Block / refs:** §4-F item 5; ECO §E.4 (U2 → C11 6.3 mm on V5.5; v6 is worse); pre-fab audit B5.
|
||||||
|
- **Evidence:** U2.7 VIN → C11 (100 nF) **20.75 mm**, C22 (10 µF actual) 18.32 mm, C10 17.04 mm (edge). F.Cu GND path C22.2 → Dbk1 anode 20.4 mm, C11.2 → Dbk1 44.1 mm. Dbk1 → U2.1 6.51 mm; L2 11.92 mm. EP 0 vias (nearest GND via 23 mm), solid pad connection ✅. FB divider R20/R21 0.67/1.48 mm ✅ (ECO §E.3 fixed). `/SW_FAN` 25.7 mm².
|
||||||
|
- **Consequence:** a 24 V non-synchronous loop of several cm², with ringing on a part whose VIN abs max is 30 V (A-01), next to `/24V`, `/COMP_FAN` (0.29 mm) and `/FREQ_FAN` (0.375 mm).
|
||||||
|
- **Fix:** preferred per A-01, delete U2 and run the fan from `/VEH5V`. If kept: a 1 µF + 100 nF 50 V X7R 0603 pair (C15849 / C14663) ≤ 1.5 mm from pins 7/5, Dbk1 anode on the same GND copper, 4 EP vias, L2 ≤ 5 mm.
|
||||||
|
- **Effort:** layout (or schematic DNP)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-09 U12 (3V3_ETH buck): catch diode 14 mm away on a different F.Cu island; `/ETH_FB` node 35 mm long, runs under the `/ETH_SW` node on In1
|
||||||
|
- **Severity:** Major (repeats the V5.5 EMC finding #3 pattern: FB far from the pin and next to SW)
|
||||||
|
- **Block / refs:** §4-F item 5; ECO §E.3/§E.4; `drogheda-einarboard-v5-audit` #3/#4.
|
||||||
|
- **Evidence:** C101.1 → U12.2 VIN 1.77 mm ✅. D11.1 → U12.1 SW **11.92 mm**, L8.1 → U12.1 15.10 mm, `/ETH_SW` 20.1 mm long / 27.2 mm². C101.2 (on the 224 mm² piece) and D11.2 (on the 178 mm² piece) are **different F.Cu GND islands** (loop closes through vias). FB divider: R88 (31.6 k) 2.59 mm from U12.4, but **R87 (100 k, top) 25.9 mm** away, so the high-impedance FB node `/ETH_FB` is 35 mm long (F.Cu + 28 mm In1), and 1.84 mm² of it lies directly **under the `/ETH_SW` copper** (In1). `/SYS5V` on In2 also passes under `/ETH_SW` (3.3 mm²).
|
||||||
|
- **Consequence:** switching noise injected into the FB node shows up as 3V3_ETH ripple/jitter at the W5500. Emissions from a 20 mm SW trace next to the RJ45 corner.
|
||||||
|
- **Fix (layout):** R87/R88 both ≤ 3 mm from U12.4, with the top resistor fed by a Kelvin trace from C102/C94. FB net ≤ 5 mm on F.Cu, nothing under `/ETH_SW`. D11 ≤ 2 mm from pin 1 with its anode on C101's GND copper. L8 ≤ 5 mm.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-10 Feedback nodes and power rails under 24 V switch nodes; LTC4040 BSTFB divider 21–23 mm from U6
|
||||||
|
- **Severity:** Minor (the U6 BSTFB part is A-14, Minor; noted here for the switch-node overlap)
|
||||||
|
- **Block / refs:** §4-F item 5 ("switch nodes not routed on inner layers under sensitive lines").
|
||||||
|
- **Evidence:** all switch nodes are F.Cu-only ✅ (`/SW_PWRIN`, `/SW_FAN`, `/SW_MODEM`, `/SW_BAT`, `/ETH_SW`). Inner copper under them: `/SW_PWRIN` over In1 `/MAIN5V` 2.41 mm², `/SW_5V` 2.91 mm², **`/VFB_BST` 1.14 mm²**; `/SW_BAT` over In1 `/SW_5V` 1.39 mm²; `/ETH_SW` over `/ETH_FB` (F-09). `/VFB_BST` (U6 RSTFB pin 10/BSTFB pin 18; R53/R54 499 k/100 k → 83 k Thevenin) is 41.2 mm long, 24 mm of it on In1, and R53/R54 sit 21.4/23.3 mm from the pins. Coupling estimate: C = ε0·4.5·1.14 mm²/0.48 mm = 0.095 pF; with dV/dt ≈ 24 V/10 ns that gives ≈ 0.23 mA spikes into an 83 kΩ node.
|
||||||
|
- **Consequence:** backup boost set-point noise (BSTFB), the mode that R1/R3 depend on. Switching noise on the F9P supply `/SW_5V`.
|
||||||
|
- **Fix:** R53/R54 ≤ 3 mm from U6.18/10 (A-14). Keep In1 under `/SW_PWRIN`/`/SW_BAT` solid GND (falls out of F-05).
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high (geometry); medium (effect size)
|
||||||
|
|
||||||
|
### F-11 Crystals 8–14 mm from their pins (Y1, Y3 HC-49); HSE lines cross an In1 slot; battery copper beside Y3
|
||||||
|
- **Severity:** Minor (HSE/LSE load and gm are covered in D-02/D-03; Y1 load in H-08)
|
||||||
|
- **Block / refs:** §4-F item 3; ECO §E.6 ("cristales ≤ 5 mm"); Copper Plan §6/§9 (crystal ≥ 10 mm from inductors; guard with ground).
|
||||||
|
- **Evidence (pad edge → IC pin; track length):**
|
||||||
|
|
||||||
|
| crystal | part | pin 1 → IC | pin 2 → IC | In1 GND under courtyard | foreign copper through courtyard | nearest inductor |
|
||||||
|
|---|---|---|---|---|---|---|
|
||||||
|
| Y1 25 MHz (W5500) | HC-49SD | **13.74 mm** (ETH_XI 23.0 mm) | **10.79 mm** (ETH_XO 22.0 mm) | 90 % | F.Cu DFU_DP/DM, In1 ETH_ACTLED, In2 SYS5V | L8 13.6 mm ✅ |
|
||||||
|
| Y2 3.6864 MHz (SC16IS) | HC-49SD | 5.51 mm | 4.64 mm | 90 % | In1 BOOT0/DOUT_4G/3V3, In2 GNSS_ANT_* | L8 21.3 ✅ |
|
||||||
|
| Y3 25 MHz (HSE) | HC-49SD | **8.32 mm** (14.5 mm) | **11.30 mm** (20.7 mm) | 94 % | In1 USART6_RX (crosses both HSE lines), BAT_PLUS on all 4 layers | L20 14.6 ✅ |
|
||||||
|
| Y4 32.768 kHz | 3215 | 3.92 mm ✅ | 6.32 mm | 100 % ✅ | F.Cu LED_C13, B.Cu MODEM_RST | 25.3 ✅ |
|
||||||
|
- **Consequence:** V5.5 worked at 12–15 mm with a solid plane under the lines. v6 adds In1 slots under Y3's lines and signals under Y1. Radiated harmonics (25/50/75 MHz) and marginal start-up (D-02).
|
||||||
|
- **Fix:** follow D-02/D-03 part swaps (3225 crystals). Y1 → 3225 25 MHz CL 10–12 pF (same family as D-02's C2901684) ≤ 3 mm from U11.30/31, caps adjacent, 2 GND vias. No inner-layer track under any crystal or its lines.
|
||||||
|
- **Effort:** both
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-12 Via stitching: 69 GND vias (V5.5: 165), 10 of 35 20 mm cells empty, 2 vias along 480 mm of board edge
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-F item 4; `drogheda-einarboard-v5-audit` ("165 GND vias, 4.6 mm median NN; 8 empty 20 mm cells" was already a finding on V5.5); ECO §E.6; Copper Plan §10.
|
||||||
|
- **Evidence:** GND vias per 20 × 20 mm cell (rows y 40→140, cols x 60→200):
|
||||||
|
`[0,5,4,3,0,1,0] [2,3,4,4,4,0,2] [2,1,2,3,0,1,3] [0,2,2,2,0,2,4] [4,5,0,2,2,0,0]`: 10 empty cells. Distance from any board point to the nearest GND via: median 7.7 mm, p90 15.7 mm, **max 27.8 mm** at (197.7, 42.3) (NE corner next to J13). Vias within 3 mm of the edge: 2 (average pitch 240 mm). NN median 5.2 mm, but the vias are clustered around the MCU.
|
||||||
|
- **Consequence:** edge radiation and ESD return paths are uncontrolled. Plane-to-plane resonances between F.Cu/In1/In2 pours are undamped at LTE frequencies. Regresses V5.5 by 96 vias.
|
||||||
|
- **Fix (layout):** a 5 mm stitching grid tying F.Cu GND, In1, In2 (skip where B.Cu 3V3 needs continuity: the vias are GND and pass through the 3V3 pour with antipads). A fence ≤ 5 mm pitch along all four edges, 1 mm inside the 0.5 mm edge clearance, and ≤ 2.5 mm around the RF runs and U.FL connectors (F-06). Expect ≈ 500–600 vias of 0.3/0.6 mm. Let the pour's `min_thickness`/island removal keep the F.Cu pieces joined.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-13 Exposed pads and module grounds: 0 thermal vias on U6/U25/U20/U2/U12; U25 and U20 EPs (and every GND pad except 5 EPs) join the pour through 0.5 mm thermal spokes
|
||||||
|
- **Severity:** Major (U6 is also in A-02; U25/U20/U2/U12 EPs in A-06)
|
||||||
|
- **Block / refs:** §4-F item 4; Review §2 "Switcher EP vias"; ECO §D2 ("EP de U6 con ≥ 9 vías").
|
||||||
|
- **Evidence:** zones use `connect_pads` default = thermal (gap 0.5 / spoke 0.5 mm) for all pads. Pad overrides `zone_connect 2` (solid) exist only on U6.25, U2.9, U12.9, U11.9, U11.29, JP1–5. Contact measured at the pad edge: U25 EP 18 %, U20 EP 13 %, D34 anode 18 %, C150 GND 21 %, U19 GND pads 18–24 %. Vias inside EP: U6 0, U25 0, U20 0, U2 0, U12 0.
|
||||||
|
- **Consequence:** junction temperature: TPS54360B/AP64350 θJA figures assume a soldered PowerPAD with vias into planes. Spokes and no vias roughly double the thermal resistance, at 45 °C port ambient. It also adds inductance in the hot-loop returns.
|
||||||
|
- **Fix:** set all copper zones to **"Thermal reliefs for PTH only"** (`(connect_pads thru_hole_only (clearance 0.3))`) so SMD pads are solid. EP via arrays of 0.3/0.6 mm: U6 3 × 3 (≥ 9, ECO D2), U25 3 × 3, U20 2 × 3, U2/U12 2 × 3, all to In1+In2. Tented on the bottom side, or plugged (JLC "via in pad, filled and capped" option) under U19/U18.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-14 DFU ESD (D14/D15/D16) hangs on stubs; D15 is 11 mm of copper from J11; J9 still has no ESD
|
||||||
|
- **Severity:** Minor (J9 = G-02, Major, not counted here)
|
||||||
|
- **Block / refs:** §4-F item 6; ECO §E.5; V5.5 finding (41 mm) fixed in placement.
|
||||||
|
- **Evidence:** DFU_DP/DM have **no series resistors** (J11 → U16 PA12/PA11 directly), so "ESD before the series R" is n/a. Pad-edge distance to the nearest J11 pad / copper path J11 → ESD / ESD on the signal path?: D14 (DP) 2.53 / 3.3 mm / **no (T-stub)**; D15 (DM) 6.07 / **10.9 mm** / no; D16 (VBUS) 2.62 / 3.0 mm / no. ESD GND pad → nearest GND via: 2.6 / 1.8 / 4.9 mm. Conn → MCU path 48–53 mm.
|
||||||
|
- **Consequence:** a stub adds series inductance to the clamp path (≈ 1 nH/mm): the clamp voltage rises at the fast IEC 61000-4-2 edge. D15 at 10.9 mm is not "at the connector".
|
||||||
|
- **Fix (layout):** route J11 D+/D− **through** the D14/D15 pads (pad-in-line), D15 ≤ 3 mm copper from J11, each ESD GND pad with its own via ≤ 1 mm. Optional: replace the three PESD5V0S1BA by one USBLC6-2SC6 (C7519) at J11 (≈ 3.5 pF/line). J9: add USBLC6-2SC6 per G-02.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-15 Outer-layer 24 V spacing: 15 spots < 0.3 mm (38 < 0.5 mm), including `/VIN_PROT` 0.16 mm from `/VEH5V`
|
||||||
|
- **Severity:** Minor (IPC-compliant under mask; the 24 → 5 V spot is the one to fix first)
|
||||||
|
- **Block / refs:** §4-F item 1; F-01.
|
||||||
|
- **Evidence (corrected classes, F.Cu, non-zone copper, unique spots):** `/SW_MODEM` U20.8 – GND 0.25 mm track **0.150**; `/VIN_MODEM` – GND track 0.150 / U20.9 0.200 / U20.2 pad–GND track 0.195; **`/VIN_PROT` 1.5 mm – `/VEH5V` 0.8 mm track 0.162 mm at (176.24, 116.28)** and – `/VEH5V` via 0.193; `/SW_MODEM` 1.0 mm – GND 0.170; `/Q23_GATE` Q23.1 and `/VIN_PROT` Q23.3 – `/USB_VBUS` 0.225; `/BST_MODEM` U20.1 – GND 0.225; `/VIN_MODEM` – U20.3 `/MODEM_PWR_EN` 0.250 / U20.4 0.250; `/SW_PWRIN` – GND 1.0 mm track 0.270; `/BST_MODEM` – GND 0.275; **`/24V` 1.5 mm – `/COMP_FAN` 0.290** (noise into the fan-buck compensation). The other 23 spots (0.30–0.50 mm) are listed in `work/FHJ/hv24_violations_corrected_rule.csv`. Same-footprint pad pairs < 0.5 mm: only U2.7/.1/.8 to U2 EP (0.355–0.416 mm), covered by the F-01 exception.
|
||||||
|
- **Consequence:** a solder splash or conductive contamination at (176.2, 116.3) puts 24 V on `/VEH5V`. The via there is untented (no tenting set), so it is bare copper 0.19 mm from a 24 V trace.
|
||||||
|
- **Fix:** 0.3 mm outer rule (F-01); reroute `/VIN_PROT` vs `/VEH5V` near R124/U25 (≥ 0.5 mm here, since it is 24 → 5 V); remove the U20 GND neck (F-07); `/USB_VBUS` away from Q23; `/COMP_FAN` ≥ 1 mm from `/24V`. Tent all vias except test vias.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-16 `/24V_IN` (HV24, 1.5 mm) runs 27 mm on In1 through the GND plane, 0.500 mm from `/SW_5V` over 2.8 mm
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** short-incident lesson ("keep 24V_IN off inner layers next to LV or reroute along board edge").
|
||||||
|
- **Evidence:** In1 segments (167.5, 128.65) → (160.6, 121.75) → (143.25, 121.75). Minimum gap to `/SW_5V` (F9P rail, In1 1.0 mm) = 0.500 mm, with 2.8 mm of `/SW_5V` within 1 mm. It cuts a 25 mm slot in In1 that the modem USB pair crosses (F-05, F-17).
|
||||||
|
- **Consequence:** meets the 0.5 mm rule exactly, with no margin, in the configuration that failed on 23-Jul.
|
||||||
|
- **Fix:** route P1.1 → F2/Q10/D10 on F.Cu along the south edge (the SE corner has room once U25 is re-clustered). If In1 must be used, keep ≥ 1.0 mm to any LV net and nothing crossing above it.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-17 USB pairs: J9 (modem, HS-capable) pair split across layers and crossing the `/24V_IN` and `/SW_5V` slots; DFU pair runs 6 mm over `/ETH_ACTLED`
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Block / refs:** §4-F item 2; pre-fab audit §7 (USB pair split); Copper Plan §9 (90 Ω pairs).
|
||||||
|
- **Evidence:** `/USB_DP` F.Cu 49.9 + In1 9.6 mm; `/USB_DM` F.Cu 50.0 + In1 8.0 + In2 1.7 mm. They cross In1 `/24V_IN` (2.5 mm gap) at (157.75, 121.75), `/SW_5V` 2.47 mm, `/5V_FAN`, `/IGATE`, `/CHRG_FAULT/STAT`. `/DFU_DM` over In1 `/ETH_ACTLED` 5.98 mm parallel.
|
||||||
|
- **Consequence:** A7670SA USB is high speed. Service firmware updates through J9 may fail to enumerate at HS or fall back. The DFU (FS) port is tolerant.
|
||||||
|
- **Fix:** both pairs on F.Cu only, over solid In1, coupled (≈ 0.2/0.15 mm on JLC7628 for 90 Ω; verify), ≤ 1 via pair, no slot crossings.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high (geometry); medium (HS failure)
|
||||||
|
|
||||||
|
### F-18 Silkscreen: 304 of 312 reference texts are 0.5 mm / 0.1 mm (JLC minimum 1.0 mm / 0.15 mm); 14 DRC silk items
|
||||||
|
- **Severity:** Minor (G-05 also covers labels; not double-counted)
|
||||||
|
- **Block / refs:** §4-F item 8; pre-fab audit §7; JLC capabilities.
|
||||||
|
- **Evidence:** reference fields: 304 × 0.5/0.1 mm visible, 6 × 0.5/0.1 hidden, 2 × 1.0/0.15. Board texts: 6 × 0.5/0.1, 2 × 1.0/0.1, 1 × 2.0/0.5. The `.kicad_dru` text rule is 0.5/0.1, so DRC stays silent. DRC: 11 silk_overlap (D27, R99/C157, C126/U19, Q21/U19, JP3, U24, U23, Q10/JP5, Q23), 2 silk_over_copper (Rigb1 ref on C9.2; C10 ref on C10.2), 1 silk_edge (P1 outline at the south edge). Polarity marks: all polarized parts use KiCad or easyeda footprints that carry pin-1/cathode marks (D_SMA/SMB/SMC/SOD-123/323/128/923, CP_Elec, LED, SOIC/QFN/LQFP), but D27/D28 (SOD-923) and the Q10 region marks are among the overlap items: check them in the 3D view.
|
||||||
|
- **Consequence:** JLC prints sub-minimum text blurred or drops it. Technicians (Jesús) cannot read refs and test points.
|
||||||
|
- **Fix:** refs ≥ 0.8 mm/0.15 mm (1.0/0.15 where it fits). Set the DRU text rule to `(min 0.8mm)`/`(min 0.15mm)`. Clear the 14 DRC items.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-19 Manufacturability vs JLC 4-layer standard: passes, with J9/J11 (USB4085 THT) at the JLC limits
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Block / refs:** §4-F item 9.
|
||||||
|
- **Evidence:**
|
||||||
|
|
||||||
|
| parameter | used on v6 | `.kicad_pro`/`.kicad_dru` | JLC 4-layer std |
|
||||||
|
|---|---|---|---|
|
||||||
|
| min track | 0.20 mm | 0.2 | 0.09 mm ✅ |
|
||||||
|
| min spacing | 0.15 mm (rule) | 0.15 | 0.09 mm ✅ |
|
||||||
|
| via drill/pad | 0.30/0.80 mm (all 210) | 0.3/0.5 min | 0.15/0.25 mm ✅ |
|
||||||
|
| via annular ring | 0.25 mm | 0.1 | ✅ |
|
||||||
|
| PTH annular ring | **0.15 mm** (J9/J11 0.7 pad/0.4 drill) | — | 0.15 abs / 0.20 rec. ⚠ |
|
||||||
|
| hole-to-hole | **0.45 mm** (J9/J11 rows) | 0.25 | 0.45 mm ⚠ (at limit) |
|
||||||
|
| PTH hole → other-net track | **0.30 mm** (J11) | — | 0.28 mm ⚠ |
|
||||||
|
| via hole → other-net copper | 0.40 mm | 0.25 | 0.2 mm ✅ |
|
||||||
|
| copper → edge | 0.625 mm (tracks), fills 0.50 | 0.5 | 0.2 mm ✅ |
|
||||||
|
| fiducials | none | — | optional ✅ |
|
||||||
|
| outline | 140.002 × 100.002 mm, 4 segments, corner gaps ≤ 2.5 µm | — | ✅ |
|
||||||
|
- **Fix (order notes):** ENIG (LGA U18/U19); stackup JLC04161H-7628 with impedance control (F-06); X-ray on U18/U19; tent vias; J9/J11 accepted at the limit (GCT USB4085 standard footprint, V5.5 fabbed fine).
|
||||||
|
- **Effort:** none (order notes)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-20 Courtyard overlaps: all 15 are bounding-box artefacts (0 real overlaps)
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Block / refs:** §4-F item 7.
|
||||||
|
- **Evidence:** real courtyard polygons from each footprint, intersected: **0.000 mm²** for all 15 (C10/C11, C10/Rcomp1, C126/R127, C142/R116, C151/C78, C151/R125, C3/C40, C30/C78, D4G1/Q22, D5/Q4, J9/Rcc2, L20/R111, Q22/R109, R50/U6, TP4/TP5). Minimum pad-to-pad gaps 0.46–3.50 mm. No other polygon overlap on the board. KiCad DRC `courtyards_overlap` (not ignored) also reports 0. Only MH5–MH8 lack courtyards.
|
||||||
|
- **Fix:** none. Watch the H-03 inductors: MWSA0804S bodies are 8.2 × 8.8 mm against an 8.0 × 8.0 courtyard basis.
|
||||||
|
- **Effort:** none
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### F-21 The one dangling `/SW_5V` track end is benign
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:** segment (88.35, 121.881) → (86.35, 121.881), 0.5 mm, F.Cu. Its end is 0.025 mm outside U21.3's pad edge but overlaps the pad by 0.085 mm². Connected per KiCad (no `track_dangling` in DRC) and per the pack's union-find.
|
||||||
|
- **Fix:** extend 0.3 mm to the pad centre (cosmetic).
|
||||||
|
- **Effort:** layout (trivial)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### H-01 U15 MAX3232ESE (narrow SOIC-16) is assigned to a wide SOIC-16W footprint: it cannot be soldered
|
||||||
|
- **Severity:** Blocker
|
||||||
|
- **Block / refs:** §4-H (package/footprint match); memory `drogheda-einarboard-v5-audit` (U13 is wide, "package truth only from the mfr ordering table").
|
||||||
|
- **Evidence:** U15 LCSC **C15846 = MAX3232ESE+T, "SOIC-16"** (JLC DB). Maxim "ESE" = 16-pin narrow SO (150 mil). Footprint `Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm`, pads 2.05 × 0.6 mm, **pad rows 9.3 mm apart** (x 117.3 / 126.6). Narrow SOIC lead span ≈ 6.0 mm, so the leads end ≈ 1.6 mm short of the pads on each side. The same combination is in V5.5 as fabbed and V5.6. (U13 PCF8574T C7605 is SOIC-16 300 mil = wide ✅.)
|
||||||
|
- **Consequence:** RS-232 (P12) dead on every v6 board. JLC either rejects or places a part that cannot be soldered. V5.5 boards probably have the same defect unless JLC substituted a part.
|
||||||
|
- **Fix (choose one):** (a) keep the layout and use a wide part: **C118514 MAX3232EEWE+T (SOIC-16 300 mil, 30 in stock, $5.68)** or C1544667 MAX3232ECDW (0–70 °C, 16 in stock). Both are thin stock, so (b) is **recommended: change the footprint to `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`** and keep C15846 (4873 in stock) or use C19268179 MAX3232ID (SOP-16, −40…125 °C, 5709 in stock, $0.45). Re-place C84–C88 hard against it.
|
||||||
|
- **Effort:** both (footprint + local re-route) for (b); schematic-only for (a)
|
||||||
|
- **Confidence:** high (DB package + footprint pad geometry). Worth one look at a V5.5 board's U15 to confirm the V5.5 history.
|
||||||
|
|
||||||
|
### H-02 Stock: U10 (15 pcs) and R53 (6 pcs) cannot be placed on a 20-board order; C103211, the A7670SA and J14 limit a 100-board order
|
||||||
|
- **Severity:** Blocker (for any order ≥ 16 boards)
|
||||||
|
- **Block / refs:** §4-H.
|
||||||
|
- **Evidence (JLC DB stock vs need at 20 / 100 boards):**
|
||||||
|
|
||||||
|
| ref | LCSC | part | stock | per board | fix |
|
||||||
|
|---|---|---|---|---|---|
|
||||||
|
| U10 | C729142 | SC16IS762IPW | **15** | 1 | **C57156 SC16IS752IPW,128** (2670, $3.80 vs $7.32; the value field already says 752; register-identical per memory) |
|
||||||
|
| R53 | C131054 | 499 k 1 % YAGEO | **6** | 1 | **C177479** RCT03499KFLF 499 k 1 % 0603 (26 862) |
|
||||||
|
| R20,R56–58,R85,R87,Ren1,Rfreq1,Rgs1 | C103211 | 100 k **5 %** RALEC | 702 | 9 | **C25803** 100 k 1 % (Basic, 10.8 M, already in BOM for R113–R115/R119) |
|
||||||
|
| U19 | C18548276 | A7670SA-LASC | 96 | 1 | pre-order/consign for qty 100 |
|
||||||
|
| U18 | C5120257 | ZED-F9P-04B | 104 | 1 | pre-order for qty ≥ 100 |
|
||||||
|
| J14 | C2977286 | JAE SF72S006 | 10 890 | 1 | category "Pre-ordered Products": pre-order into the JLC account (pre-fab B4) |
|
||||||
|
| L2+L8 / L6 / U13 / P11+P12 | C17700171 / C17700165 / C7605 / C5160226 | — | 470 / 646 / 517 / 512 | 2 / 1 / 1 / 2 | ok at 100 boards (L2+L8 = 200, P11+P12 = 200) |
|
||||||
|
- **Consequence:** JLC leaves U10/R53 unplaced (U10 = RS-485/RS-232 bridge; R53 = LTC4040 boost set-point: **the backup rail would not regulate**).
|
||||||
|
- **Fix:** LCSC swaps above (schematic field only). Re-check stock on order day (the DB is a snapshot).
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** high (DB snapshot; stock moves daily)
|
||||||
|
|
||||||
|
### H-03 Sunlord MWSA0804S inductors (L2, L6, L8, L20) sit on a Bourns SRU8028 land pattern
|
||||||
|
- **Severity:** Major
|
||||||
|
- **Block / refs:** §4-H (Leo's L7 SRU8028 vs MWSA0804S question); pre-fab audit ("check its pads against the SRU8028 land").
|
||||||
|
- **Evidence:** footprint `Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm`: pads 2.0 × 3.2 mm at ±3.9 mm (inner gap 5.8 mm, outer 9.8 mm). MWSA0804S (Sunlord spec, table 4-1): body A 8.2 ± 0.3 × B 8.8 ± 0.4 × 3.8 mm, electrodes D 1.4 × E 5.0 mm, recommended land I 2.75 / J 4.0 / H 5.5 mm (typ). Electrode inner gap ≈ 8.2 − 2 × 1.4 = 5.4 mm, so an electrode spans 2.7–4.1 mm from centre while the pad spans 2.9–4.9 mm: overlap 1.2 of 1.4 mm length × 3.2 of 5.0 mm width ≈ **55 % of the electrode area wetted**. Body 8.8 mm vs the 8.0 mm courtyard basis. The same combination on V5.5 assembled and ran.
|
||||||
|
- **Consequence:** reduced joint area and self-centring on the heaviest SMD parts, in a vibrating vehicle. L6 (backup boost, ~4 A) and L20 (modem buck, 2 A bursts) are exactly where a cracked joint would show up as the V5.5-style "modem dark on battery".
|
||||||
|
- **Fix:** make `Drogheda-v6:IND-SMD_MWSA0804S` from the Sunlord drawing (pads 2.75 × 4.0 mm, 5.5 mm inner gap → pad centres ±4.125 mm; courtyard 9.4 × 9.8 mm) and assign it to L2/L6/L8/L20 (C17700171/65/67). Or switch to true SRU8028 parts if JLC stocks them. Re-check neighbours for the 0.4 mm body growth.
|
||||||
|
- **Effort:** both (footprint swap; 4 parts re-placed)
|
||||||
|
- **Confidence:** medium (land pattern letters read from a mirrored Sunlord spec; confirm against the LCSC PDF, which is blocked from this sandbox)
|
||||||
|
|
||||||
|
### H-04 U25 footprint carries `LCSC Part` = C2071691 (AP64350) next to `LCSC` = C524806 (TPS54360B)
|
||||||
|
- **Severity:** Major (A-15 rates it Minor. I rate it Major because the AP64350 is pin-compatible (1 BST, 2 VIN, 3 EN, 4 RT, 5 FB, 6 COMP, 7 GND, 8 SW, EP): a board built with it passes the bench and then dies at the first transient above the AP64350's 40 V rating, behind a 53 V clamp)
|
||||||
|
- **Evidence:** `sch_pcb_sync.md` §2; the only such conflict on the board. Which field a BOM/CPL plugin uses depends on the tool's field-name priority.
|
||||||
|
- **Fix:** delete the `LCSC Part` property from U25 on the PCB (and in the Drogheda-v6 footprint library if it came from there). Generate BOM/CPL from the schematic `LCSC` field only.
|
||||||
|
- **Effort:** schematic/board property only
|
||||||
|
- **Confidence:** high (fact); medium (which field JLC tooling picks)
|
||||||
|
|
||||||
|
### H-05 Voltage ratings on the vehicle rail: D21 (30 V), Dbk1 (40 V), U2 (28 V operating/30 V abs) sit behind a 36.7–53.3 V TVS
|
||||||
|
- **Severity:** Note (duplicate of A-01, Blocker; listed so the BOM table is complete)
|
||||||
|
- **Evidence:** D21 PMEG3050EP C50603: VR 30 V, IR 8 mA @ 30 V. Reverse bias = /VIN_MODEM − /MAIN5V ≈ 36 − 0.45 − 4.79 ≈ 30.8 V at the top of the TVS standoff band (SMBJ33A VBR 36.7–40.6 V), ≈ 48 V at the 53.3 V clamp. Dbk1 SS34 C8678 (40 V) on `/SW_FAN` swings to `/24V`. U2 MP1584EN C15051 "4.5–28 V". All ceramics on 24 V nets are rated ≥ 50 V: C22 50 V (2.1× at 24 V, 1.8× at 28.8 V), C127/C128 50 V, C11 50 V, C149/C150 100 V ✅; C10/C151 50 V electrolytics ✅.
|
||||||
|
- **Fix:** per A-01 (DNP U2, feed U20 from MAIN5V). If D21 stays: **C53114006 PMEG6030EP (60 V, 3 A, SOD-128 drop-in, 8956 in stock)**. If Dbk1 stays: 60 V SMA Schottky (SS36 class).
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### H-06 J10, P11, P12: PCB DNP vs schematic populated; the P11/P12 schematic footprint is Vertical (not in the library) while the ordered part is right-angle
|
||||||
|
- **Severity:** Minor (= G-03; adds the part/footprint fact)
|
||||||
|
- **Evidence:** PCB DNP on J10/P11/P12; schematic `dnp` empty, so a schematic-exported BOM orders them. P11/P12 LCSC C5160226 = DEGSON 15EDGRC-3.5-03P, **right-angle**, which matches the PCB `…_Horizontal` footprint. The schematic's `…_Vertical` is stale and absent from the library (ERC footprint_link_issues). J10 C12074 HR911105A: schematic lib nickname `Connector_RJ45` is not configured (PCB `Connector_RJ`). Cost at stake per board: J10 $1.20 / $0.92, P11+P12 $0.35 / $0.28 (qty 20 / 100). With J10 DNP the populated W5500 block (U11, U12, Y1, C90–C103; ≈ $2.5) has no connector.
|
||||||
|
- **Fix:** decide intent. Set the schematic footprints to `…_Horizontal` and `Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal`, and put the DNP flags in the schematic so Update-PCB and the BOM agree. If Ethernet is not fitted on v6, DNP U11/U12/Y1 and their passives too (A-05 wants U12 gated anyway).
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### H-07 Crystal load capacitors do not match the crystals' 20 pF CL (Y1 W5500 18 pF → +70…+130 ppm)
|
||||||
|
- **Severity:** Minor (Y3/Y4 detail in D-02/D-03)
|
||||||
|
- **Evidence:** Y1/Y3 C14872 X49SM25MSD2SC: 25 MHz, **CL 20 pF**, ±20 ppm, **−20…+70 °C**. Y1 caps C95/C96 18 pF → CL_eff = 9 + ~4 pF stray = 13 pF. Pulling Δf/f = (C1/2)·[1/(C0+13) − 1/(C0+20)] with C0 3–5 pF, C1 8–15 fF gives **+69…+129 ppm**, against IEEE 802.3 100BASE-TX ±50 ppm. Y2 C2238 3.6864 MHz CL 20 pF with 22 pF caps (+~50 ppm, irrelevant for UART). The −20…+70 °C crystal rating is below a sealed port box's internal temperature.
|
||||||
|
- **Consequence:** Ethernet link margin (most PHYs tolerate ~±100 ppm total, so it probably links, as on V5.5), and frequency drift above 70 °C.
|
||||||
|
- **Fix:** Y1 caps → **33 pF C0G C1663 (Basic)**: CL_eff = 16.5 + 4 ≈ 20 pF. Better: Y1 → a 3225 CL 10–12 pF −40…+85 °C crystal with 12–15 pF caps (the same family as D-02's Y3 choice), which also fixes F-11.
|
||||||
|
- **Effort:** schematic-only (caps) / both (3225)
|
||||||
|
- **Confidence:** medium (C0/C1 are typical HC-49S values; the YXC PDF is not fetchable here)
|
||||||
|
|
||||||
|
### H-08 Value-field / BOM mismatches
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Evidence:** C22 "22uF/50V" but C138687 is **10 µF 50 V X7R 1210** (known since V5; the BOM is master). Y2 "1.8432MHz" but C2238 is 3.6864 MHz (= D-16). U10 "SC16IS752IPW" but C729142 is SC16IS762 (H-02 fixes it). C103 "100uF/6.3V" but C88744 is 35 V (harmless). C130/C131/C78 "220uF/10V" but C2827940 is 16 V, 85 °C/2000 h general-purpose (life/ripple = A-09, Major there).
|
||||||
|
- **Fix:** correct the value fields (C22 → "10uF/50V", or pick a real 22 µF/50 V 1210 if 22 µF was intended; Y2 → "3.6864MHz").
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### H-09 BOM completeness, DNP list, test points, stale symbols: pass, with details
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:** every fitted BOM line has an LCSC number except TP1–TP8 (copper test pads, no part, correct) and PF1–PF21 (virtual). DNP in the schematic: C146/C147 (LTE π, no LCSC), R107/R108, R124/R125, R127–R130 (0 R, LCSC present), U22. On the PCB also J10/P11/P12 (H-06). JP1–JP5 are excluded from BOM/CPL. F2 now C206910 (Littelfuse 0154002.DR 2 A/125 V NANO2 + holder, matches `Fuseholder_Littelfuse_Nano2_154x`). **Stale symbols:** the 10 "not found" (Q_PMOS_GDS ×2, Q_PMOS_GSD, Q_NMOS_GSD ×4, D_Zener_ANK ×2, PCF8574) and 22 "differs from library" symbols were checked pin → pad → net against the part datasheets on 25 parts. IRFR5305 DPAK 1 = G, 2 = tab = D (`/24V_IN`, `/VIN_FUSED`), 3 = S ✅; AO3401A/AO3400A/2N7002 SOT-23 1 G, 2 S, 3 D ✅; BZX84C15 1 A, 3 K (cathode on /24V, /VIN_PROT) ✅; PCF8574T SO-16W 1–3 A0–A2, 8 VSS, 14 SCL, 15 SDA, 16 VDD ✅; TPS54360B 1 BOOT…8 PH ✅; AMS1117 1 GND, 2/tab OUT, 3 IN ✅; diodes D5/D6/D10/D21/D22/D2 K on pin 1 ✅. **No hidden pin mismatch.** Current-sense/power resistors: RS1 10 mΩ 1 W at 2.5 A → 62.5 mW (6 %) ✅. Rig1 22 k 0603 at 58 V → 0.15 W > 0.1 W (D-06).
|
||||||
|
- **Fix:** none beyond H-01…H-08.
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### H-10 Cost: ≈ $132 (qty 20) / $124 (qty 100) per board in parts; +$91 vs V5.6, 94 % of it ZED-F9P + A7670SA; 79 Extended parts = $237 setup per order
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence (DB price breaks at the per-board quantity × board count; `bom_check.csv`):**
|
||||||
|
- v6 fitted parts: 284 placements (schematic BOM less DNP, including J10/P11/P12). **Qty 20: $131.98/board. Qty 100: $124.40.** Modules: ZED-F9P-04B $80.11 (flat) + A7670SA-LASC $6.07 = $86.18. Everything else: $45.80 at qty 20.
|
||||||
|
- V5.6 (same method, `ref_versions/v56_components.csv`, 235 placements): **$40.69 (qty 20) / $33.83 (qty 100)**. Delta **+$91.30 / +$90.14 per board**. The main additions are F9P $80.11, A7670SA $6.07, F2+holder $1.10, 2 × 74LVC2T45 $0.82, L22 $0.72, U25 $0.56, D21 $0.39, J14 $0.36; removed are 2 × 220 µF polymer, 2 × TMP102, 2 XBee sockets, USBLC6, SW4G1 (−$1.9).
|
||||||
|
- The board delta excludes what v6 removes from the unit: the ArduSimple simpleRTK2B (its own ZED-F9P) and the 4G NTRIP Master. The **system** cost almost certainly drops (Inputs needed).
|
||||||
|
- Setup: 79 unique Extended parts × $3 = **$237/order** ($11.85/board at 20, $2.37 at 100). The DB flags only 351 parts Basic; some here are Basic at JLC in reality (e.g. C1589 10 nF). Cheap consolidations: C14676 → C21190 (1 k 1 % Basic), C14675/C103211 → C25803, C304185 → C21189 (0 R Basic): −4 fees.
|
||||||
|
- A7670SA at $6.07 looks low for this module. Treat it as a DB snapshot price and confirm at order.
|
||||||
|
- **Confidence:** medium (DB snapshot prices, excl. PCB/assembly/THT fees)
|
||||||
|
|
||||||
|
### J-01 DRC "0 errors" is produced by the rule set, not by the copper
|
||||||
|
- **Severity:** Major (process; the rule fix itself is F-01 Blocker)
|
||||||
|
- **Evidence:** DRC ran with "Minimum clearance 1" = 0.15 mm overriding every class (F-01). With the corrected netclasses and DRU: **6 inner-layer errors** (all `/IGN_IN`, F-02) + **15 outer-layer errors** at the 0.3 mm rule (38 at 0.5 mm), plus ≈ 178 zone-fill proximities that disappear on refill. If Default = 0.2 mm were enforced without the floor rule: +471 pairs. An RF class added now would also be silently overridden by the 0.15 mm rule.
|
||||||
|
- **Fix:** F-01 rules → refill → DRC. Accept only after the new DRC is clean (the T15 width warnings excepted per J-02).
|
||||||
|
- **Effort:** rules + layout
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### J-02 track_width warnings: 59 real (power paths under-sized for their current), 124 benign (T15 rule over-strict)
|
||||||
|
- **Severity:** Major (the copper fix for `/SW_BAT`, `/BAT_PLUS`, `/VEH5V`, `/VIN_SW` is A-02/A-07; the modem nets are block B)
|
||||||
|
- **Evidence (IPC-2221, 1 oz, 10 °C rise: 0.25 mm ext 0.88 A / int 0.44 A; 0.5 mm ext 1.45 A / int 0.72 A; 0.8 mm ext 2.03 A):**
|
||||||
|
|
||||||
|
| net | DRC hits | widths (mm) | est. current | verdict |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| `/SW_BAT` | 6 | 0.25/0.3/0.5 | ~4 A backup boost | **real** (2 hits; 4 are ≤ 1.5 mm pin necks) |
|
||||||
|
| `/BAT_PLUS` | 4 | 0.25/0.5 | 2.4 A charge / ~4 A backup | **real** |
|
||||||
|
| `/MAIN5V` | 21 | 0.3/0.5 | 2.5 A | **real** (19) |
|
||||||
|
| `/VEH5V` | 15 | 0.25–0.8 (incl. In1) | 3 A | **real** (11) |
|
||||||
|
| `/VIN_SW` | 10 | 0.25–0.8 (incl. In2) | 2.5 A | **real** (8) |
|
||||||
|
| `/VIN_MODEM` | 9 | 0.3/0.5 | 1.9 A on battery | **real** (8) |
|
||||||
|
| `/VBAT_MODEM` | 7 | 0.25/0.5 (incl. In1) | 2 A bursts | **real** (7) |
|
||||||
|
| `/3V3_ETH` | 54 | 0.25–0.5 (In1) | 0.15 A | benign: move the net to Default |
|
||||||
|
| `/5V_FAN`, `/FAN_RET`, `/SW_FAN` | 14/7/8 | 0.5 | ≤ 0.3 A | benign |
|
||||||
|
| `/SW_5V`, `/SW_IN` | 9/7 | 0.3/0.5 | 0.2 A | benign |
|
||||||
|
| `/SYS5V` | 6 | 0.5/0.8 | ~0.6 A | benign |
|
||||||
|
| `/VIN_PROT`, `/VIN_FUSED` | 5/1 | 0.5 | 0.8 A at 24 V | benign (current); keep the 0.8 mm rule for pulse/fuse coordination |
|
||||||
|
Per-item classification in `ercdrc_classified.csv`.
|
||||||
|
- **Fix:** widen/pour the seven real nets (targets per A-02/A-07 and block B: `/SW_BAT` ≥ 2 mm pour, `/BAT_PLUS` ≥ 1.5 mm, `/MAIN5V`/`/VEH5V`/`/VIN_SW` ≥ 1.5 mm or F.Cu pours, `/VBAT_MODEM` ≥ 1.5–3 mm, `/VIN_MODEM` ≥ 0.8 mm). Relax T15 for the benign nets so the warning list becomes a clean gate.
|
||||||
|
- **Effort:** layout
|
||||||
|
- **Confidence:** high (widths); medium (current estimates, stated per net)
|
||||||
|
|
||||||
|
### J-03 ERC pin-to-pin (104) are pin-type noise; no real driver conflict
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Evidence:** all 104 involve pins typed `unspecified` in easyeda-imported symbols (U19, U20, U23, U24, U26, D21, D22, D27, D28, J12, J13): 50 Unspecified–Passive, 46 Unspecified–Unspecified, 5 –Bidirectional, 2 –Power output, 1 –Input. Net-by-net check found no conflict. U23 DIR (pin 5) = GND (B → A: `/DIN_4G` → `/DIN_4G_M`), U24 DIR = VCCA (A → B: `DOUT_4G_M` → `DOUT_4G`, `MODEM_STATUS_M` → `MODEM_STATUS`); unused channel inputs tied (U23.6 B2 = GND); single drivers on every UART/status net; Q20/Q21 open drain.
|
||||||
|
- **Consequence:** 104 standing warnings hide the next real one.
|
||||||
|
- **Fix:** retype pins in `Drogheda-v6.kicad_sym` (power_in/power_out/input/output/passive). ERC then shows only real items.
|
||||||
|
- **Effort:** schematic-only (library)
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### J-04 ERC cosmetics: 23 orphan NC flags, 4 NC flags on connected pins, 2 wire stubs, 10 symbols missing from KiCad 10 libs, 22 lib-mismatched symbols
|
||||||
|
- **Severity:** Minor
|
||||||
|
- **Evidence:** orphan NC flags at x = 453.898 (13) and 484.378 mm (10), left from the deleted SimpleRTK2B socket. NC flags on connected pins U16.37/38 (USART6) and U10.13/14 (I2C), with the nets connected in the netlist (= D-11). Wire stubs at P1.4 and R52.2; both pins are GND in the netlist, so these are dangling extra segments (uuid 2b755f7f…, 46f71e27…, 7c1dbfc0…). Lib issues and mismatches: pin maps verified (H-09).
|
||||||
|
- **Fix:** delete flags/stubs. Copy the 10 missing symbols into `Drogheda-sym` and re-link. Leave the 22 mismatches (do not bulk-update).
|
||||||
|
- **Effort:** schematic-only
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
### J-05 Ignored DRC checks and library-mismatch warnings hide nothing real today
|
||||||
|
- **Severity:** Note
|
||||||
|
- **Evidence:**
|
||||||
|
- `missing_courtyard`: only MH5–MH8 lack one.
|
||||||
|
- `footprint_type_mismatch`: JP1–5 and TP1–8 are attribute "unspecified" with SMD pads. JP1–5 are excluded from BOM/CPL; TP1–8 are in the CPL without LCSC, so JLC ignores them. U19/L22 are now `smd` ✅ (pre-fab B2).
|
||||||
|
- `track_not_centered_on_via`: 178 track ends inside a via pad but off-centre (up to 0.40 mm), all connected per union-find.
|
||||||
|
- `footprint_filters_mismatch`, `tuning_profile`: no tuned nets.
|
||||||
|
- `lib_footprint_mismatch` 82: KiCad 10 library revisions. `lib_footprint_issues` 4: MountingHole nickname not in `fp-lib-table`.
|
||||||
|
- **Fix:** re-enable `footprint_type_mismatch` after setting TP1–8 to SMD + "exclude from BOM". Do **not** run "Update footprints from library" (it would swap P11/P12 and reset pads).
|
||||||
|
- **Confidence:** high
|
||||||
|
|
||||||
|
## Pass checks
|
||||||
|
| Check | Evidence (one line) | Result |
|
||||||
|
|---|---|---|
|
||||||
|
| `/24V_IN` (only HV24 net) clearance | ≥ 0.500 mm to everything on all 4 layers | ✅ |
|
||||||
|
| Switch nodes only on outer layer | SW_PWRIN/SW_FAN/SW_MODEM/SW_BAT/ETH_SW F.Cu-only | ✅ |
|
||||||
|
| U20 VIN cap, BST, L20 placement | C128 0.72 mm, C129 1.8 mm, L20 2.24 mm | ✅ |
|
||||||
|
| U25 BST cap, FB/COMP/RT | C152 1.49 mm; R122 1.0, R121 2.9 mm; FB net 4.1 mm | ✅ |
|
||||||
|
| U2 FB divider (ECO §E.3) | R20 0.67 / R21 1.48 mm from U2.4; FB net 4.1 mm | ✅ |
|
||||||
|
| Crystal ↔ inductor ≥ 10 mm | nearest 13.6 mm (Y1–L8) | ✅ |
|
||||||
|
| GNSS island ↔ switchers ≥ 25 mm | U18 body + RF_GNSS to nearest SW copper: `/ETH_SW` 27.5 mm, L8 35.3 mm, `/SW_FAN` 54.1 mm, others ≥ 77 mm | ✅ |
|
||||||
|
| RF_GNSS/RF_ANT_* over a solid plane | 0 slot crossings on In1 | ✅ |
|
||||||
|
| DFU ESD at J11 | 2.5–6.1 mm pad edge (V5.5: 41 mm) | ✅ (stubs: F-14) |
|
||||||
|
| Courtyard overlaps real | 0 of 15 (polygon intersection 0.000 mm²) | ✅ |
|
||||||
|
| Dangling track ends | 1, benign (F-21) | ✅ |
|
||||||
|
| Board outline / holes | 140 × 100 mm, 4 MH + 2 NPTH, corner gaps ≤ 2.5 µm | ✅ |
|
||||||
|
| Min track/space/drill vs JLC | 0.20/0.15/0.30 mm vs 0.09/0.09/0.15 | ✅ |
|
||||||
|
| J9/J11 PTH ring & hole spacing | 0.15 mm / 0.45 mm = JLC minimum | ⚠ |
|
||||||
|
| Thermal vias in regulator EPs | 0 in U6/U25/U20/U2/U12 | ❌ F-13 |
|
||||||
|
| Module GND vias (U19/U18) | 1 / 0 under bodies | ❌ F-04 |
|
||||||
|
| In1 plane integrity | 8 islands, 19 % void, 1572 mm tracks | ❌ F-05 |
|
||||||
|
| Via stitching / edge fence | 69 GND vias, 2 at the edge | ❌ F-12 |
|
||||||
|
| Netclasses resolve | 1 of 14 HV nets in HV24; RF/PWR_MODEM missing | ❌ F-01 |
|
||||||
|
| Every fitted BOM line has LCSC | all except TP1–8 (pads) | ✅ |
|
||||||
|
| LCSC parts exist in the JLC DB | 121/121 found | ✅ |
|
||||||
|
| Stock for 20 boards | U10 15, R53 6 | ❌ H-02 |
|
||||||
|
| Package ↔ footprint | 1 hard mismatch (U15), 4 land mismatches (MWSA0804S) | ❌ H-01/H-03 |
|
||||||
|
| Ceramic voltage margin on 24 V | all ≥ 50 V (≥ 1.8× at 28.8 V) | ✅ |
|
||||||
|
| Sense resistor rating | RS1 62.5 mW of 1 W | ✅ |
|
||||||
|
| Stale symbols hide pin errors | 25 parts checked, 0 mismatches | ✅ |
|
||||||
|
| U19/L22 fab attribute | both `smd` | ✅ |
|
||||||
|
| F2 part number | C206910 (was TBD) | ✅ |
|
||||||
|
| ERC errors / DRC errors | 0 / 0 (DRC not meaningful: J-01) | ⚠ |
|
||||||
|
|
||||||
|
## Review-vs-Lessons §4 checklist items re-verified
|
||||||
|
| # | Item | Status now | Evidence |
|
||||||
|
|---|---|---|---|
|
||||||
|
| 1 | U6 copper + EP vias + re-cluster | ❌ improved placement, copper and vias unchanged | L6 → U6.21/22 10.65 mm ctr (was 15.2); EP 0 vias; `/SW_BAT` 0.25–0.5 mm (DRC 6 hits); C30/C31 7.2/6.2 mm edge (A-02) |
|
||||||
|
| 2 | U25 set-point + re-cluster | ❌ placement improved, loop still open | L22 17.0 mm ctr (25.9), D34 6.6 (18.2), C150 5.1 / C149 8.5 ctr; **Cin GND on a different F.Cu island** (F-03); R121 still 53.6 k (A-04) |
|
||||||
|
| 4 | Modem rail layout | ❌ | `/VBAT_MODEM` 0.25/0.5 mm (7 real DRC hits), 6.3 mm on In1; `/VIN_MODEM` 0.3/0.5 (8 real); U20 GND neck (F-07); bulk distances = block B |
|
||||||
|
| 7 | J9 USB ESD | ❌ still none | nets `/USB_DP/DM/VBUS` = J9 + U19 only (G-02) |
|
||||||
|
| 10 | F2 part number / F1 size | ✅ F2 / ⚠ F1 | F2 = C206910 NANO2 2 A in holder; F1 still 3 A PPTC C20627123 (A-block) |
|
||||||
|
| §2 | Switcher EP vias (U20, U25) | ❌ | 0 vias in both EPs; both EPs on thermal spokes (13–18 %) (F-13) |
|
||||||
|
| Pre-fab B2 | U19/L22 attribute | ✅ | both `smd` |
|
||||||
|
| Pre-fab B3 | LCSC on all parts | ✅ (except TP pads) | 0 fitted lines without LCSC |
|
||||||
|
| Pre-fab B4 | J14 pre-order | ⚠ open | C2977286 still in "Pre-ordered Products" |
|
||||||
|
| Pre-fab B5 | Switcher placement | ❌ partly improved | U25/U2/U12 loops (F-03, F-08, F-09); U20 ✅ except GND neck |
|
||||||
|
| Pre-fab B6 | Power widths | ❌ | 59 real width hits (J-02) |
|
||||||
|
| Pre-fab §7 | RF_LTE on In1 | ❌ unchanged | 22.1 mm In1 (F-06) |
|
||||||
|
| Pre-fab §7 | USB pair on one layer | ❌ unchanged | DP In1 / DM In1+In2 (F-17) |
|
||||||
|
| Pre-fab §7 | Silkscreen size | ❌ unchanged | 304 refs at 0.5/0.1 mm (F-18) |
|
||||||
|
| Pre-fab §7 | Stubs | ✅ | 1 benign end (F-21) |
|
||||||
|
| ECO §E.1/§E.2 | SW_BAT/BAT_PLUS | ❌ | see #1 |
|
||||||
|
| ECO §E.3 | Fan FB divider at U2.4 | ✅ | 0.67/1.48 mm, FB net 4.1 mm (but U12 now repeats the pattern: F-09) |
|
||||||
|
| ECO §E.4 | Cin loops < 3 mm | ⚠ | U20 0.72 ✅, U25 2.88 (VIN) but GND split ❌, U2 20.8 ❌, U12 1.77 (VIN) / GND island split ❌ |
|
||||||
|
| ECO §E.5 | DFU ESD at J11 / J9 ESD | ✅ / ❌ | F-14, G-02 |
|
||||||
|
| ECO §E.6 | Crystals ≤ 5 mm; stitching cells | ❌ | Y1 13.7/10.8, Y3 8.3/11.3 mm; 10 empty 20 mm cells (F-11, F-12) |
|
||||||
|
|
||||||
|
## Requirements input R1–R5
|
||||||
|
- **R1 (10-min cycle on battery, report):** layout input needed. The backup boost feedback routing (F-10/A-14) and the modem power path copper (J-02 `/VIN_MODEM`, `/VBAT_MODEM`, `/MAIN5V`; F-07) must be fixed so the boost holds regulation during a cold modem start. **H-02 (R53 out of stock) must be fixed or the boost set-point resistor is missing.** H-03 (L6/L20 land) matters for durability.
|
||||||
|
- **R2 (MCU control of the modem):** no layout/BOM item from these blocks.
|
||||||
|
- **R3 (report on battery):** same as R1, plus modem RF/grounding (F-04, F-06) for link quality at the cycle edge.
|
||||||
|
- **R4 (thermal management):** needs change F-13 (EP vias/solid pads on U6, U25, U20) and F-04 (U19 heat into the planes); sensors are the power auditor's (F-51/F-52).
|
||||||
|
- **R5 (EMC list of the second batch):** needs changes F-03, F-05, F-06, F-07, F-08/A-01, F-09, F-11, F-12, F-14 and G-02 (J9 ESD). v6 does not meet ECO §E as laid out.
|
||||||
|
|
||||||
|
## Firmware implications (things board_v6.h / FW 0.7.x must do)
|
||||||
|
- None of F/H/J forces a pin change. Consequences of the choices above:
|
||||||
|
- If Y4/Y3 keep their current caps (D-02/D-03/H-07), use LSE high-drive (`LSEMOD`) and allow for +40…+130 ppm; RTC smooth calibration can trim LSE.
|
||||||
|
- If H-01 is not fixed, RS-232 (P12 via U15) is dead. The firmware must not depend on it, and the self-test should report `rs232=absent`.
|
||||||
|
- U10 swap SC16IS762 → SC16IS752 (H-02): register-compatible per memory. Keep `XTAL_FREQ = 3686400` (Y2 = 3.6864 MHz, not the 1.8432 MHz label).
|
||||||
|
- Bench/G3: log modem TX power vs F9P C/N0 before and after F-04/F-06 to confirm desense is gone.
|
||||||
|
|
||||||
|
## Inputs needed from Leo
|
||||||
|
1. Fab stackup and impedance control: confirm JLC04161H-7628 (assumed for F-06 numbers) and whether controlled impedance is ordered.
|
||||||
|
2. Order quantity for v6 (20 vs 100) decides whether U19/U18 must be pre-ordered (H-02).
|
||||||
|
3. Is Ethernet (J10) and are RS-485/RS-232 (P11/P12) fitted on v6? (H-06, H-01.)
|
||||||
|
4. Do the V5.5 boards have a soldered U15? (MAX3232ESE on the wide footprint.) A continuity check on P12 would settle the history of H-01.
|
||||||
|
5. Enclosure internal temperature at 45 °C ambient, for the crystal (−20…+70 °C) and electrolytic ratings (H-07, A-09).
|
||||||
|
6. Unit purchase prices of the ArduSimple simpleRTK2B and 4G NTRIP Master (500-unit order), for a system-level cost delta (H-10).
|
||||||
|
7. Fan current (assumed ≤ 0.3 A in J-02).
|
||||||
@ -0,0 +1,153 @@
|
|||||||
|
references,value,footprint,qty_lines,qty_fitted_per_board,lcsc,mfr_part (JLC DB),db_package/spec,db_library_type,db_stock,stock_ok_20_boards,stock_ok_100_boards,footprint_vs_package,unit_price_usd_at_20/100_boards,notes
|
||||||
|
C3,47uF,CP_Elec_6.3x7.7,1,1,C88734,50TZV47M6.3X8 Rubycon,D6.3xL8 elec 47uF 50V 105C,Extended,17970,yes,OK,OK 6.3x8 on CP_Elec_6.3x7.7,0.1215/0.1215,
|
||||||
|
"C5,C7,C9,C11,C24,C80,C81,C84-C89,C92,C93,C98,C104-C109,C152,C157,Cu3,Cu4",100nF,C_0603_1608Metric,26,26,C14663,CC0603KRX7R9BB104,0603 100nF 50V X7R,Basic,37493696,yes,OK,OK 0603,0.0026/0.0026,
|
||||||
|
C10,47uF/50V,CP_Elec_6.3x7.7,1,1,C165527,MVK50V47M6.3*8,D6.3xL8 elec 47uF 50V 105C,Extended,4673,yes,OK,OK 6.3x8 on CP_Elec_6.3x7.7,0.1028/0.1028,
|
||||||
|
C22,22uF/50V,C_1210_3225Metric,1,1,C138687,CL32B106KBJNNNE,1210 10uF 50V X7R,Extended,226744,yes,OK,OK 1210; VALUE MISMATCH 22uF vs 10uF part,0.1770/0.1446,VALUE MISMATCH: sch says 22uF/50V
|
||||||
|
"C23,C118",22uF/16V,C_0805_2012Metric,2,2,C86817,GRM21BR61C226ME44L,0805 22uF 16V X5R,Extended,4144,yes,OK,OK 0805,0.0921/0.0921,stock 4144; 7/board
|
||||||
|
"C30,C34,C90,C94,C117,C119,C120,C124,C127,C160",10uF,C_0805_2012Metric,10,10,C440198,GRM21BR61H106KE43L,0805 10uF 50V X5R,Basic,1940473,yes,OK,OK 0805,0.0670/0.0551,
|
||||||
|
"C31,C125",2.2uF,C_0603_1608Metric,2,2,C23630,CL10A225KO8NNNC,0603 2.2uF 16V X5R,Basic,4599924,yes,OK,OK 0603,0.0057/0.0057,
|
||||||
|
"C32,C33",47uF,C_1210_3225Metric,2,2,C5440143,CS3225X7R476K160NRL,1210 47uF 16V X7R,Extended,242640,yes,OK,OK 1210,0.0926/0.0926,
|
||||||
|
"C35,C40,C101,C102,C132",22uF,C_0805_2012Metric,5,5,C86817,GRM21BR61C226ME44L,0805 22uF 16V X5R,Extended,4144,yes,OK,OK 0805,0.0921/0.0779,stock 4144; 7/board
|
||||||
|
"C78,C130,C131",220uF/10V,CP_Elec_6.3x7.7,3,3,C2827940,MVG 16V 220UF 6.3*7.7,D6.3xL7.7 elec 220uF 16V 85C,Extended,15956,yes,OK,OK 6.3x7.7,0.0914/0.0730,"85 C rated, 130 mA ripple"
|
||||||
|
"C82,C83",22pF,C_0603_1608Metric,2,2,C1653,CL10C220JB8NNNC,0603 22pF C0G,Basic,4013700,yes,OK,OK 0603,0.0040/0.0040,
|
||||||
|
C91,4.7uF,C_0805_2012Metric,1,1,C1779,CL21A475KAQNNNE,0805 4.7uF 25V X5R,Basic,4715349,yes,OK,OK 0805,0.0135/0.0135,
|
||||||
|
"C95,C96",18pF,C_0603_1608Metric,2,2,C1647,CL10C180JB8NNNC,0603 18pF C0G,Basic,651661,yes,OK,OK 0603,0.0047/0.0047,
|
||||||
|
C97,6.8nF,C_0603_1608Metric,1,1,C1631,0603B682K500NT,0603 6.8nF 50V X7R,Basic,491854,yes,OK,OK 0603,0.0032/0.0032,
|
||||||
|
"C99,Ccomp1",2.2nF,C_0603_1608Metric,2,2,C1604,0603B222K500NT,0603 2.2nF 50V X7R,Basic,795434,yes,OK,OK 0603,0.0027/0.0027,
|
||||||
|
"C100,Cbst1",10nF,C_0603_1608Metric,2,2,C1589,CL10B103KB8NNNC,0603 10nF 50V X7R,Extended,6584349,yes,OK,OK 0603,0.0033/0.0033,DB says Extended; commonly JLC Basic
|
||||||
|
C103,100uF/6.3V,CP_Elec_6.3x7.7,1,1,C88744,35TZV100M6.3X8 Rubycon,D6.3xL8 elec 100uF 35V 105C,Extended,153587,yes,OK,"OK 6.3x8 can on CP_Elec_6.3x7.7 (fp tolerance ok); value says 6.3V, part 35V",0.1280/0.1280,sch value 100uF/6.3V (part is 35V: fine)
|
||||||
|
"C110,C111",4.7uF,C_0603_1608Metric,2,2,C19666,CL10A475KO8NNNC,0603 4.7uF 16V X5R,Basic,5643370,yes,OK,OK 0603,0.0096/0.0096,
|
||||||
|
"C112,C128,C133",1uF,C_0603_1608Metric,3,3,C15849,CL10A105KB8NNNC,0603 1uF 50V X5R,Basic,7169422,yes,OK,OK 0603,0.0071/0.0071,
|
||||||
|
"C113,C114",15pF,C_0603_1608Metric,2,2,C1644,CL10C150JB8NNNC,0603 15pF C0G,Basic,1857047,yes,OK,OK 0603,0.0049/0.0049,
|
||||||
|
"C115,C116",12pF,C_0603_1608Metric,2,2,C38523,CL10C120JB8NNNC,0603 12pF C0G,Basic,3346489,yes,OK,OK 0603,0.0046/0.0046,
|
||||||
|
"C121-C123,C126,C129,C134,C137-C140,C144,C158,C159",100nF,C_0402_1005Metric,13,13,C1525,CL05B104KO5NNNC,0402 100nF 16V X7R,Basic,43509060,yes,OK,OK 0402,0.0012/0.0012,
|
||||||
|
C135,33pF,C_0402_1005Metric,1,1,C1562,0402CG330J500NT,0402 33pF C0G,Basic,791476,yes,OK,OK 0402,0.0010/0.0010,
|
||||||
|
C136,10pF,C_0402_1005Metric,1,1,C32949,CL05C100JB5NNNC,0402 10pF C0G,Basic,1571686,yes,OK,OK 0402,0.0041/0.0041,
|
||||||
|
C141,3.3nF,C_0402_1005Metric,1,1,C1536,0402B332K500NT,0402 3.3nF 50V X7R,Extended,67810,yes,OK,OK 0402,0.0011/0.0011,
|
||||||
|
C142,47pF,C_0402_1005Metric,1,1,C1567,0402CG470J500NT,0402 47pF C0G,Basic,890588,yes,OK,OK 0402,0.0010/0.0010,
|
||||||
|
C143,100nF-RF,C_0402_1005Metric,1,1,C1525,CL05B104KO5NNNC,0402 100nF 16V X7R,Basic,43509060,yes,OK,OK 0402,0.0012/0.0012,
|
||||||
|
C145,100pF,C_0402_1005Metric,1,1,C1546,0402CG101J500NT,0402 100pF C0G,Basic,5042547,yes,OK,OK 0402,0.0010/0.0010,
|
||||||
|
"C146,C147",DNP-pi,C_0402_1005Metric,2,0,,,,,,,,,,no LCSC: DNP
|
||||||
|
"C149,C150",2.2uF/100V,C_1210_3225Metric,2,2,C153036,FS32X225K101EGG,1210 2.2uF 100V X7R,Extended,471514,yes,OK,OK 1210,0.0587/0.0587,
|
||||||
|
C151,100uF/50V,CP_Elec_8x10,1,1,C116241,UUD1H101MNL1GS Nichicon,D8xL10.5 elec 100uF 50V 105C,Extended,176649,yes,OK,OK 8x10.5 on CP_Elec_8x10,0.2388/0.2388,
|
||||||
|
"C153,C154",47uF/16V,C_1210_3225Metric,2,2,C5440143,CS3225X7R476K160NRL,1210 47uF 16V X7R,Extended,242640,yes,OK,OK 1210,0.0926/0.0926,
|
||||||
|
C155,6.8nF,C_0402_1005Metric,1,1,C1542,0402B682K500NT,0402 6.8nF 50V X7R,Preferred,128063,yes,OK,OK 0402,0.0011/0.0011,
|
||||||
|
C156,39pF,C_0402_1005Metric,1,1,C1563,0402CG390J500NT,0402 39pF C0G,Extended,243509,yes,OK,OK 0402,0.0011/0.0011,
|
||||||
|
"D1,D4G1,DB1-DB4",LED,LED_0805_2012Metric,6,6,C2297,KT-0805G,0805 LED green,Basic,2234536,yes,OK,OK 0805 LED,0.0147/0.0147,
|
||||||
|
"D2,D11-D13,D20,Dbk1",SS34,D_SMA,6,6,C8678,SS34 MDD,SMA Schottky 40V 3A,Basic,2100322,yes,OK,OK SMA,0.0276/0.0276,Dbk1: 40V < 53.3V TVS clamp
|
||||||
|
D5,BAT54,D_SOD-123,1,1,C131469,BAT54W CJ,SOD-123 Schottky 30V,Extended,2652,yes,OK,OK SOD-123 (BAT54W),0.0221/0.0221,
|
||||||
|
D6,1N4148W,D_SOD-123,1,1,C2099,1N4148W CJ,SOD-123 switching,Extended,555236,yes,OK,OK SOD-123,0.0087/0.0087,
|
||||||
|
D10,SMBJ33A,D_SMB,1,1,C224019,SMBJ33A Littelfuse,SMB TVS 33V Vc53.3V,Extended,9624,yes,OK,OK SMB,0.0979/0.0979,
|
||||||
|
"D14-D16,D23-D25",PESD5V0S1BA,D_SOD-323,6,6,C2827694,PESD5V0S1BA TECH PUBLIC,SOD-323 ESD 5V bidir,Extended,303975,yes,OK,OK SOD-323,0.0307/0.0307,
|
||||||
|
D17,LED C13 (blue),LED_0603_1608Metric,1,1,C125103,LTST-C193TBKT-5A,0603 LED blue,Extended,145825,yes,OK,OK 0603 LED,0.0175/0.0175,
|
||||||
|
D18,LED PWR (green),LED_0603_1608Metric,1,1,C125098,LTST-C191KGKT,0603 LED yel-green,Extended,387510,yes,OK,OK 0603 LED,0.0187/0.0187,
|
||||||
|
D21,PMEG3050EP,SOD-128_L3.7-W2.5-LS4.7-RD,1,1,C50603,"PMEG3050EP,115",SOD-128 Schottky 30V 5A,Extended,23104,yes,OK,OK SOD-128,0.3911/0.3067,VR 30V < /24V transient
|
||||||
|
D22,SMAJ5.0A,SMA_L4.4-W2.6-LS5.0-RD,1,1,C113952,SMAJ5.0A MDD,SMA TVS 5V,Extended,1223816,yes,OK,OK SMA,0.0363/0.0363,
|
||||||
|
"D27,D28",ESD9L5.0ST5G,SOD-923_L0.8-W0.6-LS1.0-RD,2,2,C82326,ESD9L5.0ST5G,SOD-923 ESD 0.9pF,Extended,84360,yes,OK,OK SOD-923,0.0501/0.0501,
|
||||||
|
D32,SMCJ33A,D_SMC,1,1,C699039,SMCJ33A Yangjie,SMC TVS 33V 1.5kW,Extended,2593,yes,OK,OK SMC,0.1142/0.0907,
|
||||||
|
"D33,DzG1",BZX84C15,SOT-23,2,2,C80857,BZX84C15LT1G,SOT-23 zener 15V,Extended,17320,yes,OK,OK SOT-23,0.0314/0.0314,
|
||||||
|
D34,B560C,D_SMC,1,1,C85100,B560C-13-F,SMC Schottky 60V 5A,Extended,63402,yes,OK,OK SMC,0.2197/0.1785,
|
||||||
|
F1,PPTC 3A,Fuse_1812_4532Metric,1,1,C20627123,1812L300/24GR LUTE,1812 PPTC 3A 24V,Extended,179764,yes,OK,OK 1812,0.1262/0.1262,
|
||||||
|
F2,2A/125V-NANO2-in-holder,Fuseholder_Littelfuse_Nano2_154x,1,1,C206910,0154002.DR Littelfuse,NANO2 2A 125V w/holder,Extended,5505,yes,OK,OK Littelfuse 154 NANO2 holder,1.0963/0.8133,
|
||||||
|
H4,TTL_UARTB,PinHeader_1x04_P2.54mm_Vertical,1,1,C5116483,2.54-1*4 ZHOURI,1x4 header THT,Extended,6733,yes,OK,OK 1x4 2.54,0.0228/0.0228,THT
|
||||||
|
J9,USB-C,USB_C_Receptacle_GCT_USB4085,1,1,C7095263,USB4085-GF-A GCT,USB-C THT,Extended,1047,yes,OK,"OK GCT USB4085 (THT, annular 0.15 mm = JLC min)",1.0844/0.9630,"THT; stock 1047, 2/board"
|
||||||
|
J10,HR911105A,RJ45_Hanrun_HR911105A_Horizontal,1,1,C12074,HR911105A,RJ45 magjack THT,Extended,110098,yes,OK,OK (HR911105A); schematic fp lib nickname Connector_RJ45 vs PCB Connector_RJ,1.2030/0.9170,THT; DNP on PCB; PCB DNP: J10 (schematic populated)
|
||||||
|
J11,USB-C DFU,USB_C_Receptacle_GCT_USB4085,1,1,C7095263,USB4085-GF-A GCT,USB-C THT,Extended,1047,yes,OK,"OK GCT USB4085 (THT, annular 0.15 mm = JLC min)",1.0844/0.9630,"THT; stock 1047, 2/board"
|
||||||
|
J12,UFL-GNSS,RF-SMD_FRF05002-JSS103M,1,1,C88374,U.FL-R-SMT-1(80) Hirose,U.FL SMD,Extended,226395,yes,OK,OK Hirose U.FL fp from part,0.1154/0.1154,
|
||||||
|
J13,UFL-LTE,RF-SMD_FRF05002-JSS103M,1,1,C88374,U.FL-R-SMT-1(80) Hirose,U.FL SMD,Extended,226395,yes,OK,OK Hirose U.FL fp from part,0.1154/0.1154,
|
||||||
|
J14,NanoSIM-JAE-SF72S006,JAE_SIM_Card_SF72S006,1,1,C2977286,SF72S006VBDR2500 JAE,nano-SIM push-push,Extended,10890,yes,OK,OK JAE SF72S006 fp,0.3570/0.3570,PRE-ORDER part
|
||||||
|
K1,G5V-1 DC5,Relay_SPDT_Omron_G5V-1,1,1,C28695,G5V-1 DC5 Omron,relay THT,Extended,20906,yes,OK,OK G5V-1,1.0015/0.8207,THT
|
||||||
|
L2,10uH,L_Bourns-SRU8028_8.0x8.0mm,1,1,C17700171,MWSA0804S-100MT Sunlord,8.8x8.2 power L 10uH,Extended,470,yes,OK,"MISMATCH-RISK: Sunlord MWSA0804S 8.2x8.8 mm (electrodes 1.4x5.0 mm) on Bourns SRU8028 8.0x8.0 land (pads 2.0x3.2 at 7.8 mm pitch): ~55% electrode overlap, body 0.4 mm over",0.2841/0.2373,footprint SRU8028 8.0x8.0; stock 470 for 2/board
|
||||||
|
L6,2.2uH/8A,L_Bourns-SRU8028_8.0x8.0mm,1,1,C17700165,MWSA0804S-2R2MT Sunlord,8.8x8.2 power L 2.2uH,Extended,646,yes,OK,MISMATCH-RISK: as above (MWSA0804S on SRU8028 land),0.2419/0.1951,footprint SRU8028
|
||||||
|
L8,10uH/2A,L_Bourns-SRU8028_8.0x8.0mm,1,1,C17700171,MWSA0804S-100MT Sunlord,8.8x8.2 power L 10uH,Extended,470,yes,OK,"MISMATCH-RISK: Sunlord MWSA0804S 8.2x8.8 mm (electrodes 1.4x5.0 mm) on Bourns SRU8028 8.0x8.0 land (pads 2.0x3.2 at 7.8 mm pitch): ~55% electrode overlap, body 0.4 mm over",0.2841/0.2373,footprint SRU8028 8.0x8.0; stock 470 for 2/board
|
||||||
|
L20,4.7uH/5A,L_Bourns-SRU8028_8.0x8.0mm,1,1,C17700167,MWSA0804S-4R7MT Sunlord,8.8x8.2 power L 4.7uH,Extended,1675,yes,OK,MISMATCH-RISK: as above (MWSA0804S on SRU8028 land),0.2606/0.2138,footprint SRU8028
|
||||||
|
L21,68nH,L_0603_1608Metric,1,1,C162555,LQG18HN68NJ00D Murata,0603 68nH,Extended,27525,yes,OK,OK 0603,0.0767/0.0767,
|
||||||
|
L22,10uH/SRP1265A,IND-SMD_L13.5-W12.5,1,1,C840531,SRP1265A-100M Bourns,13.5x12.5 10uH 10A,Extended,1536,yes,OK,OK 13.5x12.5 (Drogheda-v6 fp from part),0.7230/0.5541,
|
||||||
|
P1,GX16-5,"TerminalBlock_Phoenix_MKDS-1,5-5_1x05_P5.00mm_Horizontal",1,1,C424683,DB128V-5.0-5P DORABO,5-pos 5.0mm screw term THT,Extended,2749,yes,OK,OK pitch 5.0 mm/5 pos (value says GX16-5: it is the board terminal for the GX16 harness),0.3748/0.3378,THT
|
||||||
|
P2,5V-IN-SD15B05,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,1,C158012,B2B-XH-A JST,XH 2p THT,Extended,490842,yes,OK,OK XH 2p,0.0347/0.0347,THT
|
||||||
|
P3,BATT-1S4P+NTC,JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical,1,1,C144394,B3B-XH-A JST,XH 3p THT,Extended,126183,yes,OK,OK XH 3p,0.0498/0.0498,THT
|
||||||
|
P4,FAN 2-pin,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,1,C158012,B2B-XH-A JST,XH 2p THT,Extended,490842,yes,OK,OK XH 2p,0.0347/0.0347,THT
|
||||||
|
P5,CUTOFF-SW,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,1,C158012,B2B-XH-A JST,XH 2p THT,Extended,490842,yes,OK,OK XH 2p,0.0347/0.0347,THT
|
||||||
|
P6,RESET-EXT,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,1,C158012,B2B-XH-A JST,XH 2p THT,Extended,490842,yes,OK,OK XH 2p,0.0347/0.0347,THT
|
||||||
|
P7,NTC-HOTSPOT,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,1,C158012,B2B-XH-A JST,XH 2p THT,Extended,490842,yes,OK,OK XH 2p,0.0347/0.0347,THT
|
||||||
|
P8,NTC-PROBE-2,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,1,C158012,B2B-XH-A JST,XH 2p THT,Extended,490842,yes,OK,OK XH 2p,0.0347/0.0347,THT
|
||||||
|
P9,PANEL_LED,JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical,1,1,C158012,B2B-XH-A JST,XH 2p THT,Extended,490842,yes,OK,OK XH 2p,0.0347/0.0347,THT
|
||||||
|
P10,RGB_LED_EXT,JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical,1,1,C144395,B4B-XH-A JST,XH 4p THT,Extended,418436,yes,OK,OK XH 4p,0.0495/0.0495,THT
|
||||||
|
P11,RS485_OUT,"PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical",1,1,C5160226,15EDGRC-3.5-03P DEGSON,3p 3.5mm R/A pluggable THT,Extended,512,yes,OK,OK vs PCB (right-angle = Horizontal fp); schematic still has Vertical fp (not in lib),0.1757/0.1384,THT; right-angle = PCB Horizontal fp; PCB DNP: P11 (schematic populated)
|
||||||
|
P12,RS232_OUT,"PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical",1,1,C5160226,15EDGRC-3.5-03P DEGSON,3p 3.5mm R/A pluggable THT,Extended,512,yes,OK,OK vs PCB (right-angle = Horizontal fp); schematic still has Vertical fp (not in lib),0.1757/0.1384,THT; right-angle = PCB Horizontal fp; PCB DNP: P12 (schematic populated)
|
||||||
|
"PF1,PF2,PF4-PF21",PWR_FLAG,,20,20,,,,,,,,,,virtual PWR_FLAG
|
||||||
|
Q1,AO3401A,SOT-23,1,1,C15127,AO3401A,SOT-23 PMOS,Basic,2830530,yes,OK,OK SOT-23,0.0553/0.0553,
|
||||||
|
"Q2,Q4",AO3400A,SOT-23,2,2,C20917,AO3400A,SOT-23 NMOS,Basic,1814497,yes,OK,OK SOT-23,0.0739/0.0739,
|
||||||
|
"Q5,Q6,Q22",MMBT3904,SOT-23,3,3,C20526,MMBT3904 CJ,SOT-23 NPN,Basic,1358689,yes,OK,OK SOT-23,0.0089/0.0089,
|
||||||
|
Q7,AO4406A,SOIC-8_3.9x4.9mm_P1.27mm,1,1,C35349,AO4406AL,SOIC-8 NMOS,Extended,4982,yes,OK,OK SOIC-8,0.2696/0.2341,
|
||||||
|
"Q10,Q23",IRFR5305,TO-252-2,2,2,C2624,IRFR5305TRPBF,DPAK PMOS 55V,Extended,31705,yes,OK,OK DPAK,0.2619/0.1929,
|
||||||
|
"Q20,Q21",2N7002,SOT-23,2,2,C8545,2N7002 CJ,SOT-23 NMOS 60V,Basic,2716354,yes,OK,OK SOT-23,0.0126/0.0126,
|
||||||
|
"R1,R40,R102,R103,R112,Rmled1",1k,R_0603_1608Metric,6,6,C14676,RC0603JR-071KL,0603 1k 5%,Extended,757955,yes,OK,OK 0603,0.0013/0.0013,use C21190 (Basic)
|
||||||
|
"R2,R5-R8,R41,R80,R81,R84,R98,R99,R105,Rled1,Rrp1",10k,R_0603_1608Metric,14,14,C25804,0603WAF1002T5E,0603 10k 1%,Basic,22319909,yes,OK,OK 0603,0.0012/0.0012,
|
||||||
|
"R3,R82,R89-R91,RB1-RB4",120R,R_0603_1608Metric,9,9,C22787,0603WAF1200T5E,0603 120R 1%,Basic,1754376,yes,OK,OK 0603,0.0016/0.0016,
|
||||||
|
"R20,R56-R58,R85,R87,Ren1,Rfreq1,Rgs1",100k,R_0603_1608Metric,9,9,C103211,RTT03104JTP RALEC,0603 100k 5%,Extended,702,yes,NO,OK 0603,0.0010/0.0010,STOCK 702 < 9/board x100; use C25803
|
||||||
|
R21,19.1k,R_0603_1608Metric,1,1,C103370,RTT031912FTP,0603 19.1k 1%,Extended,2040,yes,OK,OK 0603,0.0012/0.0012,
|
||||||
|
"R30,R31,R109",4.7k,R_0603_1608Metric,3,3,C23162,0603WAF4701T5E,0603 4.7k 1%,Basic,21915184,yes,OK,OK 0603,0.0011/0.0011,
|
||||||
|
"R42,R55,R126",10k/1%,R_0603_1608Metric,3,3,C25804,0603WAF1002T5E,0603 10k 1%,Basic,22319909,yes,OK,OK 0603,0.0012/0.0012,
|
||||||
|
R50,825R/1%,R_0603_1608Metric,1,1,C50214,0603WAF8250T5E,0603 825R 1%,Extended,3004,yes,OK,OK 0603,0.0013/0.0013,value change to 1.5k (block A)
|
||||||
|
R51,270k/1%,R_0603_1608Metric,1,1,C22965,0603WAF2703T5E,0603 270k 1%,Preferred,107639,yes,OK,OK 0603,0.0011/0.0011,
|
||||||
|
"R52,R54",100k/1%,R_0603_1608Metric,2,2,C14675,RC0603FR-07100KL,0603 100k 1%,Extended,1436720,yes,OK,OK 0603,0.0012/0.0012,use C25803 (Basic)
|
||||||
|
R53,499k/1%,R_0603_1608Metric,1,1,C131054,RC0603FR-07499KL,0603 499k 1%,Extended,6,NO,NO,OK 0603,0.0013/0.0013,STOCK 6 -> OUT; use C177479
|
||||||
|
R83,12.4k/1%,R_0603_1608Metric,1,1,C103261,RTT031242FTP,0603 12.4k 1%,Extended,1873,yes,OK,OK 0603,0.0013/0.0013,
|
||||||
|
"R86,Rcomp1",40.2k,R_0603_1608Metric,2,2,C209139,RMS06FT4022,0603 40.2k 1%,Extended,2472,yes,OK,OK 0603,0.0020/0.0020,
|
||||||
|
R88,31.6k/1%,R_0603_1608Metric,1,1,C25967,0603WAF3162T5E,0603 31.6k 1%,Extended,355276,yes,OK,OK 0603,0.0012/0.0012,
|
||||||
|
R92-R95,49.9R/1%,R_0603_1608Metric,4,4,C218051,ARG03FTC49R9,0603 49.9R 1% thin film,Extended,14778,yes,OK,OK 0603,0.0068/0.0068,
|
||||||
|
"R96,R97",330R,R_0603_1608Metric,2,2,C23138,0603WAF3300T5E,0603 330R 1%,Basic,3511720,yes,OK,OK 0603,0.0014/0.0014,
|
||||||
|
"R100,R101,Rcc1,Rcc2",5.1k,R_0603_1608Metric,4,4,C23186,0603WAF5101T5E,0603 5.1k 1%,Basic,2076828,yes,OK,OK 0603,0.0013/0.0013,
|
||||||
|
R104,10R,R_0603_1608Metric,1,1,C22859,0603WAF100JT5E,0603 10R,Basic,2613887,yes,OK,OK 0603,0.0015/0.0015,
|
||||||
|
"R106,Rg1",100R,R_0603_1608Metric,2,2,C22775,0603WAF1000T5E,0603 100R 1%,Basic,9270288,yes,OK,OK 0603,0.0012/0.0012,
|
||||||
|
"R107,R108",0R-DNP,R_0603_1608Metric,2,0,,,,,,,,,,no LCSC: DNP
|
||||||
|
R110,75k/1%,R_0603_1608Metric,1,1,C23242,0603WAF7502T5E,0603 75k 1%,Basic,728776,yes,OK,OK 0603,0.0010/0.0010,
|
||||||
|
R111,20k/1%,R_0603_1608Metric,1,1,C4184,0603WAF2002T5E,0603 20k 1%,Basic,6650154,yes,OK,OK 0603,0.0011/0.0011,
|
||||||
|
"R113-R115,R119",100k,R_0603_1608Metric,4,4,C25803,0603WAF1003T5E,0603 100k 1%,Basic,10814547,yes,OK,OK 0603,0.0012/0.0012,
|
||||||
|
R116,14k,R_0603_1608Metric,1,1,C22803,0603WAF1402T5E,0603 14k 1%,Extended,316288,yes,OK,OK 0603,0.0012/0.0012,
|
||||||
|
R117,200k/1%,R_0603_1608Metric,1,1,C25811,0603WAF2003T5E,0603 200k 1%,Basic,1678266,yes,OK,OK 0603,0.0011/0.0011,
|
||||||
|
R118,0R,R_0402_1005Metric,1,1,C17168,0402WGF0000TCE,0402 0R,Basic,4907393,yes,OK,OK 0402,0.0008/0.0008,
|
||||||
|
R120,162k/1%,R_0603_1608Metric,1,1,C165760,RC0603FR-07162KL,0603 162k 1%,Extended,19430,yes,OK,OK 0603,0.0014/0.0014,
|
||||||
|
R121,53.6k/1%,R_0603_1608Metric,1,1,C23074,0603WAF5362T5E,0603 53.6k 1%,Extended,207510,yes,OK,OK 0603,0.0012/0.0012,value change 57.6k (block A)
|
||||||
|
R122,10.2k/1%,R_0603_1608Metric,1,1,C22772,0603WAF1022T5E,0603 10.2k 1%,Extended,223870,yes,OK,OK 0603,0.0012/0.0012,
|
||||||
|
R123,13k,R_0603_1608Metric,1,1,C22797,0603WAF1302T5E,0603 13k 1%,Basic,303822,yes,OK,OK 0603,0.0014/0.0014,
|
||||||
|
R124,523k/1%-DNP,R_0603_1608Metric,1,0,,,,,,,,,,no LCSC: DNP
|
||||||
|
R125,84.5k/1%-DNP,R_0603_1608Metric,1,0,,,,,,,,,,no LCSC: DNP
|
||||||
|
R127-R130,0R,R_0603_1608Metric,4,0,C304185,CR-03FL7----0R Viking,0603 0R,Extended,2962,yes,OK,OK 0603,0.0000/0.0000,use C21189 (Basic); PCB DNP: R127 R128 R129 R130 (schematic populated)
|
||||||
|
R131-R134,0R,R_0603_1608Metric,4,4,C304185,CR-03FL7----0R Viking,0603 0R,Extended,2962,yes,OK,OK 0603,0.0016/0.0016,use C21189 (Basic)
|
||||||
|
"Rdfu1,Rig1,Rig2",22k,R_0603_1608Metric,3,3,C88614,RS-03K223JT,0603 22k 5%,Extended,12616,yes,OK,OK 0603,0.0010/0.0010,
|
||||||
|
Ren2,20k,R_0603_1608Metric,1,1,C4184,0603WAF2002T5E,0603 20k 1%,Basic,6650154,yes,OK,OK 0603,0.0011/0.0011,
|
||||||
|
Rigb1,3.3k,R_0603_1608Metric,1,1,C22978,0603WAF3301T5E,0603 3.3k 1%,Basic,3412895,yes,OK,OK 0603,0.0014/0.0014,
|
||||||
|
RS1,10mR/1%,R_1206_3216Metric,1,1,C105362,FMF06FTHR010-LH,1206 10mR 1W 1%,Extended,317181,yes,OK,OK 1206,0.0296/0.0296,
|
||||||
|
SW1,RESET,SW_PUSH_6mm,1,1,C83205,K2-6639DP-B4SW-04,6x6 tact THT,Extended,9520,yes,OK,OK 6x6 THT,0.0425/0.0425,THT
|
||||||
|
SW2,BOOT0,SW_PUSH_6mm,1,1,C83205,K2-6639DP-B4SW-04,6x6 tact THT,Extended,9520,yes,OK,OK 6x6 THT,0.0425/0.0425,THT
|
||||||
|
TP1,CLPROG,TestPoint_Pad_D1.5mm,1,1,,,,,,,,,,no LCSC: test pad (copper only) - OK
|
||||||
|
TP2,PFO,TestPoint_Pad_D1.5mm,1,1,,,,,,,,,,no LCSC: test pad (copper only) - OK
|
||||||
|
TP3,SWDIO,TestPoint_Pad_D1.5mm,1,1,,,,,,,,,,no LCSC: test pad (copper only) - OK
|
||||||
|
TP4,SWCLK,TestPoint_Pad_D1.5mm,1,1,,,,,,,,,,no LCSC: test pad (copper only) - OK
|
||||||
|
TP5,NRST,TestPoint_Pad_D1.5mm,1,1,,,,,,,,,,no LCSC: test pad (copper only) - OK
|
||||||
|
TP6,GND,TestPoint_Pad_D1.5mm,1,1,,,,,,,,,,no LCSC: test pad (copper only) - OK
|
||||||
|
TP7,3V3,TestPoint_Pad_D1.5mm,1,1,,,,,,,,,,no LCSC: test pad (copper only) - OK
|
||||||
|
TP8,USB_BOOT,TestPoint_Pad_D1.5mm,1,1,,,,,,,,,,no LCSC: test pad (copper only) - OK
|
||||||
|
"U2,U12",MP1584EN,SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm,2,2,C15051,MP1584EN-LF-Z,SOIC-8-EP buck 4.5-28V,Extended,10132,yes,OK,OK SOIC-8-EP,2.3319/2.2059,VIN max 28V on /24V (U2)
|
||||||
|
U3,SHT40-AD1B,Sensirion_DFN-4_1.5x1.5mm_P0.8mm_SHT4x_NoCentralPad,1,1,C2848306,SHT40-AD1B-R3,DFN-4 1.5x1.5,Extended,4860,yes,OK,OK DFN-4 1.5x1.5 (fp NoCentralPad; part DFN-4-EP: EP unused is allowed by Sensirion),1.4356/1.1111,
|
||||||
|
U6,LTC4040EUFD,QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm,1,1,C687163,LTC4040EUFD#TRPBF,VQFN-24 4x5,Extended,2390,yes,OK,OK QFN-24 4x5,7.7807/6.3526,
|
||||||
|
U10,SC16IS752IPW,TSSOP-28_4.4x9.7mm_P0.65mm,1,1,C729142,"SC16IS762IPW,128",TSSOP-28,Extended,15,NO,NO,OK TSSOP-28,6.2978/5.1496,STOCK 15 -> use C57156 SC16IS752IPW
|
||||||
|
U11,W5500,LQFP-48_7x7mm_P0.5mm,1,1,C32843,W5500,LQFP-48,Extended,41147,yes,OK,OK LQFP-48,2.2696/1.8133,
|
||||||
|
U13,PCF8574,SOIC-16W_7.5x10.3mm_P1.27mm,1,1,C7605,PCF8574T/3,SOIC-16 300mil,Extended,517,yes,OK,OK SOIC-16 300 mil (wide) = SOIC-16W,1.5867/1.1689,stock 517
|
||||||
|
U14,SP3485EN,SOIC-8_3.9x4.9mm_P1.27mm,1,1,C8963,SP3485EN-L/TR,SOIC-8,Basic,172770,yes,OK,OK SOIC-8,0.2264/0.2264,
|
||||||
|
U15,MAX3232,SOIC-16W_7.5x10.3mm_P1.27mm,1,1,C15846,MAX3232ESE+T,SOIC-16 NARROW 150mil,Extended,4873,yes,OK,"MISMATCH: part is SOIC-16 narrow (150 mil, MAX3232ESE), footprint SOIC-16W 7.5 mm (pad rows 9.3 mm apart) -> leads cannot reach pads",1.1615/0.9244,FOOTPRINT MISMATCH: fp SOIC-16W
|
||||||
|
U16,STM32F411RET6,LQFP-64_10x10mm_P0.5mm,1,1,C94355,STM32F411RET6,LQFP-64,Extended,5342,yes,OK,OK LQFP-64,2.1156/1.4533,
|
||||||
|
U17,AMS1117-3.3,SOT-223-3_TabPin2,1,1,C6186,AMS1117-3.3,SOT-223,Basic,949581,yes,OK,OK SOT-223,0.2090/0.1630,
|
||||||
|
U18,ZED-F9P-04B,LCC-LGA-102_L22.0-W17.0_FM660,1,1,C5120257,ZED-F9P-04B,22x17 LGA,Extended,104,yes,OK,OK (easyeda fp from part),80.1052/80.1052,stock 104
|
||||||
|
U19,A7670SA-LASC,LGA-124_L24.0-W24.0-P1.0-A7670C-LASS,1,1,C18548276,A7670SA-LASC,24x24 LGA,Extended,96,yes,NO,OK (easyeda fp from part),6.0741/6.0741,stock 96 (<100)
|
||||||
|
U20,AP64350SP-13,SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP,1,1,C2071691,AP64350SP-13,SO-8-EP buck 3.8-40V,Extended,14905,yes,OK,OK SO-8-EP (same easyeda fp as U25; verify EP vs Diodes SP drawing),0.7393/0.5822,
|
||||||
|
U21,AP2112K-3.3,SOT-23-5,1,1,C51118,AP2112K-3.3TRG1,SOT-25,Extended,173566,yes,OK,OK SOT-23-5,0.1330/0.1330,
|
||||||
|
U22,MFF2-SIM-carrier,MFF2_6x5,1,0,,,,,,,,,,no LCSC: DNP
|
||||||
|
"U23,U24",74LVC2T45,VSSOP-8_L2.1-W2.4-P0.50-LS3.2-BL,2,2,C730237,"74LVC2T45DC,125",VSSOP-8,Extended,4391,yes,OK,OK VSSOP-8 0.5 mm,0.4074/0.2889,
|
||||||
|
U25,TPS54360B,SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP,1,1,C524806,TPS54360BDDAR,SOIC-8-EP (DDA) buck 60V,Extended,10155,yes,OK,OK SO-8-EP (verify EP 3.2x2.5 vs TI DDA drawing),0.5585/0.4281,
|
||||||
|
U26,SC7A20TR,LGA-12_L2.0-W2.0-P0.50-BL,1,1,C5126709,SC7A20TR,LGA-12 2x2,Extended,15693,yes,OK,OK LGA-12 2x2,0.3201/0.3201,
|
||||||
|
"Y1,Y3",25MHz,Crystal_SMD_HC49-SD,2,2,C14872,X49SM25MSD2SC YXC,HC-49S-SMD 25MHz CL20pF -20..70C,Extended,28533,yes,OK,OK HC-49S-SMD on HC49-SD fp,0.0964/0.0964,CL 20pF vs 15/18pF caps
|
||||||
|
Y2,1.8432MHz,Crystal_SMD_HC49-SD,1,1,C2238,X49SM36864MSD2SC-1,HC-49S-SMD 3.6864MHz CL20pF,Extended,3014,yes,OK,OK package; VALUE label 1.8432MHz but part = 3.6864 MHz,0.1074/0.0837,sch value 1.8432MHz = label error
|
||||||
|
Y4,32.768kHz,Crystal_SMD_3215-2Pin_3.2x1.5mm,1,1,C32346,Q13FC13500004 Epson,3215 32.768k CL12.5pF,Basic,614447,yes,OK,OK 3215,0.1649/0.1649,
|
||||||
|
@ -0,0 +1,161 @@
|
|||||||
|
# DRC summary — EinarBoard v6 (`hbox-watchdog-v6.kicad_pcb`, sha256 6ddec80d…36bf)
|
||||||
|
|
||||||
|
Run via KiCad MCP `open_project` + `run_drc` (swig backend, KiCad 10), report created 2026-09-28T14:28:42 (Mac local time = 20:28 UTC). Nothing was saved. Full text report: `drc_full.rpt`; JSON: `drc_full.json`; every item as a row: `drc_items.csv`.
|
||||||
|
|
||||||
|
- **Total violations: 283 — errors 0, warnings 283**
|
||||||
|
- **Unconnected items: 0** (reported separately by KiCad; this pack's own union-find check also finds 0 multi-pad nets unrouted — see net_routing_summary.csv)
|
||||||
|
- Footprint errors (schematic parity is NOT part of this run): 0
|
||||||
|
- Checks set to ignore in the project (so never reported): Footprint has no courtyard defined, Track endpoint not centered on via, Tuning profile track geometries, Footprint doesn't match symbol's footprint filters, Footprint component type doesn't match footprint pads
|
||||||
|
- Zone fills: DRC used the fills stored in the file (the tool does not report a refill); fills present on all 4 copper zones.
|
||||||
|
|
||||||
|
## Counts by type
|
||||||
|
|
||||||
|
| type | count | severity |
|
||||||
|
|---|---|---|
|
||||||
|
| track_width | 183 | warning |
|
||||||
|
| lib_footprint_mismatch | 82 | warning |
|
||||||
|
| silk_overlap | 11 | warning |
|
||||||
|
| lib_footprint_issues | 4 | warning |
|
||||||
|
| silk_over_copper | 2 | warning |
|
||||||
|
| silk_edge_clearance | 1 | warning |
|
||||||
|
|
||||||
|
## track_width (all from the custom T15 "power width" warning rules in .kicad_dru)
|
||||||
|
|
||||||
|
| net | rule | count | actual widths (mm) | total length flagged (mm) |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| /3V3_ETH | T15 power width: PWR_MID >= 0.6 mm | 54 | 0.2500 0.3000 0.5000 | 107.99 |
|
||||||
|
| /MAIN5V | T15 power width: PWR_HI >= 1.0 mm | 21 | 0.3000 0.5000 | 31.38 |
|
||||||
|
| /VEH5V | T15 power width: PWR_HI >= 1.0 mm | 15 | 0.2500 0.3000 0.5000 0.8000 | 31.91 |
|
||||||
|
| /5V_FAN | T15 power width: PWR_MID >= 0.6 mm | 14 | 0.5000 | 100.04 |
|
||||||
|
| /VIN_SW | T15 power width: PWR_HI >= 1.0 mm | 10 | 0.2500 0.5000 0.8000 | 27.97 |
|
||||||
|
| /SW_5V | T15 power width: PWR_MID >= 0.6 mm | 9 | 0.3000 0.5000 | 14.87 |
|
||||||
|
| /VIN_MODEM | T15 power width: modem + vehicle PSU paths >= 0.8 mm | 9 | 0.3000 0.5000 | 11.13 |
|
||||||
|
| /SW_FAN | T15 power width: PWR_MID >= 0.6 mm | 8 | 0.5000 | 20.96 |
|
||||||
|
| /VBAT_MODEM | T15 power width: modem + vehicle PSU paths >= 0.8 mm | 7 | 0.2500 0.5000 | 12.43 |
|
||||||
|
| /FAN_RET | T15 power width: PWR_MID >= 0.6 mm | 7 | 0.5000 | 63.54 |
|
||||||
|
| /SW_IN | T15 power width: PWR_MID >= 0.6 mm | 7 | 0.3000 0.5000 | 7.50 |
|
||||||
|
| /SYS5V | T15 power width: PWR_HI >= 1.0 mm | 6 | 0.5000 0.8000 | 7.01 |
|
||||||
|
| /SW_BAT | T15 power width: PWR_HI >= 1.0 mm | 6 | 0.2500 0.3000 0.5000 | 12.89 |
|
||||||
|
| /VIN_PROT | T15 power width: modem + vehicle PSU paths >= 0.8 mm | 5 | 0.5000 | 11.72 |
|
||||||
|
| /BAT_PLUS | T15 power width: PWR_HI >= 1.0 mm | 4 | 0.2500 0.5000 | 16.16 |
|
||||||
|
| /VIN_FUSED | T15 power width: modem + vehicle PSU paths >= 0.8 mm | 1 | 0.5000 | 1.47 |
|
||||||
|
|
||||||
|
## lib_footprint_mismatch (82)
|
||||||
|
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(116.7, 97.0) Footprint C81
|
||||||
|
- Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD' — @(83.75, 53.45) Footprint C102
|
||||||
|
- Footprint 'JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical' does not match copy in library 'Connector_JST' — @(196.0, 110.5) Footprint P3
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(94.5, 61.275) Footprint C92
|
||||||
|
- Footprint 'JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical' does not match copy in library 'Connector_JST' — @(100.25, 44.0) Footprint P6
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(101.5, 57.5) Footprint C93
|
||||||
|
- Footprint 'LQFP-64_10x10mm_P0.5mm' does not match copy in library 'Package_QFP' — @(120.7, 67.425) Footprint U16
|
||||||
|
- Footprint 'LQFP-48_7x7mm_P0.5mm' does not match copy in library 'Package_QFP' — @(95.1625, 53.83) Footprint U11
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(86.675, 50.5) Footprint R93
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(92.5, 61.275) Footprint C98
|
||||||
|
- Footprint 'SOT-223-3_TabPin2' does not match copy in library 'Package_TO_SOT_SMD' — @(92.5, 80.0) Footprint U17
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(86.0, 82.265) Footprint R85
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(116.3, 58.25) Footprint C111
|
||||||
|
- Footprint 'Crystal_SMD_3215-2Pin_3.2x1.5mm' does not match copy in library 'Crystal' — @(132.05, 73.5) Footprint Y4
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(139.975, 68.175) Footprint C113
|
||||||
|
- Footprint 'D_SOD-323' does not match copy in library 'Diode_SMD' — @(73.15, 69.0) Footprint D15
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(128.3, 73.25) Footprint C110
|
||||||
|
- Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD' — @(102.375, 62.945) Footprint C91
|
||||||
|
- Footprint 'SolderJumper-2_P1.3mm_Open_TrianglePad1.0x1.5mm' does not match copy in library 'Jumper' — @(138.4, 127.5) Footprint JP5
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(106.17, 68.25) Footprint R87
|
||||||
|
- Footprint 'PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal' does not match copy in library 'Connector_Phoenix_MC' — @(135.48, 131.5675) Footprint P11
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(133.55, 70.75) Footprint C116
|
||||||
|
- Footprint 'Crystal_SMD_HC49-SD' does not match copy in library 'Crystal' — @(136.475, 62.925) Footprint Y3
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(117.7, 124.5) Footprint C80
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(113.675, 106.25) Footprint C86
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(130.275, 61.7796) Footprint C112
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(86.675, 48.5) Footprint R84
|
||||||
|
- Footprint 'D_SOD-323' does not match copy in library 'Diode_SMD' — @(72.5, 77.0) Footprint D16
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(86.675, 54.5) Footprint R95
|
||||||
|
- Footprint 'Sensirion_DFN-4_1.5x1.5mm_P0.8mm_SHT4x_NoCentralPad' does not match copy in library 'Sensor_Humidity' — @(122.375, 77.3) Footprint U3
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(78.25, 76.75) Footprint R86
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(83.5, 57.5) Footprint R97
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(86.0, 80.0) Footprint R88
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(116.7, 90.475) Footprint C82
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(139.975, 57.675) Footprint C114
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(114.2, 115.25) Footprint R90
|
||||||
|
- Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD' — @(83.75, 48.95) Footprint C94
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(136.15, 127.67) Footprint R82
|
||||||
|
- Footprint 'PinHeader_1x04_P2.54mm_Vertical' does not match copy in library 'Connector_PinHeader_2.54mm' — @(72.45, 135.75) Footprint H4
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(86.675, 58.5) Footprint C97
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(126.375, 76.85) Footprint R81
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(128.95, 101.775) Footprint C89
|
||||||
|
- Footprint 'JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical' does not match copy in library 'Connector_JST' — @(119.25, 43.965) Footprint P9
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(130.05, 70.75) Footprint C115
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(113.775, 59.0) Footprint C105
|
||||||
|
- Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD' — @(78.5, 73.05) Footprint C101
|
||||||
|
- Footprint 'TerminalBlock_Phoenix_MKDS-1,5-5_1x05_P5.00mm_Horizontal' does not match copy in library 'TerminalBlock_Phoenix' — @(167.5, 135.0) Footprint P1
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(116.7, 93.725) Footprint C83
|
||||||
|
- Footprint 'SOIC-8_3.9x4.9mm_P1.27mm' does not match copy in library 'Package_SO' — @(122.025, 84.9663) Footprint U14
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(126.75, 83.8512) Footprint C84
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(113.675, 108.25) Footprint C88
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(126.025, 59.0) Footprint C106
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(116.7, 87.0) Footprint R80
|
||||||
|
- Footprint 'LED_0603_1608Metric' does not match copy in library 'LED_SMD' — @(132.6375, 80.8171) Footprint D18
|
||||||
|
- Footprint 'LED_0603_1608Metric' does not match copy in library 'LED_SMD' — @(132.5875, 75.8171) Footprint D17
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(114.2, 113.5) Footprint R89
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(112.45, 102.975) Footprint C85
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(83.5, 65.275) Footprint C95
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(114.2, 117.0) Footprint R91
|
||||||
|
- Footprint 'SOIC-16W_7.5x10.3mm_P1.27mm' does not match copy in library 'Package_SO' — @(122.2, 118.0) Footprint U13
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(114.45, 102.975) Footprint C87
|
||||||
|
- Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD' — @(85.5, 85.5) Footprint C117
|
||||||
|
- Footprint 'Crystal_SMD_HC49-SD' does not match copy in library 'Crystal' — @(113.15, 91.9013) Footprint Y2
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(113.0, 72.5) Footprint C107
|
||||||
|
- Footprint 'Crystal_SMD_HC49-SD' does not match copy in library 'Crystal' — @(91.5, 65.5) Footprint Y1
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(104.5, 62.725) Footprint C96
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(83.5, 61.325) Footprint R96
|
||||||
|
- Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD' — @(88.0, 85.5) Footprint C118
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(86.675, 56.5) Footprint R94
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(130.275, 67.25) Footprint C104
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(86.675, 52.5) Footprint R92
|
||||||
|
- Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD' — @(100.0, 62.945) Footprint C90
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(130.275, 65.25) Footprint C109
|
||||||
|
- Footprint 'D_SOD-323' does not match copy in library 'Diode_SMD' — @(72.5, 72.5) Footprint D14
|
||||||
|
- Footprint 'TSSOP-28_4.4x9.7mm_P0.65mm' does not match copy in library 'Package_SO' — @(122.3875, 93.9762) Footprint U10
|
||||||
|
- Footprint 'SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm' does not match copy in library 'Package_SO' — @(84.0, 76.35) Footprint U12
|
||||||
|
- Footprint 'JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical' does not match copy in library 'Connector_JST' — @(115.7, 136.5) Footprint P10
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(75.825, 77.5) Footprint C99
|
||||||
|
- Footprint 'PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal' does not match copy in library 'Connector_Phoenix_MC' — @(122.155, 131.5675) Footprint P12
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(84.3, 72.75) Footprint C100
|
||||||
|
- Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD' — @(128.3, 76.45) Footprint C108
|
||||||
|
- Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD' — @(86.675, 60.5) Footprint R83
|
||||||
|
|
||||||
|
## silk_overlap (11)
|
||||||
|
|
||||||
|
- Silkscreen clearance — @(70.6, 127.075) Reference field of D27 | @(70.3024, 127.475) Polygon of D27 on F.Silkscreen
|
||||||
|
- Silkscreen clearance — @(70.23, 127.555) Segment of D27 on F.Silkscreen | @(70.6, 127.075) Reference field of D27
|
||||||
|
- Silkscreen clearance — @(118.5225, 58.4873) Segment of R99 on F.Silkscreen | @(118.8, 58.0) Reference field of C157
|
||||||
|
- Silkscreen clearance — @(187.25, 80.75) Reference field of C126 | @(186.25, 80.53) Segment of U19 on F.Silkscreen
|
||||||
|
- Silkscreen clearance — @(161.5, 83.5) Reference field of Q21 | @(162.25, 84.0) Segment of U19 on F.Silkscreen
|
||||||
|
- Silkscreen clearance — @(171.45, 99.0) Segment of JP3 on F.Silkscreen | @(171.25, 99.25) Reference field of JP3
|
||||||
|
- Silkscreen clearance — @(171.75, 98.7) Segment of JP3 on F.Silkscreen | @(171.25, 99.25) Reference field of JP3
|
||||||
|
- Silkscreen clearance — @(155.75, 73.98) Arc of U24 on F.Silkscreen | @(155.75, 75.0) Reference field of U24
|
||||||
|
- Silkscreen clearance — @(155.6, 69.77) Segment of U23 on F.Silkscreen | @(156.55, 69.02) Reference field of U23
|
||||||
|
- Silkscreen clearance — @(137.05, 125.17) Segment of Q10 on F.Silkscreen | @(138.4, 125.5) Reference field of JP5
|
||||||
|
- Silkscreen clearance — @(155.25, 116.75) Reference field of Q23 | @(152.05, 116.9775) Segment of Q23 on F.Silkscreen
|
||||||
|
|
||||||
|
## lib_footprint_issues (4)
|
||||||
|
|
||||||
|
- Footprint 'MountingHole_3.2mm' not found in library 'MountingHole' — @(195.2, 135.3) Footprint MH8
|
||||||
|
- Footprint 'MountingHole_3.2mm' not found in library 'MountingHole' — @(65.2, 45.3) Footprint MH5
|
||||||
|
- Footprint 'MountingHole_3.2mm' not found in library 'MountingHole' — @(195.2, 45.3) Footprint MH7
|
||||||
|
- Footprint 'MountingHole_3.2mm' not found in library 'MountingHole' — @(65.2, 135.3) Footprint MH6
|
||||||
|
|
||||||
|
## silk_over_copper (2)
|
||||||
|
|
||||||
|
- Silkscreen clipped by solder mask — @(123.55, 56.75) Reference field of Rigb1 | @(123.3, 57.225) Pad 2 [GND] of C9 on F.Cu
|
||||||
|
- Silkscreen clipped by solder mask — @(145.5, 109.25) Reference field of C10 | @(145.5, 110.55) Pad 2 [GND] of C10 on F.Cu
|
||||||
|
|
||||||
|
## silk_edge_clearance (1)
|
||||||
|
|
||||||
|
- Silkscreen clipped by board edge — @(200.1917, 140.3231) Segment on Edge.Cuts | @(167.5, 139.72) Polygon of P1 on F.Silkscreen
|
||||||
|
|
||||||
|
## Stale report for comparison (Sep-25 `hbox-watchdog-v6_drc_violations.json`, NOT current)
|
||||||
|
|
||||||
|
- total 303 counts {'silk_edge_clearance': 1, 'lib_footprint_issues': 4, 'lib_footprint_mismatch': 82, 'track_width': 199, 'silk_overlap': 14, 'silk_over_copper': 3} severities {'error': 0, 'warning': 303, 'info': 0} timestamp 2026-09-25T13:53:38
|
||||||
|
- Note: the MCP `run_drc` call on 28-Sep rewrote `kicad/hbox-watchdog-v6_drc_violations.json` with the current result (gitignored generated file); the Sep-25 copy is preserved in this pack as `src/hbox-watchdog-v6_drc_violations.json` and on the Mac as `evidence/drc_stale_20260925_violations.json`.
|
||||||
@ -0,0 +1,152 @@
|
|||||||
|
# ERC summary — EinarBoard v6 (`hbox-watchdog-v6.kicad_sch`)
|
||||||
|
|
||||||
|
**KiCad 10.0.4 ERC (via KiCad MCP `run_erc`, kicad-cli): 166 violations = 0 errors + 166 warnings.** Same total on the original file and on the byte-identical copy.
|
||||||
|
|
||||||
|
## How the full list was obtained
|
||||||
|
|
||||||
|
- `run_erc` prints only the first 30 items (sorted by position) and has no report/offset option (tried extra params; ignored).
|
||||||
|
- A byte-identical copy of the schematic plus copies of the `.kicad_pro`, `sym-lib-table`, `fp-lib-table` and project libraries was placed in `evidence/_erc_work/` on the Mac. The unmodified copy reproduces **166**. Then the copy's `.kicad_pro` ERC severities were switched so that one group of checks ran at a time (and, for pin conflicts, a single pin-map cell).
|
||||||
|
- Library checks: 22 mismatches (complete, 22 ≤ 30) + 10 not-found (complete). All other non-pin checks: 30 (complete). Pin-to-pin: 104. **22 + 10 + 30 + 104 = 166 ✓**
|
||||||
|
- The 104 pin-to-pin markers are listed from a model of KiCad's reporting (per net, repeatedly mark the pin with the most remaining conflicts). The model reproduces KiCad's totals exactly (104 with the project pin map; 70 with only the Unspecified–Unspecified cell) and 29 of the 30 visible KiCad positions in the pin-only run; which pin carries the marker on ties can differ, and KiCad itself is not stable run-to-run (see NC note).
|
||||||
|
- Raw tool outputs: `evidence/erc/kicad_run_*.txt`. Items with source `kicad (exact)` are verbatim KiCad; `model` items are reconstructed.
|
||||||
|
|
||||||
|
## Counts by category
|
||||||
|
|
||||||
|
| category | count | severity | source |
|
||||||
|
|---|---|---|---|
|
||||||
|
| pin_to_pin | 104 | warning | model (count = KiCad) |
|
||||||
|
| no_connect_dangling | 23 | warning | KiCad exact |
|
||||||
|
| lib_symbol_mismatch | 22 | warning | KiCad exact |
|
||||||
|
| lib_symbol_issues | 10 | warning | KiCad exact |
|
||||||
|
| footprint_link_issues | 3 | warning | KiCad exact |
|
||||||
|
| no_connect_connected | 2 | warning | KiCad exact |
|
||||||
|
| unconnected_wire_endpoint | 2 | warning | KiCad exact |
|
||||||
|
| **total** | **166** | | |
|
||||||
|
|
||||||
|
## Library: symbol not found in library (10)
|
||||||
|
|
||||||
|
- Symbol 'Q_PMOS_GDS' not found in symbol library 'Device' @ (72.00, 345.00) — Q23 Device:Q_PMOS_GDS value=IRFR5305 fp=Package_TO_SOT_SMD:TO-252-2
|
||||||
|
- Symbol 'D_Zener_ANK' not found in symbol library 'Device' @ (81.28, 100.33) — DzG1 Device:D_Zener_ANK value=BZX84C15 fp=Package_TO_SOT_SMD:SOT-23
|
||||||
|
- Symbol 'Q_PMOS_GDS' not found in symbol library 'Device' @ (83.82, 115.57) — Q10 Device:Q_PMOS_GDS value=IRFR5305 fp=Package_TO_SOT_SMD:TO-252-2
|
||||||
|
- Symbol 'D_Zener_ANK' not found in symbol library 'Device' @ (92.00, 352.00) — D33 Device:D_Zener_ANK value=BZX84C15 fp=Package_TO_SOT_SMD:SOT-23
|
||||||
|
- Symbol 'Q_NMOS_GSD' not found in symbol library 'Device' @ (205.74, 121.92) — Q2 Device:Q_NMOS_GSD value=AO3400A fp=Package_TO_SOT_SMD:SOT-23
|
||||||
|
- Symbol 'Q_PMOS_GSD' not found in symbol library 'Device' @ (214.63, 80.01) — Q1 Device:Q_PMOS_GSD value=AO3401A fp=Package_TO_SOT_SMD:SOT-23
|
||||||
|
- Symbol 'Q_NMOS_GSD' not found in symbol library 'Device' @ (246.00, 330.00) — Q20 Device:Q_NMOS_GSD value=2N7002 fp=Package_TO_SOT_SMD:SOT-23
|
||||||
|
- Symbol 'Q_NMOS_GSD' not found in symbol library 'Device' @ (270.00, 330.00) — Q21 Device:Q_NMOS_GSD value=2N7002 fp=Package_TO_SOT_SMD:SOT-23
|
||||||
|
- Symbol 'Q_NMOS_GSD' not found in symbol library 'Device' @ (271.78, 104.14) — Q4 Device:Q_NMOS_GSD value=AO3400A fp=Package_TO_SOT_SMD:SOT-23
|
||||||
|
- Symbol 'PCF8574' not found in symbol library 'Interface_Expansion' @ (565.15, 59.69) — U13 Interface_Expansion:PCF8574 value=PCF8574 fp=Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm
|
||||||
|
|
||||||
|
## Library: symbol differs from library copy (22)
|
||||||
|
|
||||||
|
- Symbol 'Fuse_CER' doesn't match copy in library 'Drogheda-sym' @ (55.00, 345.00) — F2 Drogheda-sym:Fuse_CER value=2A/125V-NANO2-in-holder fp=Fuse:Fuseholder_Littelfuse_Nano2_154x
|
||||||
|
- Symbol 'TPS54360B' doesn't match copy in library 'Drogheda-sym' @ (145.00, 348.00) — U25 Drogheda-sym:TPS54360B value=TPS54360B fp=Drogheda-v6:SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP
|
||||||
|
- Symbol 'L' doesn't match copy in library 'Device' @ (152.40, 228.60) — L2 Device:L value=10uH fp=Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm
|
||||||
|
- Symbol 'L' doesn't match copy in library 'Device' @ (174.00, 348.00) — L22 Device:L value=10uH/SRP1265A fp=Drogheda-v6:IND-SMD_L13.5-W12.5
|
||||||
|
- Symbol 'SW_Push' doesn't match copy in library 'Switch' @ (300.00, 110.00) — SW1 Switch:SW_Push value=RESET fp=Button_Switch_THT:SW_PUSH_6mm
|
||||||
|
- Symbol 'L' doesn't match copy in library 'Device' @ (300.00, 300.00) — L20 Device:L value=4.7uH/5A fp=Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm
|
||||||
|
- Symbol 'L' doesn't match copy in library 'Device' @ (330.20, 166.12) — L6 Device:L value=2.2uH/8A fp=Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm
|
||||||
|
- Symbol 'NANOSIM_JAE' doesn't match copy in library 'Drogheda-sym' @ (340.00, 485.00) — J14 Drogheda-sym:NANOSIM_JAE value=NanoSIM-JAE-SF72S006 fp=Drogheda:JAE_SIM_Card_SF72S006
|
||||||
|
- Symbol 'MFF2_SIM' doesn't match copy in library 'Drogheda-sym' @ (400.00, 340.00) — U22 Drogheda-sym:MFF2_SIM value=MFF2-SIM-carrier fp=Drogheda:MFF2_6x5
|
||||||
|
- Symbol 'L' doesn't match copy in library 'Device' @ (424.00, 160.00) — L21 Device:L value=68nH fp=Inductor_SMD:L_0603_1608Metric
|
||||||
|
- Symbol 'SW_Push' doesn't match copy in library 'Switch' @ (436.88, 502.92) — SW2 Switch:SW_Push value=BOOT0 fp=Button_Switch_THT:SW_PUSH_6mm
|
||||||
|
- Symbol 'Crystal' doesn't match copy in library 'Device' @ (436.88, 530.86) — Y3 Device:Crystal value=25MHz fp=Crystal:Crystal_SMD_HC49-SD
|
||||||
|
- Symbol 'AO4406A' doesn't match copy in library 'Drogheda-sym' @ (447.04, 230.89) — Q7 Drogheda-sym:AO4406A value=AO4406A fp=Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
|
||||||
|
- Symbol 'Crystal' doesn't match copy in library 'Device' @ (474.98, 530.86) — Y4 Device:Crystal value=32.768kHz fp=Crystal:Crystal_SMD_3215-2Pin_3.2x1.5mm
|
||||||
|
- Symbol 'STM32F411RETx' doesn't match copy in library 'MCU_ST_STM32F4' @ (500.38, 434.34) — U16 MCU_ST_STM32F4:STM32F411RETx value=STM32F411RET6 fp=Package_QFP:LQFP-64_10x10mm_P0.5mm
|
||||||
|
- Symbol 'D' doesn't match copy in library 'Device' @ (519.97, 202.99) — D6 Device:D value=1N4148W fp=Diode_SMD:D_SOD-123
|
||||||
|
- Symbol 'Crystal' doesn't match copy in library 'Device' @ (539.75, 167.64) — Y2 Device:Crystal value=1.8432MHz fp=Crystal:Crystal_SMD_HC49-SD
|
||||||
|
- Symbol 'SP3485EN' doesn't match copy in library 'Interface_UART' @ (609.60, 139.70) — U14 Interface_UART:SP3485EN value=SP3485EN fp=Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
|
||||||
|
- Symbol 'AMS1117-3.3' doesn't match copy in library 'Regulator_Linear' @ (665.48, 502.92) — U17 Regulator_Linear:AMS1117-3.3 value=AMS1117-3.3 fp=Package_TO_SOT_SMD:SOT-223-3_TabPin2
|
||||||
|
- Symbol 'Crystal' doesn't match copy in library 'Device' @ (694.69, 175.26) — Y1 Device:Crystal value=25MHz fp=Crystal:Crystal_SMD_HC49-SD
|
||||||
|
- Symbol 'L' doesn't match copy in library 'Device' @ (722.63, 222.25) — L8 Device:L value=10uH/2A fp=Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm
|
||||||
|
- Symbol 'RJ45_Hanrun_HR911105A_Horizontal' doesn't match copy in library 'Connector' @ (800.10, 90.17) — J10 Connector:RJ45_Hanrun_HR911105A_Horizontal value=HR911105A fp=Connector_RJ45:RJ45_Hanrun_HR911105A_Horizontal
|
||||||
|
|
||||||
|
## Footprint link issues (3)
|
||||||
|
|
||||||
|
- Footprint 'PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical' not found in library 'Connector_Phoenix_MC' @ (650.24, 139.70) — P11 Connector_Generic:Conn_01x03 value=RS485_OUT fp=Connector_Phoenix_MC:PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical
|
||||||
|
- Footprint 'PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical' not found in library 'Connector_Phoenix_MC' @ (650.24, 204.47) — P12 Connector_Generic:Conn_01x03 value=RS232_OUT fp=Connector_Phoenix_MC:PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical
|
||||||
|
- The current configuration does not include the footprint library 'Connector_RJ45' @ (800.10, 90.17) — J10 Connector:RJ45_Hanrun_HR911105A_Horizontal value=HR911105A fp=Connector_RJ45:RJ45_Hanrun_HR911105A_Horizontal
|
||||||
|
|
||||||
|
## No-connect flag on a connected pin (KiCad reports 2 markers)
|
||||||
|
|
||||||
|
- A pin with a "no connection" flag is connected @ (31.75, 163.83) — marker placed on pin R31.2 of net /I2C_SDA; NC flag sits on U10.14
|
||||||
|
- A pin with a "no connection" flag is connected @ (513.59, 182.37) — marker placed on pin K1.10 of net /USART6_TX; NC flag sits on U16.37
|
||||||
|
|
||||||
|
Offline check (`scripts/erc_reconstruct.py`): NC flags sit on 4 connected pins — U16.37 (/USART6_TX → K1.10), U16.38 (/USART6_RX → R106.2), U10.13 (/I2C_SCL), U10.14 (/I2C_SDA). KiCad emits 2 markers (nets /USART6_TX and /I2C_SDA in these runs) and places each on some other pin of the net (R31.2 or U26.2 for /I2C_SDA in different runs).
|
||||||
|
|
||||||
|
## Unconnected wire endpoints (2)
|
||||||
|
|
||||||
|
- Unconnected wire endpoint @ (50.80, 25.40) — marker at pin P1.4; wire(s) ending here: (50.8, 25.4)->(51.054, 25.4) (len 0.254 mm, uuid 2b755f7f-c78f-466c-b9d8-140a145268c9); (48.768, 25.4)->(50.8, 25.4) (len 2.032 mm, uuid 46f71e27-a82d-4536-bb46-4c32a263bac7)
|
||||||
|
- Unconnected wire endpoint @ (201.68, 216.41) — marker at pin R52.2; wire(s) ending here: (201.676, 216.408)->(201.676, 219.71) (len 3.302 mm, uuid 7c1dbfc0-4b21-4965-a5ed-b43ba9c04a56)
|
||||||
|
|
||||||
|
## Orphan no-connect flags (23)
|
||||||
|
|
||||||
|
All at x = 453.898 mm (13) and x = 484.378 mm (10), y 89.4–130.0 mm, on a 2.54 mm pitch in two columns 30.48 mm apart; they touch no pin or wire. (Fact for context: the schematic lib_symbols cache still contains `Drogheda-sym:SimpleRTK2B_Pro_Socket`, which no placed symbol uses.)
|
||||||
|
|
||||||
|
- (453.898, 99.568)
|
||||||
|
- (453.898, 102.108)
|
||||||
|
- (453.898, 104.648)
|
||||||
|
- (453.898, 107.188)
|
||||||
|
- (453.898, 109.728)
|
||||||
|
- (453.898, 112.268)
|
||||||
|
- (453.898, 114.808)
|
||||||
|
- (453.898, 117.348)
|
||||||
|
- (453.898, 119.888)
|
||||||
|
- (453.898, 122.428)
|
||||||
|
- (453.898, 124.968)
|
||||||
|
- (453.898, 127.508)
|
||||||
|
- (453.898, 130.048)
|
||||||
|
- (484.378, 89.408)
|
||||||
|
- (484.378, 91.948)
|
||||||
|
- (484.378, 97.028)
|
||||||
|
- (484.378, 107.188)
|
||||||
|
- (484.378, 109.728)
|
||||||
|
- (484.378, 112.268)
|
||||||
|
- (484.378, 114.808)
|
||||||
|
- (484.378, 117.348)
|
||||||
|
- (484.378, 119.888)
|
||||||
|
- (484.378, 124.968)
|
||||||
|
|
||||||
|
## Pin-to-pin conflicts (104 markers, all warnings)
|
||||||
|
|
||||||
|
| net | markers | marker pins (model) |
|
||||||
|
|---|---|---|
|
||||||
|
| GND | 55 | D22.2 D27.2 D28.2 J12.2 J12.3 J13.2 J13.3 U19.17 U19.18 U19.2 U19.29 U19.39 U19.45 U19.46 U19.54 U19.58 U19.59 U19.61 U19.62 U19.63 U19.64 U19.65 U19.69 U19.70 U19.71 U19.72 U19.73 U19.74 U19.75 U19.76 U19.77 U19.78 U19.79 U19.80 U19.81 U19.82 U19.83 U19.84 U19.85 U19.86 U19.87 U19.88 U19.89 U19.91 U19.92 U19.94 U20.7 U20.9 U23.4 U23.5 U23.6 U24.4 U26.1 U26.8 U26.9 |
|
||||||
|
| /3V3 | 5 | U23.8 U24.8 U26.10 U26.3 U26.7 |
|
||||||
|
| /1V8_MODEM | 4 | U19.15 U23.1 U24.1 U24.5 |
|
||||||
|
| /VBAT_MODEM | 4 | D22.1 U19.55 U19.56 U19.57 |
|
||||||
|
| /VIN_MODEM | 2 | D21.1 U20.2 |
|
||||||
|
| /DIN_4G_M | 2 | U19.10 U23.2 |
|
||||||
|
| /DOUT_4G_M | 2 | U19.9 U24.2 |
|
||||||
|
| /RF_ANT_LTE | 2 | D28.1 J13.1 |
|
||||||
|
| /RF_ANT_GNSS | 2 | D27.1 J12.1 |
|
||||||
|
| /I2C_SDA | 1 | U26.2 |
|
||||||
|
| /ACC_INT1 | 1 | U26.5 |
|
||||||
|
| /I2C_SCL | 1 | U26.12 |
|
||||||
|
| /MODEM_STATUS_M | 1 | U24.3 |
|
||||||
|
| /MAIN5V | 1 | D21.2 |
|
||||||
|
| /BST_MODEM | 1 | U20.1 |
|
||||||
|
| /MODEM_PWR_EN | 1 | U20.3 |
|
||||||
|
| /RT_MODEM | 1 | U20.4 |
|
||||||
|
| /DIN_4G | 1 | U23.7 |
|
||||||
|
| /DOUT_4G | 1 | U24.7 |
|
||||||
|
| /MODEM_STATUS | 1 | U24.6 |
|
||||||
|
| /SW_MODEM | 1 | U20.8 |
|
||||||
|
| /COMP_MODEM | 1 | U20.6 |
|
||||||
|
| /FB_MODEM | 1 | U20.5 |
|
||||||
|
| /MODEM_PWRKEY_M | 1 | U19.1 |
|
||||||
|
| /MODEM_BOOT | 1 | U19.6 |
|
||||||
|
| /MODEM_RST_M | 1 | U19.16 |
|
||||||
|
| /USB_VBUS | 1 | U19.24 |
|
||||||
|
| /USB_DP | 1 | U19.27 |
|
||||||
|
| /USB_DM | 1 | U19.28 |
|
||||||
|
| /SIM_VDD | 1 | U19.30 |
|
||||||
|
| /SIM_DATA | 1 | U19.31 |
|
||||||
|
| /SIM_CLK | 1 | U19.32 |
|
||||||
|
| /SIM_RST | 1 | U19.33 |
|
||||||
|
| /NETLIGHT_1V8 | 1 | U19.52 |
|
||||||
|
| /RF_LTE | 1 | U19.60 |
|
||||||
|
|
||||||
|
Message mix: Pins of type Unspecified and Passive are connected: 50, Pins of type Unspecified and Bidirectional are connected: 5, Pins of type Unspecified and Input are connected: 1, Pins of type Unspecified and Unspecified are connected: 46, Pins of type Unspecified and Power output are connected: 2
|
||||||
|
|
||||||
|
Root cause pattern: symbols whose pins are all typed `unspecified` (easyeda2kicad imports in `Drogheda-v6.kicad_sym`: U19 A7670SA, U20 AP64350, U23/U24 74LVC2T45, U26 SC7A20, D21, J12/J13 U.FL …) conflict with every other pin type under the default pin map.
|
||||||
@ -0,0 +1,450 @@
|
|||||||
|
tool,idx,type,severity,message,x_mm,y_mm,item/refs,net,actual_width_mm,rule,seg_length_mm,layer,classification,justification
|
||||||
|
ERC,1,no_connect_connected,warning,"A pin with a ""no connection"" flag is connected",31.75,163.83,R31,/I2C_SDA,,,,,needs-fix-cosmetic,"NC flag on a connected pin (U16.37/38 USART6, U10.13/14 I2C); nets are connected in the netlist; remove the stray flags so ERC stays meaningful"
|
||||||
|
ERC,2,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,47.3,401.65,U26 C158,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,3,pin_to_pin,warning,Pins of type Unspecified and Bidirectional are connected,47.3,404.19,U26 U3,/I2C_SDA,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,4,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,47.3,406.73,U26 C158,/3V3,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,5,pin_to_pin,warning,Pins of type Unspecified and Bidirectional are connected,47.3,411.81,U26 U16,/ACC_INT1,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,6,unconnected_wire_endpoint,warning,Unconnected wire endpoint,50.8,25.4,P1,,,,,,needs-fix-cosmetic,"dangling wire stub at a pin that is connected by another wire (P1.4=GND, R52.2=GND in netlist); delete stub"
|
||||||
|
ERC,7,lib_symbol_mismatch,warning,Symbol 'Fuse_CER' doesn't match copy in library 'Drogheda-sym',55.0,345.0,F2,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,8,lib_symbol_issues,warning,Symbol 'Q_PMOS_GDS' not found in symbol library 'Device',72.0,345.0,Q23,,,,,,needs-fix-cosmetic,"symbol renamed/removed in KiCad 10 libs (Q_*MOS_G?S, D_Zener_ANK, PCF8574); pin maps verified vs part datasheets (IRFR5305 DPAK G-D(tab)-S, AO3401A/AO3400A/2N7002 G-S-D, BZX84 A-NC-K, PCF8574T SO16); re-link to project lib to keep them editable"
|
||||||
|
ERC,9,pin_to_pin,warning,Pins of type Unspecified and Input are connected,72.7,401.65,U26 U3,/I2C_SCL,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,10,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,72.7,406.73,U26 U26,/3V3,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,11,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,72.7,409.27,U26 U26,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,12,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,72.7,411.81,U26 C158,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,13,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,72.7,414.35,U26 C158,/3V3,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,14,lib_symbol_issues,warning,Symbol 'D_Zener_ANK' not found in symbol library 'Device',81.28,100.33,DzG1,,,,,,needs-fix-cosmetic,"symbol renamed/removed in KiCad 10 libs (Q_*MOS_G?S, D_Zener_ANK, PCF8574); pin maps verified vs part datasheets (IRFR5305 DPAK G-D(tab)-S, AO3401A/AO3400A/2N7002 G-S-D, BZX84 A-NC-K, PCF8574T SO16); re-link to project lib to keep them editable"
|
||||||
|
ERC,15,lib_symbol_issues,warning,Symbol 'Q_PMOS_GDS' not found in symbol library 'Device',83.82,115.57,Q10,,,,,,needs-fix-cosmetic,"symbol renamed/removed in KiCad 10 libs (Q_*MOS_G?S, D_Zener_ANK, PCF8574); pin maps verified vs part datasheets (IRFR5305 DPAK G-D(tab)-S, AO3401A/AO3400A/2N7002 G-S-D, BZX84 A-NC-K, PCF8574T SO16); re-link to project lib to keep them editable"
|
||||||
|
ERC,16,lib_symbol_issues,warning,Symbol 'D_Zener_ANK' not found in symbol library 'Device',92.0,352.0,D33,,,,,,needs-fix-cosmetic,"symbol renamed/removed in KiCad 10 libs (Q_*MOS_G?S, D_Zener_ANK, PCF8574); pin maps verified vs part datasheets (IRFR5305 DPAK G-D(tab)-S, AO3401A/AO3400A/2N7002 G-S-D, BZX84 A-NC-K, PCF8574T SO16); re-link to project lib to keep them editable"
|
||||||
|
ERC,17,lib_symbol_mismatch,warning,Symbol 'TPS54360B' doesn't match copy in library 'Drogheda-sym',145.0,348.0,U25,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,18,lib_symbol_mismatch,warning,Symbol 'L' doesn't match copy in library 'Device',152.4,228.6,L2,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,19,lib_symbol_mismatch,warning,Symbol 'L' doesn't match copy in library 'Device',174.0,348.0,L22,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,20,unconnected_wire_endpoint,warning,Unconnected wire endpoint,201.676,216.408,R52,,,,,,needs-fix-cosmetic,"dangling wire stub at a pin that is connected by another wire (P1.4=GND, R52.2=GND in netlist); delete stub"
|
||||||
|
ERC,21,lib_symbol_issues,warning,Symbol 'Q_NMOS_GSD' not found in symbol library 'Device',205.74,121.92,Q2,,,,,,needs-fix-cosmetic,"symbol renamed/removed in KiCad 10 libs (Q_*MOS_G?S, D_Zener_ANK, PCF8574); pin maps verified vs part datasheets (IRFR5305 DPAK G-D(tab)-S, AO3401A/AO3400A/2N7002 G-S-D, BZX84 A-NC-K, PCF8574T SO16); re-link to project lib to keep them editable"
|
||||||
|
ERC,22,lib_symbol_issues,warning,Symbol 'Q_PMOS_GSD' not found in symbol library 'Device',214.63,80.01,Q1,,,,,,needs-fix-cosmetic,"symbol renamed/removed in KiCad 10 libs (Q_*MOS_G?S, D_Zener_ANK, PCF8574); pin maps verified vs part datasheets (IRFR5305 DPAK G-D(tab)-S, AO3401A/AO3400A/2N7002 G-S-D, BZX84 A-NC-K, PCF8574T SO16); re-link to project lib to keep them editable"
|
||||||
|
ERC,23,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,234.92,293.0,D21 D20,/VIN_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,24,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,241.03,381.19,U23 C137,/1V8_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,25,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,241.03,383.73,U23 U19,/DIN_4G_M,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,26,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,241.03,388.81,U23 C137,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,27,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,241.03,404.19,U24 C139,/1V8_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,28,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,241.03,406.73,U24 U19,/DOUT_4G_M,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,29,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,241.03,409.27,U24 U19,/MODEM_STATUS_M,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,30,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,241.03,411.81,U24 C139,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,31,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,245.08,293.0,D21 JP4,/MAIN5V,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,32,lib_symbol_issues,warning,Symbol 'Q_NMOS_GSD' not found in symbol library 'Device',246.0,330.0,Q20,,,,,,needs-fix-cosmetic,"symbol renamed/removed in KiCad 10 libs (Q_*MOS_G?S, D_Zener_ANK, PCF8574); pin maps verified vs part datasheets (IRFR5305 DPAK G-D(tab)-S, AO3401A/AO3400A/2N7002 G-S-D, BZX84 A-NC-K, PCF8574T SO16); re-link to project lib to keep them editable"
|
||||||
|
ERC,33,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,249.3,297.46,U20 C129,/BST_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,34,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,249.3,300.0,U20 D21,/VIN_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,35,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,249.3,302.54,U20 R113,/MODEM_PWR_EN,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,36,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,249.3,305.08,U20 R117,/RT_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,37,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,262.0,292.38,U20 C128,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,38,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,268.97,381.19,U23 C138,/3V3,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,39,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,268.97,383.73,U23 R108,/DIN_4G,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,40,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,268.97,386.27,U23 U23,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,41,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,268.97,388.81,U23 C138,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,42,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,268.97,404.19,U24 C140,/3V3,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,43,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,268.97,406.73,U24 R107,/DOUT_4G,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,44,pin_to_pin,warning,Pins of type Unspecified and Bidirectional are connected,268.97,409.27,U24 U16,/MODEM_STATUS,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,45,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,268.97,411.81,U24 C139,/1V8_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,46,lib_symbol_issues,warning,Symbol 'Q_NMOS_GSD' not found in symbol library 'Device',270.0,330.0,Q21,,,,,,needs-fix-cosmetic,"symbol renamed/removed in KiCad 10 libs (Q_*MOS_G?S, D_Zener_ANK, PCF8574); pin maps verified vs part datasheets (IRFR5305 DPAK G-D(tab)-S, AO3401A/AO3400A/2N7002 G-S-D, BZX84 A-NC-K, PCF8574T SO16); re-link to project lib to keep them editable"
|
||||||
|
ERC,47,lib_symbol_issues,warning,Symbol 'Q_NMOS_GSD' not found in symbol library 'Device',271.78,104.14,Q4,,,,,,needs-fix-cosmetic,"symbol renamed/removed in KiCad 10 libs (Q_*MOS_G?S, D_Zener_ANK, PCF8574); pin maps verified vs part datasheets (IRFR5305 DPAK G-D(tab)-S, AO3401A/AO3400A/2N7002 G-S-D, BZX84 A-NC-K, PCF8574T SO16); re-link to project lib to keep them editable"
|
||||||
|
ERC,48,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,274.7,297.46,U20 C129,/SW_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,49,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,274.7,300.0,U20 R113,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,50,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,274.7,302.54,U20 C142,/COMP_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,51,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,274.7,305.08,U20 R110,/FB_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,52,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,294.92,370.0,D22 C130,/VBAT_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,53,lib_symbol_mismatch,warning,Symbol 'SW_Push' doesn't match copy in library 'Switch',300.0,110.0,SW1,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,54,lib_symbol_mismatch,warning,Symbol 'L' doesn't match copy in library 'Device',300.0,300.0,L20,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,55,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.08,370.0,D22 C130,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,56,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,252.53,U19 Q20,/MODEM_PWRKEY_M,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,57,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,255.07,U19 C147,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,58,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,265.23,U19 TP8,/MODEM_BOOT,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,59,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,272.85,U19 R107,/DOUT_4G_M,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,60,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,275.39,U19 R108,/DIN_4G_M,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,61,pin_to_pin,warning,Pins of type Unspecified and Power output are connected,305.87,288.09,U19 PF17,/1V8_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,62,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,290.63,U19 Q21,/MODEM_RST_M,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,63,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,293.17,U19 R111,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,64,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,305.87,295.71,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,65,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,310.95,U19 J9,/USB_VBUS,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,66,pin_to_pin,warning,Pins of type Unspecified and Bidirectional are connected,305.87,318.57,U19 J9,/USB_DP,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,67,pin_to_pin,warning,Pins of type Unspecified and Bidirectional are connected,305.87,321.11,U19 J9,/USB_DM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,68,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,323.65,U19 R111,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,69,pin_to_pin,warning,Pins of type Unspecified and Power output are connected,305.87,326.19,U19 PF18,/SIM_VDD,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,70,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,328.73,U19 D23,/SIM_DATA,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,71,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,331.27,U19 R129,/SIM_CLK,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,72,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,333.81,U19 R128,/SIM_RST,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,73,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,305.87,349.05,U19 D22,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,74,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,305.87,364.29,U19 D22,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,75,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,305.87,366.83,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,76,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,382.07,U19 R109,/NETLIGHT_1V8,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,77,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,387.15,U19 C130,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,78,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,305.87,389.69,U19 D22,/VBAT_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,79,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,305.87,392.23,U19 U19,/VBAT_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,80,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,305.87,394.77,U19 U19,/VBAT_MODEM,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,81,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,305.87,397.31,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,82,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,305.87,399.85,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,83,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,305.87,402.39,U19 R118,/RF_LTE,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,84,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,305.87,404.93,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,85,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,305.87,407.47,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,86,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,317.3,259.46,J13 C147,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,87,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,330.0,267.08,J13 D28,/RF_ANT_LTE,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,88,lib_symbol_mismatch,warning,Symbol 'L' doesn't match copy in library 'Device',330.2,166.116,L6,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,89,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,338.92,262.0,D28 C147,/RF_ANT_LTE,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,90,lib_symbol_mismatch,warning,Symbol 'NANOSIM_JAE' doesn't match copy in library 'Drogheda-sym',340.0,485.0,J14,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,91,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,342.7,259.46,J13 D28,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,92,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,349.08,262.0,D28 C24,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,93,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,328.73,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,94,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,333.81,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,95,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,336.35,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,96,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,341.43,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,97,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,343.97,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,98,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,346.51,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,99,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,349.05,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,100,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,351.59,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,101,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,354.13,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,102,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,356.67,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,103,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,359.21,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,104,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,361.75,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,105,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,364.29,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,106,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,366.83,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,107,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,369.37,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,108,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,351.59,371.91,U19 C136,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,109,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,351.59,374.45,U19 C136,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,110,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,376.99,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,111,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,379.53,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,112,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,382.07,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,113,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,384.61,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,114,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,387.15,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,115,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,389.69,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,116,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,392.23,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,117,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,402.39,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,118,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,351.59,404.93,U19 U19,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,119,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,351.59,407.47,U19 C136,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,120,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,387.3,152.46,J12 C123,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,121,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,400.0,160.08,J12 D27,/RF_ANT_GNSS,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,122,lib_symbol_mismatch,warning,Symbol 'MFF2_SIM' doesn't match copy in library 'Drogheda-sym',400.0,340.0,U22,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,123,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,400.92,165.0,D27 L21,/RF_ANT_GNSS,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,124,pin_to_pin,warning,Pins of type Unspecified and Passive are connected,411.08,165.0,D27 C144,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,125,pin_to_pin,warning,Pins of type Unspecified and Unspecified are connected,412.7,152.46,J12 D27,GND,,,,,pre-existing-benign,"easyeda-imported symbols with all pins typed Unspecified (U19/U20/U23/U24/U26/D21/D22/D27/D28/J12/J13); net-by-net review found no driver conflict (U23 DIR=GND B->A, U24 DIR=VCCA A->B, open-drain Q20/Q21, single drivers on UART/STATUS)"
|
||||||
|
ERC,126,lib_symbol_mismatch,warning,Symbol 'L' doesn't match copy in library 'Device',424.0,160.0,L21,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,127,lib_symbol_mismatch,warning,Symbol 'SW_Push' doesn't match copy in library 'Switch',436.88,502.92,SW2,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,128,lib_symbol_mismatch,warning,Symbol 'Crystal' doesn't match copy in library 'Device',436.88,530.86,Y3,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,129,lib_symbol_mismatch,warning,Symbol 'AO4406A' doesn't match copy in library 'Drogheda-sym',447.04,230.886,Q7,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,130,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,99.568,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,131,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,102.108,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,132,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,104.648,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,133,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,107.188,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,134,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,109.728,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,135,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,112.268,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,136,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,114.808,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,137,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,117.348,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,138,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,119.888,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,139,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,122.428,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,140,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,124.968,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,141,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,127.508,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,142,no_connect_dangling,warning,"Unconnected ""no connection"" flag",453.898,130.048,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,143,lib_symbol_mismatch,warning,Symbol 'Crystal' doesn't match copy in library 'Device',474.98,530.86,Y4,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,144,no_connect_dangling,warning,"Unconnected ""no connection"" flag",484.378,89.408,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,145,no_connect_dangling,warning,"Unconnected ""no connection"" flag",484.378,91.948,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,146,no_connect_dangling,warning,"Unconnected ""no connection"" flag",484.378,97.028,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,147,no_connect_dangling,warning,"Unconnected ""no connection"" flag",484.378,107.188,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,148,no_connect_dangling,warning,"Unconnected ""no connection"" flag",484.378,109.728,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,149,no_connect_dangling,warning,"Unconnected ""no connection"" flag",484.378,112.268,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,150,no_connect_dangling,warning,"Unconnected ""no connection"" flag",484.378,114.808,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,151,no_connect_dangling,warning,"Unconnected ""no connection"" flag",484.378,117.348,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,152,no_connect_dangling,warning,"Unconnected ""no connection"" flag",484.378,119.888,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,153,no_connect_dangling,warning,"Unconnected ""no connection"" flag",484.378,124.968,,,,,,,needs-fix-cosmetic,orphan NC flags left from the deleted SimpleRTK2B socket (two columns x=453.9/484.4 mm); touch nothing; delete
|
||||||
|
ERC,154,lib_symbol_mismatch,warning,Symbol 'STM32F411RETx' doesn't match copy in library 'MCU_ST_STM32F4',500.38,434.34,U16,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,155,no_connect_connected,warning,"A pin with a ""no connection"" flag is connected",513.588,182.372,K1,/USART6_TX,,,,,needs-fix-cosmetic,"NC flag on a connected pin (U16.37/38 USART6, U10.13/14 I2C); nets are connected in the netlist; remove the stray flags so ERC stays meaningful"
|
||||||
|
ERC,156,lib_symbol_mismatch,warning,Symbol 'D' doesn't match copy in library 'Device',519.968,202.992,D6,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,157,lib_symbol_mismatch,warning,Symbol 'Crystal' doesn't match copy in library 'Device',539.75,167.64,Y2,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,158,lib_symbol_issues,warning,Symbol 'PCF8574' not found in symbol library 'Interface_Expansion',565.15,59.69,U13,,,,,,needs-fix-cosmetic,"symbol renamed/removed in KiCad 10 libs (Q_*MOS_G?S, D_Zener_ANK, PCF8574); pin maps verified vs part datasheets (IRFR5305 DPAK G-D(tab)-S, AO3401A/AO3400A/2N7002 G-S-D, BZX84 A-NC-K, PCF8574T SO16); re-link to project lib to keep them editable"
|
||||||
|
ERC,159,lib_symbol_mismatch,warning,Symbol 'SP3485EN' doesn't match copy in library 'Interface_UART',609.6,139.7,U14,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,160,footprint_link_issues,warning,"Footprint 'PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical' not found in library 'Connector_Phoenix_MC'",650.24,139.7,P11,,,,,,real,P11/P12 schematic fp = Vertical (not in lib) while PCB + LCSC C5160226 are right-angle/Horizontal; J10 lib nickname Connector_RJ45 not configured. An Update-PCB would swap/flip these (DNP too)
|
||||||
|
ERC,161,footprint_link_issues,warning,"Footprint 'PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical' not found in library 'Connector_Phoenix_MC'",650.24,204.47,P12,,,,,,real,P11/P12 schematic fp = Vertical (not in lib) while PCB + LCSC C5160226 are right-angle/Horizontal; J10 lib nickname Connector_RJ45 not configured. An Update-PCB would swap/flip these (DNP too)
|
||||||
|
ERC,162,lib_symbol_mismatch,warning,Symbol 'AMS1117-3.3' doesn't match copy in library 'Regulator_Linear',665.48,502.92,U17,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,163,lib_symbol_mismatch,warning,Symbol 'Crystal' doesn't match copy in library 'Device',694.69,175.26,Y1,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,164,lib_symbol_mismatch,warning,Symbol 'L' doesn't match copy in library 'Device',722.63,222.25,L8,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,165,lib_symbol_mismatch,warning,Symbol 'RJ45_Hanrun_HR911105A_Horizontal' doesn't match copy in library 'Connector',800.1,90.17,J10,,,,,,pre-existing-benign,"embedded symbol differs from current lib copy; pin->pad->net verified on sampled parts (U25 vs TPS54360B DS, U17, Q7, D6, crystals, L); do not bulk-update"
|
||||||
|
ERC,166,footprint_link_issues,warning,The current configuration does not include the footprint library 'Connector_RJ45',800.1,90.17,J10,,,,,,real,P11/P12 schematic fp = Vertical (not in lib) while PCB + LCSC C5160226 are right-angle/Horizontal; J10 lib nickname Connector_RJ45 not configured. An Update-PCB would swap/flip these (DNP too)
|
||||||
|
DRC,1,silk_edge_clearance,warning,Silkscreen clipped by board edge,200.1917,140.3231,Segment on Edge.Cuts,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,2,lib_footprint_issues,warning,Footprint 'MountingHole_3.2mm' not found in library 'MountingHole',195.2,135.3,Footprint MH8,,,Local override,,,needs-fix-cosmetic,MountingHole library nickname not in fp-lib-table; board-only MH5-8 are fine for fab
|
||||||
|
DRC,3,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',116.7,97.0,Footprint C81,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,4,lib_footprint_mismatch,warning,Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD',83.75,53.45,Footprint C102,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,5,lib_footprint_mismatch,warning,Footprint 'JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical' does not match copy in library 'Connector_JST',196.0,110.5,Footprint P3,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,6,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',94.5,61.275,Footprint C92,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,7,lib_footprint_mismatch,warning,Footprint 'JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical' does not match copy in library 'Connector_JST',100.25,44.0,Footprint P6,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,8,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',101.5,57.5,Footprint C93,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,9,lib_footprint_mismatch,warning,Footprint 'LQFP-64_10x10mm_P0.5mm' does not match copy in library 'Package_QFP',120.7,67.425,Footprint U16,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,10,lib_footprint_mismatch,warning,Footprint 'LQFP-48_7x7mm_P0.5mm' does not match copy in library 'Package_QFP',95.1625,53.83,Footprint U11,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,11,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',86.675,50.5,Footprint R93,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,12,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',92.5,61.275,Footprint C98,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,13,lib_footprint_mismatch,warning,Footprint 'SOT-223-3_TabPin2' does not match copy in library 'Package_TO_SOT_SMD',92.5,80.0,Footprint U17,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,14,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',86.0,82.265,Footprint R85,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,15,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',116.3,58.25,Footprint C111,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,16,lib_footprint_mismatch,warning,Footprint 'Crystal_SMD_3215-2Pin_3.2x1.5mm' does not match copy in library 'Crystal',132.05,73.5,Footprint Y4,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,17,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',139.975,68.175,Footprint C113,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,18,lib_footprint_mismatch,warning,Footprint 'D_SOD-323' does not match copy in library 'Diode_SMD',73.15,69.0,Footprint D15,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,19,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',128.3,73.25,Footprint C110,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,20,lib_footprint_mismatch,warning,Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD',102.375,62.945,Footprint C91,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,21,lib_footprint_mismatch,warning,Footprint 'SolderJumper-2_P1.3mm_Open_TrianglePad1.0x1.5mm' does not match copy in library 'Jumper',138.4,127.5,Footprint JP5,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,22,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',106.17,68.25,Footprint R87,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,23,lib_footprint_mismatch,warning,"Footprint 'PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal' does not match copy in library 'Connector_Phoenix_MC'",135.48,131.5675,Footprint P11,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,24,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',133.55,70.75,Footprint C116,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,25,lib_footprint_mismatch,warning,Footprint 'Crystal_SMD_HC49-SD' does not match copy in library 'Crystal',136.475,62.925,Footprint Y3,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,26,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',117.7,124.5,Footprint C80,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,27,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',113.675,106.25,Footprint C86,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,28,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',130.275,61.7796,Footprint C112,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,29,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',86.675,48.5,Footprint R84,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,30,lib_footprint_mismatch,warning,Footprint 'D_SOD-323' does not match copy in library 'Diode_SMD',72.5,77.0,Footprint D16,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,31,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',86.675,54.5,Footprint R95,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,32,lib_footprint_mismatch,warning,Footprint 'Sensirion_DFN-4_1.5x1.5mm_P0.8mm_SHT4x_NoCentralPad' does not match copy in library 'Sensor_Humidity',122.375,77.3,Footprint U3,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,33,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',78.25,76.75,Footprint R86,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,34,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',83.5,57.5,Footprint R97,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,35,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',86.0,80.0,Footprint R88,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,36,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',116.7,90.475,Footprint C82,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,37,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',139.975,57.675,Footprint C114,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,38,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',114.2,115.25,Footprint R90,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,39,lib_footprint_mismatch,warning,Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD',83.75,48.95,Footprint C94,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,40,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',136.15,127.67,Footprint R82,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,41,lib_footprint_mismatch,warning,Footprint 'PinHeader_1x04_P2.54mm_Vertical' does not match copy in library 'Connector_PinHeader_2.54mm',72.45,135.75,Footprint H4,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,42,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',86.675,58.5,Footprint C97,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,43,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',126.375,76.85,Footprint R81,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,44,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',128.95,101.775,Footprint C89,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,45,lib_footprint_mismatch,warning,Footprint 'JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical' does not match copy in library 'Connector_JST',119.25,43.965,Footprint P9,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,46,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',130.05,70.75,Footprint C115,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,47,lib_footprint_issues,warning,Footprint 'MountingHole_3.2mm' not found in library 'MountingHole',65.2,45.3,Footprint MH5,,,Local override,,,needs-fix-cosmetic,MountingHole library nickname not in fp-lib-table; board-only MH5-8 are fine for fab
|
||||||
|
DRC,48,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',113.775,59.0,Footprint C105,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,49,lib_footprint_mismatch,warning,Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD',78.5,73.05,Footprint C101,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,50,lib_footprint_mismatch,warning,"Footprint 'TerminalBlock_Phoenix_MKDS-1,5-5_1x05_P5.00mm_Horizontal' does not match copy in library 'TerminalBlock_Phoen",167.5,135.0,Footprint P1,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,51,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',116.7,93.725,Footprint C83,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,52,lib_footprint_mismatch,warning,Footprint 'SOIC-8_3.9x4.9mm_P1.27mm' does not match copy in library 'Package_SO',122.025,84.9663,Footprint U14,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,53,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',126.75,83.8512,Footprint C84,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,54,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',113.675,108.25,Footprint C88,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,55,lib_footprint_issues,warning,Footprint 'MountingHole_3.2mm' not found in library 'MountingHole',195.2,45.3,Footprint MH7,,,Local override,,,needs-fix-cosmetic,MountingHole library nickname not in fp-lib-table; board-only MH5-8 are fine for fab
|
||||||
|
DRC,56,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',126.025,59.0,Footprint C106,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,57,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',116.7,87.0,Footprint R80,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,58,lib_footprint_mismatch,warning,Footprint 'LED_0603_1608Metric' does not match copy in library 'LED_SMD',132.6375,80.8171,Footprint D18,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,59,lib_footprint_mismatch,warning,Footprint 'LED_0603_1608Metric' does not match copy in library 'LED_SMD',132.5875,75.8171,Footprint D17,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,60,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',114.2,113.5,Footprint R89,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,61,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',112.45,102.975,Footprint C85,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,62,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',83.5,65.275,Footprint C95,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,63,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',114.2,117.0,Footprint R91,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,64,lib_footprint_mismatch,warning,Footprint 'SOIC-16W_7.5x10.3mm_P1.27mm' does not match copy in library 'Package_SO',122.2,118.0,Footprint U13,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,65,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',114.45,102.975,Footprint C87,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,66,lib_footprint_mismatch,warning,Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD',85.5,85.5,Footprint C117,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,67,lib_footprint_mismatch,warning,Footprint 'Crystal_SMD_HC49-SD' does not match copy in library 'Crystal',113.15,91.9013,Footprint Y2,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,68,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',113.0,72.5,Footprint C107,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,69,lib_footprint_mismatch,warning,Footprint 'Crystal_SMD_HC49-SD' does not match copy in library 'Crystal',91.5,65.5,Footprint Y1,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,70,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',104.5,62.725,Footprint C96,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,71,lib_footprint_issues,warning,Footprint 'MountingHole_3.2mm' not found in library 'MountingHole',65.2,135.3,Footprint MH6,,,Local override,,,needs-fix-cosmetic,MountingHole library nickname not in fp-lib-table; board-only MH5-8 are fine for fab
|
||||||
|
DRC,72,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',83.5,61.325,Footprint R96,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,73,lib_footprint_mismatch,warning,Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD',88.0,85.5,Footprint C118,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,74,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',86.675,56.5,Footprint R94,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,75,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',130.275,67.25,Footprint C104,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,76,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',86.675,52.5,Footprint R92,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,77,lib_footprint_mismatch,warning,Footprint 'C_0805_2012Metric' does not match copy in library 'Capacitor_SMD',100.0,62.945,Footprint C90,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,78,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',130.275,65.25,Footprint C109,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,79,lib_footprint_mismatch,warning,Footprint 'D_SOD-323' does not match copy in library 'Diode_SMD',72.5,72.5,Footprint D14,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,80,lib_footprint_mismatch,warning,Footprint 'TSSOP-28_4.4x9.7mm_P0.65mm' does not match copy in library 'Package_SO',122.3875,93.9762,Footprint U10,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,81,lib_footprint_mismatch,warning,Footprint 'SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm' does not match copy in library 'Package_SO',84.0,76.35,Footprint U12,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,82,lib_footprint_mismatch,warning,Footprint 'JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical' does not match copy in library 'Connector_JST',115.7,136.5,Footprint P10,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,83,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',75.825,77.5,Footprint C99,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,84,lib_footprint_mismatch,warning,"Footprint 'PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal' does not match copy in library 'Connector_Phoenix_MC'",122.155,131.5675,Footprint P12,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,85,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',84.3,72.75,Footprint C100,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,86,lib_footprint_mismatch,warning,Footprint 'C_0603_1608Metric' does not match copy in library 'Capacitor_SMD',128.3,76.45,Footprint C108,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,87,lib_footprint_mismatch,warning,Footprint 'R_0603_1608Metric' does not match copy in library 'Resistor_SMD',86.675,60.5,Footprint R83,,,Local override,,,pre-existing-benign,"board footprint differs from KiCad 10 library copy (library revisions); geometry verified by DRC/IPC-356; do NOT ""update footprints from library"" (would swap P11/P12, reset pads)"
|
||||||
|
DRC,88,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.8000 mm),176.6,45.3,"Track [/SYS5V] on F.Cu, length 2.8850 mm",/SYS5V,0.8,T15 power width: PWR_HI >= 1.0 mm,2.89,F.Cu,pre-existing-benign,0.8 mm F.Cu capacity 2.03 A >= est. 0.6 A (U12+U17+K1+F9P rail: ~0.1+0.2+0.03+0.15 A); T15 rule over-strict for this net
|
||||||
|
DRC,89,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),88.215,75.715,"Track [/SYS5V] on F.Cu, length 0.0495 mm",/SYS5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.05,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.6 A (U12+U17+K1+F9P rail: ~0.1+0.2+0.03+0.15 A); T15 rule over-strict for this net
|
||||||
|
DRC,90,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),176.4,45.5,"Track [/SYS5V] on F.Cu, length 0.2828 mm",/SYS5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.28,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.6 A (U12+U17+K1+F9P rail: ~0.1+0.2+0.03+0.15 A); T15 rule over-strict for this net
|
||||||
|
DRC,91,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.8000 mm),175.5,46.4,"Track [/SYS5V] on F.Cu, length 1.2728 mm",/SYS5V,0.8,T15 power width: PWR_HI >= 1.0 mm,1.27,F.Cu,pre-existing-benign,0.8 mm F.Cu capacity 2.03 A >= est. 0.6 A (U12+U17+K1+F9P rail: ~0.1+0.2+0.03+0.15 A); T15 rule over-strict for this net
|
||||||
|
DRC,92,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),181.0825,46.8975,"Track [/SYS5V] on F.Cu, length 0.2600 mm",/SYS5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.26,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.6 A (U12+U17+K1+F9P rail: ~0.1+0.2+0.03+0.15 A); T15 rule over-strict for this net
|
||||||
|
DRC,93,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.8000 mm),179.485,45.3,"Track [/SYS5V] on F.Cu, length 2.2592 mm",/SYS5V,0.8,T15 power width: PWR_HI >= 1.0 mm,2.89,F.Cu,pre-existing-benign,0.8 mm F.Cu capacity 2.03 A >= est. 0.6 A (U12+U17+K1+F9P rail: ~0.1+0.2+0.03+0.15 A); T15 rule over-strict for this net
|
||||||
|
DRC,94,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),136.25,98.765,"Track [/SW_FAN] on F.Cu, length 1.0150 mm",/SW_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,1.02,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan buck switch node); T15 rule over-strict for this net
|
||||||
|
DRC,95,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),144.75,93.25,"Track [/SW_FAN] on F.Cu, length 3.1820 mm",/SW_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,3.18,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan buck switch node); T15 rule over-strict for this net
|
||||||
|
DRC,96,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),138.12,99.92,"Track [/SW_FAN] on F.Cu, length 2.3052 mm",/SW_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,2.31,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan buck switch node); T15 rule over-strict for this net
|
||||||
|
DRC,97,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),137.405,99.92,"Track [/SW_FAN] on F.Cu, length 1.6334 mm",/SW_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,1.63,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan buck switch node); T15 rule over-strict for this net
|
||||||
|
DRC,98,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),136.25,97.75,"Track [/SW_FAN] on F.Cu, length 6.3640 mm",/SW_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,1.02,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan buck switch node); T15 rule over-strict for this net
|
||||||
|
DRC,99,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),137.405,99.92,"Track [/SW_FAN] on F.Cu, length 0.7150 mm",/SW_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,1.63,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan buck switch node); T15 rule over-strict for this net
|
||||||
|
DRC,100,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),147.0,95.5,"Track [/SW_FAN] on F.Cu, length 1.7450 mm",/SW_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,3.18,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan buck switch node); T15 rule over-strict for this net
|
||||||
|
DRC,101,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),140.75,93.25,"Track [/SW_FAN] on F.Cu, length 4.0000 mm",/SW_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,6.36,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan buck switch node); T15 rule over-strict for this net
|
||||||
|
DRC,102,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),93.2375,54.58,"Track [/3V3_ETH] on F.Cu, length 0.0177 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,2.14,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,103,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),79.25,56.335,"Track [/3V3_ETH] on F.Cu, length 1.8243 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,1.82,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,104,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),83.5,56.675,"Track [/3V3_ETH] on F.Cu, length 1.4142 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,1.41,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,105,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),94.4125,60.4125,"Track [/3V3_ETH] on F.Cu, length 2.4200 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,2.42,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,106,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),92.5,60.5,"Track [/3V3_ETH] on F.Cu, length 2.0000 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,2.0,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,107,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),84.5,59.5,"Track [/3V3_ETH] on F.Cu, length 1.4142 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,1.41,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,108,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),99.325,55.08,"Track [/3V3_ETH] on F.Cu, length 2.7699 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,2.77,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,109,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),84.5,57.675,"Track [/3V3_ETH] on F.Cu, length 1.8250 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,1.41,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,110,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),85.15,54.8086,"Track [/3V3_ETH] on F.Cu, length 1.6086 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,1.61,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,111,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),96.4125,57.2226,"Track [/3V3_ETH] on F.Cu, length 0.7699 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,0.77,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,112,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),94.4125,57.2226,"Track [/3V3_ETH] on F.Cu, length 0.3784 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,0.77,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,113,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),94.5,60.5,"Track [/3V3_ETH] on F.Cu, length 1.2500 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,2.0,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,114,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),83.75,48.0,"Track [/3V3_ETH] on F.Cu, length 1.6000 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,1.6,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,115,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),93.4125,57.9925,"Track [/3V3_ETH] on F.Cu, length 0.7699 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,0.77,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,116,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),83.75,52.5,"Track [/3V3_ETH] on F.Cu, length 2.1000 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,2.1,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,117,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),91.0,52.58,"Track [/3V3_ETH] on F.Cu, length 1.5346 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,1.53,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,118,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),84.9378,55.0208,"Track [/3V3_ETH] on F.Cu, length 0.3001 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,0.22,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,119,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),85.15,53.2,"Track [/3V3_ETH] on F.Cu, length 0.9899 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,1.61,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,120,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),96.1449,56.955,"Track [/3V3_ETH] on F.Cu, length 0.3784 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,1.46,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,121,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),100.305,55.08,"Track [/3V3_ETH] on F.Cu, length 0.9800 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,0.98,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,122,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),101.5,56.725,"Track [/3V3_ETH] on F.Cu, length 0.4500 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,0.45,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,123,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),101.5,56.275,"Track [/3V3_ETH] on F.Cu, length 1.6900 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,0.45,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,124,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),85.85,48.5,"Track [/3V3_ETH] on F.Cu, length 4.0000 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,4.0,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,125,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),96.5551,55.08,"Track [/3V3_ETH] on F.Cu, length 2.6517 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,2.77,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,126,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),88.5723,52.58,"Track [/3V3_ETH] on F.Cu, length 0.9475 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,2.43,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,127,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),94.5,60.5,"Track [/3V3_ETH] on F.Cu, length 0.1237 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,2.0,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,128,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),83.5,56.675,"Track [/3V3_ETH] on F.Cu, length 2.0334 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,1.41,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,129,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),82.55,57.625,"Track [/3V3_ETH] on F.Cu, length 1.3435 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,1.34,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,130,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),79.4,44.0,"Track [/3V3_ETH] on F.Cu, length 0.2121 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,0.21,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,131,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),94.4125,57.9925,"Track [/3V3_ETH] on F.Cu, length 0.7699 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,0.77,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,132,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),85.35,48.0,"Track [/3V3_ETH] on F.Cu, length 0.7071 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,1.6,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,133,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),86.6,53.25,"Track [/3V3_ETH] on F.Cu, length 1.0607 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,1.06,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,134,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),93.6801,56.955,"Track [/3V3_ETH] on F.Cu, length 1.0000 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,1.0,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,135,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),93.4125,57.2226,"Track [/3V3_ETH] on F.Cu, length 0.3784 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,0.77,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,136,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),91.0,54.58,"Track [/3V3_ETH] on F.Cu, length 2.2375 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,2.24,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,137,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),84.9378,55.2372,"Track [/3V3_ETH] on F.Cu, length 0.2164 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,2.03,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,138,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),79.25,44.15,"Track [/3V3_ETH] on F.Cu, length 12.1850 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,0.21,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,139,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),80.54,57.625,"Track [/3V3_ETH] on F.Cu, length 2.0100 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,1.82,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,140,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),93.25,54.5675,"Track [/3V3_ETH] on F.Cu, length 2.1390 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,0.02,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,141,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),93.25,53.2954,"Track [/3V3_ETH] on F.Cu, length 1.2721 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,1.01,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,142,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),92.5346,52.58,"Track [/3V3_ETH] on F.Cu, length 1.0117 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,1.01,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,143,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),91.0,52.58,"Track [/3V3_ETH] on F.Cu, length 2.4277 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,1.53,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,144,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),87.9023,53.25,"Track [/3V3_ETH] on F.Cu, length 1.3023 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,0.95,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,145,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),94.6801,56.955,"Track [/3V3_ETH] on F.Cu, length 1.4648 mm",/3V3_ETH,0.3,T15 power width: PWR_MID >= 0.6 mm,1.46,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,146,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.2500 mm),91.7375,56.08,"Track [/3V3_ETH] on F.Cu, length 0.7375 mm",/3V3_ETH,0.25,T15 power width: PWR_MID >= 0.6 mm,2.14,F.Cu,pre-existing-benign,0.25 mm F.Cu capacity 0.88 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,147,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),98.425,61.43,"Track [/3V3_ETH] on In1.Cu, length 12.1198 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,12.12,In1.Cu,pre-existing-benign,0.5 mm In1.Cu capacity 0.72 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,148,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),95.75,60.5,"Track [/3V3_ETH] on In1.Cu, length 3.7830 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,3.78,In1.Cu,pre-existing-benign,0.5 mm In1.Cu capacity 0.72 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,149,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),98.425,57.825,"Track [/3V3_ETH] on In1.Cu, length 3.6050 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,3.78,In1.Cu,pre-existing-benign,0.5 mm In1.Cu capacity 0.72 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,150,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),85.017,55.1,"Track [/3V3_ETH] on In1.Cu, length 2.2766 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,0.11,In1.Cu,pre-existing-benign,0.5 mm In1.Cu capacity 0.72 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,151,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),87.2936,55.1,"Track [/3V3_ETH] on In1.Cu, length 3.6770 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,2.28,In1.Cu,pre-existing-benign,0.5 mm In1.Cu capacity 0.72 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,152,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),94.75,52.5,"Track [/3V3_ETH] on In1.Cu, length 5.1972 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,5.2,In1.Cu,pre-existing-benign,0.5 mm In1.Cu capacity 0.72 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,153,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),98.425,56.175,"Track [/3V3_ETH] on In1.Cu, length 1.6500 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,5.2,In1.Cu,pre-existing-benign,0.5 mm In1.Cu capacity 0.72 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,154,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),84.9378,55.0208,"Track [/3V3_ETH] on In1.Cu, length 0.1120 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,0.11,In1.Cu,pre-existing-benign,0.5 mm In1.Cu capacity 0.72 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,155,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),89.8936,52.5,"Track [/3V3_ETH] on In1.Cu, length 4.8564 mm",/3V3_ETH,0.5,T15 power width: PWR_MID >= 0.6 mm,3.68,In1.Cu,pre-existing-benign,0.5 mm In1.Cu capacity 0.72 A >= est. 0.15 A (W5500 132 mA typ at 100M + RJ45 LEDs); T15 rule over-strict for this net
|
||||||
|
DRC,156,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.2500 mm),193.4,103.6937,"Track [/BAT_PLUS] on F.Cu, length 4.9020 mm",/BAT_PLUS,0.25,T15 power width: PWR_HI >= 1.0 mm,4.9,F.Cu,real,0.25 mm F.Cu carries ~3.5 A vs IPC-2221 10C capacity 0.88 A (pack current: backup draw 5V*2.5A/(3.3V*0.9)=4.2 A peak; charge 2.42 A (R50 825R))
|
||||||
|
DRC,157,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),139.0,55.9,"Track [/BAT_PLUS] on F.Cu, length 0.2828 mm",/BAT_PLUS,0.5,T15 power width: PWR_HI >= 1.0 mm,0.28,F.Cu,real,0.5 mm F.Cu carries ~3.5 A vs IPC-2221 10C capacity 1.45 A (pack current: backup draw 5V*2.5A/(3.3V*0.9)=4.2 A peak; charge 2.42 A (R50 825R))
|
||||||
|
DRC,158,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.2500 mm),189.9338,107.16,"Track [/BAT_PLUS] on F.Cu, length 0.4838 mm",/BAT_PLUS,0.25,T15 power width: PWR_HI >= 1.0 mm,4.9,F.Cu,real,0.25 mm F.Cu carries ~3.5 A vs IPC-2221 10C capacity 0.88 A (pack current: backup draw 5V*2.5A/(3.3V*0.9)=4.2 A peak; charge 2.42 A (R50 825R))
|
||||||
|
DRC,159,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),193.4,93.2,"Track [/BAT_PLUS] on F.Cu, length 10.4938 mm",/BAT_PLUS,0.5,T15 power width: PWR_HI >= 1.0 mm,10.49,F.Cu,real,0.5 mm F.Cu carries ~3.5 A vs IPC-2221 10C capacity 1.45 A (pack current: backup draw 5V*2.5A/(3.3V*0.9)=4.2 A peak; charge 2.42 A (R50 825R))
|
||||||
|
DRC,160,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.2500 mm),154.25,59.15,"Track [/VBAT_MODEM] on F.Cu, length 0.3536 mm",/VBAT_MODEM,0.25,T15 power width: modem + vehicle PSU paths >= 0.8 mm,0.35,F.Cu,real,"0.25 mm F.Cu carries ~2.0 A vs IPC-2221 10C capacity 0.88 A (A7670SA VBAT burst up to 2 A (GSM TX), LTE ~1 A)"
|
||||||
|
DRC,161,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.2500 mm),154.25,59.75,"Track [/VBAT_MODEM] on F.Cu, length 0.6000 mm",/VBAT_MODEM,0.25,T15 power width: modem + vehicle PSU paths >= 0.8 mm,0.6,F.Cu,real,"0.25 mm F.Cu carries ~2.0 A vs IPC-2221 10C capacity 0.88 A (A7670SA VBAT burst up to 2 A (GSM TX), LTE ~1 A)"
|
||||||
|
DRC,162,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),179.75,57.0,"Track [/VBAT_MODEM] on F.Cu, length 0.7071 mm",/VBAT_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,0.71,F.Cu,real,"0.5 mm F.Cu carries ~2.0 A vs IPC-2221 10C capacity 1.45 A (A7670SA VBAT burst up to 2 A (GSM TX), LTE ~1 A)"
|
||||||
|
DRC,163,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),179.25,57.5,"Track [/VBAT_MODEM] on F.Cu, length 2.5000 mm",/VBAT_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,0.71,F.Cu,real,"0.5 mm F.Cu carries ~2.0 A vs IPC-2221 10C capacity 1.45 A (A7670SA VBAT burst up to 2 A (GSM TX), LTE ~1 A)"
|
||||||
|
DRC,164,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),179.25,60.0,"Track [/VBAT_MODEM] on F.Cu, length 2.0000 mm",/VBAT_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,2.5,F.Cu,real,"0.5 mm F.Cu carries ~2.0 A vs IPC-2221 10C capacity 1.45 A (A7670SA VBAT burst up to 2 A (GSM TX), LTE ~1 A)"
|
||||||
|
DRC,165,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),154.0,58.9,"Track [/VBAT_MODEM] on In1.Cu, length 0.6718 mm",/VBAT_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,0.67,In1.Cu,real,"0.5 mm In1.Cu carries ~2.0 A vs IPC-2221 10C capacity 0.72 A (A7670SA VBAT burst up to 2 A (GSM TX), LTE ~1 A)"
|
||||||
|
DRC,166,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),154.475,58.425,"Track [/VBAT_MODEM] on In1.Cu, length 5.6000 mm",/VBAT_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,0.67,In1.Cu,real,"0.5 mm In1.Cu carries ~2.0 A vs IPC-2221 10C capacity 0.72 A (A7670SA VBAT burst up to 2 A (GSM TX), LTE ~1 A)"
|
||||||
|
DRC,167,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),147.75,103.75,"Track [/5V_FAN] on F.Cu, length 0.9899 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,0.99,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,168,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),160.25,104.5,"Track [/5V_FAN] on F.Cu, length 2.0500 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,2.05,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,169,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),174.275,100.975,"Track [/5V_FAN] on F.Cu, length 3.0759 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,3.08,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,170,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),144.3,104.45,"Track [/5V_FAN] on F.Cu, length 1.1314 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,1.13,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,171,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),147.05,104.45,"Track [/5V_FAN] on F.Cu, length 2.7500 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,0.99,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,172,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),176.45,98.8,"Track [/5V_FAN] on F.Cu, length 1.3000 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,3.08,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,173,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),174.25,98.55,"Track [/5V_FAN] on B.Cu, length 38.0500 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,38.05,B.Cu,pre-existing-benign,0.5 mm B.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,174,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),174.25,60.5,"Track [/5V_FAN] on B.Cu, length 25.7387 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,38.05,B.Cu,pre-existing-benign,0.5 mm B.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,175,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),156.05,42.3,"Track [/5V_FAN] on B.Cu, length 2.6500 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,25.74,B.Cu,pre-existing-benign,0.5 mm B.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,176,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),174.275,100.975,"Track [/5V_FAN] on B.Cu, length 2.4000 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,3.08,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,177,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),153.4,42.3,"Track [/5V_FAN] on B.Cu, length 2.3335 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,2.65,B.Cu,pre-existing-benign,0.5 mm B.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,178,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),174.275,98.575,"Track [/5V_FAN] on B.Cu, length 0.0354 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,2.4,B.Cu,pre-existing-benign,0.5 mm B.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,179,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),174.275,100.975,"Track [/5V_FAN] on In1.Cu, length 4.9851 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,3.08,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,180,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),170.75,104.5,"Track [/5V_FAN] on In1.Cu, length 12.5500 mm",/5V_FAN,0.5,T15 power width: PWR_MID >= 0.6 mm,4.99,In1.Cu,pre-existing-benign,0.5 mm In1.Cu capacity 0.72 A >= est. 0.3 A (2-pin 5 V fan (assumed <=0.3 A)); T15 rule over-strict for this net
|
||||||
|
DRC,181,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),161.6875,98.5,"Track [/FAN_RET] on F.Cu, length 0.8125 mm",/FAN_RET,0.5,T15 power width: PWR_MID >= 0.6 mm,0.81,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan low-side return); T15 rule over-strict for this net
|
||||||
|
DRC,182,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),161.6875,99.3125,"Track [/FAN_RET] on F.Cu, length 1.6794 mm",/FAN_RET,0.5,T15 power width: PWR_MID >= 0.6 mm,0.81,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan low-side return); T15 rule over-strict for this net
|
||||||
|
DRC,183,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),161.6875,98.5,"Track [/FAN_RET] on F.Cu, length 1.5000 mm",/FAN_RET,0.5,T15 power width: PWR_MID >= 0.6 mm,0.81,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan low-side return); T15 rule over-strict for this net
|
||||||
|
DRC,184,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),164.0,53.7,"Track [/FAN_RET] on B.Cu, length 13.7886 mm",/FAN_RET,0.5,T15 power width: PWR_MID >= 0.6 mm,13.79,B.Cu,pre-existing-benign,0.5 mm B.Cu capacity 1.45 A >= est. 0.3 A (fan low-side return); T15 rule over-strict for this net
|
||||||
|
DRC,185,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),164.0,93.1,"Track [/FAN_RET] on B.Cu, length 39.4000 mm",/FAN_RET,0.5,T15 power width: PWR_MID >= 0.6 mm,39.4,B.Cu,pre-existing-benign,0.5 mm B.Cu capacity 1.45 A >= est. 0.3 A (fan low-side return); T15 rule over-strict for this net
|
||||||
|
DRC,186,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),161.6875,98.5,"Track [/FAN_RET] on B.Cu, length 3.0875 mm",/FAN_RET,0.5,T15 power width: PWR_MID >= 0.6 mm,0.81,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.3 A (fan low-side return); T15 rule over-strict for this net
|
||||||
|
DRC,187,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),161.6875,95.4125,"Track [/FAN_RET] on B.Cu, length 3.2704 mm",/FAN_RET,0.5,T15 power width: PWR_MID >= 0.6 mm,3.09,B.Cu,pre-existing-benign,0.5 mm B.Cu capacity 1.45 A >= est. 0.3 A (fan low-side return); T15 rule over-strict for this net
|
||||||
|
DRC,188,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.2500 mm),187.0,111.0,"Track [/VEH5V] on F.Cu, length 1.3900 mm",/VEH5V,0.25,T15 power width: PWR_HI >= 1.0 mm,1.39,F.Cu,pre-existing-benign,1.39 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,189,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),176.8,116.5,"Track [/VEH5V] on F.Cu, length 0.2000 mm",/VEH5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.2,F.Cu,real,"0.5 mm F.Cu carries ~3.0 A vs IPC-2221 10C capacity 1.45 A (U25 5 V output, 3 A rated; feeds LTC4040 input (<=2.5 A via RS1) + modem path)"
|
||||||
|
DRC,190,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),169.27,123.65,"Track [/VEH5V] on F.Cu, length 0.1838 mm",/VEH5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.18,F.Cu,real,"0.5 mm F.Cu carries ~3.0 A vs IPC-2221 10C capacity 1.45 A (U25 5 V output, 3 A rated; feeds LTC4040 input (<=2.5 A via RS1) + modem path)"
|
||||||
|
DRC,191,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),186.0,105.0375,"Track [/VEH5V] on F.Cu, length 0.1688 mm",/VEH5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.17,F.Cu,pre-existing-benign,0.17 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,192,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),183.5,113.45,"Track [/VEH5V] on F.Cu, length 1.0500 mm",/VEH5V,0.5,T15 power width: PWR_HI >= 1.0 mm,1.05,F.Cu,real,"0.5 mm F.Cu carries ~3.0 A vs IPC-2221 10C capacity 1.45 A (U25 5 V output, 3 A rated; feeds LTC4040 input (<=2.5 A via RS1) + modem path)"
|
||||||
|
DRC,193,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.3000 mm),186.0,105.8,"Track [/VEH5V] on F.Cu, length 0.7625 mm",/VEH5V,0.3,T15 power width: PWR_HI >= 1.0 mm,0.76,F.Cu,pre-existing-benign,0.76 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,194,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),179.65,113.45,"Track [/VEH5V] on F.Cu, length 0.3500 mm",/VEH5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.35,F.Cu,real,"0.5 mm F.Cu carries ~3.0 A vs IPC-2221 10C capacity 1.45 A (U25 5 V output, 3 A rated; feeds LTC4040 input (<=2.5 A via RS1) + modem path)"
|
||||||
|
DRC,195,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.2500 mm),185.475,112.525,"Track [/VEH5V] on F.Cu, length 2.1567 mm",/VEH5V,0.25,T15 power width: PWR_HI >= 1.0 mm,2.16,F.Cu,real,"0.25 mm F.Cu carries ~3.0 A vs IPC-2221 10C capacity 0.88 A (U25 5 V output, 3 A rated; feeds LTC4040 input (<=2.5 A via RS1) + modem path)"
|
||||||
|
DRC,196,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.8000 mm),176.8,116.3,"Track [/VEH5V] on F.Cu, length 4.0305 mm",/VEH5V,0.8,T15 power width: PWR_HI >= 1.0 mm,4.03,F.Cu,real,"0.8 mm F.Cu carries ~3.0 A vs IPC-2221 10C capacity 2.03 A (U25 5 V output, 3 A rated; feeds LTC4040 input (<=2.5 A via RS1) + modem path)"
|
||||||
|
DRC,197,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),186.0,104.8688,"Track [/VEH5V] on F.Cu, length 5.0647 mm",/VEH5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.17,F.Cu,pre-existing-benign,0.17 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,198,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),182.4187,101.2875,"Track [/VEH5V] on F.Cu, length 0.1688 mm",/VEH5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.17,F.Cu,real,"0.5 mm F.Cu carries ~3.0 A vs IPC-2221 10C capacity 1.45 A (U25 5 V output, 3 A rated; feeds LTC4040 input (<=2.5 A via RS1) + modem path)"
|
||||||
|
DRC,199,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),184.55,113.45,"Track [/VEH5V] on F.Cu, length 1.3081 mm",/VEH5V,0.5,T15 power width: PWR_HI >= 1.0 mm,1.05,F.Cu,real,"0.5 mm F.Cu carries ~3.0 A vs IPC-2221 10C capacity 1.45 A (U25 5 V output, 3 A rated; feeds LTC4040 input (<=2.5 A via RS1) + modem path)"
|
||||||
|
DRC,200,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.3000 mm),184.575,114.525,"Track [/VEH5V] on F.Cu, length 1.5203 mm",/VEH5V,0.3,T15 power width: PWR_HI >= 1.0 mm,1.52,F.Cu,real,"0.3 mm F.Cu carries ~3.0 A vs IPC-2221 10C capacity 1.00 A (U25 5 V output, 3 A rated; feeds LTC4040 input (<=2.5 A via RS1) + modem path)"
|
||||||
|
DRC,201,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),181.1438,111.0938,"Track [/VEH5V] on In1.Cu, length 8.7000 mm",/VEH5V,0.5,T15 power width: PWR_HI >= 1.0 mm,4.85,In1.Cu,real,"0.5 mm In1.Cu carries ~3.0 A vs IPC-2221 10C capacity 0.72 A (U25 5 V output, 3 A rated; feeds LTC4040 input (<=2.5 A via RS1) + modem path)"
|
||||||
|
DRC,202,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),184.575,114.525,"Track [/VEH5V] on In1.Cu, length 4.8525 mm",/VEH5V,0.5,T15 power width: PWR_HI >= 1.0 mm,4.85,In1.Cu,real,"0.5 mm In1.Cu carries ~3.0 A vs IPC-2221 10C capacity 0.72 A (U25 5 V output, 3 A rated; feeds LTC4040 input (<=2.5 A via RS1) + modem path)"
|
||||||
|
DRC,203,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),179.2,108.6,"Track [/MAIN5V] on F.Cu, length 0.0707 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.07,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,204,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),174.25,98.255,"Track [/MAIN5V] on F.Cu, length 0.7550 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.75,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,205,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.3000 mm),188.5,105.71,"Track [/MAIN5V] on F.Cu, length 0.3000 mm",/MAIN5V,0.3,T15 power width: PWR_HI >= 1.0 mm,0.3,F.Cu,pre-existing-benign,0.30 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,206,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.3000 mm),188.8,105.71,"Track [/MAIN5V] on F.Cu, length 0.9192 mm",/MAIN5V,0.3,T15 power width: PWR_HI >= 1.0 mm,0.3,F.Cu,pre-existing-benign,0.30 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,207,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),178.3,127.6,"Track [/MAIN5V] on F.Cu, length 0.1414 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.14,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,208,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),187.4,101.265,"Track [/MAIN5V] on F.Cu, length 0.2970 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.3,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,209,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),187.19,97.7138,"Track [/MAIN5V] on F.Cu, length 2.9965 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,3.0,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,210,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),169.0,103.25,"Track [/MAIN5V] on F.Cu, length 0.2550 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.25,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,211,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),169.255,103.25,"Track [/MAIN5V] on F.Cu, length 7.0640 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.25,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,212,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),179.15,108.55,"Track [/MAIN5V] on F.Cu, length 1.0500 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.07,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,213,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.3000 mm),189.45,106.36,"Track [/MAIN5V] on F.Cu, length 0.3000 mm",/MAIN5V,0.3,T15 power width: PWR_HI >= 1.0 mm,0.92,F.Cu,real,0.3 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.00 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,214,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),190.75,102.25,"Track [/MAIN5V] on F.Cu, length 1.7678 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,1.77,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,215,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),190.75,105.36,"Track [/MAIN5V] on F.Cu, length 1.8031 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,1.8,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,216,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),169.0,99.63,"Track [/MAIN5V] on F.Cu, length 0.3182 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.32,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,217,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),169.0,103.25,"Track [/MAIN5V] on F.Cu, length 3.6200 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.25,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,218,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),187.19,101.055,"Track [/MAIN5V] on F.Cu, length 3.3412 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.3,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,219,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),179.2,109.7,"Track [/MAIN5V] on F.Cu, length 1.1000 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,1.1,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,220,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),189.475,106.635,"Track [/MAIN5V] on F.Cu, length 0.0250 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,1.8,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,221,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),190.75,105.36,"Track [/MAIN5V] on F.Cu, length 3.1100 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,1.8,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,222,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),176.435,127.6,"Track [/MAIN5V] on F.Cu, length 1.8650 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,1.87,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,223,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),178.4,127.5,"Track [/MAIN5V] on In1.Cu, length 0.2828 mm",/MAIN5V,0.5,T15 power width: PWR_HI >= 1.0 mm,0.14,F.Cu,real,0.5 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.45 A (LTC4040 output: whole 5 V system in backup (boost limit ~2.5 A))
|
||||||
|
DRC,224,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),175.63,116.17,"Track [/VIN_PROT] on F.Cu, length 1.7300 mm",/VIN_PROT,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,1.73,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.8 A (U25 input at 24 V: 5 V*3 A/0.9/24 V = 0.7 A (1.1 A at 16 V)); T15 rule over-strict for this net
|
||||||
|
DRC,225,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),175.63,117.9,"Track [/VIN_PROT] on F.Cu, length 0.2828 mm",/VIN_PROT,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,1.73,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.8 A (U25 input at 24 V: 5 V*3 A/0.9/24 V = 0.7 A (1.1 A at 16 V)); T15 rule over-strict for this net
|
||||||
|
DRC,226,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),176.2,113.1,"Track [/VIN_PROT] on F.Cu, length 2.8284 mm",/VIN_PROT,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,2.83,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.8 A (U25 input at 24 V: 5 V*3 A/0.9/24 V = 0.7 A (1.1 A at 16 V)); T15 rule over-strict for this net
|
||||||
|
DRC,227,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),174.2,115.1,"Track [/VIN_PROT] on F.Cu, length 5.2500 mm",/VIN_PROT,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,2.83,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.8 A (U25 input at 24 V: 5 V*3 A/0.9/24 V = 0.7 A (1.1 A at 16 V)); T15 rule over-strict for this net
|
||||||
|
DRC,228,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),168.95,115.1,"Track [/VIN_PROT] on F.Cu, length 1.6263 mm",/VIN_PROT,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,5.25,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.8 A (U25 input at 24 V: 5 V*3 A/0.9/24 V = 0.7 A (1.1 A at 16 V)); T15 rule over-strict for this net
|
||||||
|
DRC,229,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),192.8125,60.1125,"Track [/SW_IN] on F.Cu, length 1.2291 mm",/SW_IN,0.3,T15 power width: PWR_MID >= 0.6 mm,1.23,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.2 A (F1 output -> Q1 (F9P rail)); T15 rule over-strict for this net
|
||||||
|
DRC,230,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),190.65,53.75,"Track [/SW_IN] on F.Cu, length 0.2121 mm",/SW_IN,0.5,T15 power width: PWR_MID >= 0.6 mm,0.21,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.2 A (F1 output -> Q1 (F9P rail)); T15 rule over-strict for this net
|
||||||
|
DRC,231,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),195.4125,61.6875,"Track [/SW_IN] on F.Cu, length 1.3081 mm",/SW_IN,0.5,T15 power width: PWR_MID >= 0.6 mm,1.31,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.2 A (F1 output -> Q1 (F9P rail)); T15 rule over-strict for this net
|
||||||
|
DRC,232,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),195.4,61.7,"Track [/SW_IN] on F.Cu, length 0.0177 mm",/SW_IN,0.3,T15 power width: PWR_MID >= 0.6 mm,0.02,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.2 A (F1 output -> Q1 (F9P rail)); T15 rule over-strict for this net
|
||||||
|
DRC,233,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),192.8125,61.3416,"Track [/SW_IN] on F.Cu, length 0.5069 mm",/SW_IN,0.3,T15 power width: PWR_MID >= 0.6 mm,0.51,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.2 A (F1 output -> Q1 (F9P rail)); T15 rule over-strict for this net
|
||||||
|
DRC,234,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),191.4,58.7,"Track [/SW_IN] on F.Cu, length 1.9976 mm",/SW_IN,0.5,T15 power width: PWR_MID >= 0.6 mm,2.0,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.2 A (F1 output -> Q1 (F9P rail)); T15 rule over-strict for this net
|
||||||
|
DRC,235,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),193.1709,61.7,"Track [/SW_IN] on F.Cu, length 2.2291 mm",/SW_IN,0.5,T15 power width: PWR_MID >= 0.6 mm,2.23,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.2 A (F1 output -> Q1 (F9P rail)); T15 rule over-strict for this net
|
||||||
|
DRC,236,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),84.125,121.9313,"Track [/SW_5V] on F.Cu, length 1.3188 mm",/SW_5V,0.5,T15 power width: PWR_MID >= 0.6 mm,1.32,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.2 A (F9P rail through Q1: ZED-F9P ~70-100 mA + active antenna 20-30 mA); T15 rule over-strict for this net
|
||||||
|
DRC,237,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),198.2125,59.8125,"Track [/SW_5V] on F.Cu, length 0.8309 mm",/SW_5V,0.5,T15 power width: PWR_MID >= 0.6 mm,0.83,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.2 A (F9P rail through Q1: ZED-F9P ~70-100 mA + active antenna 20-30 mA); T15 rule over-strict for this net
|
||||||
|
DRC,238,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),84.125,123.25,"Track [/SW_5V] on F.Cu, length 1.3562 mm",/SW_5V,0.5,T15 power width: PWR_MID >= 0.6 mm,1.32,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.2 A (F9P rail through Q1: ZED-F9P ~70-100 mA + active antenna 20-30 mA); T15 rule over-strict for this net
|
||||||
|
DRC,239,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),88.35,121.8812,"Track [/SW_5V] on F.Cu, length 2.0000 mm",/SW_5V,0.5,T15 power width: PWR_MID >= 0.6 mm,2.0,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.2 A (F9P rail through Q1: ZED-F9P ~70-100 mA + active antenna 20-30 mA); T15 rule over-strict for this net
|
||||||
|
DRC,240,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),82.5406,126.2406,"Track [/SW_5V] on F.Cu, length 3.5187 mm",/SW_5V,0.3,T15 power width: PWR_MID >= 0.6 mm,3.52,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.2 A (F9P rail through Q1: ZED-F9P ~70-100 mA + active antenna 20-30 mA); T15 rule over-strict for this net
|
||||||
|
DRC,241,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),88.35,123.95,"Track [/SW_5V] on F.Cu, length 2.0688 mm",/SW_5V,0.3,T15 power width: PWR_MID >= 0.6 mm,2.07,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.2 A (F9P rail through Q1: ZED-F9P ~70-100 mA + active antenna 20-30 mA); T15 rule over-strict for this net
|
||||||
|
DRC,242,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),198.8,60.4,"Track [/SW_5V] on F.Cu, length 0.5000 mm",/SW_5V,0.5,T15 power width: PWR_MID >= 0.6 mm,0.83,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.2 A (F9P rail through Q1: ZED-F9P ~70-100 mA + active antenna 20-30 mA); T15 rule over-strict for this net
|
||||||
|
DRC,243,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.3000 mm),86.0594,126.2406,"Track [/SW_5V] on F.Cu, length 3.2394 mm",/SW_5V,0.3,T15 power width: PWR_MID >= 0.6 mm,3.24,F.Cu,pre-existing-benign,0.3 mm F.Cu capacity 1.00 A >= est. 0.2 A (F9P rail through Q1: ZED-F9P ~70-100 mA + active antenna 20-30 mA); T15 rule over-strict for this net
|
||||||
|
DRC,244,track_width,warning,Track width (rule 'T15 power width: PWR_MID >= 0.6 mm' min width 0.6000 mm; actual 0.5000 mm),84.125,124.6063,"Track [/SW_5V] on F.Cu, length 0.0354 mm",/SW_5V,0.5,T15 power width: PWR_MID >= 0.6 mm,0.04,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.2 A (F9P rail through Q1: ZED-F9P ~70-100 mA + active antenna 20-30 mA); T15 rule over-strict for this net
|
||||||
|
DRC,245,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.2500 mm),185.5,105.71,"Track [/VIN_SW] on F.Cu, length 0.5100 mm",/VIN_SW,0.25,T15 power width: PWR_HI >= 1.0 mm,0.51,F.Cu,pre-existing-benign,0.51 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,246,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.2500 mm),184.5125,104.2125,"Track [/VIN_SW] on F.Cu, length 0.6000 mm",/VIN_SW,0.25,T15 power width: PWR_HI >= 1.0 mm,0.6,F.Cu,real,0.25 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 0.88 A (after RS1: LTC4040 input current limit 25 mV/10 mOhm = 2.5 A)
|
||||||
|
DRC,247,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.8000 mm),182.25,104.2125,"Track [/VIN_SW] on F.Cu, length 1.6625 mm",/VIN_SW,0.8,T15 power width: PWR_HI >= 1.0 mm,1.66,F.Cu,real,0.8 mm F.Cu carries ~2.5 A vs IPC-2221 10C capacity 2.03 A (after RS1: LTC4040 input current limit 25 mV/10 mOhm = 2.5 A)
|
||||||
|
DRC,248,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.2500 mm),185.5,105.2,"Track [/VIN_SW] on F.Cu, length 1.3965 mm",/VIN_SW,0.25,T15 power width: PWR_HI >= 1.0 mm,0.51,F.Cu,pre-existing-benign,0.51 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,249,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.8000 mm),167.275,99.3,"Track [/VIN_SW] on In2.Cu, length 4.2426 mm",/VIN_SW,0.8,T15 power width: PWR_HI >= 1.0 mm,4.24,In2.Cu,real,0.8 mm In2.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.02 A (after RS1: LTC4040 input current limit 25 mV/10 mOhm = 2.5 A)
|
||||||
|
DRC,250,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.8000 mm),180.6,99.7,"Track [/VIN_SW] on In2.Cu, length 4.6846 mm",/VIN_SW,0.8,T15 power width: PWR_HI >= 1.0 mm,4.68,In2.Cu,real,0.8 mm In2.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.02 A (after RS1: LTC4040 input current limit 25 mV/10 mOhm = 2.5 A)
|
||||||
|
DRC,251,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.8000 mm),167.275,99.3,"Track [/VIN_SW] on In2.Cu, length 0.5657 mm",/VIN_SW,0.8,T15 power width: PWR_HI >= 1.0 mm,4.24,In2.Cu,real,0.8 mm In2.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.02 A (after RS1: LTC4040 input current limit 25 mV/10 mOhm = 2.5 A)
|
||||||
|
DRC,252,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.8000 mm),183.9125,103.0125,"Track [/VIN_SW] on In2.Cu, length 1.2000 mm",/VIN_SW,0.8,T15 power width: PWR_HI >= 1.0 mm,4.68,In2.Cu,real,0.8 mm In2.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.02 A (after RS1: LTC4040 input current limit 25 mV/10 mOhm = 2.5 A)
|
||||||
|
DRC,253,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.8000 mm),167.675,99.7,"Track [/VIN_SW] on In2.Cu, length 12.9250 mm",/VIN_SW,0.8,T15 power width: PWR_HI >= 1.0 mm,0.57,In2.Cu,real,0.8 mm In2.Cu carries ~2.5 A vs IPC-2221 10C capacity 1.02 A (after RS1: LTC4040 input current limit 25 mV/10 mOhm = 2.5 A)
|
||||||
|
DRC,254,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),183.9125,104.0311,"Track [/VIN_SW] on In2.Cu, length 0.1814 mm",/VIN_SW,0.5,T15 power width: PWR_HI >= 1.0 mm,0.18,In2.Cu,real,0.5 mm In2.Cu carries ~2.5 A vs IPC-2221 10C capacity 0.72 A (after RS1: LTC4040 input current limit 25 mV/10 mOhm = 2.5 A)
|
||||||
|
DRC,255,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),145.2,62.575,"Track [/VIN_MODEM] on F.Cu, length 0.7000 mm",/VIN_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,0.7,F.Cu,pre-existing-benign,0.70 mm neck at U20 pin (pad-limited)
|
||||||
|
DRC,256,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),142.5,62.48,"Track [/VIN_MODEM] on F.Cu, length 1.9050 mm",/VIN_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,1.91,F.Cu,real,0.5 mm F.Cu carries ~1.9 A vs IPC-2221 10C capacity 1.45 A (U20 input on battery: 3.8 V*2 A/0.9/4.5 V = 1.9 A peak (0.35 A at 24 V))
|
||||||
|
DRC,257,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),142.5,62.48,"Track [/VIN_MODEM] on F.Cu, length 1.5300 mm",/VIN_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,1.91,F.Cu,real,0.5 mm F.Cu carries ~1.9 A vs IPC-2221 10C capacity 1.45 A (U20 input on battery: 3.8 V*2 A/0.9/4.5 V = 1.9 A peak (0.35 A at 24 V))
|
||||||
|
DRC,258,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),140.97,62.48,"Track [/VIN_MODEM] on F.Cu, length 0.5233 mm",/VIN_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,1.53,F.Cu,real,0.5 mm F.Cu carries ~1.9 A vs IPC-2221 10C capacity 1.45 A (U20 input on battery: 3.8 V*2 A/0.9/4.5 V = 1.9 A peak (0.35 A at 24 V))
|
||||||
|
DRC,259,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),144.405,62.48,"Track [/VIN_MODEM] on F.Cu, length 0.1344 mm",/VIN_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,1.91,F.Cu,real,0.5 mm F.Cu carries ~1.9 A vs IPC-2221 10C capacity 1.45 A (U20 input on battery: 3.8 V*2 A/0.9/4.5 V = 1.9 A peak (0.35 A at 24 V))
|
||||||
|
DRC,260,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),146.2,68.5,"Track [/VIN_MODEM] on F.Cu, length 0.4950 mm",/VIN_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,0.49,F.Cu,real,0.5 mm F.Cu carries ~1.9 A vs IPC-2221 10C capacity 1.45 A (U20 input on battery: 3.8 V*2 A/0.9/4.5 V = 1.9 A peak (0.35 A at 24 V))
|
||||||
|
DRC,261,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),145.8,68.1,"Track [/VIN_MODEM] on F.Cu, length 4.9250 mm",/VIN_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,4.92,F.Cu,real,0.5 mm F.Cu carries ~1.9 A vs IPC-2221 10C capacity 1.45 A (U20 input on battery: 3.8 V*2 A/0.9/4.5 V = 1.9 A peak (0.35 A at 24 V))
|
||||||
|
DRC,262,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.3000 mm),145.85,68.15,"Track [/VIN_MODEM] on F.Cu, length 0.0707 mm",/VIN_MODEM,0.3,T15 power width: modem + vehicle PSU paths >= 0.8 mm,0.07,F.Cu,real,0.3 mm F.Cu carries ~1.9 A vs IPC-2221 10C capacity 1.00 A (U20 input on battery: 3.8 V*2 A/0.9/4.5 V = 1.9 A peak (0.35 A at 24 V))
|
||||||
|
DRC,263,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),145.8,63.175,"Track [/VIN_MODEM] on F.Cu, length 0.8485 mm",/VIN_MODEM,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,4.92,F.Cu,real,0.5 mm F.Cu carries ~1.9 A vs IPC-2221 10C capacity 1.45 A (U20 input on battery: 3.8 V*2 A/0.9/4.5 V = 1.9 A peak (0.35 A at 24 V))
|
||||||
|
DRC,264,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.2500 mm),189.45,107.9,"Track [/SW_BAT] on F.Cu, length 0.2400 mm",/SW_BAT,0.25,T15 power width: PWR_HI >= 1.0 mm,0.24,F.Cu,pre-existing-benign,0.24 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,265,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.2500 mm),189.45,108.16,"Track [/SW_BAT] on F.Cu, length 0.2600 mm",/SW_BAT,0.25,T15 power width: PWR_HI >= 1.0 mm,0.26,F.Cu,pre-existing-benign,0.26 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,266,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),190.113,107.9,"Track [/SW_BAT] on F.Cu, length 7.6184 mm",/SW_BAT,0.5,T15 power width: PWR_HI >= 1.0 mm,7.62,F.Cu,real,"0.5 mm F.Cu carries ~4.0 A vs IPC-2221 10C capacity 1.45 A (LTC4040 boost switch, ~4 A in backup (5 V/2.5 A from 3.2-3.7 V pack) - V5 EMC audit)"
|
||||||
|
DRC,267,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),189.45,107.9,"Track [/SW_BAT] on F.Cu, length 0.6630 mm",/SW_BAT,0.5,T15 power width: PWR_HI >= 1.0 mm,0.66,F.Cu,pre-existing-benign,0.66 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,268,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.3000 mm),189.45,108.16,"Track [/SW_BAT] on F.Cu, length 0.5000 mm",/SW_BAT,0.3,T15 power width: PWR_HI >= 1.0 mm,0.5,F.Cu,pre-existing-benign,0.50 mm neck at U6 pin (pad-limited)
|
||||||
|
DRC,269,track_width,warning,Track width (rule 'T15 power width: PWR_HI >= 1.0 mm' min width 1.0000 mm; actual 0.5000 mm),195.5,102.513,"Track [/SW_BAT] on F.Cu, length 3.6130 mm",/SW_BAT,0.5,T15 power width: PWR_HI >= 1.0 mm,7.62,F.Cu,real,"0.5 mm F.Cu carries ~4.0 A vs IPC-2221 10C capacity 1.45 A (LTC4040 boost switch, ~4 A in backup (5 V/2.5 A from 3.2-3.7 V pack) - V5 EMC audit)"
|
||||||
|
DRC,270,track_width,warning,Track width (rule 'T15 power width: modem + vehicle PSU paths >= 0.8 mm' min width 0.8000 mm; actual 0.5000 mm),153.9,121.9,"Track [/VIN_FUSED] on F.Cu, length 1.4725 mm",/VIN_FUSED,0.5,T15 power width: modem + vehicle PSU paths >= 0.8 mm,1.47,F.Cu,pre-existing-benign,0.5 mm F.Cu capacity 1.45 A >= est. 0.8 A (same as VIN_PROT); T15 rule over-strict for this net
|
||||||
|
DRC,271,silk_overlap,warning,Silkscreen clearance,70.6,127.075,Reference field of D27,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,272,silk_overlap,warning,Silkscreen clearance,70.23,127.555,Segment of D27 on F.Silkscreen,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,273,silk_overlap,warning,Silkscreen clearance,118.5225,58.4873,Segment of R99 on F.Silkscreen,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,274,silk_overlap,warning,Silkscreen clearance,187.25,80.75,Reference field of C126,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,275,silk_overlap,warning,Silkscreen clearance,161.5,83.5,Reference field of Q21,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,276,silk_overlap,warning,Silkscreen clearance,171.45,99.0,Segment of JP3 on F.Silkscreen,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,277,silk_overlap,warning,Silkscreen clearance,171.75,98.7,Segment of JP3 on F.Silkscreen,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,278,silk_overlap,warning,Silkscreen clearance,155.75,73.98,Arc of U24 on F.Silkscreen,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,279,silk_overlap,warning,Silkscreen clearance,155.6,69.77,Segment of U23 on F.Silkscreen,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,280,silk_overlap,warning,Silkscreen clearance,137.05,125.17,Segment of Q10 on F.Silkscreen,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,281,silk_overlap,warning,Silkscreen clearance,155.25,116.75,Reference field of Q23,,,board setup constraints silk,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,282,silk_over_copper,warning,Silkscreen clipped by solder mask,123.55,56.75,Reference field of Rigb1,,,Local override,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
DRC,283,silk_over_copper,warning,Silkscreen clipped by solder mask,145.5,109.25,Reference field of C10,,,Local override,,,needs-fix-cosmetic,silkscreen legibility; JLC clips silk on pads/edge automatically
|
||||||
|
@ -0,0 +1,320 @@
|
|||||||
|
# Verification 1 — Power (A-xx, F-51) + Modem / GNSS / Ethernet (B/C/E)
|
||||||
|
Snapshot: sch ecee9fed… / pcb 6ddec80d… (evidence pack 2026-09-28). Verifier scripts: `/home/claude/v6audit/work/verifier1/` (`geo.py` pad/track polygons from the evidence CSVs, `zonefill.py` → `zonefills.json` (filled polygons parsed with `kisexp`), `islands.py` / `clusters.py` (F.Cu GND islands and pad/track-joined clusters with via counts), `vbat_sim.py` (averaged current-mode model of U20 → VBAT_MODEM burst droop)). No auditor script was reused.
|
||||||
|
|
||||||
|
Datasheets used (fetched this session): LTC4040 Rev B (`4040fb`, p.3–4, 10–11, 15–19); TPS54360B SNVSB93 (§6.1/6.5/6.6); AP64350 DS41976 Rev 5-2 (p.4–5, 10–11, 13, 15, 18–20); MP1584 Rev 1.0 (abs max, EN); PMEG3050EP v3 (Table 7); SIMCom A7672X/A7670X HD V1.03 (Table 1, Table 8 p.26–27, Table 30 p.50, Fig. 33 / Table 40 p.54); u-blox ZED-F9P-04B DS UBX-21044850 R05 (pin table, Table 14/15) and Integration Manual UBX-18010802 R02 §8.6; AP2112 DS39724 Rev 2-2 (p.4); TPS7A20 SBVS338H; TPS2552 SLVS841F; W5500 DS v1.0.2 (§5.3, crystal spec, pin 37); TI TIDUC41 Table 4 (ISO 7637-2 pulse levels). Part data: KiCad-MCP JLC lookups (numbers quoted inline).
|
||||||
|
|
||||||
|
**Transient levels assumed for the 24 V discussion:** 24 V truck bus 27–29 V while charging (up to ≈ 30 V with cold compensation); ISO 16750-2 over-voltage 36 V for 60 min (24 V systems); ISO 7637-2:2011 pulse 2a +37…+50 V, Ri 2 Ω, 50 µs (TI TIDUC41 Table 4; the auditor's +112 V is an older/OEM level); ISO 16750-2 load dump Test A 151–202 V, Ri 1–8 Ω, 100–350 ms; suppressed load dump (Test B) ≈ 58 V for 24 V systems.
|
||||||
|
|
||||||
|
## Summary table
|
||||||
|
| ID | Auditor severity | Verdict | Verified severity | One-line reason |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| A-01 | Blocker | CONFIRMED-WITH-CORRECTION | **Blocker** | Topology and ratings reproduced. The Blocker rests on D21 (30 V Schottky, 18.5–23.5 V reverse on a charging 24 V bus, thermal-runaway range) plus the unfused branch, not on U2 (U2-on-24 V has field history). Pulse 2a is +50 V per ISO 7637-2:2011, not +112 V. D32 does clamp `/24V` transients through Q10–F2–Q23. |
|
||||||
|
| A-02 | Blocker | CONFIRMED | **Blocker** | SW_BAT 0.5 mm × 11.9 mm with 0.25/0.30 mm necks, EP 0 vias, L6 8.65 mm, C30/C31 7.2/6.2 mm, nearest sensor 71.4 mm. This repeats lesson F5 / ECO D2 ("Obligatorio"). The H0008 OT-cycling causality is still unproven. |
|
||||||
|
| A-03 | Blocker | CONFIRMED | **Blocker** | 825 Ω → 2.42 A nominal (2.28–2.57 A). The top corner is above the LTC4040's 2.5 A maximum. 1.43 k is the largest E96 value with a worst-case minimum ≥ 1.3 A (1.316 A); 1.5 k gives 1.254 A. |
|
||||||
|
| B-01 | Blocker | CONFIRMED (merge → A-01) | Blocker | Same root cause as A-01. D21 stress and leakage reproduced from the PMEG3050EP datasheet. |
|
||||||
|
| B-02 | Blocker | SEVERITY-CHANGE | **Major** | C2827940 is a SamYoung MVG general-purpose e-cap (85 °C/2000 h), and the compensation is the AP64350 5 V Table 1 row. Simulated 2 A GSM droop on battery with new caps is 0.25–0.28 V (VBAT ≥ 3.52 V), so it works on day 1. It fails when cold or aged (0.44–0.52 V). This is a lifetime issue; the fix is BOM-only. |
|
||||||
|
| B-03 | Blocker | CONFIRMED-WITH-CORRECTION | **Blocker** | Unidirectional ESD9L on the TX line clips at −0.6 V even at 23 dBm (4.47 V pk). The proposed PGB1010402KR is rated 12 VDC max operating, below the 14.1 V GSM peak, so use PESD0402-240 (C1975527, 24 V) or DNP. |
|
||||||
|
| B-04 | Blocker | SEVERITY-CHANGE (merge → F-12) | **Major** | Measured: 1 GND via in the U19 courtyard, U20 EP 0 vias (nearest 3.45 mm), J13 20–21 mm to a via, 3611 mm² cluster with 5 vias. No R1–R5 violation, no V5.5 field failure, no damage path, so this is Major. |
|
||||||
|
| C-01 | Blocker | CONFIRMED | **Blocker** | u-blox IM R02 §8.6 says a 10 Ω limiter is "required". VCC_RF is 300 mA abs max; AP2112 current limit ≈ 0.6–0.8 A. ANT_DETECT/ANT_SHORT_N are F9P inputs with nothing driving them. The TPS2552 fix checks out. |
|
||||||
|
| A-04 | Major | CONFIRMED | Major | 53.6k/10.2k → 4.871/5.004/5.140 V; 57.6k → 5.176/5.318/5.463 V (37 mV under the LTC4040 5.5 V VIN max). PFI falls at 4.27/4.40/4.54 V. The V5_PFI constant 4.60 is stale. |
|
||||||
|
| A-05 | Major | CONFIRMED-WITH-CORRECTION | Major | Budget reproduced: 2.25–2.33 A at MAIN5V on a GSM burst. The "93–97 %" is against the datasheet's guaranteed 2.5 A. ILIM(BST) ≥ 5.5 A still leaves ≈ 30–40 % switch headroom at 3.5 V. |
|
||||||
|
| A-06 | Major | CONFIRMED | Major | U25 input caps' GND (252 mm² cluster) and U25 EP/D34 (3611 mm² cluster) are separate. 0 EP vias on U25/U20/U2/U12. L22 is 13.75 mm edge, not 17.0. |
|
||||||
|
| A-07 | Major | CONFIRMED | Major | VEH5V In1 0.5 × 13.6 mm, VIN_SW In2 0.8 × 23.6 mm. These are also a prerequisite for A-01's MAIN5V modem feed. |
|
||||||
|
| A-08 | Major | CONFIRMED | Major | LDO_IN 4.27–4.67 V on battery vs ≈ 4.3 V needed. Iq 5/11 mA ≈ 27–60 mW referred to the battery, against a 20–50 mW floor target. |
|
||||||
|
| A-09 | Major | CONFIRMED (C130/C131 merge → B-02) | Major | MVG 85 °C/2000 h → ≈ 8000 h at 65 °C. C881921 polymer verified (105 °C, 16 V, 6.3×7.7, stock 2442). |
|
||||||
|
| F-51 | Major | CONFIRMED | Major | No TMP102 on v6; `/NTC` goes to U6.17 only; PC5/PB10/PA9/PD2 free; 0x48 does not clash with U10 (0x4D). |
|
||||||
|
| B-05 | Major | CONFIRMED (merge → F-06) | Major | RF_LTE In1 22.14 mm with two vias. Crossed by VBAT_MODEM, SYS5V, SW_IN and MODEM_LED on F.Cu and DIN_4G on In2. 1 GND via within 1.5 mm. |
|
||||||
|
| B-06 | Major | CONFIRMED (absorbs F-07, A-06/U20) | Major | C128/C127 GND → U20.7 6.86/8.48 mm, EP 0 vias. Resolved Cin: 2 × 22 µF. |
|
||||||
|
| B-07 | Major | CONFIRMED (absorbs G-02, F-14/J9, F-17) | Major | USB_DP/DM/VBUS = J9 + U19 only. USBLC6-2SC6 C7519 (stock 1415) verified. |
|
||||||
|
| C-02 | Major | CONFIRMED | Major (low end) | AP2112 has no soft-start (tS 20 µs, no load). With ≈ 18 µF, the ramp is ≈ 28–80 µs/V: inside 20–8000 µs/V but not guaranteed. TPS7A2033P is a drop-in: 239–367 µs/V. |
|
||||||
|
| C-03 | Major | CONFIRMED (merge → F-12) | Major | U18 0 vias; 946 mm² cluster with 5 vias. Correction: J12.3 has a GND via 0.73 mm away. |
|
||||||
|
| C-04 | Major | CONFIRMED | Major | Q1 9.0 mm and Q5 7.1 mm from J13. `/SW_5V` In1 181.3 mm. |
|
||||||
|
| E-01 | Major | CONFIRMED (absorbs A-05 fix 1) | Major | U12.2 EN on `/SYS5V`. W5500 VIH max 5.5 V (5 V-tolerant I/O), so gating 3V3_ETH does not back-power it through SPI. |
|
||||||
|
| E-02 | Major | CONFIRMED-WITH-CORRECTION (absorbs D-04) | Major (Minor once E-01 is in) | W5500 RSTn also has an internal 62–112 kΩ pull-up, so 100 k fails even without PA15. 4.7 k gives ≤ 0.62 V worst case. D-04's "PD2 + 100 k" alternative fails. |
|
||||||
|
| E-03 | Major | SEVERITY-CHANGE (absorbs H-07, F-11/Y1) | **Minor** | CL mismatch confirmed (+80…+160 ppm). V5.5 as-fabbed has the identical Y1 (C14872) and C95/C96 18 pF (C1647) and works; J10 is DNP on the prototypes. Conflicting fixes resolved below. |
|
||||||
|
|
||||||
|
Counts: CONFIRMED 17 · CONFIRMED-WITH-CORRECTION 4 · SEVERITY-CHANGE 3 · REFUTED 0 · CANNOT-VERIFY 0.
|
||||||
|
|
||||||
|
## Per-item notes
|
||||||
|
|
||||||
|
### A-01 (with B-01, H-05, F-53) — vehicle-voltage exposure of U2 / U20 / D21
|
||||||
|
- **Topology (nets.json):**
|
||||||
|
- `/24V_IN` = {P1.1, D10, F2.1, Q10.D}.
|
||||||
|
- `F2 → /VIN_FUSED → Q23 → /VIN_PROT` = {D32, C149–C151, U25.2, R124}.
|
||||||
|
- `Q10.S → /24V` = {C10, C11, C22, Ren1, U2.7, D20.A, DzG1.K}.
|
||||||
|
- `/VIN_MODEM` = {D20.K, D21.K, C127, C128, U20.2}.
|
||||||
|
- D21.A = `/MAIN5V`, which is VSYS of the LTC4040, downstream of RS1 and Q7.
|
||||||
|
- Confirmed: `/24V` is not behind F2.
|
||||||
|
- **Correction (clamping):** for µs–ms transients `/24V` is clamped by D10 *and* by D32 through Q10 (65 mΩ) → F2 (≈ 0.05 Ω) → Q23 (65 mΩ), ≈ 0.2 Ω in total. "Outside the D32 clamp" is only true for fusing and for DC. Neither TVS conducts at 36 V DC (VBR 36.7–40.6 V).
|
||||||
|
- **Ratings (datasheets):**
|
||||||
|
- **U2 MP1584:** VIN operating 4.5–28 V, abs max **30 V**, EN abs max 6 V. EN = V24·20k/120k → 4.8 V at 28.8 V and 6.0 V at 36 V.
|
||||||
|
- **U20 AP64350:** abs max 42 V DC / 45 V for 400 ms.
|
||||||
|
- **D21 PMEG3050EP:** VR 30 V, IR 2.6 mA typ / 8 mA max at 30 V and 25 °C, 330 µA typ at 5 V. The datasheet explicitly warns about thermal runaway. Rth(j-a) 60–200 K/W.
|
||||||
|
- **D20 / Dbk1 SS34 (C8678, MDD):** 40 V.
|
||||||
|
- **Stress by operating point:**
|
||||||
|
- Charging bus 28.8 V: D21 VR = 28.8 − 0.3 − 5.0 = **23.5 V** (78 % of VRRM); U2 is 0.8 V over its operating maximum; U20 is fine.
|
||||||
|
- 36 V / 60 min: D21 VR = **30.7 V > 30 V**; U2 is 6 V over its abs max (it dies); U20 is fine.
|
||||||
|
- Pulse 2a (+50 V, 2 Ω): ≈ 4–5 A into D10 ∥ D32 → clamp ≈ 42–45 V (dynamic R ≈ 1.1 Ω SMBJ / 0.45 Ω SMCJ). U20 sits at its 45 V/400 ms limit, U2 far above 30 V, and D21 reverse ≈ 37–40 V (avalanche for 50 µs).
|
||||||
|
- Suppressed load dump 58 V: every part on `/24V` is over its rating, and the TVSs cannot absorb it (A-19).
|
||||||
|
- **D21 thermal runaway (new quantification):**
|
||||||
|
- Typical IR at 23.5 V and 25 °C ≈ 1.8 mA, interpolated from 0.33 mA at 5 V and 2.6 mA at 30 V. Leakage roughly doubles per 10 °C.
|
||||||
|
- Stability needs k·PR·Rth < 1, with k = ln2/10 = 0.069 K⁻¹. That means PR < 0.12 W at 120 K/W, or 0.24 W at 60 K/W.
|
||||||
|
- At a 45 °C board: IR ≈ 7 mA → PR ≈ 0.17 W. At 60 °C: IR ≈ 20 mA → PR ≈ 0.48 W. **Runaway is plausible at port-box temperatures.**
|
||||||
|
- A D21 that fails short puts `/24V` onto MAIN5V with no fuse: LTC4040 VSYS (6 V abs max), U21 (6 V), U17, the F9P and the MCU would all be exposed. **This damage path makes it a Blocker.**
|
||||||
|
- **Field-history weighting:** on V5.x, P1 = 24 V fed only U2 (`drogheda-einarboard-harness`), and there is no record of U2 failing. U2 alone therefore rates Major (outside operating range at 28–29 V, abs max only exceeded at ≥ 30 V events). D21, U20/D20 on the unfused branch, and the D21-short failure mode are new on v6.
|
||||||
|
- **Proposed fix "U20 from MAIN5V only, delete D20, bridge D21" — numbers:**
|
||||||
|
- *Where MAIN5V sits:* downstream of the LTC4040 input sense resistor. The path is VEH5V → RS1 → `/VIN_SW` → Q7 → MAIN5V, so modem current counts against the RS1 limit (23.5–26.5 mV / 10 mΩ = 2.35–2.65 A). The LTC4040 "does not actually limit the external load but … reduces charge current" (DS p.16). The modem therefore takes priority and the charger backs off.
|
||||||
|
- *Added U20 input current at MAIN5V ≈ 5.25 V (η 0.9):* LTE 23 dBm 0.67 A → 0.54 A; GSM 2.0 A → **1.61 A**; HD V1.00 2.8 A peak → 2.25 A.
|
||||||
|
- *RS1 path, steady, charging at 1.43 k + LTE TX:* 0.35 (logic) + 0.54 + 1.19 (charger input at 1.4 A) = **2.08 A** (under the limit).
|
||||||
|
- *RS1 path during a GSM burst:* system 1.96 A, and the charger is throttled to 0.4–0.7 A.
|
||||||
|
- *U25:* ≤ RS1 limit 2.65 A + fan 0.3 A (A-01 fix 1) = **≤ 2.95 A** against a 3.5 A rating and ≥ 4.5 A peak switch limit. A sub-ms overshoot before the input-limit loop settles reaches ≈ 3.45 A, which gives an inductor peak ≈ 3.8 A, still under 4.5 A.
|
||||||
|
- *D34 loss:* ≈ 0.8 W with A-03, versus ≈ 1.0 W as-is at the 825 Ω RS1-limited charge. No thermal regression.
|
||||||
|
- *Battery:* the modem already shares the 2.5 A boost as-is, through D21. Removing D21 raises VIN(U20) from ≈ 4.42 V to ≈ 4.72 V (+0.30 V) and lowers MAIN5V current at 2 A GSM from 2.25–2.33 A to ≈ 2.0–2.13 A.
|
||||||
|
- *F2 at 24 V:* 2.95·5.3/(0.88·24) = 0.74 A. At 12 V it is 1.48 A; at 9 V, 1.97 A.
|
||||||
|
- *PFI margin with 57.6 k (A-04):* 5.176 V − ≈ 0.2 V droop on a 1.6 A step = 4.98 V, versus PFI falling max 4.54 V, i.e. 0.44 V margin. As-is (53.6 k) the margin is 0.13 V.
|
||||||
|
- *Hand-over:* at PFI hand-over the modem load is already on MAIN5V, and effective CSYS is only ≈ 57–69 µF. Add A-05's CSYS and a 220 µF polymer at U20.2 (≈ 0.18 V hold-up for 2 A × 20 µs).
|
||||||
|
- **Alternative: D20 to `/VIN_PROT` behind F2, D21 → 60 V Schottky.**
|
||||||
|
- U20 still sees 20–36 V DC, and in pulse 2a ≈ 42–45 V (D32 ∥ D10). That is zero margin to 45 V/400 ms and over it for a 58 V suppressed load dump.
|
||||||
|
- PMEG6045ETPX (C552943, genuine Nexperia, 60 V/4.5 A, SOD-128 same land, IR 400 µA at 60 V, stock 2722) removes the D21 runaway. Its VF ≈ 0.45 V at 2 A costs ≈ 0.15 V more battery headroom than today.
|
||||||
|
- F2 must also carry U20's input.
|
||||||
|
- **Rejected.** The JSMSEMI clone C53114006 (H-05) has unknown leakage.
|
||||||
|
- **Recommended single topology:**
|
||||||
|
- U20 from MAIN5V: delete D20 and the 48 mm `/VIN_MODEM` run, and merge `/VIN_MODEM` into `/MAIN5V` (copper, no D21).
|
||||||
|
- Fan from VEH5V: JP1 bridged (bridged-jumper footprint or 0 Ω 0805), U2 block DNP.
|
||||||
|
- Q10/DzG1/Rrp1/C10/C11/C22 DNP.
|
||||||
|
- **F2 → 3 A 0154003.DR (C206912, stock 2217), placed electrically *ahead of* D10.** Use 4 A C206914 only if sustained 9 V operation is required.
|
||||||
|
- Dependencies: A-07 (widen VEH5V/VIN_SW/MAIN5V paths), A-04 (57.6 k), A-05 CSYS, B-06 (2 × 22 µF at U20.2) plus 1 × 220 µF polymer C881921 at U20.2.
|
||||||
|
- Note for Leo: U20 then sits upstream of the P5 cutoff. The ECO §A intent ("the physical cutoff switches everything off") is still met functionally, because cutting SYS5V unpowers the MCU and R113 holds U20 EN low. U20 shutdown current is µA.
|
||||||
|
|
||||||
|
### A-02 — LTC4040 copper / placement
|
||||||
|
- **Re-measured (edge-to-edge, true pad shapes):**
|
||||||
|
- `/SW_BAT`: 6 F.Cu segments: 0.5 mm × 11.89 mm, plus 0.25 mm (0.50 mm) and 0.30 mm (0.50 mm) necks at pins 21/22. 0 vias.
|
||||||
|
- `/BAT_PLUS` P3 → L6.2: 1.0 mm × 21.27 mm (2.12 + 0.71 + 14.90 + 3.54).
|
||||||
|
- `/BAT_PLUS` L6.2 → U6.23: 1.0 mm, then 0.5 mm × 10.49 mm, then 0.25 mm × 5.38 mm.
|
||||||
|
- U6 EP: 0 vias. Nearest GND via: 3.04 mm edge at (191.6, 104.3); (188.6, 102.7) is 3.23 mm edge / 5.21 mm centre. The auditor's 5.21 mm is a centre distance.
|
||||||
|
- L6.1 ↔ U6.21/22: **8.65 mm**.
|
||||||
|
- C30 / C31 → U6.6: **7.20 / 6.18 mm**.
|
||||||
|
- C32 / C33 / C34 → U6.1: 3.90 / 3.44 / 4.74 mm.
|
||||||
|
- C35 → L6.2: 20.2 mm edge (the auditor's 21.9 mm is a centre distance).
|
||||||
|
- Nearest temperature sensor: U3 at **71.4 mm**.
|
||||||
|
- Cluster map: U6 EP, C32, C30/C31 and C35 are in a 252 mm² F.Cu cluster with 5 vias; C33 is in the 3611 mm² cluster.
|
||||||
|
- **IPC-2221 external rise** re-computed: SW_BAT 0.5 mm → +32 °C at 2.42 A, +80 °C at 3.6 A. BAT_PLUS 1.0 mm → +25 °C at 3.6 A. This matches the auditor.
|
||||||
|
- **Correction / caveat:** at bench ambient an LTC4040 dissipating ≈ 0.75 W needs θJA > 150 °C/W to reach OT. The H0008 cycling hypothesis is therefore weak. The 1.3 A figure itself is inferred from an OCV slope, not measured. The Blocker stands on lesson F5 / ECO D2 and the datasheet layout guidance, independent of H0008.
|
||||||
|
- **Fix:** as proposed. It is feasible: QFN 0.5 mm pitch, so start the ≥ 2 mm pour after the combined 21+22 pin fan-out. Put the F-51 TMP102 in this cluster.
|
||||||
|
|
||||||
|
### A-03 — R50
|
||||||
|
- **Datasheet:** RPROG = 2000 V/ICHG (hPROG 2500, VPROG 0.8 V); ICHG 950/1000/1050 mA at 2 k (±5 %); maximum charge current 2.5 A (DS p.3, 10, 18).
|
||||||
|
|
||||||
|
| R50 (1 %) | min | nom | max |
|
||||||
|
|---|---|---|---|
|
||||||
|
| 825 Ω | 2.280 A | 2.424 A | **2.571 A** (above the 2.5 A maximum) |
|
||||||
|
| 1.43 k | **1.316 A** | 1.399 A | 1.483 A |
|
||||||
|
| 1.47 k | 1.280 A | 1.361 A | 1.443 A |
|
||||||
|
| 1.5 k (ECO) | 1.254 A | 1.333 A | 1.414 A |
|
||||||
|
|
||||||
|
- 1.43 k is the largest E96 value that holds ≥ 1.3 A at every corner. It costs about 10 % more I²R than 1.5 k.
|
||||||
|
- **Fix part:** C22840 checked: 1.43 kΩ 1 % 0603, Extended, stock 4965.
|
||||||
|
- **Rating:** keep **Blocker**. It is an approved ECO C change missing from v6, 825 Ω exceeds the IC's 2.5 A maximum at the top corner, and it drives R5 (≥ 1.3 A without thermal cycling). The fix is one resistor.
|
||||||
|
|
||||||
|
### B-01 — see A-01
|
||||||
|
All of the auditor's numbers reproduce: VR 30.3–30.7 V at 36 V; the 30 V rating; IR from the datasheet. B-01's "Option B (recommended)" is exactly A-01's "Option A". Only the labels differ (see Fix conflicts).
|
||||||
|
|
||||||
|
### B-02 (with A-09 C130/C131, A-17) — VBAT_MODEM bulk and U20 compensation
|
||||||
|
- **Part:** C2827940 = SamYoung "MVG 16V 220UF 6.3×7.7", aluminium electrolytic, −40…+85 °C, 2000 h at 85 °C, 130 mA at 120 Hz (JLC). **General purpose, not polymer.** Confirmed. The value field reads "220uF/10V" while the part is 16 V (cosmetic).
|
||||||
|
- **Placement:** C131 8.70 mm and C130 16.26 mm from U19.55–57. The cap nearest L20.2 is C130 at 10.1 mm.
|
||||||
|
- **Compensation:** R116 14 k / C141 3.3 nF / C142 47 pF = **AP64350 Table 1 VOUT = 5.0 V row** (R5 14.00 k, C5 3.3 nF, C6 47 pF, designed for 2 × 22 µF ceramic). Confirmed.
|
||||||
|
- **Droop (my averaged current-mode model, `vbat_sim.py`):** mid-band gain Gm = 2π·R5/(4.67e3·VOUT) from DS eq. p.19; L 4.7 µH; slew limited by (VIN·0.95 − VOUT − I·0.115 Ω)/L; ceramic 13 µF.
|
||||||
|
|
||||||
|
| Condition | 2 A GSM burst | 0.7 A LTE |
|
||||||
|
|---|---|---|
|
||||||
|
| Battery, via D21 (4.42 V), MVG new (ESR 0.2 Ω pair) | **0.28 V** (VBAT 3.52 V) | 0.08 V |
|
||||||
|
| Same, cold / aged (0.6 Ω pair) | **0.52 V** (3.29 V, under the 3.4 V minimum) | 0.13 V |
|
||||||
|
| Battery, polymer + 113 k/6.8 nF | 0.06 V | 0.02 V |
|
||||||
|
| Battery, polymer with the as-is 14 k | 0.18 V (phase margin ≈ 27°, see below) | 0.06 V |
|
||||||
|
|
||||||
|
- **Why Major, not Blocker:** it works on day 1 and inside SIMCom's 300 mV drop limit, with the planned LTE-only firmware on battery. It fails with cold or aged caps. MVG life is ≈ 8000 h at 65 °C local, so "modem dark" on GSM bursts is likely within about a year. That is a reliability failure → Major. The fix is BOM-only on the same land, so do it before fab.
|
||||||
|
- **Fix check:**
|
||||||
|
- C881921 verified: Lelon OVZ 220 µF/16 V polymer, 105 °C/2000 h, 6.3×7.7, stock 2442.
|
||||||
|
- R116 → 113 k (C22862, stock 59 728); C141 → 6.8 nF X7R 0402 (C1542, Preferred); C142 → 56 pF C0G (C1572).
|
||||||
|
- Checks: R5 = 4.67e3·14 kHz·3.8·454 µF = 112.8 k; C5 = 3.8·454 µ/(2 A·113 k) = 7.6 nF; zero 207 Hz, fc 14 kHz, C6 pole 25 kHz → phase margin ≈ 60°.
|
||||||
|
- **Coupling rule:** 113 k is valid only with the polymer bank. With MVG caps, the ESR zero at ≈ 1.8 kHz lies below fc. Change the caps and the compensation together.
|
||||||
|
- Add 2 × 22 µF (C86817, stock 4144) at L20.2 as proposed.
|
||||||
|
|
||||||
|
### B-03 — LTE antenna ESD
|
||||||
|
- **D28 = C82326 onsemi ESD9L5.0ST5G:** "Unidirectional, 0.9 pF, VRWM 5 V, VBR 5.4 V, VC 9.8 V". Shunt: pin 1 (C) on `/RF_ANT_LTE`, pin 2 (A) on GND.
|
||||||
|
- **A7670SA output power** (HD V1.03 Table 30; GSM supported per Table 1): GSM850/900 33 dBm ±2, DCS/PCS 30 dBm, LTE 23 dBm ±2.7.
|
||||||
|
- **Peak voltage at 50 Ω:** V = √(2·P·50) → 23 dBm = **4.47 V**, 33 dBm = **14.1 V**. At VSWR 3:1 (×1.5): 6.7 / 21.2 V.
|
||||||
|
- A unidirectional diode forward-conducts at ≈ −0.6 V on every negative half-cycle, even in LTE, and avalanches at 5.4 V on GSM positive peaks. The result is hard clipping, spurious emissions and diode heating. **Blocker confirmed.** SIMCom Fig. 33: "D1 is a Bidirectional ESD Protection device" (recommended PESD0402-03 / CE0201S05G01R, neither in the JLC DB).
|
||||||
|
- **Fix check:** C10676 = Littelfuse PGB1010402KR is the correct number (0402, bidirectional, 0.04 pF, stock 59 948). Its **max operating voltage is 12 VDC** (TME/Newark), below the 14.1 V GSM peak. **Use Littelfuse PESD0402-240, C1975527** instead (bidirectional, 24 V working, 0.25 pF → −j335 Ω shunt at 1.9 GHz, |Γ| ≈ 0.07; stock 9394), or DNP D28. Either needs an 0402 land (the current land is SOD-923), which comes with the B-05 re-route. Keep D27: the GNSS line carries +3.2 V bias and no TX.
|
||||||
|
|
||||||
|
### B-04 (→ merged into F-12) — modem ground vias
|
||||||
|
- **Re-measured:**
|
||||||
|
- U19 courtyard (162.25–186.25 × 60–84) contains **1 GND via** at (184.6, 81.775); 4 more in a 5 mm ring. 39 GND pads: 20 × 2.1 mm on a 3.8 mm grid (1.7 mm gaps), 14 + 5 perimeter pads.
|
||||||
|
- U20 EP: 0 vias; nearest 3.45 mm edge; none within 2 mm.
|
||||||
|
- J13 GND pads: nearest via 20.3 / 21.3 mm. D28 GND: 19.1 mm.
|
||||||
|
- F.Cu cluster containing U19, U20, U25, U2, J13, D34: **3611 mm², 5 vias**, at (145.7, 129.9), (148.1, 135.3), (152.6, 62.5), (153.5, 77.0), (198.8, 78.1). This exactly reproduces BCE's figure.
|
||||||
|
- **Severity:** Major, not Blocker. It is a substantial EMC, desense and thermal risk, but it does not violate R1–R5, does not repeat a V5.5 field failure, has no damage mechanism, and is manufacturable. It belongs among the first layout actions, but it is not a gate.
|
||||||
|
- **Fix check:**
|
||||||
|
- 0.6/0.3 mm tented vias fit U19's 1.7 mm inner gaps with 0.55 mm clearance per side.
|
||||||
|
- For U18 (1.1 mm pads on 2.1 mm pitch), use the **diagonal centres** between four pads: pad-corner distance 0.707 mm, so a 0.6 mm via keeps 0.41 mm clearance. 35 positions are available, and no 0.45/0.2 mm microvias are needed.
|
||||||
|
|
||||||
|
### C-01 — GNSS antenna bias
|
||||||
|
- `/VCC_RF_GNSS` = {U18.7, L21, C144, C145}. L21 = C162555 LQG18HN68NJ00D: 68 nH, 0.8 Ω, **400 mA**, SRF 1 GHz. u-blox recommends 120 nH.
|
||||||
|
- ZED-F9P-04B DS R05 pin table:
|
||||||
|
- pin 4 ANT_DETECT = **Input** (active high)
|
||||||
|
- pin 5 ANT_OFF = Output
|
||||||
|
- pin 6 ANT_SHORT_N = **Input** (active low)
|
||||||
|
- VCC_RF 50 mA operating, **300 mA abs max**
|
||||||
|
- On v6 pins 4/6 connect only to PC1/PC2 (MCU inputs), so they are undriven. Confirmed. D-07 is the same finding.
|
||||||
|
- **IM UBX-18010802 R02 §8.6:** "a 10 Ω current limiting resistor is required to prevent against short circuits destroying the BIAS-T inductor."
|
||||||
|
- **Consequence:** a crushed coax lets U21 (AP2112, current limit ≈ 0.6–0.8 A) push more than VCC_RF's 300 mA abs max and L21's 400 mA. That is a hardware-damage path, and the class of fault is proven in the field (H0005/H0014). **Blocker confirmed.**
|
||||||
|
- **Fix check:** TPS2552DBVR, C46506 (SOT-23-6, stock 3002).
|
||||||
|
- Pinout 1 IN / 2 GND / 3 EN̅ (active-low on the 2552) / 4 FAULT̅ / 5 ILIM / 6 OUT; ILIM tied to IN → **75 mA typ**; VIN 2.5–6.5 V; FAULT̅ deglitch 7.5 ms; constant-current into a short, ≈ 0.25 W at 3.3 V.
|
||||||
|
- Polarity: ANT_OFF high → EN̅ high → antenna off, matching the F9P's active-high ANT_OFF. The 100 k pull-down keeps the antenna ON by default. FAULT̅ → ANT_SHORT_N (active low) with 10 k to 3V3_GNSS matches.
|
||||||
|
- U21 load becomes 130 mA + 75 mA.
|
||||||
|
- The 10 Ω fallback gives 3.2 V/10.8 Ω ≈ 0.30 A, right at VCC_RF's abs max. That is only acceptable as u-blox's stated minimum.
|
||||||
|
|
||||||
|
### A-04 — U25 set-point
|
||||||
|
- **Datasheet:** TPS54360B Vref 0.792/0.800/0.808 V over −40…150 °C.
|
||||||
|
- **Computed with 1 % parts:**
|
||||||
|
- 53.6k/10.2k: **4.871 / 5.004 / 5.140 V**
|
||||||
|
- 56.2k: 5.069 / 5.208 / 5.350 V
|
||||||
|
- **57.6k: 5.176 / 5.318 / 5.463 V**
|
||||||
|
- 57.6k with 0.1 % parts: 5.256 – 5.380 V
|
||||||
|
- **PFI** (R51 270 k / R52 100 k, 1.17/1.19/1.21 V, +30 mV hysteresis): falling 4.266 / 4.403 / 4.543 V, rising 4.376 / 4.514 / 4.656 V.
|
||||||
|
- **Firmware constants:** CHG_RAIL_ON 5.05, CHG_RAIL_OFF 4.90, V5_PFI 4.60. V5_PFI came from 287 k: 4.605 V typ. Stale confirmed.
|
||||||
|
- As-is nominal is under CHG_RAIL_ON, confirmed.
|
||||||
|
- **Fix:** 57.6 k = C23082, Extended, stock 3673. The top corner (5.463 V) is 37 mV under the LTC4040 VIN operating maximum of 5.5 V. Load-release overshoot (≈ +0.1–0.2 V once the modem is on MAIN5V) is brief and well under the abs max. Acceptable. 0.1 % parts are optional; I could not find 0.1 % LCSC numbers in the local DB.
|
||||||
|
|
||||||
|
### A-05 — battery-mode budget
|
||||||
|
- **Reproduced at VSYS 4.79 V:**
|
||||||
|
- Modem 2 A at 3.8 V → U20 input 1.89 A at 4.42 V (η 0.91).
|
||||||
|
- SYS5V ≈ 0.36 A: 3V3 0.12 A, F9P 0.10 A, W5500 0.107 A referred to 5 V, K1 0.03 A.
|
||||||
|
- MAIN5V total **2.25 A** (auditor 2.28–2.33 A).
|
||||||
|
- Battery current at 3.5 V = 2.25·4.79/(3.5·0.9) = **3.42 A**; at 3.7 V, 3.24 A.
|
||||||
|
- **Correction:** 90 % of the datasheet's guaranteed "2.5 A from a battery as low as 3.2 V". The hard limit is ILIM(BST) ≥ 5.5 A. At 3.5 V the inductor peak ≈ 3.6–3.9 A, which leaves ≈ 30–40 % headroom. A 2.8 A GSM peak at a 3.2 V battery reaches ≈ 5.4 A, i.e. the limit. The conclusions hold: LTE-only on battery, E-01, and firmware sequencing.
|
||||||
|
- **CSYS:** effective ≈ 57–69 µF (Samwha 47 µF 16 V X7R 1210 with DC-bias loss, plus 10 µF 50 V X5R), under the 75 µF transient guidance. Confirmed. This matters more with A-01's MAIN5V feed.
|
||||||
|
|
||||||
|
### A-06 — hot loops / EP grounding
|
||||||
|
- **U25:** C150.1 → U25.2 **2.88 mm**; C149.1 6.36 mm; C151.1 6.42 mm. C149/C150/C151 GND pads are in the 252 mm² U6 cluster; U25.7/EP and D34.2 are in the 3611 mm² cluster. D34 → SW **4.28 mm**; L22.1 → SW **13.75 mm** edge (not 17.0); C152 1.49 mm.
|
||||||
|
- **U20:** see B-06.
|
||||||
|
- **U2:** C22/C10/C11 → U2.7 18.3/17.0/20.7 mm.
|
||||||
|
- **U12:** C101 6.40 mm; D11 11.6 mm; L8 15.1 mm. D11.2 is in a different cluster (174 mm², 1 via) from C101.2/U12 GND (204 mm², 2 vias).
|
||||||
|
- **EP vias:** 0 on U25/U20/U2/U12. Nearest GND via 12.0 / 3.45 / 17.4 / 4.86 mm.
|
||||||
|
- **D34 loss:** 0.78·2.5 A·0.5 V ≈ 0.98 W. Confirmed.
|
||||||
|
|
||||||
|
### A-07 — 5 V path bottlenecks
|
||||||
|
- VEH5V: In1 0.5 mm × **13.6 mm** (plus In2 1.0 mm × 66.6 mm). VIN_SW: In2 0.8 mm × **23.6 mm**. IPC-2221 internal (35 µm): +168 °C at 2.5 A for the 0.5 mm run, matching the auditor. With JLC's default 0.5 oz inner copper it is worse (R ≈ 27 mΩ, 0.17 W over 13.6 mm).
|
||||||
|
- These paths already carry the RS1-limited 2.35–2.65 A whenever charging. A-01's fix adds more hours at that level, so A-07 becomes a **dependency** of A-01.
|
||||||
|
|
||||||
|
### A-08 — AMS1117
|
||||||
|
- LDO_IN on battery = 4.60–4.99 V − D12 (≈ 0.3 V) = 4.27–4.67 V. AMS1117 dropout ≈ 1.0 V at 0.1 A, so it needs ≈ 4.3 V. Marginal at the low corner. Iq 5/11 mA → 27–60 mW referred to the battery (boost η 0.88), against the 20–50 mW floor in `drogheda-backup-lowpower`. Confirmed.
|
||||||
|
- **Fix check:** C15578 TLV1117LV33DCYR: SOT-223, same 1-GND / 2-OUT / 3-IN pinout, 1 A, 455 mV at 1 A, 100 µA Iq, VIN max 5.5 V against LDO_IN max ≈ 5.21 V with 57.6 k; stock 26 999. OK.
|
||||||
|
|
||||||
|
### A-09 — electrolytics
|
||||||
|
- **Part data (JLC):** C2827940 MVG 85 °C/2000 h, 130 mA; C165527 MVK 105 °C/1000 h (C10); C88734 50TZV 105 °C/2000 h; C116241 UUD 105 °C/5000 h. Confirmed.
|
||||||
|
- **Life:** MVG at 65 °C ≈ 8000 h; polymer (×10 per −20 °C) ≈ 200 000 h.
|
||||||
|
- C130/C131 merge into B-02. C78 stays here (→ C881921). Its effect on the U25 loop is benign: fc ≈ 4.4 kHz with 276 µF against the 1.8 kHz compensation zero → phase margin ≈ 68°.
|
||||||
|
|
||||||
|
### F-51 — temperature sensors
|
||||||
|
- **Measured:** U3 SHT40 at 71.4 mm from U6; P7 / P8 at 100 / 83.5 mm; no TMP102 anywhere in `components.csv`; `/NTC` = {P3.3, R55, U6.17}. Free pins: PC5 (ADC1_IN15), PB10, PA9, PD2 (NC flags).
|
||||||
|
- **I²C bus:** SHT40 0x44, SC7A20, U13, U10 SC16IS752. U10 A0 = A1 = GND → 0x4D. TMP102 at 0x48 does not clash.
|
||||||
|
- **Fix check:**
|
||||||
|
- C99269 TMP102AIDRLR: SOT-563, stock 34 854.
|
||||||
|
- NTC tap: a 220 k load shifts the LTC4040 hot threshold by ≈ 0.7 °C (B3380) (auditor: < 0.6 °C; negligible difference). PC5 ≤ 5.463·120/220 = 2.98 V.
|
||||||
|
- Caveat: VEH5V = 0 on battery, so `tcell` is available only on vehicle power (auditor states this).
|
||||||
|
- **Rating:** Major. R4 is still reachable with the P7 probe on the pack plus the LTC4040's hardware NTC pause. Leo can promote it to Blocker if the brief's "sensor ≤ 10 mm of U6" is binding for R4.
|
||||||
|
|
||||||
|
### B-05 (→ merged into F-06) — RF_LTE on In1
|
||||||
|
- **Reproduced:** F.Cu 4.01 mm + In1 **22.14 mm** (0.5 mm), vias at (174.25, 58.25) and (194.27, 53.72); total 31.8 mm with `/RF_ANT_LTE`.
|
||||||
|
- **Copper within ±0.25 mm of the In1 run:** VBAT_MODEM F.Cu 1.15 mm², SYS5V 0.71, SW_IN 0.40, MODEM_LED_K 0.56 / _A 0.10, DIN_4G In2 0.71. GND vias within 1.5 mm of the whole LTE path: 1 at (175.2, 58.7).
|
||||||
|
- **Fix geometry check** (Wadell CPWG, JLC04161H-7628 L1–L2 0.2104 mm, εr 4.4, no mask / no copper thickness):
|
||||||
|
- w0.30 / s0.20 → **56.6 Ω** (≈ 50–52 Ω with mask and 35 µm copper, consistent with BCE's FD 53.3 / 48.4)
|
||||||
|
- w0.35 / s0.20 → 52.1 Ω
|
||||||
|
- existing w0.50 / s0.15 → 41 Ω (BCE 38.4)
|
||||||
|
- Use 0.30/0.20, confirm in JLC's calculator, and order impedance control.
|
||||||
|
|
||||||
|
### B-06 — U20 hot loop
|
||||||
|
- **Reproduced:** C128.1 → U20.2 0.72 mm; C127.1 2.38 mm; C128.2 → U20.7 **6.86 mm**, C127.2 **8.48 mm** (→ EP 3.30 / 4.94 mm); EP 0 vias, nearest 3.45 mm; L20.1 → SW 2.24 mm.
|
||||||
|
- At 5 V input, C127 (GRM21BR61H106 10 µF 50 V X5R) plus C128 ≈ 9.5 µF effective. Input ripple ΔV = 2 A·D(1−D)/(f·C) = 2·0.154/(500 k·9.5 µ) ≈ **65 mV p-p**; input RMS current 0.78 A.
|
||||||
|
- **Fix (resolved):** add 2 × 22 µF 16 V (C86817) ≤ 3 mm → ≈ 17 mV p-p. The 16 V parts are only valid once A-01 removes the 24 V feed.
|
||||||
|
|
||||||
|
### B-07 — J9 ESD
|
||||||
|
- Nets confirmed: USB_DP = J9.A6/B6 + U19.27; DM = J9.A7/B7 + U19.28; VBUS = J9.A4/A9/B4/B9 + U19.24. No protection device. J9 is 64.6 mm (centre) from U19.
|
||||||
|
- **Fix check:** C7519 USBLC6-2SC6, SOT-23-6, 3.5 pF, stock 1415. OK.
|
||||||
|
- Severity Major (Review lists it as a 🟠 F8 robustness item, not a field failure).
|
||||||
|
|
||||||
|
### C-02 — F9P VCC ramp
|
||||||
|
- **AP2112 DS39724:** tS = 20 µs at no load; short-circuit current 50 mA (foldback); no soft-start.
|
||||||
|
- `/3V3_GNSS` ≈ 18 µF (2 × 10 µF X5R + 3 × 100 nF).
|
||||||
|
- **Ramp:** foldback from 50 mA toward ≈ 0.7 A gives ≈ 400 µs/V at start and ≈ 28 µs/V near regulation (C/(Ilim − 0.1 A load)), ≈ 80 µs/V average. That is **inside** 20–8000 µs/V, but the fast-end margin (≈ 1.4×) depends on the AP2112's unspecified current-limit maximum. BCE's 20–25 µs/V is consistent.
|
||||||
|
- **Fix check:** TPS7A2033PDBVR C2862740.
|
||||||
|
- Same DBV pinout (1 IN, 2 GND, 3 EN, 4 NC, 5 OUT); t_STR 750–1150 µs → 239–367 µs/V.
|
||||||
|
- Current limit ≥ 360 mA, above 20 µF·3.3 V/0.75 ms = 88 mA plus load.
|
||||||
|
- VIN max 6.0 V against SW_5V ≤ 5.46 V; COUT 0.47–200 µF OK; stock 28 370.
|
||||||
|
- **Rating:** keep Major, at the low end. There are ≈ 52 000 starts per year, and the fix is a drop-in.
|
||||||
|
|
||||||
|
### C-03 (→ merged into F-12)
|
||||||
|
- U18 courtyard: 0 vias. 48 × 1.1 mm plus 8 × 0.8×1.5 mm GND pads. Cluster 946 mm², 5 vias. Reproduced.
|
||||||
|
- Correction: **J12.3 has a GND via 0.73 mm away** at (62.8, 124.7); J12.2's nearest is 3.7 mm. BCE's "0 vias ≤ 3 mm" and FHJ's "4.1 mm" are both off.
|
||||||
|
|
||||||
|
### C-04
|
||||||
|
- Q1 (197.28, 59.81) is **9.0 mm** from J13 and Q5 7.1 mm (centres). `/SW_5V` In1 = **181.32 mm**, plus F.Cu 19.7 mm, 2 vias. Reproduced. This is part of F-05's In1 usage problem.
|
||||||
|
|
||||||
|
### E-01 (absorbs A-05 fix 1)
|
||||||
|
- U12.2 EN is on `/SYS5V`. Confirmed. MP1584 EN: internal 1 µA pull-up to ≈ 3 V, rising threshold 1.5 V, abs max 6 V. With 100 k to GND, EN sits at 0.1 V → OFF. PD2 at 3.3 V turns it ON. Fix OK.
|
||||||
|
- W5500 VIH max 5.5 V (5 V-tolerant inputs), so MCU-driven SPI/RST lines do not back-power a gated 3V3_ETH.
|
||||||
|
- Even the W5500's 13 mA power-down current costs ≈ 57 mW from the battery, more than the whole sleep floor. Hardware gating is required for R1's energy target.
|
||||||
|
|
||||||
|
### E-02 (absorbs D-04)
|
||||||
|
- **MCU side:** PA15 resets to JTDI with pull-up (RM0383: GPIOA_PUPDR reset 0x6400 0000); R_PU 30–50 kΩ (DS10314).
|
||||||
|
- **New:** W5500 RSTn has its **own internal pull-up, 62–112 kΩ** (DS v1.0.2 §5.3); VIL 0.8 V; Schmitt VT− 0.95–1.09 V.
|
||||||
|
- **100 k pull-down:** 3.3·100/(100 + 30k∥62k = 20.2k) = **2.75 V**. Even with PA15 floating: 3.3·100/(100 + 62…112) = 1.56–2.04 V (undefined or high). The Review's 100 k could never have worked.
|
||||||
|
- **4.7 k (C23162, Basic):** worst case 3.3·4.7/(4.7 + 20.2) = **0.62 V** (typical 0.49 V) → reliably LOW. Drive current 0.70 mA.
|
||||||
|
- **D-04's "move to PD2 with 100 k" is rejected** (1.56–2.04 V, and PD2 is needed for ETH_PWR_EN).
|
||||||
|
- **Severity:** Major standalone. It becomes Minor (vehicle-power resets only) once E-01 gates 3V3_ETH.
|
||||||
|
|
||||||
|
### E-03 (absorbs H-07, F-11/Y1)
|
||||||
|
- Y1 = C14872 X49SM25MSD2SC (HC-49S, **CL 20 pF**, ±20 ppm, −20…+70 °C). The W5500 specifies CL 18 pF and ±30 ppm. C95/C96 = C1647 18 pF C0G. Distances 10.8 / 13.7 mm; traces 22.0 / 23.0 mm.
|
||||||
|
- **CL:** = (C1+Cp)(C2+Cp)/(C1+C2+2Cp) + Cshunt, with Cp ≈ 3 pF (pin) + ≈ 2.5 pF (22 mm trace over a 0.21 mm dielectric) and Cshunt ≈ 1 pF.
|
||||||
|
- 18 pF → **CL ≈ 12.8 pF**.
|
||||||
|
- Pulling (C1 10–20 fF, C0 5 pF) = (C1/2)·[1/(C0+12.8) − 1/(C0+20)] ≈ **+78…+156 ppm**.
|
||||||
|
- **Why Minor:** V5.5 as-fabbed and V5.6 have the identical Y1 and C95/C96 and Ethernet works; J10 is DNP on the v6 prototypes.
|
||||||
|
- 63 × 25 MHz = 1575.000 MHz, 420 kHz from L1, is true. The +100 ppm pull moves it to ≈ 1575.16 MHz, *closer* to L1 centre. That is an EMC note shared with Y3.
|
||||||
|
|
||||||
|
## Duplicates / merges proposed
|
||||||
|
| Primary | Absorbs | Agreed fix | Severity |
|
||||||
|
|---|---|---|---|
|
||||||
|
| **A-01** | B-01, H-05, F-53, A-06 (U2 row), F-08 | U20 from MAIN5V (delete D20, merge `/VIN_MODEM` into `/MAIN5V`, no D21); fan from VEH5V (JP1 bridged, U2 block DNP); Q10 branch DNP; F2 → 3 A C206912 ahead of D10; with A-07, A-04, A-05 CSYS, B-06 Cin + 220 µF polymer at U20.2 | Blocker |
|
||||||
|
| **A-02** | F-13 (U6 EP part), A-14 (In1 cuts under U6) | as A-02 | Blocker |
|
||||||
|
| **B-02** | A-09 (C130/C131), A-17 | C130/C131 → C881921; R116 113 k C22862, C141 6.8 nF C1542, C142 56 pF C1572; + 2 × 22 µF at L20.2 | Major |
|
||||||
|
| **F-12** (umbrella) | B-04, C-03, F-04, F-13 (EP arrays + solid SMD connection; U6 stays in A-02), EP-via clauses of A-06/B-06/F-07 | Zones `connect_pads thru_hole_only`; EP arrays (U25 3×3, U20 2×3, U12 2×3); U19 ≥ 30–40 tented gap vias + ring; U18 ≥ 24 at the diagonal centres; 2 vias ≤ 1 mm per U.FL GND pad; RF fences ≤ 3 mm; 5 mm board grid + edge fence ≤ 5 mm. Acceptance: every GND pad of U19/U18/U20/U25/J12/J13 in an F.Cu cluster with ≥ 1 plane via ≤ 2 mm | Major |
|
||||||
|
| **F-06** | B-05, C-05, B-12 (stackup/netclass) | Both RF lines F.Cu CPWG 0.30/0.20 over solid In1, JLC04161H-7628 set in the board file, impedance control, RF netclass | Major |
|
||||||
|
| **B-06** | F-07, A-06 (U20 row), A-05 fix 3 | Cin GND to EP ≤ 2 mm, delete the 0.25 mm GND neck, EP 2×3 vias, 2 × 22 µF C86817 + 220 µF C881921 at U20.2 | Major |
|
||||||
|
| **B-07** | G-02, F-14 (J9), F-17 | USBLC6-2SC6 C7519 ≤ 5 mm from J9; pair coupled on F.Cu | Major |
|
||||||
|
| **C-01** | D-07 | TPS2552DBVR current-limited feed; ANT_OFF → EN̅; FAULT̅ → ANT_SHORT_N | Blocker |
|
||||||
|
| **E-01** | A-05 fix 1 | `/ETH_PWR_EN` PD2 → U12 EN, 100 k to GND | Major |
|
||||||
|
| **E-02** | D-04 | 4.7 k C23162 `/ETH_RST` → GND at U11 | Major (Minor with E-01) |
|
||||||
|
| **E-03** | H-07, F-11 (Y1) | see conflict (f) below | Minor |
|
||||||
|
| **A-07** | J-02 ("59 real" width warnings on these nets) | as A-07 | Major |
|
||||||
|
|
||||||
|
## Fix conflicts resolved
|
||||||
|
- **(a) U20 feed.** A-01's "Option A" and B-01's "Option B" are the same fix. Adopt **MAIN5V-only with no D21**. The other option (D20 → `/VIN_PROT`, 60 V Schottky) keeps a 42 V part at 0–3 V margin to the pulse-2a clamp and costs ≈ 0.15 V more battery headroom. If D21 must remain for any reason, use the genuine Nexperia C552943, not the C53114006 clone.
|
||||||
|
- **(b) F2 rating.** "3 A" (A-01) vs "4 A class" (B-01 Option A). With MAIN5V-only, F2 carries ≤ 0.74 A at 24 V and ≤ 1.5 A at 12 V → **3 A C206912**. 4 A (C206914, stock 778) only for sustained 9 V operation.
|
||||||
|
- **(c) U20 compensation.** A-17 proposes R116 = 10 k with polymer; B-02 proposes 113 k / 6.8 nF / 56 pF. With 454 µF polymer: 10 k → fc 1.24 kHz, zero 4.8 kHz → **phase margin ≈ 15° (near-unstable, wrong direction)**. 113 k → fc 14 kHz, zero 207 Hz, pole 25 kHz → phase margin ≈ 60°. **Adopt B-02.**
|
||||||
|
- **(d) U20 input caps.** 1 × 22 µF (B-06), 2 × 22 µF + 220 µF (A-05), or a second 10 µF 50 V 1206 (F-07). **2 × 22 µF 16 V C86817** (ripple 65 → 17 mV p-p) plus **1 × 220 µF C881921**, because at PFI hand-over the modem load sits on a CSYS of only ≈ 60 µF.
|
||||||
|
- **(e) LTE ESD part.** PGB1010402KR (12 VDC max) → **PESD0402-240 C1975527 (24 V)**, or DNP.
|
||||||
|
- **(f) Y1 load caps, 18 pF vs 33 pF.** Both are right, for different crystals.
|
||||||
|
- Keeping the HC-49 C14872 (CL 20 pF): C95/C96 → **33 pF C1663** (Basic) → CL ≈ (33+5.5)/2 + 1 ≈ 20.3 pF, or ≈ 19.3 pF once relocated.
|
||||||
|
- Preferred, since Y1 moves ≤ 5 mm anyway: **Y1 → C9006** (YXC 3225, 25 MHz, **CL 12 pF**, ±10 ppm, −40…+85 °C, Basic, stock 528 k) and **keep 18 pF**: CL = 9 + ≈ 3 = 12 pF.
|
||||||
|
- The same crystal and caps suit Y3 (gm_crit ≈ 0.77 mA/V at ESR 40 Ω, C0 2 pF, under the F411's 1 mA/V). D-02's C2901684 gives more margin, so the MCU auditor decides Y3.
|
||||||
|
- **(g) ETH_RST.** 4.7 k on PA15 (E-02), not PD2 + 100 k (D-04).
|
||||||
|
- **(h) Spare-pin allocation.** PD2 = ETH_PWR_EN (E-01), PB10 = PFO (A-13), PC5 = NTC cell tap (F-51), PA9 spare.
|
||||||
|
- **(i) R50.** 1.43 k (A-03) over 1.5 k (ECO C).
|
||||||
|
- **(j) CPWG geometry.** 0.30/0.20 (B-05) vs 0.30–0.35/0.20–0.25 (F-06). Adopt 0.30/0.20; the calculator decides the final value.
|
||||||
|
|
||||||
|
## Anything else you noticed
|
||||||
|
1. **New, Major: reverse polarity defeated by D10 placement.** D10 (C224019) and D32 (C699039) are **unidirectional** parts drawn with a bidirectional A1/A2 symbol, with pad 1 (cathode) on the + rail. D10 sits on `/24V_IN` ahead of F2 and ahead of the Q10/Q23 reverse-polarity FETs. A reversed P1 therefore forward-biases D10 straight across the harness with no board fuse. The SMB part carries harness-fuse current until it fails, typically short. **Fix:** F2 electrically first (P1 → F2 → D10 ∥ Q23). A reversed connection then blows the socketed Nano2 fuse. A-01 lists this only as "optional"; make it mandatory. ISO 7637-2 pulse 1 (24 V: −600 V, 50 Ω, 1 ms ≈ 12 A, I²t ≈ 0.07 A²s) is ≈ 7 % of a 3 A Nano2's I²t, so it is fine.
|
||||||
|
2. **Cutoff intent (ECO §A).** With U20 on MAIN5V (as-is through D21, or with the fix), P5 no longer cuts modem power directly. R113 disables U20 whenever the MCU is unpowered, so the functional intent holds. Record it as a decision.
|
||||||
|
3. **H0008 evidence is weaker than A-02/A-03 imply.** The ≈ 1.3 A figure is inferred from the OCV slope, and an LTC4040 dissipating ≈ 0.75 W is unlikely to reach OT at bench ambient. The ratings stand on ECO D2/C and the datasheet, not on H0008. The clamp-meter test is still worth doing.
|
||||||
|
4. **AP64350 EN pull-up** is 1.5 µA (+4 µA hysteresis source), not 5.5 µA (A-power pass table). R113 100 k → 0.15 V, still OFF.
|
||||||
@ -0,0 +1,372 @@
|
|||||||
|
# Verification 2 — Layout/EMC (F), BOM (H), ERC/DRC (J), MCU/connectors (D/G)
|
||||||
|
|
||||||
|
Verifier 2, 2026-09-28. Scope: F-01, F-02, H-01, H-02 (Blockers); F-03…F-09, F-12, F-13, H-03, H-04, J-01, J-02, D-01, D-06, G-01, G-02 (Majors); D-02.
|
||||||
|
Method: my own scripts in `work/verifier2/` (`load_pcb.py` sexpdata zone-fill parser, `geom.py` pad/track/via → shapely, `hv24_gaps.py`, `vias_cnt.py`, `fcu_islands.py`, `in1cross.py`, `rfpar.py`, `z0.py`, `widths.py`). Primary sources: `src/*.kicad_pro/.kicad_dru/.kicad_pcb`, v6/V5.5/V5.6 netlists, `src/v5_current/…v5.kicad_pcb` (= V5.6 PCB, carries the V5.5 layout), evidence CSVs, JLC DB (`get_jlcpcb_part`), datasheets (cited per item), Fabrication-Toolkit source (GitHub `bennymeg/Fabrication-Toolkit@master`).
|
||||||
|
|
||||||
|
## Summary table
|
||||||
|
|
||||||
|
| ID | Auditor severity | Verdict | Verified severity | One-line reason |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| F-01 | Blocker | CONFIRMED-WITH-CORRECTION | **Blocker** | Only `/24V_IN` is HV24 and a 0.15 mm catch-all overrides every class. The proposed `.kicad_dru` has a hole: HV24↔HV24 pairs fall through to the 0.5 mm class value, which adds 4 false errors. Corrected rule set below. |
|
||||||
|
| F-02 | Blocker | CONFIRMED | **Blocker** | `/IGN_IN` runs 106.47 mm on In2 at 0.221 mm from `/VEH5V`. That is the 23-Jul geometry (0.20–0.25 mm on In2) again. |
|
||||||
|
| H-01 | Blocker | CONFIRMED-WITH-CORRECTION | **Blocker** | MAX3232ESE+ = 16 Narrow SO, placed on the SOIC-16W land (rows 9.3 mm apart). V5.5 did **not** have this: its PCB uses the narrow SOIC-16 land. v6 is a regression from re-syncing footprints from the schematic. |
|
||||||
|
| H-02 | Blocker | CONFIRMED-WITH-CORRECTION | **Blocker (order gate), U10 + R53 only** | R53 C131054 has 6 in stock against a 20-piece minimum, so it cannot be bought at any quantity. U10 has 15. The swaps are exact drop-ins. C103211, U19, U18 and J14 become a Major "re-check at order". |
|
||||||
|
| F-03 | Major | CONFIRMED | Major | U25's input-cap GND is on a 270 mm² F.Cu island. U25's EP and D34's anode are on the 3766 mm² island, whose nearest via is 30 mm away. |
|
||||||
|
| F-04 | Major | CONFIRMED | Major | 69 GND vias on the board. 1 via under U19, 0 under U18. The 3766 mm² east pour has 5 vias. (B-04 rates this Blocker; I rate it Major. See merges.) |
|
||||||
|
| F-05 | Major | CONFIRMED | Major | In1 is 18.8 % void and carries 1571.9 mm of tracks from 49 nets. USB, crystal, SIM and I²C lines cross slots or run broadside over foreign tracks. |
|
||||||
|
| F-06 | Major | CONFIRMED-WITH-CORRECTION | Major | LTE feed: 22.14 mm on In1, 2 vias, 1 fence via. GNSS bias line: minimum gap 0.274 mm over 3.3 mm and ≤ 0.5 mm over 13.4 mm, not "16.7 mm at 0.27". Impedance re-derived. |
|
||||||
|
| F-07 | Major | CONFIRMED | Major | C128's GND reaches U20's EP through a 0.25 mm neck between pin 1 and pin 2 (gaps 0.225/0.195 mm). EP has 0 vias. |
|
||||||
|
| F-08 | Major | CONFIRMED | Major (moot if U2 deleted, A-01) | U2 VIN (pin 7) to C11/C22/C10: 20.75/18.33/17.04 mm. |
|
||||||
|
| F-09 | Major | CONFIRMED-WITH-CORRECTION | Major | The auditor's Cin distance (1.77 mm) was measured to U12 **pin 2 = EN**. To VIN (pin 7) it is **6.40 mm**. D11 is 11.92 mm away and R87 25.9 mm. |
|
||||||
|
| F-12 | Major | CONFIRMED | Major | 69 GND vias (V5.5: 165), 10 of 35 20-mm cells empty, 2 vias along the edge. The via target is corrected to ≥ 400 (auditor: 500–600). |
|
||||||
|
| F-13 | Major | CONFIRMED-WITH-CORRECTION | Major (U6 EP part = A-02 Blocker) | 0 EP vias on U6/U25/U20/U2/U12. Correct the proposed fix: a board-wide "thru_hole_only" makes 23 × 0402 pads solid (tombstone risk). Use pad-level solid instead. |
|
||||||
|
| H-03 | Major | SEVERITY-CHANGE | **Minor** | Same part/land pairing on L2/L6/L7/L8 of 15 assembled V5.5 boards that work. Joint area is ≈ 55–64 % of the electrode, which is ample in strength. Change the footprint, not the part. |
|
||||||
|
| H-04 | Major (A-15 Minor) | SEVERITY-CHANGE | **Blocker** | Fabrication Toolkit (the tool the 25-Sep pre-fab audit prescribes) reads `LCSC Part` **before** `LCSC`. The BOM would order AP64350 (40 V) for U25 behind a 53 V clamp. |
|
||||||
|
| J-01 | Major | CONFIRMED (duplicate) | → F-01 | Same root cause as F-01. Merged. |
|
||||||
|
| J-02 | Major | CONFIRMED-WITH-CORRECTION | Major (copper → A-02/A-07/B-08) | 6 nets are really under-sized (BAT_PLUS, MAIN5V, VEH5V, SW_BAT, VIN_SW, VBAT_MODEM). VIN_MODEM is only a 0.1 mm neck. JLC's standard inner copper is 0.5 oz, which makes the inner runs worse than the auditor stated. |
|
||||||
|
| D-01 | Major (C-06 Minor) | CONFIRMED-WITH-CORRECTION | Major | U24 drives 3.3 V into an unpowered F9P RXD2 (ZED-F9P abs max VCC + 0.5 V). The 10 k series-R alternative is not enough. Use the Nexperia gate C12518 (Ioff), not the clone. |
|
||||||
|
| D-06 | Major | SEVERITY-CHANGE | **Blocker** (merged into F-02) | Same net and same geometry as F-02; this repeats the paid-for lesson. |
|
||||||
|
| G-01 | Major (Blocker if V5.5 standoffs) | CONFIRMED-WITH-CORRECTION | **Blocker unless Leo confirms a re-drilled backplate** | V5.5 MH4 (193.2, 90.3) is missing and L6 covers that point. The design brief says "no enclosure rework". The planned MH11 heatsink-clamp holes are also missing. |
|
||||||
|
| G-02 | Major | CONFIRMED | Major | `/USB_DP/DM/VBUS` = J9 + U19 only. USBLC6-2SC6 C7519 checked (SOT-23-6, 1415 in stock). |
|
||||||
|
| D-02 | Minor/Major-cond. | CONFIRMED | Minor | Y3 is 8.32/11.30 mm (pad edge) from PH0/PH1. The gm margin is thin only at max ESR. Leo graded ECO §E.6 🟡 and V5.5 starts in the field. |
|
||||||
|
|
||||||
|
Counts: 10 CONFIRMED, 9 CONFIRMED-WITH-CORRECTION, 3 SEVERITY-CHANGE, 0 REFUTED, 0 CANNOT-VERIFY. H-03's exact Sunlord land letters could not be read from the drawing (see its note).
|
||||||
|
|
||||||
|
**Severity calibration note on R5.** ECO §0 R5 is "the EMC list of the second batch" (ECO §E), and Leo graded its items himself: 🔴 SW_BAT and BAT_PLUS; 🟠 fan FB divider, Cin loops < 3 mm, DFU ESD and J9 ESD; 🟡 crystals ≤ 5 mm and stitching cells. I kept those grades: 🔴 → Blocker, 🟠 → Major, 🟡 → Minor. The only exception is stitching (F-12). v6 puts an LTE PA and a GNSS receiver on the board, which V5.5 did not have, so I keep F-12 at Major.
|
||||||
|
|
||||||
|
## Per-item notes
|
||||||
|
|
||||||
|
### F-01 Netclasses and custom rules
|
||||||
|
- **Re-derived.** `.kicad_pro` `netclass_patterns` (parsed with json): HV24 = `/24V_IN`, `24V`, `IGN_IN`, `Q10_GATE`. KiCad netclass patterns are anchored wildcard/regex matches against the full name, so the three un-prefixed patterns match nothing. The netlist `class` attribute (KiCad's own resolution, parsed from `src/netlists/v6-netlist.xml`) gives: HV24 = {`/24V_IN`} only; PWR_HI = 6 nets; PWR_MID = 6 nets (incl. `/3V3_ETH`); Default = 338 nets. The Default set includes `/24V`, `/IGN_IN`, `/Q10_GATE`, `/VIN_PROT`, `/VIN_FUSED`, `/VIN_MODEM`, `/Q23_GATE`, `/SW_PWRIN`, `/BOOT_PWRIN`, `/SW_MODEM`, `/BST_MODEM`, `/BST_FAN`, `/VBAT_MODEM`, `/RF_LTE` and `/RF_GNSS`. There are no RF or PWR_MODEM classes.
|
||||||
|
- **Rule precedence.** The rule `"Minimum clearance 1"`, `(min 0.15mm)`, has condition `A.NetClass != 'HV24' && B.NetClass != 'HV24'`, no layer clause and no type clause. KiCad turns netclass values into implicit rules and appends custom rules after them. The last matching rule wins; it does not take the max (JeffYoung, KiCad forum "Netclass clearance override by custom rules"). So this rule replaces Default/PWR 0.2 mm for every non-HV24 pair.
|
||||||
|
- **Zone clearance.** KiCad's zone-properties documentation (8.0) says "if two clearance values are in conflict, the larger clearance value will be used". The stored fills contradict that:
|
||||||
|
- My shapely measurement of the fill gives 0.1505 mm to every non-HV24 net (for example the `/24V` In1 1.5 mm track and `P1.3` `/IGN_IN` on In1/In2) and 0.5005 mm to `/24V_IN`.
|
||||||
|
- All 5 zones have `(connect_pads (clearance 0.3))` in the file.
|
||||||
|
- DRC reports 0 clearance items.
|
||||||
|
|
||||||
|
So in KiCad 10.0.4 the custom rule does override the zone field in practice. The corrected fix below does not depend on either interpretation, because it states every value explicitly.
|
||||||
|
- **Differences from the auditor's claim.** The facts are confirmed. The proposed `.kicad_dru` is syntactically valid KiCad DRC language (`(layer outer)`/`(layer inner)`, `A.NetClass`, `A.Type == 'Pad'`, `memberOfFootprint()`, `(constraint clearance (min …))`), but it misses one case. A pair where both nets are HV24 matches neither "HV24 outer/inner" (`B.NetClass != 'HV24'`) nor the floor rule, so it falls through to the HV24 netclass value of 0.5 mm. On today's copper that produces 4 false errors:
|
||||||
|
- `/BST_MODEM` C129.1 ↔ `/SW_MODEM` 0.180 mm (bootstrap, ≈ 5 V difference)
|
||||||
|
- `/BST_FAN` Cbst1.1 ↔ `/SW_FAN` 0.285 mm
|
||||||
|
- `/Q23_GATE` D33.1 ↔ `/VIN_PROT` 0.388 mm
|
||||||
|
- `/SW_FAN` ↔ `/VIN_MODEM` 0.400 mm
|
||||||
|
- **Corrected fix** (netclass table as the auditor gave it; the rule order matters because later rules win):
|
||||||
|
```
|
||||||
|
(rule "Floor 0.15 (non-HV24, non-RF)"
|
||||||
|
(condition "A.NetClass != 'HV24' && B.NetClass != 'HV24' && A.NetClass != 'RF' && B.NetClass != 'RF'")
|
||||||
|
(constraint clearance (min 0.15mm)))
|
||||||
|
(rule "HV24 to HV24"
|
||||||
|
(condition "A.NetClass == 'HV24' && B.NetClass == 'HV24'")
|
||||||
|
(constraint clearance (min 0.2mm)))
|
||||||
|
(rule "HV24 outer"
|
||||||
|
(layer outer)
|
||||||
|
(condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
|
||||||
|
(constraint clearance (min 0.3mm)))
|
||||||
|
(rule "HV24 inner"
|
||||||
|
(layer inner)
|
||||||
|
(condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
|
||||||
|
(constraint clearance (min 0.5mm)))
|
||||||
|
(rule "HV24 IC land patterns"
|
||||||
|
(layer outer)
|
||||||
|
(condition "A.Type == 'Pad' && B.Type == 'Pad' && ((A.memberOfFootprint('U2') && B.memberOfFootprint('U2')) || (A.memberOfFootprint('U20') && B.memberOfFootprint('U20')) || (A.memberOfFootprint('U25') && B.memberOfFootprint('U25')))")
|
||||||
|
(constraint clearance (min 0.15mm)))
|
||||||
|
```
|
||||||
|
Notes on the rule set:
|
||||||
|
- RF pairs resolve through the netclass implicit rules, where the larger class value wins, so the RF class clearance becomes the CPWG gap. Set HV24's class clearance to 0.3 mm so any fall-through is sane.
|
||||||
|
- Change the HV24 net list if A-01 is adopted: U2 deleted takes out `/SW_FAN` and `/BST_FAN`; U20 moved to MAIN5V takes out `/VIN_MODEM`.
|
||||||
|
- The IPC basis stands. IPC-2221B Table 6-1, 51–100 V row: B1 internal 0.1 mm, B4 external coated 0.13 mm, A6 0.13 mm. The 0.5 mm inner value is a defect/CAF margin taken from the 23-Jul lesson, not a dielectric requirement.
|
||||||
|
- Check: after the change, run KiCad Inspect → Clearance Resolution on one `/24V` ↔ GND-zone pair and one GND-zone ↔ Default pair, then refill and run DRC.
|
||||||
|
- **Remeasured worst inner-layer gaps** (non-zone copper; `hv24_gaps.py`):
|
||||||
|
|
||||||
|
| layer | gap (mm) | pair |
|
||||||
|
|---|---|---|
|
||||||
|
| In2 | 0.221 | `/IGN_IN` ↔ `/VEH5V` 1.0 mm track |
|
||||||
|
| In2 | 0.250 | `/IGN_IN` ↔ GND via |
|
||||||
|
| In2 | 0.291 | `/IGN_IN` ↔ `/FAN_PWM` |
|
||||||
|
| In2 | 0.300 | `/IGN_IN` ↔ `/5V_FAN` via |
|
||||||
|
| In1 | 0.305 | `/IGN_IN` via ↔ `/NTC2` |
|
||||||
|
| In1 | 0.500 | `/24V_IN` ↔ `/SW_5V` |
|
||||||
|
|
||||||
|
The zone gap to all 24 V nets except `/24V_IN` is 0.1505 mm. Outer layer: 12 pairs below 0.3 mm (worst `/SW_MODEM`–GND 0.150, `/VIN_MODEM`–GND 0.150, `/VIN_PROT`–`/VEH5V` 0.162). These match the auditor.
|
||||||
|
|
||||||
|
### F-02 `/IGN_IN` on In2 (primary of merge M-B; absorbs D-06, F-16)
|
||||||
|
- **Re-derived.**
|
||||||
|
- Routing: 4.08 mm F.Cu plus 106.47 mm In2, all 0.5 mm wide, with 1 via at (127.6, 50.75). P1.3 is at (177.5, 135.0) and Rig1.1 at (123.55, 50.675).
|
||||||
|
- Gap to `/VEH5V`: 0.2214 mm on In2, to track segment (147.85, 66.95).
|
||||||
|
- 23-Jul geometry (`docs/memory/drogheda-einarboard-short-incident.md`): `/24V_IN` on In2 at 0.202–0.25 mm from MAIN5V/VEH5V, **and `VEH5V↔IGN_IN` at 0.2 mm on In2**. v6 is within 0.02 mm of that geometry, on the same net pair.
|
||||||
|
- The incident's root cause was still "suspected" when the memory was written. Even so, the corrective action ("24V-to-LV ≥ 0.5–1 mm, keep 24 V off inner layers next to LV") is written into the audit brief §4-A.
|
||||||
|
- **Rating.** Blocker: it repeats a paid-for lesson, a failure would damage hardware (vehicle-fused 24 V onto LTC4040 VIN, 6 V class), and an inner-layer defect cannot be inspected or reworked. D-06's Major under-rates it.
|
||||||
|
- **Fix check.**
|
||||||
|
- Rig1 (22 k 0603, C88614) goes ≤ 3 mm of copper from P1.3. The 106 mm run then becomes `/IGN_SENSE`, limited to (36 V − 5 V)/22 k = 1.4 mA (2.5 mA at 58 V) into any bridged 5 V net. C9 at the MCU keeps τ = (22 k ∥ 2.87 k) × 100 nF = 0.25 ms.
|
||||||
|
- Add D-06's SMBJ33A (C224019, Littelfuse, DO-214AA, 9624 in stock; VR 33 V, VC 53.3 V at 11.3 A) at P1.3. It also clamps negative ISO 7637 pulses at about −1 V, which removes D-06's −27 mA PA5 injection. BAT54S becomes optional.
|
||||||
|
- Rig1 at 58 V dissipates 0.13 W for the 400 ms load dump. An 0603 thick-film part (75 V max working voltage, 2.5× short-time overload) is acceptable once the TVS is fitted; 1206 is optional.
|
||||||
|
- The In1 IGN via next to `/NTC2` goes away with the reroute.
|
||||||
|
- Conflict (≤ 3 mm vs ≤ 5 mm): use ≤ 3 mm of copper.
|
||||||
|
- **F-16 (sub-item, Minor).** `/24V_IN` on In1 is 27.11 mm of 1.5 mm track at exactly 0.500 mm from `/SW_5V`. Move it to F.Cu along the south edge, or keep ≥ 1.0 mm from LV (the upper end of Leo's rule). The `/24V` In1 track (12.75 mm) with a 0.15 mm zone gap re-pours to 0.5 mm under F-01.
|
||||||
|
|
||||||
|
### H-01 U15 package vs land
|
||||||
|
- **Re-derived.**
|
||||||
|
- JLC DB: C15846 = MAX3232ESE+T, package "SOIC-16". Compare C7605 PCF8574T, which the DB lists as "SOIC-16-300mil".
|
||||||
|
- Maxim/ADI datasheet 19-0273 Rev 10 (5/19), Ordering Information: "MAX3232ESE+ −40 °C to +85 °C 16 Narrow SO S16+5"; "MAX3232EWE+ … 16 Wide SO".
|
||||||
|
- v6 PCB U15: `SOIC-16W_7.5x10.3mm`, pads 2.05 × 0.6 mm, pad-row centres at x = 117.3 and 126.6 (9.3 mm apart). A narrow SO lead tip reaches ±3.0–3.1 mm, and the inner pad edge is at ±3.625 mm, so the leads end 0.5–0.6 mm short of the pads. The joint cannot form.
|
||||||
|
- **History, corrected.**
|
||||||
|
- V5.5 as-fabbed netlist and V5.6 netlist: U15 footprint field = SOIC-16W, the same stale field.
|
||||||
|
- The **V5 PCB** (`src/v5_current/…v5.kicad_pcb`, identical to the V5.6 PCB, which carries the V5.5 layout; U15 is placed in it) uses `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`, pads 1.95 × 0.6 at ±2.475 mm. That is the correct narrow land.
|
||||||
|
- So V5.5 boards were built on the right land, and the auditor's statement "the same combination is in V5.5 as fabbed" is wrong. v6 regressed when its PCB footprints were rebuilt from the schematic (02-Sep fresh-layout baseline, `drogheda-v6-resync-protocol`).
|
||||||
|
- A sweep of every LCSC part common to the V5 and v6 PCBs shows U15 is the **only** carried-over part whose footprint changed.
|
||||||
|
- **Fix.** Option (b): set `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm` in the v6 schematic **and** PCB, keep C15846 (genuine Maxim, 4873 in stock), and re-place C84–C88 against U15. Also fix the stale field in the V5.x schematic so a future Update-PCB cannot repeat this. C19268179 is a TECH PUBLIC clone; use it only as an alternate. Option (a), the wide part C118514 with 30 in stock, is not recommended.
|
||||||
|
|
||||||
|
### H-02 Stock
|
||||||
|
- **Re-queried** (JLC DB snapshot):
|
||||||
|
|
||||||
|
| ref | LCSC | stock | note |
|
||||||
|
|---|---|---|---|
|
||||||
|
| U10 | C729142 (SC16IS762IPW) | 15 | — |
|
||||||
|
| R53 | C131054 | 6 | first price break 20+, so JLC's 20-piece minimum cannot be met at any board quantity |
|
||||||
|
| 9 refs | C103211 (RALEC 100 k **5 %**) | 702 | 9 per board → 78 boards maximum |
|
||||||
|
| U19 | C18548276 (A7670SA) | 96 | — |
|
||||||
|
| U18 | C5120257 (ZED-F9P-04B) | 104 | — |
|
||||||
|
| J14 | C2977286 | 10 890 | category "Pre-ordered Products", so it must be pre-ordered into the JLC account |
|
||||||
|
- **Drop-in check.**
|
||||||
|
- C57156 SC16IS752IPW,128: same TSSOP-28, same pinout and registers. U10 runs in **I²C mode** (pin 9 = 3V3, `ic_pins_U10.csv`); in I²C mode the 752 and 762 are identical, and they differ only in SPI/IrDA top speed. The value field already says 752. 2670 in stock. ✅
|
||||||
|
- C177479 HKR RCT03499KFLF: 499 k, 1 %, 100 ppm, 0603, 100 mW, 75 V. The same rating as YAGEO RC0603FR-07499KL. 26 862 in stock. ✅
|
||||||
|
- C25803 UNI-ROYAL 100 k 1 % (Basic, 10.8 M) replaces the 5 % C103211. That is an upgrade: R87 sets 3V3_ETH, R20 sets the fan output. ✅
|
||||||
|
- **Rating.** Blocker only as an order gate for U10/R53 (both swaps are free and carry no design risk). C103211, U19, U18 and J14: Major, re-check on order day against the order quantity.
|
||||||
|
|
||||||
|
### F-03 U25 hot loop (merge M-D)
|
||||||
|
- **Re-derived** (`fcu_islands.py`):
|
||||||
|
- F.Cu GND copper (pour + GND pads + GND tracks) forms 55 pieces.
|
||||||
|
- U25.9 (EP), U25.7 and D34.2 sit on piece "east", 3766 mm² with 5 GND vias. The nearest on-piece via is 29.5–30.4 mm from the EP and 37.9 mm from D34.2.
|
||||||
|
- C149.2, C150.2 and C151.2 sit on the 270 mm² U6 piece (5 vias, nearest 9.4–11.4 mm).
|
||||||
|
- C150.1 → U25.2 = 2.88 mm; D34.1 → U25.8 = 4.28 mm; L22.1 → U25.8 = 13.75 mm.
|
||||||
|
- The auditor's "nearest GND via 28 mm" is correct as an on-island figure. Straight-line, the nearest GND via is 14.4 mm, but it sits on another island.
|
||||||
|
- **Fix.** See the M-D layout instruction below.
|
||||||
|
|
||||||
|
### F-04 Module grounds (merge M-C)
|
||||||
|
- **Re-derived** (`vias_cnt.py`):
|
||||||
|
- U19: 39 GND pads, of which 20 are 2.1 × 2.1 mm centre pads. 1 GND via under the courtyard, 4 in a 5 mm ring.
|
||||||
|
- U18: 56 GND pads, 0 vias under the courtyard, 5 in the ring.
|
||||||
|
- East piece: pour points to the nearest GND via have median 10.4 mm, p90 19.8 mm, maximum 29.5 mm.
|
||||||
|
- **Rating.** Confirmed Major. I disagree with B-04's Blocker. No R1–R5 item is violated outright, there is no V5.5 field precedent for an on-board modem, and there is no damage path. It is still a zero-BOM-cost must-do alongside the Blockers.
|
||||||
|
|
||||||
|
### F-05 In1 plane
|
||||||
|
- **Re-derived** (`in1cross.py`):
|
||||||
|
- In1 fill is 11 370.5 mm²: 18.8 % void against 14 000 mm², or 17.4 % against the 139 × 99 mm usable area.
|
||||||
|
- In1 carries 1571.9 mm of tracks from 49 nets.
|
||||||
|
- Length of each F.Cu net over In1 voids:
|
||||||
|
|
||||||
|
| net | length over void | notes |
|
||||||
|
|---|---|---|
|
||||||
|
| USB_DP / USB_DM | 10.4 / 9.7 mm | directly over `/24V_IN` and `/SW_5V` |
|
||||||
|
| I2C_SDA | 25.2 mm | 14.2 mm directly over `/SER_TXB` |
|
||||||
|
| ETH_XO | 8.3 mm | 6.95 mm over `/ETH_RST` |
|
||||||
|
| NRST | 21.1 mm | 7.2 mm over `/USART6_RX` |
|
||||||
|
| DFU_DM | 13.2 mm | — |
|
||||||
|
| SIMB_CLK | 9.1 mm | 5.8 mm over `/SW_5V` |
|
||||||
|
| DOUT_4G_M | 13.1 mm | — |
|
||||||
|
| RF_GNSS / RF_ANT_* | 0 mm ✅ | — |
|
||||||
|
- **Correction to the fix (scope).** A full "In1 = plane" re-layout is ideal. The minimum is to clear In1 under the USB pairs, the crystals and their lines, all switch nodes, VBAT_MODEM/the RF area, SIM, and the three broadside parallels listed above. Acceptance: ≤ 3 In1 islands, and no critical net over a void longer than 1 mm.
|
||||||
|
|
||||||
|
### F-06 RF feeds (merge M-E; absorbs B-05, C-05)
|
||||||
|
- **Re-derived.**
|
||||||
|
- `/RF_LTE` = 4.01 mm F.Cu + 22.14 mm In1. `/RF_ANT_LTE` = 5.62 mm F.Cu.
|
||||||
|
- GND vias within 3.5 mm of the 31.5 mm LTE path: 1. Within 3.5 mm of the 27.2 mm GNSS path: 2.
|
||||||
|
- GNSS bias line `/VCC_RF_GNSS` beside `/RF_GNSS` (`rfpar.py`): minimum edge gap 0.274 mm; 3.25 mm of run at ≤ 0.3 mm, 13.4 mm at ≤ 0.5 mm, 17.9 mm within 1 mm. The auditor's "16.7 mm at 0.27 mm" overstates it; BCE's "≈ 0.46 mm for 10 mm" is closer.
|
||||||
|
- **Impedance** (`z0.py`, Hammerstad-Jensen with thickness correction; CPWG by conformal mapping without thickness).
|
||||||
|
|
||||||
|
Assumed stackup **JLC04161H-7628**: L1–L2 7628 prepreg 0.2104 mm, εr 4.4; core 1.065 mm; outer 1 oz, inner 0.5 oz.
|
||||||
|
|
||||||
|
| geometry | JLC04161H-7628 | file stackup (0.48 mm, εr 4.5) |
|
||||||
|
|---|---|---|
|
||||||
|
| 0.5 mm microstrip | **42.1 Ω** (εeff 3.41) | 66.6 Ω |
|
||||||
|
| CPWG 0.5 mm / 0.15 mm gap (as built) | 41.0 Ω | — |
|
||||||
|
| CPWG 0.30 / 0.20 | 56.6 Ω bare | — |
|
||||||
|
| CPWG 0.35 / 0.20 | 52.1 Ω bare | — |
|
||||||
|
|
||||||
|
BCE's FD solver gives 53.3 Ω bare and 48.4 Ω masked for 0.30/0.20; closed forms read 2–4 Ω high. The In1 LTE section is ≈ 30–47 Ω, varying with F.Cu coverage, which agrees with BCE's 32.5/47.1 Ω.
|
||||||
|
- **Fix, conflict resolved.** Start from CPWG w 0.30 mm / gap 0.20 mm on F.Cu over solid In1 and finalise in JLC's calculator with impedance control ordered. Via fence ≤ 3 mm pitch (λg/20 = 3.1 mm at 2.69 GHz, εeff 3.2), ≤ 1 mm from the gap edge, 2 vias per U.FL GND pad. Keep `/VCC_RF_GNSS` ≥ 1 mm from the RF line, with a stitched GND strip between. Set the real stackup in Board Setup.
|
||||||
|
|
||||||
|
### F-07 U20 GND neck (merge M-D; = B-06)
|
||||||
|
- **Re-derived.** The GND track (0.25 mm) runs C128.2 (142.5, 60.93) → (143.525, 61.955) → (145.3225, 61.955) → (151.02, 62.1) and joins the EP (147.5, 63.205; 3.2 × 2.5 mm). At y = 61.955 it passes between U20.1 (y 61.305, pad 0.6 mm wide) and U20.2 (y 62.575). Gaps: 0.225 mm to pin 1 and 0.195 mm to pin 2.
|
||||||
|
- **Fix.** Confirmed. C128 and C127 GND pads go on solid F.Cu bonded to the EP, with EP vias (see M-C).
|
||||||
|
|
||||||
|
### F-08 U2 input caps
|
||||||
|
- **Re-derived.** U2.7 (MP1584 VIN) to C11 = 20.75 mm, C22 = 18.33 mm, C10 = 17.04 mm. Dbk1 6.51 mm. The EP (solid) has 0 vias and its nearest GND via is 19.7 mm away.
|
||||||
|
- **Fix.** Confirmed. The item is moot if A-01 deletes U2.
|
||||||
|
|
||||||
|
### F-09 U12 (correction)
|
||||||
|
- **Re-derived.** U12 is an MP1584EN: pin 2 = EN (tied to `/SYS5V`), pin 7 = VIN.
|
||||||
|
- C101.1 → U12.7 = **6.40 mm** (A-06 had this right; FHJ's 1.77 mm was measured to EN).
|
||||||
|
- D11 → U12.1 = 11.92 mm; L8 = 15.10 mm; R87 (FB top) = 25.9 mm.
|
||||||
|
- C101.2 is on the 224 mm² piece and D11.2 on the 178 mm² piece.
|
||||||
|
- **Why it matters.** This is the same R5 🟠 item that was 8.5 mm on V5.5, and it is still > 3 mm.
|
||||||
|
|
||||||
|
### F-12 Stitching (merge M-C)
|
||||||
|
- **Re-derived.**
|
||||||
|
- GND vias per 20 mm cell, rows from y 40.32:
|
||||||
|
```
|
||||||
|
[0,5,4,3,0,1,0]
|
||||||
|
[2,3,4,4,4,0,2]
|
||||||
|
[2,1,2,3,0,1,3]
|
||||||
|
[0,2,2,2,0,2,4]
|
||||||
|
[4,5,0,2,2,0,0]
|
||||||
|
```
|
||||||
|
That is 10 of 35 cells empty. GND vias within 3 mm of the edge: 2.
|
||||||
|
- My grid matches the auditor's exactly.
|
||||||
|
- **Target, corrected.** 480 mm of perimeter at 5 mm pitch needs ≈ 96 vias. The 7890 mm² of F.Cu GND copper at 1 via per 25 mm² needs ≈ 316. Target **≥ 400**, not 500–600.
|
||||||
|
|
||||||
|
### F-13 EP vias and pad connection (primary of merge M-C)
|
||||||
|
- **Re-derived.**
|
||||||
|
- All 5 zones use default thermal relief (gap 0.5, spoke 0.5).
|
||||||
|
- Pad-level solid overrides exist only on U6.25, U2.9, U12.9, U11.9, U11.29 and JP1–JP5.
|
||||||
|
- Vias inside the EP: 0 on U6, U25, U20, U2 and U12.
|
||||||
|
- **Correction.** A board-wide `(connect_pads thru_hole_only …)` would make the 23 × 0402 and 142 × 0603 GND pads solid, which is a tombstoning risk. Instead set pad-level `zone_connect` solid on the EPs, all U18/U19 GND pads, D34/Dbk1/D11 anodes and the buck Cin/Cout GND pads. Keep the zone default thermal (≥ 2 spokes) for small passives.
|
||||||
|
- **Via arrays, corrected for fit** (0.3 mm drill / 0.6 mm pad at 1.0 mm pitch):
|
||||||
|
- U25 and U20 EPs are 3.2 × 2.5 mm. A 3 × 3 array at 1.0 mm pitch needs 2.6 mm, so it does **not** fit the 2.5 mm side (F-03's claim is wrong). Use 2 × 3 = 6, or 2 × 4 = 8 at 0.8 mm pitch with 0.3/0.5 vias.
|
||||||
|
- U6 EP is 2.65 × 3.65 mm: 3 × 3 at 0.9 × 1.2 mm fits and meets ECO D2's ≥ 9.
|
||||||
|
- U2 and U12 EPs are 2.29 × 3.0 mm: 2 × 3 fits.
|
||||||
|
|
||||||
|
### H-03 MWSA0804S on the SRU8028 land
|
||||||
|
- **Re-derived.**
|
||||||
|
- Land: pads 2.0 (along the axis) × 3.2 mm at ±3.9 mm, spanning 2.9–4.9 mm from centre (KiCad `L_Bourns-SRU8028`, also confirmed from the GitHub library copy).
|
||||||
|
- Sunlord MWSA-S spec Table 4-1 row MWSA0804S: A 8.2 ± 0.3, B 8.8 ± 0.4, C 3.8 ± 0.2, D 1.4 ± 0.3, E 5.0 ± 0.3; land I 2.75 / J 4.0 / H 5.5 (typ).
|
||||||
|
- The figure that defines H/I/J could not be read: the LCSC, Digikey and alfatec PDFs are blocked from this sandbox or render text only.
|
||||||
|
- Electrode overlap is 86–100 % along the axis (depending on whether the 8.2 or the 8.8 side carries the electrodes) × 64 % across (3.2 / 5.0), so **55–64 %** of the electrode area is wetted.
|
||||||
|
- **Rating.** V5.5 used exactly this pairing on L2, L6, L7 and L8 (V5 PCB: C17700165/C17700171 on `L_Bourns-SRU8028`), and 15 boards were assembled and run. Pad area per joint is ≈ 3.8 mm²; SAC shear strength at ≈ 30 MPa gives ≈ 100 N against ≈ 0.1 N/g inertial load, so strength is not the problem. The V5.5 "modem dark on battery" was root-caused to back-feed and UVLO (FW 0.5.5/0.5.6), not to inductor joints. **Minor.**
|
||||||
|
- **Fix.** Change the footprint, not the part. The SRU8028-class Bourns parts have lower Isat than MWSA0804S-2R2 for L6. Build `Drogheda-v6:IND-SMD_MWSA0804S` from the LCSC drawing (Leo or Michelle can open it) while L6/L20 are being re-placed anyway (A-02/M-D).
|
||||||
|
|
||||||
|
### H-04 U25 `LCSC Part`
|
||||||
|
- **Re-derived.**
|
||||||
|
- v6 PCB fields: 14 footprints carry `LCSC Part`, all inherited from the easyeda `Drogheda-v6.pretty` footprints. U25 is the only one whose value differs from `LCSC` (C2071691 vs C524806).
|
||||||
|
- Source: `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` line 12, `(property "LCSC Part" "C2071691")`. U20 and U25 share this footprint.
|
||||||
|
- Fabrication-Toolkit `plugins/process.py::_get_mpn_from_footprint` builds its key list as `['LCSC Part #','LCSC Part', …]` + fallback `['LCSC', …]` and returns the first non-empty field.
|
||||||
|
- The 25-Sep pre-fab audit says "Generate BOM/CPL from the board … (Fabrication Toolkit)", and the V5.5 `production/` folder is the toolkit's output folder.
|
||||||
|
- **Consequence.** U25 would be ordered as the AP64350. It is pin-compatible (1 BST, 2 VIN, 3 EN, 4 RT/CLK, 5 FB, 6 COMP, 7 GND, 8 SW) with the same 0.8 V FB, so it passes the bench and then fails at the first transient above 40 V. **Blocker** (damage risk).
|
||||||
|
- **Fix.** Delete `LCSC Part` from U25 on the board **and** from the library footprint, or delete it from all 10 `Drogheda-v6.pretty` footprints. Alternatively generate the BOM from the schematic (`kicad-cli`); `evidence/bom.csv` is correct.
|
||||||
|
|
||||||
|
### J-01
|
||||||
|
- Same root cause as F-01. Merged (M-A).
|
||||||
|
|
||||||
|
### J-02 Track widths
|
||||||
|
- **Sampled.** All 16 flagged nets, `widths.py`. Criterion: IPC-2221 k = 0.048 (≈ IPC-2152 baseline) at ΔT 20 °C; outer 1 oz; **inner 0.5 oz** (JLC04161H default, not the file's 1 oz). Design currents: BAT_PLUS/SW_BAT 4.2 A (backup), MAIN5V/VEH5V/VIN_SW 2.5 A, VBAT_MODEM 2 A, VIN_MODEM 1.8 A, SYS5V 0.8 A, fans ≤ 0.3 A, SW_5V/SW_IN 0.25 A, 3V3_ETH 0.15 A.
|
||||||
|
- **Length under capacity:**
|
||||||
|
|
||||||
|
| net | length under capacity | notes |
|
||||||
|
|---|---|---|
|
||||||
|
| BAT_PLUS | 123 mm | incl. 69.9 mm of In2 1.0 mm ≈ 1.45 A |
|
||||||
|
| MAIN5V | 111 mm | — |
|
||||||
|
| VEH5V | 102 mm | incl. In2 1.0 mm 66.6 mm |
|
||||||
|
| SW_BAT | 12.9 mm | all of it |
|
||||||
|
| VIN_SW | 26 mm | — |
|
||||||
|
| VBAT_MODEM | 12.5 mm | — |
|
||||||
|
| VIN_MODEM | 0.1 mm | neck only, and bursts are RMS-light |
|
||||||
|
| 3V3_ETH, fan nets, SW_5V, SW_IN, SYS5V, VIN_PROT, VIN_FUSED | 0 mm | benign |
|
||||||
|
|
||||||
|
So **6 nets are real**, carrying 63 DRC hits (vs the auditor's 59 with VIN_MODEM counted). The conclusion stands and is stronger for the inner layers.
|
||||||
|
- **Fix.** The copper is owned by A-02 (SW_BAT/BAT_PLUS, R5 🔴, Blocker), A-07 (VEH5V/VIN_SW/MAIN5V) and B-08 (VBAT_MODEM). Either order 1 oz inner copper or widen inner runs by 1.65×. J-02's residual item (relax T15 for the benign nets) is Minor.
|
||||||
|
|
||||||
|
### D-01 F9P back-power via U24 (merge M-G; absorbs C-06)
|
||||||
|
- **Re-derived.**
|
||||||
|
- `/DOUT_4G` = {U24.7 (1B), R106.1, R107.2 DNP, U18.26 RXD2}. U24 has VCCA = `/1V8_MODEM`, VCCB = `/3V3` (always on) and DIR = VCCA.
|
||||||
|
- `/3V3_GNSS` = U21 out plus U18.33/34 only.
|
||||||
|
- ZED-F9P-04B datasheet UBX-21044850 R05 Table 14: input pin voltage −0.5 … VCC + 0.5 V for VCC ≤ 3.1 V. At VCC = 0, a 3.3 V push-pull high exceeds that by 2.8 V.
|
||||||
|
- The 74LVC2T45's VCC isolation protects the modem side only (U23), not U24's B output into a dead load.
|
||||||
|
- Same mechanism as the V5.5 FW 0.5.5 lesson (CHANGELOG: an idle-high UART held the simpleRTK2B/modem rails up through ESD diodes, so no POR), now built into hardware.
|
||||||
|
- **Rating.** Major, not Blocker: firmware sequencing (modem off before F9P off, never F9P-only cycles with the modem up) avoids it, as the ECO A sequence does.
|
||||||
|
- **Fix check.**
|
||||||
|
- The 10 k series-R alternative injects ≈ 0.28 mA. That is the same order as the leakage that held the V5.5 modem rail at ≈ 1 V (0.5.6: `3V3_MODEM = 0.99 V`), so it does not reliably protect the F9P's 20–8000 µs/V ramp.
|
||||||
|
- Use the gate: **C12518 Nexperia 74LVC1G125GV,125** (SOT-753; pin 1 OE, 2 A, 3 GND, 4 Y, 5 VCC; datasheet Rev 17.1: "IOFF circuitry provides partial Power-down mode operation", IOFF ±2 µA max). Power it from `/3V3_GNSS`, OE tied to GND, with 100 nF C14663. C3040595 is a TECH PUBLIC clone and should not be relied on for Ioff.
|
||||||
|
- Keep PC7/R106 on `/DOUT_4G`. Moving U24's VCCB to `/3V3_GNSS` is not an option: MODEM_STATUS and the RTCM tap would die with the F9P off (R2).
|
||||||
|
- Rdfu1 22 k → 100 k (C25803) still leaves ≈ 27 µA into U18.27. Bench-check `/3V3_GNSS` with PA1 low and the modem on: it must read < 0.3 V.
|
||||||
|
|
||||||
|
### D-06
|
||||||
|
- Merged into F-02 (M-B). Rated Blocker there.
|
||||||
|
|
||||||
|
### G-01 Mounting holes
|
||||||
|
- **Re-derived.**
|
||||||
|
- V5 PCB holes: MH5 (65.2, 45.3), MH6 (65.2, 135.3), MH4 (193.2, 90.3), MH7/9/10/11 (M2.5 shield/heatsink).
|
||||||
|
- v6 holes: MH5, MH6, MH7 (195.2, 45.3), MH8 (195.2, 135.3).
|
||||||
|
- At (193.2, 90.3) on v6: the L6 courtyard contains the point (0.0 mm), L6.2 `/BAT_PLUS` pad centre is 2.44 mm away, R133 is 1.75 mm away.
|
||||||
|
- Design brief v1.0: "Keep 140.000 × 100.000 mm — no enclosure rework". Memory `drogheda-v6-zed-f9p-integration`: "MH4/5/6 (enclosure) and MH11 (heatsink clamp) survive". Phase-2 delta: "KEEP MH11 and add one partner near U19".
|
||||||
|
- **Also missing:** MH11 at (168.3, 84.6), which now sits 0.6 mm from the U19 courtyard, and its partner. These are the modem heatsink clamp holes for thermal gate T1.
|
||||||
|
- **Rating.** Blocker unless Leo confirms a new backplate. The documented intent was to reuse the V5.5 enclosure.
|
||||||
|
- **Fix.** Restore MH4 at (193.2, 90.3). L6 has to move anyway (A-02: ≤ 5 mm from U6). Decide on the heatsink-clamp pair near U19. Keep a ≥ 4 mm copper-free radius or use nylon washers.
|
||||||
|
- **Input needed from Leo:** the backplate hole pattern.
|
||||||
|
|
||||||
|
### G-02 J9 ESD (merge M-F; absorbs B-07's ESD part and F-14's J9 part)
|
||||||
|
- **Re-derived.** Nets are as stated, with no protection device.
|
||||||
|
- **Fix check.** C7519 USBLC6-2SC6 (ST, SOT-23-6L, 1415 in stock). Pinout: 1/6 I/O1 → USB_DM, 3/4 I/O2 → USB_DP, 5 VBUS, 2 GND. Routing conflict resolved: ≤ 3 mm of copper from the J9 pads, flow-through, with GND via ≤ 1 mm. The pair-split part of B-07 goes to F-17 (Minor).
|
||||||
|
|
||||||
|
### D-02 HSE crystal
|
||||||
|
- **Re-derived.**
|
||||||
|
- Y3 pad edge to U16.5/U16.6 = 8.32/11.30 mm. DG's 10.30/14.21 mm are pad-centre figures.
|
||||||
|
- C14872: CL 20 pF, **−20…+70 °C** rating.
|
||||||
|
- gm_crit = 4·ESR·(2πf)²·(C0 + CL)² = 1.21 mA/V (ESR 40 Ω, C0 5 pF, CL_eff 12.5 pF) to 2.37 mA/V (C0 7 pF, CL_eff 17.5 pF), against Gm_crit_max 1 mA/V. It passes at typical ESR.
|
||||||
|
- **Rating.** Minor (Leo's 🟡).
|
||||||
|
- **Fix check.**
|
||||||
|
- C2901684 (SCTF 3225, CL 10 pF, ESR 30 Ω, −40…+85 °C, 11 076 in stock) with 12 pF C38523 gives 0.46 mA/V ✅.
|
||||||
|
- Preferred: **C9006** (YXC 3225, CL 12 pF, **Basic**, 528 k in stock, −40…+85 °C) with 15 pF (C1644) gives CL_eff ≈ 11.5 pF and ≈ 0.77 mA/V at ESR 40 Ω. Confirm its ESR on the LCSC PDF.
|
||||||
|
- The −20…+70 °C rating of C14872 in a sealed port box is a further reason to swap it.
|
||||||
|
|
||||||
|
## Duplicates / merges proposed
|
||||||
|
|
||||||
|
| Merge | Primary | Absorbs | Severity | Single fix |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| **M-A 24 V rules** | F-01 | J-01, F-15 (outer spots become DRC findings), B-12 (netclass part) | Blocker | Netclass table plus the corrected `.kicad_dru` above, then refill and DRC as the gate. Re-check that the classes survive every GUI save. |
|
||||||
|
| **M-B 24 V on inner layers** | F-02 | D-06, F-16 | Blocker | Rig1 ≤ 3 mm from P1.3, plus SMBJ33A C224019 at P1.3. `/24V_IN` In1 run moved to F.Cu, or ≥ 1.0 mm from LV. |
|
||||||
|
| **M-C Ground vias / pad connection** | F-13 | F-04, F-12, B-04, C-03, A-06 (EP/via part) | Major (U6 EP → A-02 Blocker) | Layout instruction L1–L6 below. |
|
||||||
|
| **M-D Buck hot loops** | F-03 | F-07, B-06, F-08, F-09, A-06 (loop part) | Major | Layout instruction L7 below. |
|
||||||
|
| **M-E RF feeds** | F-06 | B-05, C-05 | Major | CPWG 0.30/0.20 on F.Cu over solid In1, fence ≤ 3 mm, real stackup, impedance control. |
|
||||||
|
| **M-F J9 ESD** | G-02 | B-07 (ESD), F-14 (J9 part) | Major | USBLC6-2SC6 C7519 ≤ 3 mm from J9, flow-through. |
|
||||||
|
| **M-G F9P back-power** | D-01 | C-06 | Major | 74LVC1G125 C12518 on `/3V3_GNSS` at U18.26; Rdfu1 → 100 k. |
|
||||||
|
| **M-H Power copper** | A-02 / A-07 / B-08 | J-02 | per owner | Widen/pour the 6 nets; 1 oz inner or 1.65× width on inner layers. |
|
||||||
|
| **M-I U25 BOM field** | H-04 | A-15 | Blocker | Delete `LCSC Part` (board + library). |
|
||||||
|
|
||||||
|
**Layout instruction for Michelle (M-C/M-D), quantified:**
|
||||||
|
- **L1 EP vias** (0.3 mm drill / 0.6 mm pad, tented on B.Cu, or JLC via-in-pad filled and capped):
|
||||||
|
- U6: 3 × 3 = 9 at 0.9 × 1.2 mm (ECO D2)
|
||||||
|
- U25, U20: 2 × 3 = 6 at 1.0 mm (8 at 0.8 mm with 0.3/0.5 mm vias)
|
||||||
|
- U2, U12: 2 × 3 = 6
|
||||||
|
- Every EP pad gets `zone_connect` solid.
|
||||||
|
- **L2 U19 A7670SA:** one via in each gap between adjacent 2.1 mm centre GND pads (1.7 mm gap, leaving 0.55 mm clearance) plus a via ring on the perimeter GND pads. **≥ 30, target 40**, tented, never in pads.
|
||||||
|
- **L3 U18 ZED-F9P:** vias at the diagonal interstitial points of the 2.1 mm-pitch GND array. 0.3/0.6 mm vias leave 0.41 mm to the pad corners. **≥ 24.** All GND pads of U18 and U19 solid.
|
||||||
|
- **L4 Stitching:**
|
||||||
|
- Every F.Cu GND island ≥ 20 mm² gets ≥ 2 vias.
|
||||||
|
- No F.Cu GND pour point more than 5 mm from a GND via (today: median 10.4 mm, maximum 29.5 mm in the east pour).
|
||||||
|
- Edge fence at ≤ 5 mm pitch within 1.5 mm of the edge clearance, ≈ 96 vias.
|
||||||
|
- Board total **≥ 400 GND vias** (today 69, V5.5 165). Acceptance: 0 empty 20 mm cells.
|
||||||
|
- **L5 RF:** fence ≤ 3 mm pitch on both sides of RF_LTE/RF_ANT_LTE and RF_GNSS/RF_ANT_GNSS, ≤ 1 mm from the gap edge. 2 vias ≤ 1 mm from each U.FL GND pad (J12, J13) and at D28.
|
||||||
|
- **L6 Small passives:** leave them on thermal relief (23 × 0402), not solid.
|
||||||
|
- **L7 Hot loops** (U25, U20, U12, and U2 if it stays):
|
||||||
|
- Cin (VIN and GND pads) ≤ 2 mm from the IC VIN and GND/EP pins. The Cin GND, the diode anode (D34/D11/Dbk1) and the EP on **one solid F.Cu area**, with no GND neck narrower than 1 mm.
|
||||||
|
- ≥ 2 vias ≤ 1 mm from each Cin GND pad.
|
||||||
|
- Catch diode ≤ 3 mm from SW. Inductor ≤ 5 mm from SW. SW copper ≤ 25 mm².
|
||||||
|
- FB divider ≤ 3 mm from the FB pin, with nothing on In1 under the SW copper.
|
||||||
|
- Acceptance: each input loop ≤ 1 cm² (Copper Plan §2); today U25 ≈ 3.1 cm².
|
||||||
|
|
||||||
|
## Fix conflicts resolved
|
||||||
|
1. **F-02 ≤ 3 mm vs D-06 ≤ 5 mm (Rig1).** Use ≤ 3 mm of copper, and add the D-06 TVS.
|
||||||
|
2. **Severity, F-02 Blocker vs D-06 Major.** Blocker.
|
||||||
|
3. **H-04 Major vs A-15 Minor.** Blocker (Fabrication Toolkit key order is proven in the source).
|
||||||
|
4. **F-04 Major vs B-04 Blocker.** Major. The U6 EP is the Blocker part, owned by A-02.
|
||||||
|
5. **D-01 Major vs C-06 Minor.** Major. The gate (C12518) replaces the series-R option.
|
||||||
|
6. **EP via counts** (F-03 "3 × 3 at 1.0 mm", A-06 "4 × 2", F-13 "3 × 3").
|
||||||
|
- U25/U20: 6 at 1.0 mm, or 8 at 0.8 mm. 3 × 3 at 1.0 mm does not fit 2.5 mm.
|
||||||
|
- U6: 9.
|
||||||
|
7. **Stitching count** (F-12 500–600). ≥ 400 with the acceptance criteria above.
|
||||||
|
8. **CPWG geometry** (F-06 0.30–0.35/0.20–0.25; B-05 0.30/0.20). 0.30/0.20 as the starting point (FD solver 48.4 Ω masked), finalised in the JLC calculator.
|
||||||
|
9. **J9 ESD distance** (G-02 ≤ 3 mm, B-07 ≤ 5 mm). ≤ 3 mm.
|
||||||
|
10. **Proposed `.kicad_dru`** (FHJ). Add the HV24↔HV24 rule, or 4 false errors will appear.
|
||||||
|
|
||||||
|
## Anything else you noticed
|
||||||
|
- **U12 Cin (F-09):** the auditor measured to the EN pin. The real VIN loop is 6.40 mm, so R5 🟠 item 4 is still open on U12. A-06's figure was right.
|
||||||
|
- **H-01 is a regression, not a legacy defect.** The V5.x schematics still carry the stale SOIC-16W field. Fix the field in both v6 and V5.x so a future Update-PCB on V5.6 does not break the working V5.5 land.
|
||||||
|
- **Inner copper weight.** JLC04161H-7628 ships 0.5 oz inner by default, while the file stackup says 1 oz everywhere. That lowers inner-layer current capacity by ≈ 40 % (A-07/J-02). Order 1 oz inner or widen. Record it with the stackup decision (F-06).
|
||||||
|
- **Zone clearance field 0.3 mm is not honoured by the current fills** (0.1505 mm measured). After M-A, verify with Inspect → Clearance Resolution that the GND pour keeps the intended gap to RF (CPWG gap) and to HV24.
|
||||||
|
- No REFUTED items and no new Blocker beyond the severity changes above (H-04 ↑Blocker, D-06 ↑Blocker, G-01 Blocker-conditional).
|
||||||
|
|
||||||
|
## Inputs needed from Leo
|
||||||
|
1. Backplate/enclosure hole pattern: are the V5.5 standoffs (incl. (193.2, 90.3)) reused, and is the modem heatsink clamp still planned (MH11 + partner)? (G-01)
|
||||||
|
2. BOM tool for the JLC order: Fabrication Toolkit (board fields) or kicad-cli (schematic fields)? H-04 is a Blocker in either case until the field is deleted.
|
||||||
|
3. Stackup and copper: JLC04161H-7628 with impedance control, and 1 oz inner? (F-06, J-02)
|
||||||
|
4. Order quantity: this decides whether C103211, U19 and U18 limit the order (H-02).
|
||||||
@ -0,0 +1,329 @@
|
|||||||
|
---
|
||||||
|
title: HBOX EinarBoard V5.6 — Pinout de arneses y conectores
|
||||||
|
project: Project Drogheda
|
||||||
|
date: 2026-09-29
|
||||||
|
version: "1.0"
|
||||||
|
tags: [project-drogheda, hardware, harness, pinout, einarboard, v5.6]
|
||||||
|
---
|
||||||
|
|
||||||
|
# HBOX EinarBoard V5.6 — Pinout de arneses y conectores
|
||||||
|
|
||||||
|
Auto-generated from the PCB netlist (placement-independent) / **Generado automáticamente desde la netlist del esquemático** (independiente de la colocación). `GND` = plano de tierra de la tarjeta; su lista completa de pads se omite. Las nets de potencia van marcadas ⚡ para elegir calibre de cable. Se omiten las banderas `PWR_FLAG` (PFx).
|
||||||
|
|
||||||
|
| Netlist | Valor |
|
||||||
|
|---|---|
|
||||||
|
| Archivo | `03-Architecture-Hardware/kicad/_to_delete/v56-work-20260928/p5ntc-after.xml` (exportada de `kicad/hbox-watchdog-v5.kicad_sch` con la ECO V5.6 aplicada, Eeschema 10.0.4, 2026-09-28 17:43) |
|
||||||
|
| SHA-256 | `45d3f034a327f8176bd76bf8d95698e21c3e3f914726b2648fcd80cc538e42a7` |
|
||||||
|
| Aplica a | **V5.6** (lote por pedir). Para V5.5 as-fabbed (lote 22-ago, 15 pzas) ver la sección «Diferencias V5.5 → V5.6» al final. |
|
||||||
|
|
||||||
|
## Resumen de conectores
|
||||||
|
|
||||||
|
| Conn | Función | Pines | Tipo (huella) |
|
||||||
|
|---|---|---|---|
|
||||||
|
| **P1** | GX16-5 | 5 | `TerminalBlock_Phoenix_MKDS-1,5-5_1x05_P5.00mm_Horizontal` |
|
||||||
|
| **P2** | 5V-IN-SD15B05 | 2 | `JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical` |
|
||||||
|
| **P4** | BATT-1S4P+NTC | 3 | `JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical` |
|
||||||
|
| **P6** | FAN 2-pin | 2 | `JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical` |
|
||||||
|
| **P8** | PANEL_LED | 2 | `JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical` |
|
||||||
|
| **P10** | RESET-EXT | 2 | `JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical` |
|
||||||
|
| **P11** | CUTOFF-SW | 2 | `JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical` |
|
||||||
|
| **P12** | NTC-HOTSPOT | 2 | `JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical` |
|
||||||
|
| **P14** | RGB_LED_EXT | 4 | `JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical` |
|
||||||
|
| **P15** | RS485_OUT | 3 | `PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical` |
|
||||||
|
| **P16** | RS232_OUT | 3 | `PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical` |
|
||||||
|
| **H4** | TTL_UARTB | 4 | `PinHeader_1x04_P2.54mm_Vertical` |
|
||||||
|
| **J11** | USB-C DFU | 15 | `USB_C_Receptacle_GCT_USB4085` |
|
||||||
|
| **J9** | USB-C | 15 | `USB_C_Receptacle_GCT_USB4085` |
|
||||||
|
| **J10** | HR911105A | 13 | `RJ45_Hanrun_HR911105A_Horizontal` |
|
||||||
|
| **J7** | XBEE-ROW-1 (VCC/DOUT/DIN) | 10 | `PinSocket_1x10_P2.00mm_Vertical` |
|
||||||
|
| **J8** | XBEE-ROW-2 | 10 | `PinSocket_1x10_P2.00mm_Vertical` |
|
||||||
|
| **MOD1** | simpleRTK2B-Pro on UNO female headers | 32 | `Arduino_UNO_R3` |
|
||||||
|
|
||||||
|
## Conectores de arnés (P)
|
||||||
|
|
||||||
|
### P1 — GX16-5
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `24V_IN` ⚡potencia | D10.1, Q10.2 |
|
||||||
|
| 2 | `GND` | plano de tierra |
|
||||||
|
| 3 | `IGN_IN` | Rig1.1 |
|
||||||
|
| 4 | `GND` | plano de tierra |
|
||||||
|
| 5 | — | *(sin net)* |
|
||||||
|
|
||||||
|
### P2 — 5V-IN-SD15B05
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `VEH5V` ⚡potencia | C30.1, C31.1, C78.1, JP1.2, R7.1, R51.1, R55.1, RS1.1, U6.16, U6.6 |
|
||||||
|
| 2 | `GND` | plano de tierra |
|
||||||
|
|
||||||
|
### P4 — BATT-1S4P+NTC
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `BAT_PLUS` ⚡potencia | C35.1, L6.2, R5.1, U6.23 |
|
||||||
|
| 2 | `GND` | plano de tierra |
|
||||||
|
| 3 | `NTC` | R55.2, R113.1, U6.17 |
|
||||||
|
|
||||||
|
### P6 — FAN 2-pin
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `5V_FAN` ⚡potencia | C23.1, D2.1, JP1.1, L2.2, R20.1 |
|
||||||
|
| 2 | `FAN_RET` | D2.2, Q2.3 |
|
||||||
|
|
||||||
|
### P8 — PANEL_LED
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `LED_A` | D1.2, R3.2 |
|
||||||
|
| 2 | `LED_K` | D1.1, Q4.3 |
|
||||||
|
|
||||||
|
### P10 — RESET-EXT
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `NRST` | C104.1, SW1.1, TP5.1, U16.7 |
|
||||||
|
| 2 | `GND` | plano de tierra |
|
||||||
|
|
||||||
|
### P11 — CUTOFF-SW
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `MAIN5V` ⚡potencia | C32.1, C33.1, C34.1, JP2.1, JP3.3, JP4.1, JP6.1, Q7.5, Q7.6, Q7.7, Q7.8, R53.1, U6.1, U6.24 |
|
||||||
|
| 2 | `SYS5V` ⚡potencia | C101.1, C119.1, C120.1, C121.1, D6.1, D12.2, F1.1, JP6.2, K1.2, R2.2, U7.2, U12.2, U12.7 |
|
||||||
|
|
||||||
|
### P12 — NTC-HOTSPOT
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `NTC_TEMP` | C24.1, R42.2, U16.27 |
|
||||||
|
| 2 | `GND` | plano de tierra |
|
||||||
|
|
||||||
|
### P14 — RGB_LED_EXT
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `3V3` ⚡potencia | C80.1, C81.1, C84.1, C89.1, C105.1, C106.1, C107.1, C108.1, C110.1, C118.1, C124.1, Cu3.1, Cu4.1, D5.1, DB1.2, DB2.2, DB3.2, DB4.2, … (+31) |
|
||||||
|
| 2 | `RGBR_K` | R89.1 |
|
||||||
|
| 3 | `RGBG_K` | R90.1 |
|
||||||
|
| 4 | `RGBB_K` | R91.1 |
|
||||||
|
|
||||||
|
### P15 — RS485_OUT
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `RS485_A` | R82.1, U14.6 |
|
||||||
|
| 2 | `RS485_B` | JP5.2, U14.7 |
|
||||||
|
| 3 | `GND` | plano de tierra |
|
||||||
|
|
||||||
|
### P16 — RS232_OUT
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `RS232_TX` | U15.14 |
|
||||||
|
| 2 | `RS232_RX` | U15.13 |
|
||||||
|
| 3 | `GND` | plano de tierra |
|
||||||
|
|
||||||
|
### H4 — TTL_UARTB
|
||||||
|
|
||||||
|
| Pin | Net | Conecta con |
|
||||||
|
|---|---|---|
|
||||||
|
| 1 | `3V3` ⚡potencia | C80.1, C81.1, C84.1, C89.1, C105.1, C106.1, C107.1, C108.1, C110.1, C118.1, C124.1, Cu3.1, Cu4.1, D5.1, DB1.2, DB2.2, DB3.2, DB4.2, … (+31) |
|
||||||
|
| 2 | `SER_TXB` | U10.23, U15.11 |
|
||||||
|
| 3 | `SER_RXB` | U10.24, U15.12 |
|
||||||
|
| 4 | `GND` | plano de tierra |
|
||||||
|
|
||||||
|
## Puertos de servicio (USB-C, Ethernet)
|
||||||
|
|
||||||
|
### J11 — USB-C DFU
|
||||||
|
|
||||||
|
| Pin | Señal | Net | Conecta con |
|
||||||
|
|---|---|---|---|
|
||||||
|
| A1 | GND_A1 | `GND` | plano de tierra |
|
||||||
|
| A4 | VBUS_A4 | `DFU_VBUS` ⚡potencia | D13.2, D16.1 |
|
||||||
|
| A5 | CC1_A5 | `DFU_CC1` | R100.1 |
|
||||||
|
| A6 | D+_A6 | `DFU_DP` | D14.1, U16.45 |
|
||||||
|
| A7 | D-_A7 | `DFU_DM` | D15.1, U16.44 |
|
||||||
|
| A9 | VBUS_A9 | `DFU_VBUS` ⚡potencia | D13.2, D16.1 |
|
||||||
|
| A12 | GND_A12 | `GND` | plano de tierra |
|
||||||
|
| B1 | GND_B1 | `GND` | plano de tierra |
|
||||||
|
| B4 | VBUS_B4 | `DFU_VBUS` ⚡potencia | D13.2, D16.1 |
|
||||||
|
| B5 | CC2_B5 | `DFU_CC2` | R101.1 |
|
||||||
|
| B6 | D+_B6 | `DFU_DP` | D14.1, U16.45 |
|
||||||
|
| B7 | D-_B7 | `DFU_DM` | D15.1, U16.44 |
|
||||||
|
| B9 | VBUS_B9 | `DFU_VBUS` ⚡potencia | D13.2, D16.1 |
|
||||||
|
| B12 | GND_B12 | `GND` | plano de tierra |
|
||||||
|
| SH | SHIELD_SH | `GND` | plano de tierra |
|
||||||
|
|
||||||
|
### J9 — USB-C
|
||||||
|
|
||||||
|
| Pin | Señal | Net | Conecta con |
|
||||||
|
|---|---|---|---|
|
||||||
|
| A1 | GND_A1 | `GND` | plano de tierra |
|
||||||
|
| A4 | VBUS_A4 | `USB_VBUS` ⚡potencia | D19.5, J7.6 |
|
||||||
|
| A5 | CC1_A5 | `USB_CC1` | Rcc1.1 |
|
||||||
|
| A6 | D+_A6 | `USB_DP` | D19.3, D19.4, J7.7 |
|
||||||
|
| A7 | D-_A7 | `USB_DM` | D19.1, D19.6, J7.8 |
|
||||||
|
| A9 | VBUS_A9 | `USB_VBUS` ⚡potencia | D19.5, J7.6 |
|
||||||
|
| A12 | GND_A12 | `GND` | plano de tierra |
|
||||||
|
| B1 | GND_B1 | `GND` | plano de tierra |
|
||||||
|
| B4 | VBUS_B4 | `USB_VBUS` ⚡potencia | D19.5, J7.6 |
|
||||||
|
| B5 | CC2_B5 | `USB_CC2` | Rcc2.1 |
|
||||||
|
| B6 | D+_B6 | `USB_DP` | D19.3, D19.4, J7.7 |
|
||||||
|
| B7 | D-_B7 | `USB_DM` | D19.1, D19.6, J7.8 |
|
||||||
|
| B9 | VBUS_B9 | `USB_VBUS` ⚡potencia | D19.5, J7.6 |
|
||||||
|
| B12 | GND_B12 | `GND` | plano de tierra |
|
||||||
|
| SH | SHIELD_SH | `GND` | plano de tierra |
|
||||||
|
|
||||||
|
### J10 — HR911105A
|
||||||
|
|
||||||
|
| Pin | Señal | Net | Conecta con |
|
||||||
|
|---|---|---|---|
|
||||||
|
| 1 | TD+_1 | `ETH_TXP` | R92.1, U11.2 |
|
||||||
|
| 2 | TD-_2 | `ETH_TXN` | R93.1, U11.1 |
|
||||||
|
| 3 | RD+_3 | `ETH_RXP` | R94.1, U11.6 |
|
||||||
|
| 4 | TCT_4 | `3V3_ETH` ⚡potencia | C92.1, C93.1, C94.1, C98.1, C102.1, C103.1, L8.2, R84.1, R87.1, R92.2, R93.2, R96.2, R97.2, U11.11, U11.15, U11.17, U11.21, U11.28, … (+2) |
|
||||||
|
| 5 | RCT_5 | `ETH_RCT` | C97.1, R94.2, R95.2 |
|
||||||
|
| 6 | RD-_6 | `ETH_RXN` | R95.1, U11.5 |
|
||||||
|
| 7 | NC_7 | — | *(sin net)* |
|
||||||
|
| 8 | 8 | — | *(sin net)* |
|
||||||
|
| 9 | 9 | `ETH_LNK_A` | R96.1 |
|
||||||
|
| 10 | 10 | `ETH_LINKLED` | U11.25 |
|
||||||
|
| 11 | 11 | `ETH_ACT_A` | R97.1 |
|
||||||
|
| 12 | 12 | `ETH_ACTLED` | U11.27 |
|
||||||
|
| SH | SH | `GND` | plano de tierra |
|
||||||
|
|
||||||
|
## Zócalos de módulos
|
||||||
|
|
||||||
|
### J7 — XBEE-ROW-1 (VCC/DOUT/DIN)
|
||||||
|
|
||||||
|
Fila 1 del zócalo XBee (pines 1–10 del módulo, en orden). Módem ArduSimple 4G NTRIP Master.
|
||||||
|
|
||||||
|
| Pin | Señal | Net | Conecta con |
|
||||||
|
|---|---|---|---|
|
||||||
|
| 1 | Pin_1_1 | `3V3_MODEM` ⚡potencia | C41.1, C43.1, C122.1, J8.7, L7.2, R60.1 |
|
||||||
|
| 2 | Pin_2_2 | `DOUT_4G` | MOD1.17, R111.2 |
|
||||||
|
| 3 | Pin_3_3 | `DIN_4G` | K1.5, K1.6 |
|
||||||
|
| 4 | Pin_4_4 | `GND` | plano de tierra |
|
||||||
|
| 5 | Pin_5_5 | `MODEM_RST` | R107.2, SW4G1.1 |
|
||||||
|
| 6 | Pin_6_6 | `USB_VBUS` ⚡potencia | D19.5, J9.A4, J9.A9, J9.B4, J9.B9 |
|
||||||
|
| 7 | Pin_7_7 | `USB_DP` | D19.3, D19.4, J9.A6, J9.B6 |
|
||||||
|
| 8 | Pin_8_8 | `USB_DM` | D19.1, D19.6, J9.A7, J9.B7 |
|
||||||
|
| 9 | Pin_9_9 | — | *(sin net)* |
|
||||||
|
| 10 | Pin_10_10 | `GND` | plano de tierra |
|
||||||
|
|
||||||
|
### J8 — XBEE-ROW-2
|
||||||
|
|
||||||
|
Fila 2 del zócalo XBee: **pad k = pin XBee (21 − k)** (espejo; regla verificada en el Informe técnico V3+V4 contra el footprint-R00 de ArduSimple: J8.8 = pin 13 LED, J8.6 = pin 15 GND, J8.10 = pin 11 GND). La net `XBEE_ONSLP` en J8.3 (R109 **DNP**) corresponde por esa regla al pin XBee 18; el ECO la etiqueta «pin 13 ON/SLEEP». <!-- VERIFICAR contra el datasheet del 4G NTRIP Master antes de poblar R109 -->
|
||||||
|
|
||||||
|
| Pin | Señal | Net | Conecta con |
|
||||||
|
|---|---|---|---|
|
||||||
|
| 1 | Pin_1_1 | `GND` | plano de tierra |
|
||||||
|
| 2 | Pin_2_2 | — | *(sin net)* |
|
||||||
|
| 3 | Pin_3_3 | `XBEE_ONSLP` | R109.2 |
|
||||||
|
| 4 | Pin_4_4 | — | *(sin net)* |
|
||||||
|
| 5 | Pin_5_5 | — | *(sin net)* |
|
||||||
|
| 6 | Pin_6_6 | `GND` | plano de tierra |
|
||||||
|
| 7 | Pin_7_7 | `3V3_MODEM` ⚡potencia | C41.1, C43.1, C122.1, J7.1, L7.2, R60.1 |
|
||||||
|
| 8 | Pin_8_8 | `MODEM_LED` | R108.2, Rmled1.1 |
|
||||||
|
| 9 | Pin_9_9 | — | *(sin net)* |
|
||||||
|
| 10 | Pin_10_10 | `GND` | plano de tierra |
|
||||||
|
|
||||||
|
### MOD1 — simpleRTK2B-Pro on UNO female headers
|
||||||
|
|
||||||
|
Zócalo UNO del simpleRTK2B Pro (ArduSimple). Solo se usan 5V, IOREF, GND, D0/D1 (UART1) y D2/D8 (UART2); el resto queda sin conectar por indicación de ArduSimple.
|
||||||
|
|
||||||
|
| Pin | Señal | Net | Conecta con |
|
||||||
|
|---|---|---|---|
|
||||||
|
| 1 | NC_1 | — | *(sin net)* |
|
||||||
|
| 2 | IOREF_2 | `3V3` ⚡potencia | C80.1, C81.1, C84.1, C89.1, C105.1, C106.1, C107.1, C108.1, C110.1, C118.1, C124.1, Cu3.1, Cu4.1, D5.1, DB1.2, DB2.2, DB3.2, DB4.2, … (+31) |
|
||||||
|
| 3 | RESET_3 | — | *(sin net)* |
|
||||||
|
| 4 | 3V3_OUT_4 | — | *(sin net)* |
|
||||||
|
| 5 | 5V_5 | `SW_5V` ⚡potencia | C3.1, C40.1, Q1.3 |
|
||||||
|
| 6 | GND_6 | `GND` | plano de tierra |
|
||||||
|
| 7 | GND_7 | `GND` | plano de tierra |
|
||||||
|
| 8 | VIN_8 | — | *(sin net)* |
|
||||||
|
| 9 | A0_9 | — | *(sin net)* |
|
||||||
|
| 10 | A1_10 | — | *(sin net)* |
|
||||||
|
| 11 | A2_11 | — | *(sin net)* |
|
||||||
|
| 12 | A3_12 | — | *(sin net)* |
|
||||||
|
| 13 | A4_13 | — | *(sin net)* |
|
||||||
|
| 14 | A5_14 | — | *(sin net)* |
|
||||||
|
| 15 | TX1_D0_15 | `GNSS_RX` | U16.17 |
|
||||||
|
| 16 | RX1_D1_16 | `GNSS_TX` | U16.16 |
|
||||||
|
| 17 | RX2_D2_17 | `DOUT_4G` | J7.2, R111.2 |
|
||||||
|
| 18 | D3_18 | — | *(sin net)* |
|
||||||
|
| 19 | D4_19 | — | *(sin net)* |
|
||||||
|
| 20 | D5_20 | — | *(sin net)* |
|
||||||
|
| 21 | D6_21 | — | *(sin net)* |
|
||||||
|
| 22 | D7_22 | — | *(sin net)* |
|
||||||
|
| 23 | TX2_D8_23 | `USART1_RX` | K1.1, Rdfu1.1, U16.43 |
|
||||||
|
| 24 | D9_24 | — | *(sin net)* |
|
||||||
|
| 25 | D10_25 | — | *(sin net)* |
|
||||||
|
| 26 | FENCE_D11_26 | — | *(sin net)* |
|
||||||
|
| 27 | EXTINT_D12_27 | — | *(sin net)* |
|
||||||
|
| 28 | TPS_D13_28 | — | *(sin net)* |
|
||||||
|
| 29 | GND_29 | `GND` | plano de tierra |
|
||||||
|
| 30 | AREF_30 | — | *(sin net)* |
|
||||||
|
| 31 | SDA_31 | — | *(sin net)* |
|
||||||
|
| 32 | SCL_32 | — | *(sin net)* |
|
||||||
|
|
||||||
|
## Puentes de soldadura
|
||||||
|
|
||||||
|
| Ref | Valor (estado por defecto) | Pad 1 | Pad 2 | Pad 3 |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| **JP1** | 0R | `5V_FAN` | `VEH5V` | — |
|
||||||
|
| **JP2** | F2:LFP (2-3) | `MAIN5V` | `F2_SEL` | `GND` |
|
||||||
|
| **JP3** | F1:0 | `GND` | `F1_SEL` | `MAIN5V` |
|
||||||
|
| **JP4** | F0:1 | `MAIN5V` | `F0_SEL` | `GND` |
|
||||||
|
| **JP5** | RS485_TERM | `RS485_T` | `RS485_B` | — |
|
||||||
|
| **JP6** | JP_CUT | `MAIN5V` | `SYS5V` | — |
|
||||||
|
|
||||||
|
## Botones
|
||||||
|
|
||||||
|
| Ref | Serigrafía | Pin 1 | Pin 2 |
|
||||||
|
|---|---|---|---|
|
||||||
|
| **SW1** | RESET | `NRST` (C104.1, P10.1, TP5.1, U16.7) | `GND` |
|
||||||
|
| **SW2** | BOOT0 | `3V3` (C80.1, C81.1, C84.1, C89.1, C105.1, C106.1, C107.1, C108.1, C110.1, C118.1, C124.1, Cu3.1, … (+37)) | `BOOT0` |
|
||||||
|
| **SW4G1** | RESET | `MODEM_RST` (J7.5, R107.2) | `GND` |
|
||||||
|
|
||||||
|
## Puntos de prueba
|
||||||
|
|
||||||
|
| Ref | Nombre | Net | Conecta con |
|
||||||
|
|---|---|---|---|
|
||||||
|
| **TP1** | CLPROG | `CLPROG_TP` | U6.3 |
|
||||||
|
| **TP2** | PFO | `PFO_TP` | U6.20 |
|
||||||
|
| **TP3** | SWDIO | `SWDIO` | U16.46 |
|
||||||
|
| **TP4** | SWCLK | `SWCLK` | U16.49 |
|
||||||
|
| **TP5** | NRST | `NRST` | C104.1, P10.1, SW1.1, U16.7 |
|
||||||
|
| **TP6** | GND | `GND` | plano de tierra |
|
||||||
|
| **TP7** | 3V3 | `3V3` | C80.1, C81.1, C84.1, C89.1, C105.1, C106.1, C107.1, C108.1, C110.1, C118.1, C124.1, Cu3.1, … (+37) |
|
||||||
|
|
||||||
|
## Diferencias V5.5 → V5.6 en conectores (lo que cambia para el arnés)
|
||||||
|
|
||||||
|
| Conector | V5.5 (lote 22-ago) | V5.6 | Fuente |
|
||||||
|
|---|---|---|---|
|
||||||
|
| **P5** TEMP_PROBE (3V3/GND/SDA/SCL) | Presente | **Eliminado** — ya no hay sonda externa de T/RH; la temperatura del cargador la mide U4 y la del módem U18 en la tarjeta | Informe de cambios §10 / netlist `p5ntc-after.xml` (sin P5) |
|
||||||
|
| **P4.3** NTC | Solo al LTC4040 (U6.17) con R55 10 k (Li-ion) | Además al MCU **PC5** por R113 100 k / R114 120 k / C125 10 nF (`NTC_CELL`); R55 **5.6 k** para química **LFP-HT** (NTC B3380) | netlist; Informe §9 |
|
||||||
|
| **JP2** | `F2:Li-ion` puente 1-2 | **`F2:LFP` puente 2-3** (flotación LiFePO4) | Informe §9 |
|
||||||
|
| **JP6** | No existía | Nuevo, en paralelo con P11 (`MAIN5V`↔`SYS5V`), **abierto** — puentear solo si la unidad no lleva interruptor de corte | Informe §2 |
|
||||||
|
| **J7.2** DOUT_4G | Solo a MOD1.17 | Además al MCU **PC7** (USART6_RX) por R111 1 k — escucha RTCM | Informe §3 |
|
||||||
|
| **J7.5** MODEM_RST | Solo SW4G1 | Además al MCU **PC1** por R107 1 k | Informe §3 |
|
||||||
|
| **J8.8** MODEM_LED | Solo Rmled1/D4G1 | Además al MCU **PC2** por R108 10 k | Informe §3 |
|
||||||
|
| **J8.3** | Sin conexión | `XBEE_ONSLP` → PC4 por R109 10 k **DNP** | Informe §2–3 |
|
||||||
|
| **J9** USB-C módem | Sin ESD | **D19 USBLC6-2SC6** en D+/D−/VBUS | Informe §2 |
|
||||||
|
| **J10** RJ45 | Sin cambio (sin PoE) | Sin cambio; U11 con R112 4.7 k pull-down en `ETH_RST`, C90 4.7 µF, C91 10 nF | Informe §10 |
|
||||||
|
| **P11** CUTOFF-SW | `MAIN5V`/`SYS5V` | Sin cambio (JP6 lo puentea si se desea) | netlist |
|
||||||
|
| **P1, P2, P6, P8, P10, P12, P14, P15, P16, J11, MOD1** | — | **Sin cambio** eléctrico | diff de netlist v55-baseline → V5.6 (Informe §4) |
|
||||||
|
|
||||||
|
!!! note "P13 (MODO-B-UPLINK) y P3 (RTK2B-UART1)"
|
||||||
|
Existían en la V3 (`harness-connector-pinout.md`) y **no existen en V4/V5.5/V5.6** (eliminados en V4 junto con H3: el Modo B es permanente por K1). No buscarlos en la tarjeta.
|
||||||
|
|
||||||
|
## Historial de revisiones
|
||||||
|
|
||||||
|
| Versión | Fecha | Autor | Cambio |
|
||||||
|
|---|---|---|---|
|
||||||
|
| 1.0 | 2026-09-29 | Helgen Technologies (generado por script desde la netlist) | Primera versión para V5.6 |
|
||||||
|
|
||||||
@ -1,87 +1,430 @@
|
|||||||
|
% cuerpo.tex — DRG-MAN-001 v2.0 (29-sep-2026). Fuente de verdad de los LEDs y tiempos:
|
||||||
|
% 04-Source-Code/firmware/hbox_v5_bringup/hbox_v5_bringup.ino (0.6.0). Las líneas marcadas
|
||||||
|
% "% VERIFICAR" son puntos que ingeniería debe confirmar antes de entregar el manual al cliente.
|
||||||
|
|
||||||
\section{Seguridad — leer primero}
|
\section{Seguridad — leer primero}
|
||||||
|
|
||||||
\begin{helgennotice}[Riesgo de batería de litio]
|
\begin{helgennotice}[Batería de litio dentro de la unidad]
|
||||||
La unidad contiene una batería \textbf{18650 Li-ion}. Una celda \textbf{inflada, caliente
|
La unidad lleva un \textbf{paquete de batería de litio} (V5.5: Li-ion 18650; V5.6: LiFePO$_4$ 26650,
|
||||||
o deformada} es riesgo de incendio. \textbf{No} la cargue, no la perfore ni siga
|
química más estable). Una celda \textbf{inflada, caliente al tacto o con olor} es riesgo de incendio:
|
||||||
energizando una unidad con la batería visiblemente dañada. Desconecte, aísle en bolsa o
|
\textbf{no} la cargue, no la perfore, no la desconecte con la unidad encendida. Ponga el
|
||||||
recipiente seguro, ventile y repórtelo.
|
\textbf{interruptor de corte} del panel en OFF, retire los 24 V, aísle la unidad y llame a Helgen.
|
||||||
\end{helgennotice}
|
\end{helgennotice}
|
||||||
|
|
||||||
\begin{itemize}
|
\begin{itemize}
|
||||||
\item Trabaje con la máquina \textbf{apagada y bloqueada} (LOTO) durante la instalación.
|
\item Trabaje con la máquina \textbf{apagada y bloqueada} (LOTO) durante la instalación y cualquier
|
||||||
\item Use EPP completo en todo momento en el patio.
|
intervención en el cableado de 24 V.
|
||||||
\item Respete los voltajes: la entrada al HBOX es \textbf{24 V} desde el gabinete; nunca conecte el HBOX directo a la línea de la máquina.
|
\item Use el EPP completo del patio en todo momento.
|
||||||
|
\item La unidad se alimenta \textbf{solo con 24 V de corriente directa} (acepta 19--36 V). Nunca la
|
||||||
|
conecte a 110/230 V de corriente alterna ni a 48 V.
|
||||||
|
\item \textbf{Nunca conecte ni desconecte la batería con la unidad energizada} (ni con 24 V ni con
|
||||||
|
el interruptor de corte en ON). El cambio de batería lo hace Helgen.
|
||||||
|
\item No abra la tarjeta electrónica ni suelde nada. Si algo se ve quemado, decolorado o suelto,
|
||||||
|
no energice: llame a Helgen.
|
||||||
\end{itemize}
|
\end{itemize}
|
||||||
|
|
||||||
\section{Contenido del kit}
|
\section{Contenido del kit}
|
||||||
|
|
||||||
\begin{itemize}
|
\hwtab{%
|
||||||
\item Gabinete IP67 (Yetlebox P3901) con platina, riel DIN y componentes de potencia/protección.
|
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{4.2cm} X@{}}
|
||||||
\item Unidad \textbf{HBOX} (simpleRTK2B Pro + 4G NTRIP Master + watchdog) con conector \textbf{GX16-5}.
|
\toprule
|
||||||
\item Antena GNSS multibanda (SMA) y 2 antenas LTE.
|
\rowcolor{HelgenIndigo}\textcolor{white}{Elemento} & \textcolor{white}{Descripción}\\
|
||||||
\item SIM Telcel, glándulas, herrajes de montaje y etiquetas.
|
\midrule
|
||||||
\end{itemize}
|
Unidad HBOX & Gabinete con panel: conector circular \textbf{GX16-5} (alimentación), 3 conectores de antena
|
||||||
|
\textbf{SMA}, \textbf{RJ45}, prensaestopas, \textbf{LED de panel}, \textbf{interruptor de corte},
|
||||||
|
botón \textbf{RESET} y rejilla del ventilador. Dentro: tarjeta EinarBoard V5.5/V5.6, receptor GNSS
|
||||||
|
RTK (u-blox ZED-F9P), módem 4G NTRIP, fuente Mean Well SD-15B-05 (24 V $\rightarrow$ 5 V), batería de
|
||||||
|
respaldo y ventilador.\\
|
||||||
|
Arnés GX16-5 & Cable con conector hembra GX16-5 hacia la máquina: +24 V, tierra (GND) e ignición. Largo según
|
||||||
|
la máquina.\\
|
||||||
|
Antena GNSS & Antena multibanda con base magnética o de tornillo y cable con SMA. Es la que necesita ver
|
||||||
|
el cielo.\\
|
||||||
|
Antenas 4G (2) & Dos antenas LTE con SMA. Van separadas de la antena GNSS.\\
|
||||||
|
Fusible en línea & Portafusible con fusible para el +24 V (ver sección de conexión eléctrica).\\
|
||||||
|
Herrajes & Soportes, tornillería, bridas, etiquetas con el \textbf{ID de la unidad} (H00xx).\\
|
||||||
|
\bottomrule
|
||||||
|
\end{tabularx}}
|
||||||
|
|
||||||
|
\begin{helgennotice}[Antes de instalar]
|
||||||
|
Revise que el \textbf{ID de la unidad} (etiqueta del panel, junto al GX16) coincida con la hoja de
|
||||||
|
asignación de Helgen (unidad $\leftrightarrow$ máquina). Si no coincide, no instale: llame a Helgen.
|
||||||
|
\end{helgennotice}
|
||||||
|
|
||||||
\section{Instalación del gabinete}
|
\section{Instalación del gabinete}
|
||||||
|
|
||||||
|
\subsection{Dónde montar la unidad}
|
||||||
|
|
||||||
\begin{enumerate}[leftmargin=1.5em]
|
\begin{enumerate}[leftmargin=1.5em]
|
||||||
\item \textbf{Ubicación.} Monte el gabinete en un punto firme, con la menor exposición solar posible (preferir sombra) y buena vista al cielo para las antenas.
|
\item Elija un punto \textbf{firme y protegido} de la máquina: dentro de la cabina, en un
|
||||||
\item \textbf{Alimentación.} Conecte la alimentación de la máquina al breaker/SPD del gabinete según el voltaje (esta unidad: \textbf{24 V}). La fuente Mean Well entrega 24 V regulados al HBOX.
|
compartimiento eléctrico o bajo una cubierta. Preferir \textbf{sombra}; el calor es el
|
||||||
\item \textbf{Ignición.} Lleve la señal de ignición al relevador de estado sólido (SSR); éste entrega una señal aislada al HBOX.
|
principal enemigo de la batería.
|
||||||
\item \textbf{Conexión HBOX.} Acople el \textbf{GX16-5} entre el gabinete y el HBOX; apriete el anillo de seguro.
|
\item Deje \textbf{5 cm libres} frente a la rejilla del ventilador y no tape la salida de aire.
|
||||||
\item \textbf{Antenas.} Instale la antena GNSS y las 2 LTE por glándula; aplique torque y fijador de rosca a los SMA. La antena GNSS debe ver el cielo.
|
\item Monte la unidad con los soportes del kit (4 tornillos); no perfore el gabinete.
|
||||||
\item \textbf{SIM.} Verifique que la SIM Telcel esté insertada y activa.
|
\item Deje el panel de conectores accesible para mantenimiento (se necesita ver el LED de panel y
|
||||||
\item \textbf{Sellado.} Cierre el gabinete asegurando el sello IP67; verifique glándulas apretadas.
|
alcanzar el interruptor de corte y el botón RESET).
|
||||||
\end{enumerate}
|
\end{enumerate}
|
||||||
|
|
||||||
|
\subsection{Reglas para las antenas (RTK)}
|
||||||
|
|
||||||
|
\begin{enumerate}[leftmargin=1.5em]
|
||||||
|
\item \textbf{Antena GNSS: cielo despejado.} Colóquela en el punto más alto de la máquina, con vista
|
||||||
|
libre al cielo en todas direcciones. Nada metálico por encima ni a menos de 30 cm alrededor
|
||||||
|
(spreader, luces, escaleras, techos). Sin cielo no hay RTK.
|
||||||
|
\item \textbf{Base metálica.} Si la antena es magnética, péguela sobre una superficie de acero
|
||||||
|
plana de al menos 20 $\times$ 20 cm (el plano de tierra mejora la precisión). Si es de
|
||||||
|
tornillo, use el soporte del kit.
|
||||||
|
\item \textbf{Separación con las antenas 4G: al menos 1 m.} Las antenas LTE transmiten y ensucian la
|
||||||
|
señal GNSS si están cerca. Ponga las dos antenas 4G separadas entre sí al menos 20 cm y
|
||||||
|
lejos de la GNSS.
|
||||||
|
\item \textbf{Cables.} Tienda los cables sin dobleces cerrados (radio mínimo 5 cm), lejos de
|
||||||
|
cables de potencia, sin puntos donde se aplasten o rocen; fíjelos con bridas cada 30--40 cm.
|
||||||
|
No corte ni empalme los cables de antena.
|
||||||
|
\item \textbf{Conectores SMA.} Rosque a mano hasta el tope y dé \textbf{¼ de vuelta} con llave; no
|
||||||
|
apriete de más. Deje una gota de fijador de rosca si la máquina vibra mucho.
|
||||||
|
\item \textbf{Tierra.} El GND del GX16-5 debe ir al negativo/chasis de la máquina. Si la máquina tiene
|
||||||
|
punto de tierra de carrocería, conéctelo también al tornillo de tierra del gabinete.
|
||||||
|
% VERIFICAR: el gabinete V5 ¿lleva tornillo de tierra externo? Si no, quitar la segunda frase.
|
||||||
|
\end{enumerate}
|
||||||
|
|
||||||
|
\section{Conexión eléctrica}
|
||||||
|
|
||||||
|
\begin{helgennotice}[Fusible obligatorio]
|
||||||
|
Instale el portafusible del kit en el \textbf{+24 V}, lo más cerca posible del punto de toma en la
|
||||||
|
máquina. Fusible de \textbf{3 A} lento (o el que indique la hoja de instalación de esa máquina).
|
||||||
|
% VERIFICAR: valor final del fusible en línea (3 A propuesto; consumo típico < 1 A a 24 V con pico de carga).
|
||||||
|
\end{helgennotice}
|
||||||
|
|
||||||
|
\subsection{Conector P1 — GX16-5 (panel)}
|
||||||
|
|
||||||
|
\hwtab{%
|
||||||
|
\begin{tabularx}{\textwidth}{@{}C{1.2cm} L{3.4cm} X@{}}
|
||||||
|
\toprule
|
||||||
|
\rowcolor{HelgenIndigo}\textcolor{white}{Pin} & \textcolor{white}{Señal} & \textcolor{white}{Conecte a}\\
|
||||||
|
\midrule
|
||||||
|
1 & \textbf{+24 V} & Positivo permanente de la máquina, \textbf{después del fusible}. Rango admitido 19--36 V CD.\\
|
||||||
|
2 & \textbf{GND} & Negativo / chasis de la máquina.\\
|
||||||
|
3 & \textbf{Ignición} & Señal positiva (+24 V) que aparece con la llave en marcha (circuito de ignición o relevador de llave).\\
|
||||||
|
4 & GND & Tierra (unido internamente al pin 2). Puede dejarse sin conectar.\\
|
||||||
|
5 & — & Sin uso.\\
|
||||||
|
\bottomrule
|
||||||
|
\end{tabularx}}
|
||||||
|
|
||||||
|
\begin{enumerate}[leftmargin=1.5em]
|
||||||
|
\item Con la máquina apagada y bloqueada, tienda el arnés desde la toma de 24 V hasta la unidad.
|
||||||
|
\item Conecte primero el \textbf{GND}, luego el \textbf{+24 V} (a través del fusible) y por último la
|
||||||
|
\textbf{ignición}.
|
||||||
|
\item Mida con multímetro en el conector hembra del arnés \textbf{antes} de acoplarlo a la unidad:
|
||||||
|
pin 1 a pin 2 = 24 V aprox. (19--36 V); pin 3 a pin 2 = 0 V con llave apagada y +24 V con
|
||||||
|
llave en marcha.
|
||||||
|
\item Acople el GX16-5 al panel y \textbf{apriete el anillo roscado} de seguro.
|
||||||
|
\item Ponga el \textbf{interruptor de corte} del panel en \textbf{ON}. (Viene en OFF de fábrica para
|
||||||
|
no descargar la batería en el almacén.)
|
||||||
|
\end{enumerate}
|
||||||
|
|
||||||
|
\begin{helgennotice}[Qué hace la ignición]
|
||||||
|
La unidad funciona con 24 V permanentes; la ignición solo le dice \emph{«la máquina está trabajando»}.
|
||||||
|
Con ignición el ventilador va al 100 \% y la posición se reporta cada segundo. Sin señal de ignición la
|
||||||
|
unidad sigue funcionando pero reporta el estado de la máquina como apagada. Si la máquina no tiene una
|
||||||
|
línea de ignición limpia, consúltelo con Helgen antes de improvisar.
|
||||||
|
\end{helgennotice}
|
||||||
|
|
||||||
|
\section{Conexión de red opcional}
|
||||||
|
|
||||||
|
Estas conexiones \textbf{no son necesarias} para que la unidad reporte por 4G. Úselas \textbf{solo si
|
||||||
|
Helgen lo indica} para esa máquina. Si el panel de su unidad trae tapas ciegas en estos puertos, déjelas.
|
||||||
|
|
||||||
|
\hwtab{%
|
||||||
|
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{3.2cm} X@{}}
|
||||||
|
\toprule
|
||||||
|
\rowcolor{HelgenIndigo}\textcolor{white}{Puerto} & \textcolor{white}{Para qué es y cómo se conecta}\\
|
||||||
|
\midrule
|
||||||
|
RJ45 Ethernet & Salida de datos por cable (posición y estado de la unidad) hacia una red o computadora local.
|
||||||
|
10/100 Mbit/s, cable \textbf{directo} (patch normal) categoría 5e o mejor, máximo 100 m.
|
||||||
|
\textbf{Sin PoE}: la unidad no se alimenta por el cable de red ni alimenta a nada por él; puede
|
||||||
|
conectarse a cualquier puerto de switch normal. Dirección IP según lo configure Helgen
|
||||||
|
(por omisión 192.168.7.2, o por DHCP).\\
|
||||||
|
RS-485 (clavija verde de 3 polos, A / B / GND) & Enlace serie industrial para integrarse con sistemas de la
|
||||||
|
máquina o de la terminal. Cable de par trenzado blindado; respete A con A y B con B; GND al GND.
|
||||||
|
La terminación de 120 $\Omega$ la activa Helgen dentro de la unidad.\\
|
||||||
|
RS-232 (clavija verde de 3 polos, TX / RX / GND) & Puerto serie para equipos locales (pantalla, PLC, PC de
|
||||||
|
diagnóstico). Cable cruzado: TX de la unidad al RX del equipo y viceversa; máximo 15 m.\\
|
||||||
|
\bottomrule
|
||||||
|
\end{tabularx}}
|
||||||
|
|
||||||
|
\begin{helgennotice}[Nota]
|
||||||
|
En el firmware actual (0.6.0) los puertos RS-485/RS-232 están instalados pero \textbf{sin función
|
||||||
|
asignada}; Ethernet se habilita por configuración de Helgen. No conecte nada a estos puertos sin
|
||||||
|
indicación: no dañará la unidad, pero tampoco hará nada.
|
||||||
|
\end{helgennotice}
|
||||||
|
|
||||||
\section{Encendido y verificación}
|
\section{Encendido y verificación}
|
||||||
|
|
||||||
Al energizar, observe el LED de estado. La secuencia normal es: \textbf{parpadeo rápido}
|
Cierre el gabinete, acople el GX16-5, ponga el interruptor de corte en ON y encienda la máquina. Lo que
|
||||||
(arranque, esperando 4G/GNSS) $\rightarrow$ \textbf{parpadeo lento} (buscando) $\rightarrow$
|
debe ver en los primeros minutos:
|
||||||
\textbf{encendido fijo} (operando con RTK fijo). Confirme en la plataforma que la unidad
|
|
||||||
reporta posición.
|
\hwtab{%
|
||||||
|
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{2.6cm} X@{}}
|
||||||
|
\toprule
|
||||||
|
\rowcolor{HelgenIndigo}\textcolor{white}{Momento} & \textcolor{white}{Qué pasa (normal)}\\
|
||||||
|
\midrule
|
||||||
|
0 s & El \textbf{ventilador arranca} (siempre que hay 24 V). El \textbf{LED de panel} empieza a
|
||||||
|
parpadear \textbf{una vez por segundo}: la unidad está viva.\\
|
||||||
|
$\sim$3 s & Se enciende la etapa RTK (GNSS + 4G). El LED de estado \textbf{RGB} pasa de rojo a
|
||||||
|
\textbf{magenta} (esperando datos del GNSS).\\
|
||||||
|
$\sim$8 s & La unidad da un pulso de reinicio al módem 4G: sus luces pueden apagarse y volver a
|
||||||
|
encender. Es normal.\\
|
||||||
|
$\sim$13 s & Se oye un \textbf{clic} del relevador interno: la unidad ya está supervisando el enlace.\\
|
||||||
|
$<$1 min & LED RGB \textbf{azul}: hay posición GPS (todavía sin RTK).\\
|
||||||
|
$<$2 min & El módem 4G queda registrado en la red (su LED pasa a parpadeo regular).\\
|
||||||
|
2--10 min & LED RGB \textbf{verde}: \textbf{RTK fijo}, precisión centimétrica. Con cielo despejado
|
||||||
|
tarda menos de 10 min; a la sombra de grúas o edificios puede tardar más o quedarse en azul.\\
|
||||||
|
$\sim$2.5 min & Si la batería lo necesita, empieza a cargar (no se ve en los LEDs del panel; se ve en el
|
||||||
|
monitor como \emph{CARGANDO}).\\
|
||||||
|
$<$5 min & La unidad \textbf{aparece en el monitor} de Helgen (\texttt{monitor.helgen.dev}) con su ID
|
||||||
|
H00xx, posición y estado. Pida a Helgen (o a quien tenga acceso) que confirme.\\
|
||||||
|
\bottomrule
|
||||||
|
\end{tabularx}}
|
||||||
|
|
||||||
|
\begin{helgennotice}[Prueba final de instalación]
|
||||||
|
Con la máquina en marcha: LED de panel parpadeando, LED RGB \textbf{verde} (o azul si no hay cielo),
|
||||||
|
la unidad visible en el monitor con la máquina correcta. Apague la máquina: el LED RGB pasa a
|
||||||
|
\textbf{amarillo} (en batería) y la unidad sigue reportando. Vuelva a encender: la unidad se
|
||||||
|
reinicia sola (unos 10 s con LED rojo/magenta) y regresa a verde. Anote hora, ID y máquina en la hoja
|
||||||
|
de instalación.
|
||||||
|
\end{helgennotice}
|
||||||
|
|
||||||
\section{Estados del LED}
|
\section{Estados del LED}
|
||||||
|
|
||||||
|
La unidad tiene cuatro grupos de luces. Desde afuera se ven el \textbf{LED de panel} y el
|
||||||
|
\textbf{LED RGB de estado}; los demás se ven al abrir la tapa (solo Helgen o personal autorizado).
|
||||||
|
% VERIFICAR: que el panel de las unidades entregadas lleve el LED RGB (P14) además del LED de panel (P8);
|
||||||
|
% el procedimiento de ensamble v5 solo lista P8 en el arnés de panel. Si no lo lleva, dejar solo el LED de panel.
|
||||||
|
|
||||||
|
\subsection{LED de panel (blanco, un solo LED)}
|
||||||
|
|
||||||
\hwtab{%
|
\hwtab{%
|
||||||
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{3.8cm} X@{}}
|
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{3.8cm} X@{}}
|
||||||
\toprule
|
\toprule
|
||||||
\rowcolor{HelgenIndigo}\textcolor{white}{Patrón} & \textcolor{white}{Significado / acción}\\
|
\rowcolor{HelgenIndigo}\textcolor{white}{Patrón} & \textcolor{white}{Significado / acción}\\
|
||||||
\midrule
|
\midrule
|
||||||
Parpadeo rápido & Arranque; espere a que el 4G/GNSS estabilice (normal al inicio).\\
|
Parpadeo 1 por segundo & Unidad viva (con 24 V o en batería). Correcto.\\
|
||||||
Encendido fijo & Operando con energía de máquina y RTK fijo. Correcto.\\
|
Destello corto cada 5 s & Reposo entre reportes en batería (modo ahorro, unidades V5.6). Normal.\\
|
||||||
Latido (1 s) & Modo batería (máquina apagada), reporte cada 30 s. Normal.\\
|
Apagado & Sin alimentación: revise 24 V, fusible, GX16-5 e interruptor de corte. En batería agotada
|
||||||
Parpadeo lento & Buscando / sin correcciones. Si persiste, revise antenas y señal 4G.\\
|
(menos de 3.40 V) también se apaga hasta que vuelvan los 24 V.\\
|
||||||
Doble (tipo SOS) & LIMP: sin 4G, sigue reportando posición estándar. Reporte a Helgen.\\
|
|
||||||
Estrobo & Reiniciando el stack (recuperación automática). Espere.\\
|
|
||||||
Apagado & Reposo / batería crítica. Verifique alimentación de 24 V.\\
|
|
||||||
\bottomrule
|
\bottomrule
|
||||||
\end{tabularx}}
|
\end{tabularx}}
|
||||||
|
|
||||||
\section{Mantenimiento}
|
\subsection{LED RGB de estado}
|
||||||
|
|
||||||
|
\hwtab{%
|
||||||
|
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{3.8cm} X@{}}
|
||||||
|
\toprule
|
||||||
|
\rowcolor{HelgenIndigo}\textcolor{white}{Color} & \textcolor{white}{Significado / acción}\\
|
||||||
|
\midrule
|
||||||
|
\textcolor{green!60!black}{Verde} & Operando con 24 V y \textbf{RTK fijo}. Todo correcto.\\
|
||||||
|
\textcolor{blue}{Azul} & Etapa encendida, posición GPS \textbf{sin RTK}. Normal los primeros minutos o bajo
|
||||||
|
techo. Si persiste más de 15 min a cielo abierto: revise antena GNSS, separación con las 4G y señal 4G.\\
|
||||||
|
\textcolor{magenta}{Magenta} & Etapa encendida pero \textbf{sin datos del GNSS}. Normal en el primer minuto. Si
|
||||||
|
dura más de 2 min: la unidad reinicia la etapa sola; si sigue, llame a Helgen.\\
|
||||||
|
\textcolor{orange!90!black}{Amarillo} & \textbf{Funcionando en batería} (sin 24 V). Normal con la máquina apagada.
|
||||||
|
Con la máquina encendida: revise 24 V, fusible y GX16-5.\\
|
||||||
|
\textcolor{red}{Rojo} & Etapa RTK \textbf{apagada}: primeros 3 s del arranque, batería agotada ($<$3.40 V),
|
||||||
|
temperatura interna alta ($\geq$60 \textdegree C) o unidad puesta en pausa por Helgen. Si dura con
|
||||||
|
24 V presentes: llame a Helgen.\\
|
||||||
|
Apagado & Reposo entre reportes en batería (V5.6) o sin alimentación.\\
|
||||||
|
\bottomrule
|
||||||
|
\end{tabularx}}
|
||||||
|
|
||||||
|
\subsection{Indicador de batería (4 LEDs en la tarjeta)}
|
||||||
|
|
||||||
|
Cuatro LEDs en fila junto al conector de batería; \textbf{cuantos más encendidos, más carga}.
|
||||||
|
Se apagan todos en el reposo de batería (V5.6).
|
||||||
|
|
||||||
|
\hwtab{%
|
||||||
|
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{3.8cm} X@{}}
|
||||||
|
\toprule
|
||||||
|
\rowcolor{HelgenIndigo}\textcolor{white}{LEDs encendidos} & \textcolor{white}{Nivel (paquete Li-ion, V5.5)}\\
|
||||||
|
\midrule
|
||||||
|
4 & Lleno (más de 3.97 V).\\
|
||||||
|
3 & Bueno (más de 3.90 V).\\
|
||||||
|
2 & Medio (más de 3.75 V).\\
|
||||||
|
1 & Bajo (más de 3.60 V). Con 24 V presentes debe estar cargando.\\
|
||||||
|
0 & Muy bajo (menos de 3.60 V). La unidad se apaga sola a 3.40 V. Si con 24 V no sube en 8 h: llame a Helgen.\\
|
||||||
|
\bottomrule
|
||||||
|
\end{tabularx}}
|
||||||
|
% VERIFICAR: los umbrales 3.60/3.75/3.90/3.97 V del firmware 0.6.0 son de Li-ion. Con el paquete LiFePO4 de la V5.6
|
||||||
|
% (3.2-3.5 V) el indicador marcaría 0 LEDs siempre; falta la tabla LFP en firmware. Ajustar esta tabla cuando exista.
|
||||||
|
|
||||||
|
\subsection{LED del módem 4G (en la tarjeta, junto al módulo)}
|
||||||
|
|
||||||
|
\hwtab{%
|
||||||
|
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{3.8cm} X@{}}
|
||||||
|
\toprule
|
||||||
|
\rowcolor{HelgenIndigo}\textcolor{white}{Patrón} & \textcolor{white}{Significado}\\
|
||||||
|
\midrule
|
||||||
|
Fijo & Módem arrancando (primeros segundos).\\
|
||||||
|
Parpadeo regular & Registrado en la red, enviando datos. Correcto.\\
|
||||||
|
Parpadeo irregular & Conectándose a la red / al servidor de correcciones. Espere 2 min.\\
|
||||||
|
Apagado & Módem sin energía o \textbf{«módem oscuro»} (ver batería y solución de problemas).\\
|
||||||
|
\bottomrule
|
||||||
|
\end{tabularx}}
|
||||||
|
% VERIFICAR: patrones tomados de la ECO V5.6 (fijo = arrancando, rápido = normal, lento = comandos, irregular = conectando);
|
||||||
|
% cotejar con el manual del ArduSimple 4G NTRIP Master antes de entregar.
|
||||||
|
|
||||||
|
\section{Batería de respaldo}
|
||||||
|
|
||||||
|
\subsection{Qué hace}
|
||||||
|
|
||||||
|
Cuando la máquina se apaga y los 24 V desaparecen, la unidad \textbf{sigue encendida con su batería}
|
||||||
|
sin reiniciarse y sigue reportando su posición: así el monitor sabe dónde quedó cada máquina durante
|
||||||
|
la noche. Al volver los 24 V, la unidad se reinicia sola en unos 10 s y vuelve a operar normal.
|
||||||
|
|
||||||
|
\hwtab{%
|
||||||
|
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{4.4cm} X@{}}
|
||||||
|
\toprule
|
||||||
|
\rowcolor{HelgenIndigo}\textcolor{white}{Dato} & \textcolor{white}{Valor}\\
|
||||||
|
\midrule
|
||||||
|
Paquete V5.5 & Li-ion 18650, 4 celdas en paralelo (3.0--4.2 V). Cargar solo por debajo de 45 \textdegree C.\\
|
||||||
|
Paquete V5.6 & LiFePO$_4$ de alta temperatura, 26650 (2.5--3.6 V). Carga hasta 60 \textdegree C, más de
|
||||||
|
2\,000 ciclos, química más segura.\\
|
||||||
|
Cuándo carga & Solo con 24 V presentes y la etapa encendida, a partir de $\sim$2.5 min después del arranque.
|
||||||
|
Nunca en batería.\\
|
||||||
|
Tiempo de carga & $\approx$ 8 h de vacío a lleno (corriente $\approx$ 1.4 A). Un turno de trabajo la llena.\\
|
||||||
|
Pausa por calor & Si la celda pasa de 45 \textdegree C (V5.5) la carga se pausa y el monitor muestra
|
||||||
|
\emph{PAUSA NTC}; se reanuda sola al enfriar. Es normal en tardes calurosas.\\
|
||||||
|
% VERIFICAR: umbral de pausa en firmware para LFP (hoy CHG_CELL_HOT_C = 45 C en 0.6.0; el LTC4040 con RNTB 5.6 k permite hasta 60 C).
|
||||||
|
Autonomía V5.5 & Reporte continuo $\approx$ 10--13 h desde que se pierden los 24 V.\\
|
||||||
|
Autonomía V5.6 & Un reporte cada 10 min; \textbf{varios días}.\\
|
||||||
|
% VERIFICAR: cuando el firmware con ciclo de 10 min esté liberado para V5.6.
|
||||||
|
Apagado por batería baja & A 3.40 V la unidad apaga la etapa RTK y queda en reposo (LED de panel apagado)
|
||||||
|
hasta que vuelvan los 24 V. No se daña.\\
|
||||||
|
\bottomrule
|
||||||
|
\end{tabularx}}
|
||||||
|
|
||||||
|
\subsection{¿Es normal que deje de reportar en batería?}
|
||||||
|
|
||||||
\begin{itemize}
|
\begin{itemize}
|
||||||
\item Inspección trimestral: estado del sello, glándulas, torque de antenas y conectores; sin señales de calor (decoloración) ni batería inflada.
|
\item \textbf{Sí es normal} que una unidad V5.5 deje de verse en el monitor \textbf{10--13 h} después
|
||||||
\item Mantenga el gabinete cerrado y sellado; \textbf{no} agregue ventiladores ni perforaciones (rompen el IP67).
|
de apagar la máquina (batería agotada), y que una V5.6 se vea solo \textbf{cada 10 min}.
|
||||||
\item Ante reemplazo de SIM o componentes, siga el procedimiento de Helgen y registre el cambio.
|
Al arrancar la máquina vuelven a reportar en menos de 5 min.
|
||||||
|
\item \textbf{No es normal} que la unidad deje de reportar \textbf{a los pocos minutos} de apagar la
|
||||||
|
máquina, con el LED de panel todavía parpadeando: es un \textbf{«módem oscuro»} (el módem 4G se
|
||||||
|
apagó y no arranca solo en batería, defecto conocido de la V5.5). Vea la solución de problemas.
|
||||||
|
\item \textbf{No es normal} que con la máquina encendida (24 V presentes) la unidad no cargue en toda
|
||||||
|
una jornada (indicador de batería sin subir, monitor sin \emph{CARGANDO}). Llame a Helgen.
|
||||||
|
\end{itemize}
|
||||||
|
|
||||||
|
\begin{helgennotice}[Interruptor de corte]
|
||||||
|
El interruptor del panel desconecta \textbf{todo}, incluida la batería. Póngalo en \textbf{OFF} si la
|
||||||
|
máquina va a estar parada más de dos semanas, en transporte o en taller. En operación normal debe estar
|
||||||
|
en \textbf{ON}. Nunca abra la unidad para desconectar la batería: con el interruptor basta.
|
||||||
|
\end{helgennotice}
|
||||||
|
|
||||||
|
\section{Mantenimiento}
|
||||||
|
|
||||||
|
\subsection{Cada 3 meses (o en cada mantenimiento mayor de la máquina)}
|
||||||
|
|
||||||
|
\begin{enumerate}[leftmargin=1.5em]
|
||||||
|
\item \textbf{Ventilador.} Con la máquina encendida, compruebe que gira y que sale aire por la rejilla.
|
||||||
|
Limpie la rejilla y el filtro con aire a baja presión o brocha; no use agua a presión.
|
||||||
|
% VERIFICAR: si la rejilla lleva filtro (esponja) y con qué periodicidad se cambia.
|
||||||
|
\item \textbf{Antenas.} Revise que las antenas estén firmes, sin golpes ni cables pelados; reapriete
|
||||||
|
los SMA (mano + ¼ de vuelta). Antena GNSS todavía con cielo despejado (no se movió, nada nuevo la
|
||||||
|
tapa).
|
||||||
|
\item \textbf{Conector GX16-5.} Anillo de seguro apretado, sin corrosión, cable sin roces.
|
||||||
|
\item \textbf{Sellos.} Tapa cerrada, tornillos en cruz, prensaestopas apretados, sin entrada de agua o
|
||||||
|
polvo.
|
||||||
|
\item \textbf{Calor.} Sin manchas de decoloración ni olor a quemado. Con la tapa abierta (solo personal
|
||||||
|
autorizado): batería sin inflarse, sin fugas.
|
||||||
|
\item \textbf{Luces.} LED de panel parpadeando; LED RGB verde con la máquina en marcha.
|
||||||
|
\item \textbf{Monitor.} Confirme con Helgen que la unidad reporta y que la batería sube al cargar.
|
||||||
|
\end{enumerate}
|
||||||
|
|
||||||
|
\subsection{Lo que no debe hacer}
|
||||||
|
|
||||||
|
\begin{itemize}
|
||||||
|
\item No abra ni desconecte la tarjeta electrónica; no suelde; no cambie fusibles internos.
|
||||||
|
\item No cambie la batería ni la SIM: lo hace Helgen y lo registra.
|
||||||
|
\item No conecte USB, cargadores ni fuentes a los conectores internos.
|
||||||
|
\item No pinte, perfore ni tape la rejilla del ventilador.
|
||||||
|
\item No reinstale el firmware; si Helgen lo necesita, lo hace por el puerto USB interno.
|
||||||
\end{itemize}
|
\end{itemize}
|
||||||
|
|
||||||
\section{Solución de problemas}
|
\section{Solución de problemas}
|
||||||
|
|
||||||
|
Antes de llamar, tenga a la mano: \textbf{ID de la unidad} (H00xx), \textbf{máquina}, qué luces ve y desde
|
||||||
|
cuándo.
|
||||||
|
|
||||||
\hwtab{%
|
\hwtab{%
|
||||||
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{5.2cm} X@{}}
|
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{4.0cm} L{6.6cm} X@{}}
|
||||||
\toprule
|
\toprule
|
||||||
\rowcolor{HelgenIndigo}\textcolor{white}{Síntoma} & \textcolor{white}{Acción}\\
|
\rowcolor{HelgenIndigo}\textcolor{white}{Síntoma} & \textcolor{white}{Revise usted} & \textcolor{white}{Llame a Helgen si\ldots}\\
|
||||||
\midrule
|
\midrule
|
||||||
LED apagado con alimentación & Verifique 24 V en la salida de la fuente, breaker y fusible; revise el GX16-5.\\
|
LED de panel apagado con la máquina encendida & 24 V en el conector hembra del arnés (pin 1--2), fusible en
|
||||||
LED en parpadeo lento persistente & Revise vista al cielo de la antena GNSS, torque de SMA y cobertura/saldo de la SIM 4G.\\
|
línea, anillo del GX16-5, interruptor de corte en ON. & Hay 24 V en el GX16 y sigue apagado.\\
|
||||||
Desconexiones intermitentes en plataforma & Reporte a Helgen con el ID de la unidad; puede ser un punto de backend, no la unidad.\\
|
LED RGB rojo con 24 V & Deje pasar 1 min (arranque). Mida temperatura: si la unidad está muy caliente, deje
|
||||||
Batería caliente o inflada & Detenga, desconecte y aísle la batería; \textbf{riesgo de incendio}. Reporte de inmediato.\\
|
enfriar con el ventilador girando. & Sigue rojo después de 5 min con 24 V y la unidad fría.\\
|
||||||
|
LED RGB azul más de 15 min & Antena GNSS con cielo despejado, SMA apretado, cable sin daño, antenas 4G a
|
||||||
|
más de 1 m. Mueva la máquina a cielo abierto y espere 10 min. & Sigue azul a cielo abierto: puede ser
|
||||||
|
la base RTK o la señal 4G (Helgen lo ve en el monitor).\\
|
||||||
|
LED RGB magenta más de 2 min & Espere: la unidad reinicia la etapa sola (hasta 3 intentos). & Sigue magenta
|
||||||
|
después de 15 min.\\
|
||||||
|
LED RGB amarillo con la máquina encendida & La unidad está en batería: 24 V, fusible, GX16-5, línea de +24 V
|
||||||
|
permanente (no de ignición). & Hay 24 V en el GX16 y sigue amarillo.\\
|
||||||
|
\textbf{Módem apagado en batería} (la unidad dejó de reportar a los minutos de apagar la máquina; LED de
|
||||||
|
panel parpadea) & Unidades \textbf{V5.5}: \textbf{encienda la máquina (restablezca los 24 V)}: la unidad se
|
||||||
|
reinicia sola y el módem arranca. Si con 24 V sigue sin reportar tras 3 min, pulse el botón
|
||||||
|
\textbf{RESET} del panel una vez. & Ni los 24 V ni RESET lo levantan: Helgen debe pulsar
|
||||||
|
\textbf{RESET 4G} (botón interno de la tarjeta) o revisar la unidad. En V5.6 la unidad reinicia el
|
||||||
|
módem sola.\\
|
||||||
|
% VERIFICAR: si el botón RESET 4G (SW4G1) queda accesible desde el panel en alguna unidad; hoy es SMD en la tarjeta.
|
||||||
|
No aparece en el monitor pero las luces están bien (verde) & Nada en la unidad. & Siempre: suele ser SIM,
|
||||||
|
cobertura o servidor, y se resuelve del lado de Helgen con el ID de la unidad.\\
|
||||||
|
Se ve en el monitor de Helgen pero no en la plataforma del cliente & Nada en la unidad. & Siempre: es un
|
||||||
|
punto de integración (backend), no una falla de campo.\\
|
||||||
|
Posición correcta pero \emph{brinca} varios metros & Antena GNSS bajo estructuras metálicas; antenas 4G
|
||||||
|
demasiado cerca de la GNSS. & Persiste con la antena reubicada.\\
|
||||||
|
Ventilador no gira con 24 V & Rejilla obstruida; algo trabando las aspas. & Está libre y no gira (el
|
||||||
|
ventilador es el que cuida la batería en verano).\\
|
||||||
|
Batería caliente, inflada u olor & \textbf{Interruptor de corte en OFF}, retire 24 V, aísle la unidad
|
||||||
|
lejos de combustibles. \textbf{Riesgo de incendio.} & De inmediato, siempre.\\
|
||||||
|
Unidad mojada por dentro & Interruptor en OFF, retire 24 V, no la seque con calor. & Siempre.\\
|
||||||
\bottomrule
|
\bottomrule
|
||||||
\end{tabularx}}
|
\end{tabularx}}
|
||||||
|
|
||||||
\begin{helgennotice}[Soporte]
|
\begin{helgennotice}[Regla de oro]
|
||||||
Reporte fallas a Helgen con el \textbf{ID de la unidad (cell\_id)} y la máquina. Una unidad
|
Si una unidad reporta en el monitor de Helgen, el hardware está bien. Antes de tocar cables, pida a
|
||||||
que se ve en el monitor de Helgen pero no en la plataforma del cliente suele ser un punto
|
Helgen que revise el estado en el monitor: la unidad envía batería, temperaturas, estado de carga y
|
||||||
de backend, no una falla de campo.
|
calidad RTK cada 30 s, y casi siempre el diagnóstico se hace desde ahí.
|
||||||
\end{helgennotice}
|
\end{helgennotice}
|
||||||
|
|
||||||
|
\section{Contacto}
|
||||||
|
|
||||||
|
\hwtab{%
|
||||||
|
\begin{tabularx}{\textwidth}{@{}>{\bfseries}L{4.4cm} X@{}}
|
||||||
|
\toprule
|
||||||
|
\rowcolor{HelgenIndigo}\textcolor{white}{Canal} & \textcolor{white}{Datos}\\
|
||||||
|
\midrule
|
||||||
|
Soporte técnico Helgen & \texttt{soporte@helgen.tech}\\
|
||||||
|
% VERIFICAR: buzón de soporte definitivo y teléfono/WhatsApp de guardia.
|
||||||
|
Monitor de flota & \texttt{https://monitor.helgen.dev} (acceso con usuario; pídalo a Helgen).\\
|
||||||
|
Datos para reportar & ID de la unidad (H00xx), máquina, terminal, hora, luces observadas y qué se hizo.\\
|
||||||
|
Emergencia (batería, humo) & Interruptor en OFF, retirar 24 V, aislar; avisar al supervisor de seguridad de la
|
||||||
|
terminal y a Helgen.\\
|
||||||
|
\bottomrule
|
||||||
|
\end{tabularx}}
|
||||||
|
|
||||||
|
\section*{Historial de revisiones}
|
||||||
|
|
||||||
|
\hwtab{%
|
||||||
|
\begin{tabularx}{\textwidth}{@{}C{1.6cm} L{3.4cm} X@{}}
|
||||||
|
\toprule
|
||||||
|
\rowcolor{HelgenIndigo}\textcolor{white}{Versión} & \textcolor{white}{Fecha} & \textcolor{white}{Cambios}\\
|
||||||
|
\midrule
|
||||||
|
1.0 & 20 de junio de 2026 & Primera edición: gabinete Yetlebox con HBOX de tarjeta Blackpill, LED único.\\
|
||||||
|
2.0 & 29 de septiembre de 2026 & Unidad HBOX V5.5/V5.6 (EinarBoard con STM32 a bordo, gestor de respaldo
|
||||||
|
LTC4040, batería LiFePO$_4$ en V5.6). Nuevas secciones: conexión eléctrica por GX16-5, red opcional
|
||||||
|
(Ethernet, RS-485, RS-232), secuencia de encendido, tabla de LEDs por grupo, batería de respaldo,
|
||||||
|
«módem apagado en batería». Firmware de referencia 0.6.0.\\
|
||||||
|
\bottomrule
|
||||||
|
\end{tabularx}}
|
||||||
|
|||||||
@ -1,16 +1,18 @@
|
|||||||
% Helgen Drogheda — Manual de Instalación y Operación · DRG-MAN-001 (es-MX)
|
% Helgen Drogheda — Manual de Instalación y Operación · DRG-MAN-001 (es-MX)
|
||||||
|
% v2.0 (29-sep-2026): unidad HBOX V5.5 / V5.6 (EinarBoard con STM32 a bordo, LTC4040, Ethernet, RS-485/RS-232)
|
||||||
\documentclass[11pt]{article}
|
\documentclass[11pt]{article}
|
||||||
\newcommand{\sistema}{Helgen Drogheda — HBOX RTK}
|
\newcommand{\sistema}{Helgen Drogheda — HBOX RTK}
|
||||||
\newcommand{\sistemapdf}{Helgen Drogheda HBOX RTK}
|
\newcommand{\sistemapdf}{Helgen Drogheda HBOX RTK}
|
||||||
\newcommand{\doctipo}{Manual de Instalación y Operación}
|
\newcommand{\doctipo}{Manual de Instalación y Operación}
|
||||||
\input{../../_brand/estilo-helgen.tex}
|
\input{../../_brand/estilo-helgen.tex}
|
||||||
\begin{document}
|
\begin{document}
|
||||||
\helgenportada{Manual de Instalación y Operación}{HBOX + Gabinete — equipo portuario (24 V)}{%
|
\helgenportada{Manual de Instalación y Operación}{HBOX RTK V5.5 / V5.6 — equipo portuario (24 V)}{%
|
||||||
\begin{tabular}{@{}ll@{}}
|
\begin{tabular}{@{}ll@{}}
|
||||||
\textbf{Documento} & DRG-MAN-001 — Manual de Instalación y Operación\\
|
\textbf{Documento} & DRG-MAN-001 — Manual de Instalación y Operación\\
|
||||||
\textbf{Versión} & 1.0\\
|
\textbf{Versión} & 2.0\\
|
||||||
\textbf{Fecha} & 20 de junio de 2026\\
|
\textbf{Fecha} & 29 de septiembre de 2026\\
|
||||||
\textbf{Dirigido a} & Personal de instalación y mantenimiento en sitio\\
|
\textbf{Dirigido a} & Personal de instalación y mantenimiento en sitio\\
|
||||||
|
\textbf{Aplica a} & Unidades HBOX con tarjeta EinarBoard V5.5 y V5.6, firmware 0.6.0\\
|
||||||
\textbf{Clasificación} & Confidencial — uso de Hutchison Ports y Helgen\\
|
\textbf{Clasificación} & Confidencial — uso de Hutchison Ports y Helgen\\
|
||||||
\textbf{Asistencia IA} & Elaborado con asistencia de Claude (Anthropic), revisado por el autor\\
|
\textbf{Asistencia IA} & Elaborado con asistencia de Claude (Anthropic), revisado por el autor\\
|
||||||
\end{tabular}}
|
\end{tabular}}
|
||||||
|
|||||||
BIN
03-Architecture-Hardware/hbox-watchdog-v56-schematic.pdf
Normal file
BIN
03-Architecture-Hardware/hbox-watchdog-v56-schematic.pdf
Normal file
Binary file not shown.
@ -1 +1 @@
|
|||||||
Subproject commit eab556ca5120f404c455adefdb01da1aafaee972
|
Subproject commit b929655453c1dece82022d359791f177c106d542
|
||||||
221
03-Architecture-Hardware/pinmap-v6.md
Normal file
221
03-Architecture-Hardware/pinmap-v6.md
Normal file
@ -0,0 +1,221 @@
|
|||||||
|
# EinarBoard v6 — MCU pin map (U16 STM32F411RET6, LQFP64) for `board_v6.h` / FW 0.7.x
|
||||||
|
Snapshot: sch ecee9fed… / pcb 6ddec80d… (evidence pack 2026-09-28) · Author: D/G auditor (read-only)
|
||||||
|
|
||||||
|
> **Editorial header (v1.0, 2026-09-28).** Source: the D/G auditor's `findings/pinmap-v6.md` (same date, same snapshot), republished as the standalone companion of `2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md` (§4). The table describes **v6 as drawn**. Rows marked **▶ audit** carry the pin-level consequence of a finding that was independently verified (verify_1 = power/RF, verify_2 = layout/BOM/MCU) or of the spare-pin allocation both verifiers accept. Nothing below has been applied to the schematic; the "▶ audit" notes say what changes **if** the fix is adopted. Corrections applied to the auditor's text:
|
||||||
|
> 1. **PA15 / ETH_RST:** pull-down is **4.7 kΩ (C23162)**, not 100 kΩ. The W5500 RSTn has its own internal 62–112 kΩ pull-up (DS v1.0.2 §5.3) on top of the PA15 JTDI 30–50 kΩ pull-up; 4.7 k gives ≤ 0.62 V worst case. D-04's alternative "move to PD2 + 100 k" fails (1.56–2.04 V) and is withdrawn (verify_1, E-02 absorbs D-04).
|
||||||
|
> 2. **Spare-pin allocation (verify_1 conflict (h)):** PD2 = `ETH_PWR_EN` (E-01), PB10 = `PFO` (A-13, absorbs D-10), PC5 = pack-NTC tap (F-51), PA9 = spare (D-12 test pad). D-10's CLPROG → PC5 is dropped. **Open:** D-08's board-ID strap also wanted PD2; no free pin is left for it except PA9 (Leo to choose).
|
||||||
|
> 3. **D-01:** the isolating gate is the **Nexperia 74LVC1G125GV, C12518** (verified Ioff), not the TECH PUBLIC clone C3040595; Rdfu1 22 k → 100 k (C25803). The 10 k series-R alternative is withdrawn (≈ 0.28 mA, same order as the V5.5 back-feed) (verify_2).
|
||||||
|
> 4. **D-06 is merged into F-02 and rated Blocker** (Rig1 ≤ 3 mm of copper from P1.3 + SMBJ33A C224019), not ≤ 5 mm/Major (verify_2).
|
||||||
|
> 5. **HSE distances** are pad-edge **8.32 / 11.30 mm** (the 10.30 / 14.21 mm below are pad-centre) (verify_2, D-02).
|
||||||
|
> 6. **C-01 (Blocker, absorbs D-07):** with the TPS2552 antenna feed, PC2 (`/GNSS_ANT_SHORT_N`) becomes a real short-fault input (FAULT̅, 10 k to /3V3_GNSS); PC1 stays undriven.
|
||||||
|
> 7. **PB4 decode:** the power auditor, citing the LTC4040 datasheet table (p.14), decodes "pausa NTC" = CHRG low ∧ FAULT low and bad battery = CHRG high ∧ FAULT low; this governs over the wording in the PB4 row.
|
||||||
|
|
||||||
|
**Coverage: 64 / 64 pins.** Sources: `evidence/mcu_pins.csv` (netlist), `evidence/pcb_pads.csv` (distances, pad-centre to pad-centre, same net), `evidence/firmware_pins.csv` (V5 `board_v5.h` + `hbox_v5_bringup.ino` 0.6.0), ST DS10314 (DocID026289 Rev 7) Table 8 (pin definitions, I/O structure) and Table 53 (I/O static), and ST's own alternate-function database (`STM32_open_pin_data`: `mcu/STM32F411R(C-E)Tx.xml` + `mcu/IP/GPIO-STM32F411_gpio_v1_0_Modes.xml`, the CubeMX source for DS10314 Table 9). The embedded schematic symbol was checked against the ST LQFP64 pinout: **64/64 pin numbers and names match** (the ERC "symbol differs from library" warning on U16 is cosmetic).
|
||||||
|
|
||||||
|
Legend. **FT** = 5 V-tolerant in digital mode only (DS10314 Table 8 note 4: not in analog or oscillator mode; Table 53 note 5: internal pull-up/down must be off above VDD+0.3 V). **TC** = 3.3 V-only. On this LQFP64 only **PA0** and **PB5** are TC; every other GPIO is FT. PC13–PC15 are backup-domain pins (Table 8 note 2: sink ≤ 3 mA, ≤ 2 MHz, ≤ 30 pF, never a source). **No MCU pin on v6 carries a 5 V or a 1.8 V signal**: all modem 1.8 V lines go through U23/U24 (74LVC2T45) or open-drain Q20/Q21, and every pull-up is to /3V3.
|
||||||
|
"Same?" = does the V5 macro on this pin mean the same thing on v6.
|
||||||
|
|
||||||
|
## 1. Pin table (physical pins 1–64)
|
||||||
|
|
||||||
|
| Pin | Name | v6 net | Connected parts (short) | Function on v6 | Dir / mode (FW) | Peripheral + AF / ADC / EXTI | 5 V needed? / pin | V5 macro on this pin → same? | Proposed v6 macro | Notes / conflicts |
|
||||||
|
|---|---|---|---|---|---|---|---|---|---|---|
|
||||||
|
| 1 | VBAT | /3V3 | 3V3 big net | Backup-domain supply, tied to 3V3 (no coin cell) | power | — | — / S | — | — | RTC + BKP regs + LSE lost whenever /3V3 drops (P5 cut-off open, no USB) |
|
||||||
|
| 2 | PC13 | /LED_C13 | D17 blue LED (K) ← R102 1 k ← /3V3 | Board status LED, active LOW (sink) | OUT, LOW = on | GPIO, EXTI13 | No / FT backup-domain | `PIN_LED_C13` → **same** | `PIN_LED_C13` | I = (3.3 − 2.8 V Vf, C125103) / 1 k ≈ 0.5 mA ≤ 3 mA sink limit ✓ (dim) |
|
||||||
|
| 3 | PC14-OSC32_IN | /LSE_IN | Y4.1 (32.768 kHz C32346, CL 12.5 pF), C115 12 pF | LSE | oscillator | RCC_OSC32_IN | — | `BOARD_LSE_HZ` → same | `BOARD_LSE_HZ 32768UL` | Y4.1 5.54 mm, C115 2.96 mm. Crystal/caps mismatch → D-03 |
|
||||||
|
| 4 | PC15-OSC32_OUT | /LSE_OUT | Y4.2, C116 12 pF | LSE | oscillator | RCC_OSC32_OUT | — | same | — | Y4.2 7.91 mm, C116 6.49 mm (> 5 mm) |
|
||||||
|
| 5 | PH0-OSC_IN | /HSE_IN | Y3.1 (25 MHz HC-49S C14872, CL 20 pF), C113 15 pF | HSE (USB, PLL, **ROM DFU needs it**) | oscillator | RCC_OSC_IN | — | `BOARD_HSE_HZ` → same | `BOARD_HSE_HZ 25000000UL` | Y3.1 **10.30 mm** ctr (**8.32 mm pad edge**, verify_2), C113 13.72 mm, track 14.5 mm → D-02. ▶ audit: Y3 → C2901684 + C113/C114 12 pF C38523 (alt. C9006 + 15 pF C1644) |
|
||||||
|
| 6 | PH1-OSC_OUT | /HSE_OUT | Y3.2, C114 15 pF | HSE | oscillator | RCC_OSC_OUT | — | same | — | Y3.2 **14.21 mm** ctr (**11.30 mm pad edge**, verify_2), C114 17.02 mm, track 20.7 mm → D-02 |
|
||||||
|
| 7 | NRST | /NRST | C104 100 nF (3.26 mm), SW1 RESET, P6.1 RESET-EXT, TP5 | MCU reset only | RST (int. pull-up 30–50 kΩ) | — | — | — (V5: P10) | — | NRST reaches only the MCU. Route 108.6 mm (91.9 F.Cu + 16.8 In2). P6 external cable has no ESD → G-08 |
|
||||||
|
| 8 | PC0 | /ETH_INT | U11.36 ~INT (W5500) | W5500 interrupt, active LOW | IN pull-up | GPIO, ADC1_IN10, **EXTI0** | No / FT | `PIN_ETH_INT` → **same** | `PIN_ETH_INT` | BOOT1 trap avoided (V4 had it on PB2) ✓ |
|
||||||
|
| 9 | PC1 | /GNSS_ANT_DETECT | U18.4 ANT_DETECT — **F9P input** | none usable (see D-07) | **ANALOG / hi-Z**, never drive HIGH while F9P off | GPIO, ADC1_IN11, EXTI1 | No / FT | V5: NC · **V5.6: MODEM_RST_MCU** → different | `PIN_GNSS_ANT_DET` (reserved) | No antenna-current supervisor on v6: MCU cannot learn antenna state here. ▶ audit C-01: stays undriven (open-antenna detect not implemented; infer from C/N0) |
|
||||||
|
| 10 | PC2 | /GNSS_ANT_SHORT_N | U18.6 ANT_SHORT_N — **F9P input** | none usable (D-07) | ANALOG / hi-Z | GPIO, ADC1_IN12 (SPI2_MISO AF5 unused) | No / FT | V5: NC · **V5.6: MODEM_LED_MCU** → different | `PIN_GNSS_ANT_SHORT_N` (reserved) | as PC1. ▶ audit C-01: TPS2552DBVR (C46506) FAULT̅ drives this net (10 k C25804 to /3V3_GNSS) → LOW = antenna short; input, no MCU pull; valid only while the F9P rail is on |
|
||||||
|
| 11 | PC3 | /GNSS_RTK_STAT | U18.20 RTK_STAT (output) | RTK status: 0 = fixed, blinking = corrections in use, 1 = none | IN, pull-DOWN while F9P off | GPIO, ADC1_IN13, **EXTI3** (shared with PB3) | No / FT | V5: NC · **V5.6: MODEM_EN (output!)** → different | `PIN_GNSS_RTK_STAT` | A V5.6 binary would drive this against the F9P output → D-08 |
|
||||||
|
| 12 | VSSA | GND | — | analog ground | power | — | — | — | — | |
|
||||||
|
| 13 | VDDA | /VDDA | R104 10 Ω ← 3V3, C109 100 nF (3.13 mm), C112 1 µF (4.61 mm) | ADC reference (VREF+ bonded) | power | — | — | `ADC_REF 3.3f` → same | — | ✓ DS10314 recommendation |
|
||||||
|
| 14 | PA0-WKUP | /BAT_SENSE | R5 10 k ← /BAT_PLUS, R6 10 k → GND, C5 100 nF (5.6 mm) | Pack voltage / 2 | ANALOG | **ADC1_IN0** (WKUP1 spare) | No (≤ 2.10 V at 4.2 V) / **TC** | `PIN_BAT_SENSE` → **same** | `PIN_BAT_SENSE` | `DIV_RATIO 2.0` unchanged. 0.21 mA permanent pack drain |
|
||||||
|
| 15 | PA1 | /PWR_CTRL | R1 1 k → Q5 MMBT3904 base (**no base pull-down**) → /GATE_LS (R2 10 k to SYS5V) → Q1 AO3401A → /SW_5V → U21 AP2112K → /3V3_GNSS | **F9P rail enable**, HIGH = on | OUT PP, LOW at boot | GPIO / TIM2_CH2 AF1 (soft-start PWM) | No / FT | `PIN_PWR_CTRL` → **CHANGED**: V5 = RTK + 4G stack; v6 = F9P only (modem has PC10) | `PIN_GNSS_PWR` (keep `PIN_PWR_CTRL` alias) | Floats in reset/DFU → D-09 (absorbs A-12). ▶ audit: 100 k C25803 `/BASE_LS` → GND next to Q5 |
|
||||||
|
| 16 | PA2 | /GNSS_TX | U18.43 RXD (F9P UART1 in) | MCU → F9P UART1 (UBX config) | AF PP only while F9P on; INPUT no-pull when off | **USART2_TX AF7** | No / FT | `PIN_GNSS_TX` → same (was simpleRTK2B UART1) | `PIN_GNSS_TX` | 0.5.5 float rule is mandatory (direct into F9P) |
|
||||||
|
| 17 | PA3 | /GNSS_RX | U18.42 TXD (F9P UART1 out) | F9P → MCU NMEA/UBX | AF; pull-up only while F9P on | **USART2_RX AF7** | No / FT | `PIN_GNSS_RX` → same | `PIN_GNSS_RX` | `GNSS = Serial2` |
|
||||||
|
| 18 | VSS | GND | — | ground | power | — | — | — | — | |
|
||||||
|
| 19 | VDD | /3V3 | nearest C106 3.29 mm | supply | power | — | — | — | — | per-pin cap target ≤ 2 mm (Note) |
|
||||||
|
| 20 | PA4 | /5V_SENSE | R7 10 k ← /VEH5V, R8 10 k, C7 100 nF (5.5 mm) | VEH5V / 2 (now U25 output or bench P2) | ANALOG | **ADC1_IN4** | No (2.50 V at 5.00 V, 2.66 V at 5.32 V) / FT | `PIN_5V_SENSE` → same net; source is now on-board U25 | `PIN_5V_SENSE` | LTC4040 PFI real threshold 1.19 V × 3.7 = 4.40 V (LTC4040 DS pin 19) |
|
||||||
|
| 21 | PA5 | /IGN_SENSE | Rig1 22 k ← /IGN_IN (P1.3); Rig2 22 k ∥ Rigb1 3.3 k → GND; C9 100 nF (3.09 mm); D5 BAT54 → /3V3 | Ignition present / vehicle-voltage estimate | **ANALOG** on v6 (V5 read it digital) | **ADC1_IN5** (EXTI5 if digital) | No at the pin (3.23 V at 28 V; clamp ≈ 3.55 V above 30.3 V) / FT (not in analog mode) | `PIN_IGN_SENSE` → same net, **digital read no longer adequate** (12 V vehicles) | `PIN_IGN_SENSE` | Divider midpoint, pin and C9 on one net (junction verified) · D-05, D-06. ▶ audit F-02 (Blocker, absorbs D-06): Rig1 moves ≤ 3 mm of copper from P1.3 + SMBJ33A C224019 at P1.3, so the long run becomes the 22 k-limited `/IGN_SENSE`; pin net unchanged. D-05: Rigb1 3.3 k → 2.2 k C4190 → ratio 0.0833 (12 V → 1.00 V, 24 V → 2.00 V, 36 V → 3.00 V) |
|
||||||
|
| 22 | PA6 | /FAN_PWM | Rg1 100 Ω → Q2 AO3400A gate, Rgs1 100 k | Fan low-side switch, HIGH = on | OUT PP (ON/OFF policy) | GPIO / **TIM3_CH1 AF2** | No / FT | `PIN_FAN_PWM` → **same** | `PIN_FAN` | TIM3 is also PA7's capture timer (§2.4) |
|
||||||
|
| 23 | PA7 | /GNSS_TIMEPULSE | U18.53 TIMEPULSE | F9P 1 PPS | IN, pull-down while F9P off | **TIM3_CH2 AF2** input capture / EXTI7 | No / FT | V5: NC → new | `PIN_GNSS_PPS` | |
|
||||||
|
| 24 | PC4 | /NTC2 | R126 10 k/1 % → 3V3, C157 100 nF (3.11 mm), P8.1 | External NTC probe 2 (10 k B3950) | ANALOG | **ADC1_IN14** | No / FT | V5: NC (V5.6: MODEM_ON_SLEEP, DNP) → new | `PIN_NTC2` | `$PHLG tntc2` (append) |
|
||||||
|
| 25 | PC5 | unconnected (NC flag) | — | **spare** | ANALOG (lowest Idd) | ADC1_IN15 | — | V5: NC (V5.6: MODEM_ASSOC, DNP) | `PIN_SPARE_PC5` → `PIN_NTC_CELL` | ▶ audit F-51 (verify_1 (h)): pack-NTC tap, `/NTC` → 100 k (C25803) / 120 k (C25808) + 10 nF → PC5; PC5 ≤ 2.98 V; valid only with VEH5V present. D-10's CLPROG use dropped |
|
||||||
|
| 26 | PB0 | /EXT_LED | Q4 AO3400A gate, Rled1 10 k → panel LED D1 at **P9** | Panel LED, HIGH = on | OUT PP | GPIO (TIM3_CH3 AF2) | No / FT | `PIN_EXT_LED` → same (connector P8 → P9) | `PIN_EXT_LED` | |
|
||||||
|
| 27 | PB1 | /NTC_TEMP | R42 10 k/1 % → 3V3, C24 100 nF (6.63 mm), P7.1 | External NTC probe 1 (hot-spot, `tntc`) | ANALOG | **ADC1_IN9** | No / FT | `PIN_NTC` → same (connector P12 → P7) | `PIN_NTC` | |
|
||||||
|
| 28 | PB2 | /BOOT1_STRAP | R99 10 k → GND (2.84 mm) | BOOT1 = 0 strap (DFU entry) | never reconfigure | BOOT1 | — | — (V4: ETH_INT!) | — | "never repurpose PB2" ✓ |
|
||||||
|
| 29 | PB10 | unconnected (NC flag) | — | **spare** | ANALOG | TIM2_CH3 AF1, I2C2_SCL AF4, SPI2_SCK AF5, EXTI10 | — | V5: NC | `PIN_SPARE_PB10` → `PIN_PFO` | ▶ audit A-13 (absorbs D-10): U6.20 PFO → PB10, 100 k C25803 pull-up to /3V3, EXTI10 falling = backup entry at VEH5V < 4.40 V |
|
||||||
|
| 30 | VCAP1 | /VCAP1 | C111 4.7 µF (3.19 mm) | core regulator cap | power | — | — | — | — | ✓ |
|
||||||
|
| 31 | VSS | GND | — | ground | power | — | — | — | — | |
|
||||||
|
| 32 | VDD | /3V3 | nearest C105 3.65 mm | supply | power | — | — | — | — | |
|
||||||
|
| 33 | PB12 | /ETH_CS | U11.32 SCSn | W5500 chip select | OUT PP (INPUT_PULLUP while W5500 idle) | GPIO (SPI2_NSS AF5 unused) | No / FT | `PIN_ETH_CS` → **same** | `PIN_ETH_CS` | |
|
||||||
|
| 34 | PB13 | /ETH_SCK | U11.33 | SPI2 SCK | AF | **SPI2_SCK AF5** | No / FT | `PIN_ETH_SCK` → same | `PIN_ETH_SCK` | |
|
||||||
|
| 35 | PB14 | /ETH_MISO | U11.34 | SPI2 MISO (W5500 output) | AF in | **SPI2_MISO AF5** | No / FT | `PIN_ETH_MISO` → same | `PIN_ETH_MISO` | |
|
||||||
|
| 36 | PB15 | /ETH_MOSI | U11.35 | SPI2 MOSI | AF | **SPI2_MOSI AF5** | No / FT | `PIN_ETH_MOSI` → same | `PIN_ETH_MOSI` | |
|
||||||
|
| 37 | PC6 | /USART6_TX | K1.10 (NO contact) → /DIN_4G → U23 (3.3 → 1.8 V) → U19.10 RXD | MCU → modem (AT, GGA, `$PHLG`) when K1 energised (Mode B) | AF PP while modem on; INPUT otherwise | **USART6_TX AF8** | No / FT | V5: NC. **Takes over V5 PA9 `PIN_USART1_TX` (RELAY TX)** | `PIN_MODEM_TX` | NC flag on a connected pin (cosmetic) → D-11 |
|
||||||
|
| 38 | PC7 | /USART6_RX | R106 100 Ω ← /DOUT_4G ← U24 (1.8 → 3.3 V) ← U19.9 TXD; /DOUT_4G also → U18.26 F9P RXD2 | modem → MCU (AT replies + RTCM byte count) | AF, **no pull while F9P off** | **USART6_RX AF8** | No / FT | V5: NC (V5.6 RTCM_TAP, same peripheral) | `PIN_MODEM_RX` | NC flag cosmetic (D-11 → J-04). A pull-up here back-feeds the F9P (D-01). ▶ audit D-01: U27 74LVC1G125GV C12518 on /3V3_GNSS isolates U18.26 (new net `/DOUT_4G_F9P`); PC7/R106 stay on `/DOUT_4G`. B-10: R106 100 Ω → 1 kΩ C14676 |
|
||||||
|
| 39 | PC8 | /MODEM_PWRKEY | Q20 2N7002 gate, R114 100 k PD → U19.1 PWRKEY (int. pull-up to VBAT) | Modem power key; MCU HIGH = key pressed | OUT PP, LOW at boot | GPIO (TIM3_CH3) | No / FT | V5: NC → new | `PIN_MODEM_PWRKEY` | on ≥ 50 ms, off ≥ 2.5 s (Phase-1 spec / Phase-2 delta) |
|
||||||
|
| 40 | PC9 | /MODEM_STATUS | U24.6 (2B) ← U19.66 STATUS (1.8 V) | Modem powered/ready (≈ 11.2 s after power-on) | IN **pull-DOWN** (floats when modem off: U24 Ioff) | GPIO, **EXTI9** (shared with PB9) | No / FT | V5: NC → new | `PIN_MODEM_STATUS` | poll it (EXTI9 belongs to the accelerometer) → D-14 (merged into B-10). ▶ audit B-10: 100 k C25803 `/MODEM_STATUS` → GND |
|
||||||
|
| 41 | PA8 | /CHRG_EN | U6.4 CHGOFF, R56 100 k → GND | Charger disable; HIGH = charge OFF | OUT PP | GPIO (TIM1_CH1 AF1) | No / FT | `PIN_CHRG_EN` → **same** | `PIN_CHRG_EN` | In reset/DFU R56 → charger ON (as V5). ▶ audit A-11: R56 100 k re-netted to /3V3 → charger OFF by default; polarity unchanged |
|
||||||
|
| 42 | PA9 | unconnected (NC flag) | — | **spare** | ANALOG | USART1_TX AF7, OTG_FS_VBUS AF10 | — | `PIN_USART1_TX` → **REMOVED** (role now PC6) | `PIN_DBG_TX` if a pad is added | USART1 is RX-only on v6 (TX alternates PA15/PB6 are taken). Add a test pad → D-12. ▶ audit: only remaining spare after (h); also the only candidate left for D-08's board-ID strap (open) |
|
||||||
|
| 43 | PA10 | /USART1_RX | U18.27 TXD2 (F9P UART2 out), K1.1 (NC → modem DIN), Rdfu1 22 k → /3V3 (2.28 mm) | Passive tap on the F9P → modem stream (fail-safe path through K1 NC) | AF RX, **no internal pull** (PA10 pull-up is 7–14 kΩ, DS Table 53) | **USART1_RX AF7** | No / FT | `PIN_USART1_RX` → **same** (tap), now RX-only | `PIN_F9P_TX2_TAP` | `Uart RELAY(PA10, PA9)` → RX-only instance. ▶ audit D-01: Rdfu1 22 k → 100 k C25803 (back-feed ≤ 27 µA) |
|
||||||
|
| 44 | PA11 | /DFU_DM | J11 A7/B7, D15 PESD5V0S1BA (6.74 mm from J11) | USB FS D− (ROM DFU + CDC console) | AF | **OTG_FS_DM AF10** | No / FT | `CON SerialUSB` → same | — | route 55.1 mm |
|
||||||
|
| 45 | PA12 | /DFU_DP | J11 A6/B6, D14 (3.19 mm) | USB FS D+ | AF | **OTG_FS_DP AF10** | No / FT | same | — | route 50.1 mm |
|
||||||
|
| 46 | PA13 | /SWDIO | TP3 (6.04 mm) | SWD data | AF0 (pull-up at reset) | SYS_JTMS-SWDIO AF0 | — | — | — | |
|
||||||
|
| 47 | VSS | GND | — | ground | power | — | — | — | — | |
|
||||||
|
| 48 | VDD | /3V3 | C107 2.10 mm | supply | power | — | — | — | — | ✓ |
|
||||||
|
| 49 | PA14 | /SWCLK | TP4 (5.43 mm) | SWD clock | AF0 (pull-down at reset) | SYS_JTCK-SWCLK AF0 | — | — | — | |
|
||||||
|
| 50 | PA15 | /ETH_RST | U11.37 RSTn | W5500 reset, LOW = held | OUT PP, drive LOW first thing | GPIO (**JTDI AF0 at reset, 30–50 kΩ pull-up**) | No / FT | `PIN_ETH_RST` → **same** | `PIN_ETH_RST` | W5500 is released during MCU reset/boot → E-02 (absorbs D-04). ▶ audit (verified): **4.7 k C23162 `/ETH_RST` → GND at U11.37** → ≤ 0.62 V worst case (W5500 internal 62–112 kΩ pull-up + PA15 30–50 kΩ); 100 k gives 2.75 V and fails |
|
||||||
|
| 51 | PC10 | /MODEM_PWR_EN | U20.3 EN (AP64350), R113 100 k PD | Modem buck enable, HIGH = on | OUT PP, LOW at boot | GPIO | No / FT | V5: NC (**V5.6 used PC3**) → new | `PIN_MODEM_PWR_EN` | any MCU reset power-cycles the modem (by design). ▶ audit A-01: U20 input moves to /MAIN5V only (D20 removed, no D21); EN control unchanged (R113 100 k PD, EN pull-up 1.5 µA → 0.15 V = OFF) |
|
||||||
|
| 52 | PC11 | /MODEM_RST | Q21 2N7002 gate, R115 100 k PD → U19.16 RESET | Modem reset; MCU HIGH = asserted | OUT PP, LOW at boot | GPIO | No / FT | V5: NC (**V5.6 used PC1**) → new | `PIN_MODEM_RST` | |
|
||||||
|
| 53 | PC12 | /GNSS_RESET_N | U18.49 RESET_N, R105 10 k → /3V3_GNSS | F9P hard reset, LOW = reset | **OUTPUT_OPEN_DRAIN** (or INPUT); never push HIGH | GPIO | No / FT | V5: NC → new | `PIN_GNSS_RESET_N` | push-HIGH with F9P off = back-feed |
|
||||||
|
| 54 | PD2 | unconnected (NC flag) | — | **spare** | ANALOG | TIM3_ETR AF2, EXTI2 | — | V5: NC | `PIN_ETH_PWR_EN` (▶ audit) | ▶ audit E-01 (verify_1 (h)): `/ETH_PWR_EN` → U12.2 EN, 100 k C25803 → GND; HIGH = 3V3_ETH on. D-08's 10 k board-ID strap on this pin **conflicts** and is unresolved |
|
||||||
|
| 55 | PB3 | /CHRG_STAT | U6.8 CHRG (open-drain), R57 100 k → /3V3 | LOW = charging | IN, no pull | GPIO, **EXTI3** (JTDO/SWO AF0 at reset; TIM2_CH2) | No (3V3 pull-up) / FT | `PIN_CHRG_STAT` → **same** | `PIN_CHRG_STAT` | SWO trace unavailable |
|
||||||
|
| 56 | PB4 | /CHRG_FAULT | U6.9 FAULT (open-drain), R58 100 k → /3V3 | LOW = fault / NTC pause | IN | GPIO, EXTI4 (NJTRST pull-up at reset) | No / FT | `PIN_CHRG_FAULT` → **same** | `PIN_CHRG_FAULT` | "pausa NTC" = EN allowed ∧ STAT idle ∧ FAULT low. ▶ audit: the power auditor decodes from the LTC4040 datasheet table (p.14) "pausa NTC" = CHRG low ∧ FAULT low, bad battery = CHRG high ∧ FAULT low; use that decode |
|
||||||
|
| 57 | PB5 | /BYP_CTRL | R40 1 k → Q6 MMBT3904 (R41 10 k B–E) → K1 coil (/SYS5V) | K1 Mode B; HIGH = energised = modem DIN ← PC6 | OUT PP, LOW at boot | GPIO (TIM3_CH2 AF2) | No / **TC** (output only ✓) | `PIN_BYP_CTRL` → same pin; NO contact now = PC6 (was PA9) | `PIN_BYP_CTRL` | K1 0.15 W while held |
|
||||||
|
| 58 | PB6 | /I2C_SCL | R30 4.7 k; U3 SHT40, U10 SC16IS752, U13 PCF8574, U26 SC7A20 | I2C1 SCL | AF OD | **I2C1_SCL AF4** | No / FT | `PIN_I2C_SCL` → same | `PIN_I2C_SCL` | Map: 0x18 SC7A20 (new), 0x20 PCF8574, 0x44 SHT40, 0x4D SC16IS752. **No TMP102** (0x48/0x49) on v6 as drawn. ▶ audit F-51: TMP102 C99269 at 0x48 (ADD0 → GND) between U6 and L6; F-52 option: second TMP102 at 0x49 |
|
||||||
|
| 59 | PB7 | /I2C_SDA | R31 4.7 k; same devices | I2C1 SDA | AF OD | **I2C1_SDA AF4** | No / FT | `PIN_I2C_SDA` → same | `PIN_I2C_SDA` | |
|
||||||
|
| 60 | BOOT0 | /BOOT0 | R98 10 k → GND (3.65 mm), SW2 → 3V3 | Boot select | I (B) | — | — | — | — | route 73.2 mm (61.4 mm on In1) |
|
||||||
|
| 61 | PB8 | /SER_IRQ | U10.15 IRQ (open-drain), R81 10 k → 3V3 | SC16IS752 IRQ | IN | GPIO, **EXTI8** | No / FT | `PIN_SER_IRQ` → **same** | `PIN_SER_IRQ` | |
|
||||||
|
| 62 | PB9 | /ACC_INT1 | U26.5 INT1 (push-pull, active HIGH default) | Motion interrupt / STOP wake | IN, EXTI rising | GPIO, **EXTI9** (TIM4_CH4, TIM11_CH1) | No / FT | V5: NC → new | `PIN_ACC_INT1` | owns EXTI9 |
|
||||||
|
| 63 | VSS | GND | — | ground | power | — | — | — | — | |
|
||||||
|
| 64 | VDD | /3V3 | C110 3.90 mm (shared with pin 1), C108 4.63 mm | supply | power | — | — | — | — | |
|
||||||
|
|
||||||
|
Count check: 50 GPIO pads (PA0–PA15 = 16, PB0–PB10 + PB12–PB15 = 15, PC0–PC15 = 16, PD2 = 1, PH0/PH1 = 2) + NRST, BOOT0, VBAT, VCAP1, VDDA, VSSA (6) + VDD ×4 + VSS ×4 = **64**. 60 pins are connected; the 4 truly unconnected spares are **PA9, PB10, PC5, PD2**.
|
||||||
|
|
||||||
|
## 2. Conflicts and flags
|
||||||
|
|
||||||
|
### 2.1 Firmware pins that are gone or change meaning on v6
|
||||||
|
| V5 item | v6 status | Replacement / action |
|
||||||
|
|---|---|---|
|
||||||
|
| `PIN_USART1_TX` PA9 + `Uart RELAY(PA10, PA9)` | PA9 unconnected (NC flag) | The **console was never on PA9**: `CON = SerialUSB` (PA11/PA12, J11) is unchanged. PA9 was the Mode-B injection path into the modem through K1 NO. On v6 that path is **PC6 USART6_TX → K1.10 (NO)**, and the MCU now also hears the modem on **PC7 USART6_RX**. USART1 stays as an **RX-only** tap on PA10 (F9P TXD2). No UART TX debug pin exists on v6 (D-12). |
|
||||||
|
| `PIN_PWR_CTRL` PA1 | GNSS rail only | Modem power is `PIN_MODEM_PWR_EN` PC10. Stack cycles must never be used for modem recovery. |
|
||||||
|
| PCF8574 P7 → SW4G1 `MODEM_RST` bodge (`PCF_MODEM_RST_BIT 0x80`, `ENABLE_MODEM_RST`) | U13.12 (P7) unconnected; no SW4G1 | Delete the bodge path; use PC11 (reset) / PC8 (PWRKEY) / PC10 (power). |
|
||||||
|
| TMP102 0x48 (`I2C_ADDR_TMP102`, `CHG_CELL_HOT/COOL` source) | **no TMP102 on v6** | Cell temperature for the governor has no on-board source. ▶ audit F-51 (Major, verified): TMP102 C99269 at 0x48 next to U6 (`tchg`) + pack-NTC tap on PC5 (`tcell`, valid with VEH5V present). |
|
||||||
|
| `PIN_ETH_INT` V4 = PB2 | PC0 on v6 (as V5) | ✓ |
|
||||||
|
| V5.6 `board_v56.h` (ECO §H): MODEM_EN PC3, MODEM_RST PC1, MODEM_LED PC2, ONSLP PC4, ASSOC PC5, RTCM_TAP PC7 | v6: PC1/PC2 = F9P inputs, **PC3 = F9P RTK_STAT output**, PC4 = NTC2 | `board_v56.h` and `board_v6.h` must never share a binary: a V5.6 build drives PC3 HIGH into the F9P's push-pull RTK_STAT. Hardware board-ID strap proposed (D-08); its PD2 pin is now claimed by E-01, so the strap pin is open (PA9 is the only spare left). |
|
||||||
|
|
||||||
|
### 2.2 v6 nets with no firmware counterpart (new for 0.7.x)
|
||||||
|
PA7 GNSS_TIMEPULSE · PC1/PC2 ANT_DETECT/ANT_SHORT_N (F9P inputs, reserve) · PC3 GNSS_RTK_STAT · PC4 NTC2 · PC6/PC7 USART6 · PC8 PWRKEY · PC9 STATUS · PC10 MODEM_PWR_EN · PC11 MODEM_RST · PC12 GNSS_RESET_N · PB9 ACC_INT1 (SC7A20 at 0x18).
|
||||||
|
|
||||||
|
### 2.3 ADC and 5 V checks
|
||||||
|
- Every analog net sits on an ADC-capable pad: BAT_SENSE PA0/IN0, 5V_SENSE PA4/IN4, IGN_SENSE PA5/IN5, NTC_TEMP PB1/IN9, NTC2 PC4/IN14. Spare ADC pad: PC5/IN15. ✅
|
||||||
|
- No 5 V signal on any pin; the two TC pins carry PA0 ≤ 2.10 V and PB5 (output). ✅
|
||||||
|
- IGN_SENSE is the only pin that can exceed VDD: it reaches 3.23 V at 28 V, and the BAT54 clamp holds it at ≈ 3.55–3.65 V above ≈ 30.3 V (0.24 mA at 36 V, 1.2 mA at 58 V into /3V3). In analog mode the FT tolerance is lost, so the clamp is what protects it. There is no negative clamp (D-06).
|
||||||
|
|
||||||
|
### 2.4 Alternate-function, timer and EXTI allocation
|
||||||
|
- **No AF conflicts.** USART2 PA2/PA3 AF7 · USART6 PC6/PC7 AF8 · USART1_RX PA10 AF7 (TX-less) · SPI2 PB13/PB14/PB15 AF5 (CS PB12 as GPIO) · I2C1 PB6/PB7 AF4 · OTG_FS PA11/PA12 AF10 · SWD PA13/PA14 AF0. Every peripheral uses one consistent AF set.
|
||||||
|
- USART1 TX cannot be recovered: its alternates are PA9 (NC), PA15 (ETH_RST) and PB6 (I2C1_SCL).
|
||||||
|
- **Timers:** fan PA6 = TIM3_CH1 and PPS PA7 = TIM3_CH2 share TIM3's time base. The fan policy is ON/OFF (GPIO, `drogheda-fan-policy`), so TIM3 is free for PPS capture. If PWM on the fan is ever restored, time-stamp the PPS on EXTI7 (DWT cycle counter) instead. PA1 soft-start uses TIM2_CH2 (free).
|
||||||
|
- **EXTI collisions** (one port per line, SYSCFG_EXTICR): **EXTI3** = PC3 RTK_STAT and PB3 CHRG_STAT; **EXTI9** = PB9 ACC_INT1 and PC9 MODEM_STATUS. Assign EXTI9 to the accelerometer (motion wake) and poll STATUS. Assign EXTI3 to RTK_STAT only if blink timing is wanted, and poll CHRG_STAT. EXTI0 (ETH_INT), EXTI7 (PPS) and EXTI8 (SER_IRQ) are unique.
|
||||||
|
|
||||||
|
### 2.5 Pins that touch the ZED-F9P (back-feed rule, lesson 0.5.5/0.5.6)
|
||||||
|
While `PIN_GNSS_PWR` is LOW: PA2 INPUT no-pull; PA10 no pull (its internal pull-up is 7–14 kΩ); PC7 no pull-up; PC12 released (open-drain); PA7/PC3 no pull-up; PC1/PC2 analog. **The hardware path U24 → /DOUT_4G → U18.26 cannot be fixed in firmware** except by keeping the modem off whenever the F9P is off (D-01, Major, absorbs C-06). ▶ audit fix (verify_2): U27 = Nexperia 74LVC1G125GV **C12518** (Ioff ±2 µA) powered from /3V3_GNSS, OE̅ = GND, 100 nF C14663; Rdfu1 → 100 k C25803. Bench check: /3V3_GNSS < 0.3 V with PA1 LOW and the modem on.
|
||||||
|
|
||||||
|
## 3. Boot and debug
|
||||||
|
|
||||||
|
| Item | v6 | Verdict |
|
||||||
|
|---|---|---|
|
||||||
|
| BOOT0 | R98 10 k → GND at 3.65 mm; SW2 to 3V3 (silk "BOOT") | ✅ |
|
||||||
|
| BOOT1 / PB2 DFU trap | PB2 only on R99 10 k → GND (2.84 mm); ETH_INT on PC0 | ✅ (memory `drogheda-einarboard-30-mcu-integration`) |
|
||||||
|
| ROM DFU needs HSE | Y3 25 MHz is supported, but crystal placement and gm margin are poor | ⚠ D-02 |
|
||||||
|
| NRST | C104 100 nF (3.26 mm, DS10314 value) · SW1 (6 mm tact, NRST on the 6.5 mm pad pair, GND on the other) · P6 RESET-EXT (JST-XH, was P10 on V5) · TP5. Reaches only the MCU. | ✅ circuit / ⚠ no ESD at P6 (G-08) |
|
||||||
|
| SWD | TP3 SWDIO (6.04 mm), TP4 SWCLK (5.43 mm), TP5 NRST, TP6 GND (17.6 mm away), TP7 3V3. No header. SWO impossible (PB3 = CHRG_STAT). | ⚠ usable with clips; D-12 |
|
||||||
|
| USB DFU | PA11/PA12 → J11 (USB-C, CC 5.1 k ×2), D14/D15/D16 PESD5V0S1BA at 3.19 / 6.74 / 6.83 mm from J11; VBUS → D13 → AMS1117 (diode-OR with SYS5V via D12, no back-feed into SYS5V) | ✅ ECO E.5 (DFU part) met |
|
||||||
|
| HSE | Y3 C14872 YXC HC-49S 25 MHz, **CL 20 pF**, −20…+70 °C, with C113/C114 15 pF → CL_eff = 7.5 + (5…10) pF stray = 12.5–17.5 pF. Pads 8.32/11.30 mm edge (10.30/14.21 mm centre) from PH0/PH1 (target ≤ 5). | ❌ D-02 (Minor, verified) |
|
||||||
|
| LSE | Y4 C32346 Epson FC-135, **CL 12.5 pF, ESR 70 kΩ**, with 12 pF caps → CL_eff ≈ 9 pF. Pads 5.54/7.91 mm. | ⚠ D-03 |
|
||||||
|
|
||||||
|
## 4. Specific signals
|
||||||
|
|
||||||
|
- **CHRG_STAT PB3 / CHRG_FAULT PB4:** LTC4040 open-drain (abs max 6 V), R57/R58 100 k to /3V3 (always-on MCU rail, so no back-feed). ✅ **PFO** (U6.20) goes only to TP2, with no pull-up and no MCU pin. **RST** (U6.11) is unconnected. **CLPROG** goes only to TP1 (D-10). ▶ audit: PFO → PB10 (A-13); CLPROG stays on TP1 (no ADC pin left once PC5 takes the pack NTC).
|
||||||
|
- **IGN_SENSE:** 22 k / (22 k ∥ 3.3 k = 2.870 k) → ratio 0.1154 (±1 % parts: 0.1134–0.1174). Pin voltage: **12 V → 1.385 V** (1.30 V with the internal pull-down the V5 firmware enables), **24 V → 2.769 V**, **28 V → 3.231 V**, **36 V → 4.154 V open-circuit, clamped to ≈ 3.55 V** (BAT54 0.24 mA). 58 V: 1.2 mA clamp current; Rig1 dissipates 0.135 W (> 0.1 W 0603 rating, transient only). ADC full scale is reached at 28.6 V. Digital thresholds (DS10314 Table 53, production-tested VIL 0.3 VDD = 0.99 V, VIH 0.7 VDD = 2.31 V): a HIGH is guaranteed only above **20.0 V**. **A 12–14.4 V ignition sits in the undefined band.** Junction check: /IGN_SENSE = {Rig1.2, Rig2.1, Rigb1.1, C9.1, D5.2 (A), U16.21}, one net in the netlist and on the PCB (6 pads, 1 connected group, 14.2 mm F.Cu). **The V5.6 junction loss is not present on v6.** ✅ ▶ audit F-02 (Blocker): the raw `/IGN_IN` runs 106.47 mm on In2 at 0.221 mm from `/VEH5V`; moving Rig1 to P1.3 makes that run the current-limited `/IGN_SENSE` (≤ 1.4 mA at 36 V, 2.5 mA at 58 V); C9 at the MCU keeps τ = 0.25 ms. D-05 changes the ratio to 0.0833 if Rigb1 = 2.2 k.
|
||||||
|
- **Modem control:** PC10 → U20 EN (R113 100 k PD); PC8 → Q20 → PWRKEY (R114 PD); PC11 → Q21 → RESET (R115 PD); PC9 ← U24 ← STATUS 1.8 V. All default OFF or released in reset/DFU. ✅
|
||||||
|
- **GNSS:** RESET_N PC12 with R105 10 k to /3V3_GNSS (open-drain drive) ✅; TIMEPULSE PA7 ✅; RTK_STAT PC3 ✅; ANT_DETECT/ANT_SHORT_N are receiver inputs with nothing to drive them (D-07).
|
||||||
|
- **Accelerometer INT1 (T11):** PB9 EXTI9, push-pull ✅.
|
||||||
|
- **NTC2:** PC4, R126 10 k/1 % + C157 100 nF (3.11 mm), P8 ✅.
|
||||||
|
- **USART6 PC6/PC7:** AF8 on both ✅. TX goes via K1 NO (Mode B only). RX goes via R106 100 Ω and is always connected.
|
||||||
|
- **ERC NC flags on U16.37/38 and U10.13/14:** cosmetic. All four pins are on their nets in the netlist (U16.37 ∈ /USART6_TX {K1.10}; U16.38 ∈ /USART6_RX {R106.2}; U10.13/14 ∈ /I2C_SCL/SDA), the PCB pads carry the same nets (IPC-356 verified) and all four nets are routed. The flags should still be deleted (D-11).
|
||||||
|
|
||||||
|
## 5. Firmware delta list — `board_v6.h` / FW 0.7.x
|
||||||
|
|
||||||
|
**Pins whose meaning changes vs V5:** PA1 (GNSS only), PA9 (gone), PA10 (RX-only tap, direct F9P), PB5 (K1 NO is now PC6), PA5 (read analog), PC1/PC2/PC3/PC4/PC6–PC12/PA7/PB9 (new), TMP102 and the PCF P7 reset (gone).
|
||||||
|
|
||||||
|
**New peripherals to initialise:** USART6 (PC7 RX, PC6 TX, 115200, AT + RTCM byte counter); USART1 RX-only on PA10; TIM3_CH2 capture or EXTI7 on PA7 (PPS); EXTI9 on PB9 and the SC7A20 at 0x18 (LIS3DH-compatible: CTRL_REG1/3, INT1_CFG/THS/DURATION); ADC channels IN5 (IGN) and IN14 (NTC2); LSE in high-drive mode (`LSEMOD`) with an LSI fallback for the RTC wake; W5500 as V5.
|
||||||
|
|
||||||
|
**Default LOW as the very first lines of `setup()`** (before any delay or USB init): PC10 MODEM_PWR_EN, PC8 PWRKEY, PC11 MODEM_RST, PA1 GNSS_PWR, PB5 BYP_CTRL, **PA15 ETH_RST** (it comes out of reset pulled HIGH by JTDI; the 4.7 k of E-02 holds it low until then), PA6 FAN, PB0 EXT_LED, and **PD2 ETH_PWR_EN** if E-01 is adopted. PA8 CHRG_EN is owned by the governor (HIGH until it decides).
|
||||||
|
|
||||||
|
**New inputs if the audit fixes are adopted:** PB10 PFO (EXTI10 falling, A-13); PC5 ADC1_IN15 pack NTC, ratio 120/220 (F-51); TMP102 at 0x48 (F-51) and optionally 0x49 (F-52); PC2 antenna-short fault from the TPS2552 (C-01).
|
||||||
|
|
||||||
|
**Leave hi-Z / analog:** PA9, PB10, PC5, PD2 (unless E-01 / A-13 / F-51 are adopted, which take PD2 / PB10 / PC5), PC1, PC2; all F9P-facing pins while the F9P is off (§2.5); PC7/PC9 while the modem is off (PC9 with pull-down).
|
||||||
|
|
||||||
|
**Open-drain:** PC12. The PC8/PC11 drivers are external FETs, so the MCU pins are push-pull.
|
||||||
|
|
||||||
|
**Sequencing:** PA1 HIGH → ≥ 4 s → PC10 HIGH → 100 ms → PC8 pulse HIGH ≥ 50 ms → wait PC9 HIGH (≈ 11.2 s) or AT `RDY` → work → AT power-off or PC8 HIGH ≥ 2.5 s → PC10 LOW → PA1 LOW. **Never** leave PC10 HIGH with PA1 LOW (D-01) unless the D-01 hardware fix is fitted. Any MCU reset power-cycles the modem (R113) and the F9P (PA1 floats), so recovery logic must assume a cold modem after every reset.
|
||||||
|
|
||||||
|
**Draft header:**
|
||||||
|
```c
|
||||||
|
// board_v6.h — EinarBoard v6 (hbox-watchdog-v6), STM32F411RET6 LQFP64
|
||||||
|
#define HBOX_BOARD_NAME "EinarBoard v6 (HBOX v6)"
|
||||||
|
#define HBOX_BOARD_MCU "STM32F411RET6 LQFP64"
|
||||||
|
#define BOARD_HSE_HZ 25000000UL
|
||||||
|
#define BOARD_LSE_HZ 32768UL
|
||||||
|
#define BOARD_SER_XTAL_HZ 3686400UL // Y2 = C2238 (3.6864 MHz; schematic value text says 1.8432 MHz)
|
||||||
|
// power / analog
|
||||||
|
#define PIN_BAT_SENSE PA0 // ADC1_IN0, /2
|
||||||
|
#define PIN_GNSS_PWR PA1 // HIGH = F9P rail on (Q5->Q1->SW_5V->U21). Was PIN_PWR_CTRL (stack)
|
||||||
|
#define PIN_PWR_CTRL PIN_GNSS_PWR
|
||||||
|
#define PIN_5V_SENSE PA4 // ADC1_IN4, /2 (VEH5V = U25 or P2)
|
||||||
|
#define PIN_IGN_SENSE PA5 // ADC1_IN5 — READ ANALOG (12 V: 1.39 V, 24 V: 2.77 V)
|
||||||
|
#define PIN_NTC PB1 // ADC1_IN9, P7 probe 1
|
||||||
|
#define PIN_NTC2 PC4 // ADC1_IN14, P8 probe 2
|
||||||
|
#define PIN_CHRG_EN PA8 // HIGH = charger OFF (R56 PD -> ON in reset)
|
||||||
|
#define PIN_CHRG_STAT PB3 // LOW = charging (OD, R57 100k)
|
||||||
|
#define PIN_CHRG_FAULT PB4 // LOW = fault / NTC pause (OD, R58 100k)
|
||||||
|
#define PIN_FAN PA6 // HIGH = fan on (TIM3_CH1 if PWM)
|
||||||
|
#define PIN_LED_C13 PC13 // active LOW
|
||||||
|
#define PIN_EXT_LED PB0 // HIGH = panel LED (P9)
|
||||||
|
// GNSS (ZED-F9P U18)
|
||||||
|
#define PIN_GNSS_TX PA2 // USART2_TX AF7 -> F9P RXD (hi-Z when F9P off!)
|
||||||
|
#define PIN_GNSS_RX PA3 // USART2_RX AF7 <- F9P TXD
|
||||||
|
#define PIN_F9P_TX2_TAP PA10 // USART1_RX AF7 <- F9P TXD2 (RX-only, no pull)
|
||||||
|
#define PIN_GNSS_PPS PA7 // TIM3_CH2 AF2 / EXTI7
|
||||||
|
#define PIN_GNSS_RTK_STAT PC3 // 0 fixed / blink corrections / 1 none
|
||||||
|
#define PIN_GNSS_RESET_N PC12 // OPEN-DRAIN only
|
||||||
|
#define PIN_GNSS_ANT_DET PC1 // F9P INPUT — keep analog/hi-Z
|
||||||
|
#define PIN_GNSS_ANT_SHORT_N PC2 // F9P INPUT — keep analog/hi-Z
|
||||||
|
// modem (A7670SA U19)
|
||||||
|
#define PIN_MODEM_TX PC6 // USART6_TX AF8 -> K1 NO -> U23 -> RXD (Mode B)
|
||||||
|
#define PIN_MODEM_RX PC7 // USART6_RX AF8 <- R106 <- U24 <- TXD
|
||||||
|
#define PIN_MODEM_PWRKEY PC8 // HIGH = key pressed (Q20)
|
||||||
|
#define PIN_MODEM_STATUS PC9 // INPUT_PULLDOWN, HIGH = modem on
|
||||||
|
#define PIN_MODEM_PWR_EN PC10 // HIGH = U20 on (R113 PD)
|
||||||
|
#define PIN_MODEM_RST PC11 // HIGH = reset asserted (Q21)
|
||||||
|
#define PIN_BYP_CTRL PB5 // HIGH = K1 energised (modem DIN <- PC6)
|
||||||
|
// I2C1 / expanders / sensors
|
||||||
|
#define PIN_I2C_SCL PB6
|
||||||
|
#define PIN_I2C_SDA PB7
|
||||||
|
#define PIN_SER_IRQ PB8 // SC16IS752 IRQ, EXTI8
|
||||||
|
#define PIN_ACC_INT1 PB9 // SC7A20 INT1, EXTI9
|
||||||
|
#define I2C_ADDR_SC7A20 0x18
|
||||||
|
#define I2C_ADDR_PCF8574 0x20
|
||||||
|
#define I2C_ADDR_SHT40 0x44
|
||||||
|
#define I2C_ADDR_SC16IS 0x4D
|
||||||
|
// Ethernet (W5500 U11, SPI2)
|
||||||
|
#define PIN_ETH_CS PB12
|
||||||
|
#define PIN_ETH_SCK PB13
|
||||||
|
#define PIN_ETH_MISO PB14
|
||||||
|
#define PIN_ETH_MOSI PB15
|
||||||
|
#define PIN_ETH_INT PC0
|
||||||
|
#define PIN_ETH_RST PA15 // JTDI pull-up at reset: drive LOW first (E-02: 4.7k PD C23162)
|
||||||
|
// spare as drawn: PA9 (USART1_TX), PB10, PC5 (ADC1_IN15), PD2
|
||||||
|
// --- only if the audit fixes are adopted (verify_1 conflict (h)) ---
|
||||||
|
// #define PIN_ETH_PWR_EN PD2 // E-01: HIGH = 3V3_ETH on (100k PD)
|
||||||
|
// #define PIN_PFO PB10 // A-13: LTC4040 PFO, LOW = backup, EXTI10 falling
|
||||||
|
// #define PIN_NTC_CELL PC5 // F-51: ADC1_IN15, /NTC * 120/220, valid with VEH5V
|
||||||
|
// #define I2C_ADDR_TMP102_CHG 0x48 // F-51: charger die area (U6/L6)
|
||||||
|
// #define I2C_ADDR_TMP102_MODEM 0x49 // F-52 option
|
||||||
|
// PA9 stays spare (D-12 test pad); board-ID strap (D-08) pin unresolved
|
||||||
|
```
|
||||||
@ -1 +1 @@
|
|||||||
Subproject commit b6faa4b55530a1f8df356d5958eabed45b3be564
|
Subproject commit 43f4472e933d957c4b96118e2c05dfae027f8c9b
|
||||||
@ -0,0 +1,36 @@
|
|||||||
|
# H0008 — vigilancia de carga nocturna (fw 0.6.0, V5.5, SD-15B ~5.25 V)
|
||||||
|
|
||||||
|
Contexto: el LTC4040 reporta CHRG_STAT=1 (cargando) sin falla (cflt=0) desde up=157 s, pero el paquete sube muy despacio
|
||||||
|
(3.55 V el 27-sep 14:00 → 3.83 V el 28-sep 19:08 con vbat_min 3.77 en la ventana de 30 s: oscila 60 mV = ~2.4 A conmutando).
|
||||||
|
Riel 5 V plano (v5 = v5min = 5.25): el cargador NO está tirando ~2 A de forma continua. Hipótesis: (1) ciclado térmico del LTC4040
|
||||||
|
(pista SW_BAT 0.3 mm, EP sin vías: OT interno), (2) corriente media baja por otra causa. Prueba definitiva en la mañana:
|
||||||
|
pinza DC en el cable del paquete y temperatura de U6/L6 con el dedo o IR.
|
||||||
|
|
||||||
|
| Hora (UTC) | vbat | vbat_min | chg | cflt | v5 | v5min | tbat | tmcu/tmax | up_s | pwr | eventos nuevos |
|
||||||
|
|---|---|---|---|---|---|---|---|---|---|---|---|
|
||||||
|
| 2026-09-28T01:08Z | 3.83 | 3.77 | 1 | 0 | 5.25 | 5.25 | 35 | 41/43 | 16367 | VEH | CHG_ON @157 s (v5=5.31 vbat=3.57); CHG_SHED @548 s v5=4.89 → V5_LOST (prueba); MODEM_BACK/MODEM_DARK (sag 160→6 mV, diagnóstico) |
|
||||||
|
| 2026-09-28T02:42Z | 3.94 | 3.87 | 1 | 0 | 5.25 | 5.25 | 34 | 41/43 | 21977 | VEH | ninguno nuevo (sin CHG_SHED, sin fallas). +0.11 V en 94 min → ~1.3 A medios: SÍ está cargando. Oscilación 70 mV en 30 s = corriente pulsante. |
|
||||||
|
| 2026-09-28T04:15Z | 4.01 | 3.96 | 1 | 0 | 5.27 | 5.25 | 34 | 40/43 | 27557 | VEH | ninguno nuevo. +0.07 V en 93 min (3.94→4.01): entra en zona CV (flotación 4.00 V) — la corriente empieza a bajar como debe. |
|
||||||
|
| 2026-09-28T05:51Z | 4.02 | 4.01 | 0 | 0 | 5.30 | 5.26 | 33 | 39/43 | 33317 | VEH | **CHRG_IDLE @30443 s (vbat=4.01)**: el LTC4040 terminó la carga (C/8 en flotación 4.00 V) — paquete LLENO, sin falla. Modem watch oscila MODEM_DARK/BACK cada 2–5 min con sag 38–43 mV (justo en el umbral de 40 mV): ruido, necesita histéresis en 0.5.10. |
|
||||||
|
| 2026-09-28T07:24Z | 4.02 | 4.02 | 0 | 0 | 5.30 | 5.27 | 32 | 38/43 | 38927 | VEH | ninguno nuevo. Paquete lleno y estable (4.02 V, sin oscilación: sin corriente de carga). Cargador en reposo tras terminación; recarga automática al bajar de VRECHRG (~3.9 V). |
|
||||||
|
| 2026-09-28T08:55Z | 4.01 | 4.00 | 0 | 0 | 5.33 | 5.28 | 32 | 38/43 | 44387 | VEH | ninguno nuevo. Reposo tras carga completa (4.01 V). Fin de la vigilancia nocturna: 5/5 chequeos sin alarma. |
|
||||||
|
|
||||||
|
## Conclusión (28-sep 13:35 UTC, del historial de telemetría `telemetry_history.db`, muestras cada 5 min)
|
||||||
|
|
||||||
|
**El cargador funciona. La observación "atascado en 3.80 V" no era una falla.**
|
||||||
|
|
||||||
|
- Arranque con 0.6.0: 27-sep ~20:36 UTC (up_s 61187 a las 13:35Z). CHG_ON @157 s con vbat 3.57 V.
|
||||||
|
- Cargando (`chg=Sí`) de forma continua desde 20:30Z hasta 05:00Z = **102 muestras × 5 min ≈ 8.5 h**, ninguna con `cflt` (0/242 muestras).
|
||||||
|
- Curva: 3.67 (20:30) → 3.73 (21:30) → 3.78 (22:30) → **3.77–3.80 entre 22:00 y 00:30 (la meseta que se vio en vivo)** → 3.85 (01:00) → 3.90 (02:00) → 3.95 (03:00) → 4.00 (04:00) → 4.01 (04:30–05:00).
|
||||||
|
- **Terminación: CHRG_IDLE @ up 30443 s ≈ 05:03Z** (C/8 en flotación 4.00 V, ~8.5 h después del CHG_ON). Después: 4.01–4.03 V en reposo hasta las 13:35Z, sin corriente (sin oscilación 30 s).
|
||||||
|
- Riel 5 V: 5.25 V constante durante la carga (v5min 5.27 según firmware), 5.29–5.33 V en reposo; un solo mínimo 5.10 V en la muestra del arranque. **Ningún CHG_SHED después del boot** (el único, @548 s, fue la prueba de desconexión de Leo: V5_LOST v5=2.14).
|
||||||
|
- Temperaturas durante la carga: batería P4 32–35 °C, MCU 38–42 °C (máx 43). Sin pausa NTC.
|
||||||
|
- Ahora (13:35Z): vbat 4.00, chg=0, cflt=0, v5 5.31, pwr=VEH, bkp_n=0, tbat 29 °C.
|
||||||
|
|
||||||
|
Lectura: la zona 3.75–3.82 V es la parte plana de la curva OCV del Li-ion (la mayor parte de la carga entra ahí con poca variación de tensión) y la oscilación ±60–70 mV en la ventana de 30 s es la caída IR de una corriente de carga pulsante (el LTC4040 comparte L6 entre buck de carga y boost de respaldo). Con +0.11 V/94 min en la meseta la corriente media fue del orden de 1.3 A, no los 2.4 A de R50=825 Ω: el paquete tardó 8.5 h en lugar de ~2–3 h. Eso NO es una falla, pero sí es el margen que hay que medir.
|
||||||
|
|
||||||
|
Pendientes:
|
||||||
|
1. **Pinza DC en el cable del paquete** durante la próxima carga (descargar hasta ~3.6 V y volver a conectar 24 V): esperado ~1.3 A medios; si la pinza marca ~2.4 A a pulsos, es limitación térmica/de entrada del LTC4040; si marca ~1.3 A continuos, revisar RS1/R50 en el ensamble.
|
||||||
|
2. **Temperatura de U6 / L6** con IR o dedo a los 15–20 min de carga (hipótesis de ciclado por OT: EP sin vías, SW_BAT 0.3 mm).
|
||||||
|
3. Firmware 0.5.10 / 0.6.1: **histéresis en el modem watch** (sag5 osciló 38–43 mV alrededor del umbral de 40 mV → MODEM_DARK/BACK cada 2–5 min toda la noche; propuesta: DARK < 30 mV durante 4 ventanas, BACK > 50 mV en 1 ventana).
|
||||||
|
4. Monitor: desplegar HISTORIAL (local, sin subir) para ver esta curva sin exportar CSV.
|
||||||
@ -0,0 +1,274 @@
|
|||||||
|
---
|
||||||
|
title: HBOX V5 (V5.5 / V5.6) — Configuración de una unidad
|
||||||
|
tags: [project-drogheda, hardware, hbox, v5, v5.6, configuracion, ntrip, ethernet, rs485, rs232, bateria, procedimiento]
|
||||||
|
project: Project Drogheda
|
||||||
|
author: Helgen Technologies
|
||||||
|
date: 2026-09-29
|
||||||
|
version: 1.0
|
||||||
|
status: ACTIVO — aplica a toda unidad V5.5 / V5.6 antes de embarcar o de reinstalar
|
||||||
|
audience: técnicos de banco
|
||||||
|
---
|
||||||
|
|
||||||
|
# HBOX V5 — Configuración de una unidad (V5.5 / V5.6)
|
||||||
|
|
||||||
|
**Alcance:** unidad ensamblada (EinarBoard V5.5 o V5.6 + simpleRTK2B + 4G NTRIP Master + SD-15B + paquete de
|
||||||
|
batería + antenas) que ya pasó la [prueba final](v5-prueba-final-unidad.md). Este documento dice **qué tiene que
|
||||||
|
quedar configurado** para que la unidad sea una unidad Helgen y no solo una caja que enciende.
|
||||||
|
**Duración estimada:** 30–40 min por unidad (más si hay que esperar RTK FIX).
|
||||||
|
**Registro:** acta de ensamble (`HBOX5-Exx-Axxx-Rxxxx`) y, si se probaron Ethernet o los puertos serie,
|
||||||
|
[acta Ethernet y puertos serie](../formularios/ethernet-serie.html).
|
||||||
|
|
||||||
|
## Qué es una «unidad configurada»
|
||||||
|
|
||||||
|
Una unidad está configurada cuando cumple **las siete** filas:
|
||||||
|
|
||||||
|
| # | Elemento | Queda configurado cuando… | Dónde se verifica |
|
||||||
|
|---|---|---|---|
|
||||||
|
| 1 | Módem 4G NTRIP Master | parámetros cargados (APN, caster, mountpoint, ID de estación) y registrado en Telcel | §1 |
|
||||||
|
| 2 | simpleRTK2B (ZED-F9P) | configuración Helgen guardada en flash; llega a **RTK FIX (`fix=4`)** con cielo | §2 |
|
||||||
|
| 3 | Identidad | la unidad aparece en el monitor como **`H00xx`** con posición y columna *Salud* | §3 |
|
||||||
|
| 4 | Ethernet (si la unidad lo lleva) | enlace y espejo TCP probados en banco con el build `0.6.0-eth` | §4 |
|
||||||
|
| 5 | Puertos serie (si la unidad los lleva) | `[PASS] SC16IS752` en el POST y niveles correctos en P15/P16 | §5 |
|
||||||
|
| 6 | Paquete de batería | química correcta para la tarjeta y **JP2** en la posición que corresponde | §6 |
|
||||||
|
| 7 | Firmware y consola | versión vigente y `STAT` limpio (tabla de §7) | §7 |
|
||||||
|
|
||||||
|
!!! warning "Sin secretos"
|
||||||
|
El archivo con los parámetros reales del módem (usuario/contraseña del caster y de la APN) **no está en el
|
||||||
|
sitio ni en el repositorio**. Vive **en el servidor / con Leo**. Se pide para la unidad que se va a configurar,
|
||||||
|
se usa y **no se guarda ni se reenvía**. En este documento solo aparece la plantilla.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 0. Material
|
||||||
|
|
||||||
|
| Cant. | Ítem |
|
||||||
|
|---|---|
|
||||||
|
| 1 | Laptop con terminal serie (CoolTerm / PuTTY / `screen`) a **115200**, grabando a archivo |
|
||||||
|
| 2 | Cables USB-C **con datos** |
|
||||||
|
| 1 | Fuente 24 V (o el arnés GX16 real) — ver [prueba final §0](v5-prueba-final-unidad.md) |
|
||||||
|
| 1 | Plantilla [`4G_NTRIP_HelgenSRV-NMEA.example.txt`](../descargas/4G_NTRIP_HelgenSRV-NMEA.example.txt) + el archivo **`.local.txt`** con valores reales entregado por ingeniería |
|
||||||
|
| 1 | Archivo de configuración Helgen del ZED-F9P (u-center `.txt`) — lo entrega ingeniería |
|
||||||
|
| 1 | Antena GNSS con cielo, 2 antenas LTE, SIM Telcel activa |
|
||||||
|
| — | Solo si aplica: cable Ethernet, adaptadores USB-RS485 / USB-RS232 (ver [prueba Ethernet y serie](v5-prueba-ethernet-serie.md)) |
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 1. Módem 4G NTRIP Master — parámetros
|
||||||
|
|
||||||
|
### 1a. Qué se carga
|
||||||
|
|
||||||
|
Los parámetros se envían como líneas `$$$AS+…` a 115200 baudios, una por una; cada una contesta `OK`.
|
||||||
|
La plantilla publicada trae **todas** las claves; los valores sensibles están en blanco:
|
||||||
|
|
||||||
|
| Clave | Qué es | En la plantilla |
|
||||||
|
|---|---|---|
|
||||||
|
| `AS+I=1111` | Entra a modo configuración | fijo |
|
||||||
|
| `AS+A` · `AS+Q` · `AS+q` | APN: host, usuario, contraseña | `<APN_HOST>` `<APN_USER>` `<APN_PASS>` |
|
||||||
|
| `AS+S` · `AS+P` | Caster NTRIP: host y puerto | `<NTRIP_CASTER_HOST>` `<NTRIP_CASTER_PORT>` |
|
||||||
|
| `AS+U` · `AS+M` | Caster: `usuario:contraseña` y mountpoint | `<NTRIP_USER>:<NTRIP_PASS>` `<NTRIP_MOUNTPOINT>` |
|
||||||
|
| `AS+B=115200` | Velocidad del puerto hacia el F9P | fijo |
|
||||||
|
| `AS+r` · `AS+h` · `AS+k=2` | Servidor secundario (monitor Helgen): IP, puerto, modo | `<SECONDARY_SERVER_IP>` `<SECONDARY_SERVER_PORT>` |
|
||||||
|
| `AS+K` | **ID de estación** → es el `H00xx` de la unidad (§3) | `<STATION_ID>` |
|
||||||
|
|
||||||
|
### 1b. Cómo se carga
|
||||||
|
|
||||||
|
1. **Módulo suelto (banco, antes del ensamble):** módem en el zócalo XBee del simpleRTK2B, terminal en el USB
|
||||||
|
**XBEE** del simpleRTK2B a 115200, enviar el `.local.txt` línea por línea — es el §3b de
|
||||||
|
[Módulos e integración](v5-modulos-integracion.md).
|
||||||
|
2. **Unidad ya ensamblada (módem en J7/J8 de la EinarBoard):** el USB-C **J9** de la tarjeta va al USB del módem
|
||||||
|
(`USB_DP/DM` → J7 pines 7/8, según netlist V5.6). Terminal en J9 a 115200 y mismo procedimiento.
|
||||||
|
<!-- VERIFICAR: que el módem enumere por J9 con la etapa encendida y acepte $$$AS+ por ese puerto; hasta hoy solo se ha configurado por el USB XBEE del simpleRTK2B -->
|
||||||
|
3. Al terminar: `$$$AS+I=1111` y leer de vuelta `AS+K`; anotar el ID en el acta.
|
||||||
|
|
||||||
|
!!! note "Sin cable en J9 durante las pruebas de batería"
|
||||||
|
J9 entrega VBUS al módulo. Con cable en J9 el módem queda alimentado por la laptop y las pruebas de batería
|
||||||
|
y de reset del módem **no valen**. Se conecta solo para configurar y se retira.
|
||||||
|
|
||||||
|
- [ ] Todas las líneas contestaron `OK` (ninguna `ERROR`).
|
||||||
|
- [ ] LED de red del módem en parpadeo lento / fijo (registrado en Telcel) en < 2 min con antenas puestas.
|
||||||
|
- [ ] `AS+K` anotado en el acta.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 2. simpleRTK2B — configuración y RTK FIX
|
||||||
|
|
||||||
|
1. El módulo trae la configuración Helgen desde su acta (UART1 a 115200, UART2 a la velocidad del módem, mensajes
|
||||||
|
NMEA). Si el módulo llegó sin acta: cargarla con u-center (**Tools → Receiver Configuration → Transfer file → GNSS**),
|
||||||
|
**UBX-CFG-CFG → Save**, desconectar y reconectar: debe seguir a 115200 con `$GNGGA`.
|
||||||
|
2. En la consola del HBOX (J11, 115200), con la etapa encendida (`STAT … stack=ON`), teclear **`n`**: 20 s de
|
||||||
|
tramas `$GNGGA` con `fix=` y `sats=`.
|
||||||
|
3. Con antena al cielo y módem registrado, esperar hasta **`fix=4` = RTK FIX** (típico 1–5 min; máximo 10).
|
||||||
|
`STAT` debe decir `gga=RTK_FIX sats≥10 hdop<1.5` y el LED RGB queda **verde**.
|
||||||
|
|
||||||
|
| `fix=` | Significado | Aceptable para embarcar |
|
||||||
|
|---|---|---|
|
||||||
|
| 0 | sin fix | no |
|
||||||
|
| 1 | GPS autónomo | no (correcciones no llegan) |
|
||||||
|
| 5 | RTK FLOAT | no, salvo cielo malo documentado |
|
||||||
|
| **4** | **RTK FIX** | **sí** |
|
||||||
|
|
||||||
|
- [ ] `fix=4` alcanzado y estable 5 min. Anotar tiempo y satélites.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 3. Identidad `H00xx` y registro en el monitor
|
||||||
|
|
||||||
|
- La identidad de la unidad en el monitor (**monitor.helgen.dev**, htracker) **sale del módem**: el NTRIP Master
|
||||||
|
envía una trama `$GPTXT` cuyo tercer campo es el ID de estación configurado en `AS+K`; el servidor toma ese
|
||||||
|
campo como `H00xx`. <!-- VERIFICAR: confirmar con Leo que AS+K se captura literalmente como H00xx (retranslator: parse_gptxt → parts[2]) -->
|
||||||
|
- Por eso **el `H00xx` se asigna al configurar el módem** (§1) y no cambia si se cambia la tarjeta; sí cambia si
|
||||||
|
se cambia el módem. Anotar en la etiqueta interior de la tapa: `HBOX5-Exx-Axxx-Rxxxx · H00xx`.
|
||||||
|
- Verificación: con 24 V, etapa ON y módem registrado, en ≤ 2 min el monitor muestra la fila `H00xx` con posición
|
||||||
|
a 1 Hz y la columna **Salud** (fw, `vbat`, temperaturas, `v5min`). En consola: `STAT … modoB=ON relay=… phlg_aire=…`
|
||||||
|
subiendo de 1 en 1 cada 30 s.
|
||||||
|
|
||||||
|
!!! note "Ethernet no cambia la identidad"
|
||||||
|
Por el espejo Ethernet la tarjeta manda `$PHID` (UID del MCU, fw, tarjeta, MAC). El monitor **todavía no lo usa**:
|
||||||
|
hoy la identidad sigue siendo el `$GPTXT` del módem.
|
||||||
|
|
||||||
|
- [ ] La unidad aparece en el monitor como `H00xx` con Salud. Anotar `H00xx` en el acta.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 4. Ethernet (solo unidades con RJ45 en el panel)
|
||||||
|
|
||||||
|
**Lo que hay en la tarjeta:** W5500 (U11) en SPI2, RJ45 J10 con LEDs de enlace y actividad, alimentación
|
||||||
|
`3V3_ETH` desde el 5 V del sistema. **No hay PoE** (J10 pines 7/8 sin conectar): la unidad sigue necesitando
|
||||||
|
24 V. Un switch PoE ni ayuda ni estorba.
|
||||||
|
|
||||||
|
**Lo que hace el firmware (build de banco `0.6.0-eth`, `-DENABLE_ETH=1`; el binario de campo 0.6.0 NO lo incluye):**
|
||||||
|
|
||||||
|
| Parámetro | Valor por defecto | Cómo se cambia |
|
||||||
|
|---|---|---|
|
||||||
|
| Dirección propia | **DHCP**; si no hay respuesta en 4 s → estática **192.168.7.2/24** | `-DETH_DHCP=0` · `-DETH_IP=192,168,1,50` |
|
||||||
|
| Servidor (espejo TCP) | **192.168.7.1:5010**, cliente TCP, reintento cada 5 s | `-DETH_SERVER_IP=192,168,1,10` · `-DETH_SERVER_PORT=5010` |
|
||||||
|
| Qué sale por el socket | todas las NMEA válidas del F9P + cada `$PHLG` + cada `$PHEV` + `$PHID` al conectar y cada 5 min | — |
|
||||||
|
| Cuándo está activo | solo con 5 V presente (nunca en batería ni por USB); tecla **`E`** on/off | — |
|
||||||
|
|
||||||
|
!!! warning "Cambiar IP o servidor = recompilar"
|
||||||
|
Hoy la IP y el servidor son **banderas de compilación**, no parámetros de la unidad: no se cambian desde la consola
|
||||||
|
ni se guardan. Cualquier valor distinto al de banco (192.168.7.x) lo compila ingeniería y entrega un `.bin` con
|
||||||
|
su SHA-256. **No existe todavía build de campo con Ethernet.**
|
||||||
|
|
||||||
|
!!! note "Qué hace el monitor con el espejo Ethernet: nada, por ahora"
|
||||||
|
El servidor htracker no escucha ese socket. El espejo sirve para **probar el hardware en banco** (`nc -lk 5010`
|
||||||
|
en la laptop) y como camino futuro. La unidad en el puerto sigue reportando por el módem 4G.
|
||||||
|
|
||||||
|
**Prueba de banco (resumen; detalle en [prueba Ethernet y puertos serie](v5-prueba-ethernet-serie.md)):** laptop
|
||||||
|
en 192.168.7.1/24, cable directo a J10, `nc -lk 5010`; con 24 V y etapa ON debe llegar `$PHID,…` y luego NMEA.
|
||||||
|
|
||||||
|
- [ ] Ethernet probado en banco y registrado en el acta (o «no aplica: panel sin RJ45»).
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 5. Puertos serie P15 (RS-485) y P16 (RS-232)
|
||||||
|
|
||||||
|
**Lo que hay en la tarjeta:** UART dual SC16IS752 (U10, I²C 0x4D, cristal Y2 3.6864 MHz) → canal A a un
|
||||||
|
transceptor RS-485 (U14 SP3485) en **P15**; canal B a un MAX3232 (U15) en **P16**. Ambos son clemas Phoenix MC 1,5
|
||||||
|
de 3 vías (paso 3.5 mm).
|
||||||
|
|
||||||
|
| Conector | Pin 1 | Pin 2 | Pin 3 | Notas |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| **P15 RS-485** | **A** | **B** | **GND** | Semi-dúplex (2 hilos). **JP5** = terminación 120 Ω (R82) entre A y B |
|
||||||
|
| **P16 RS-232** | **TX** (sale del HBOX) | **RX** (entra al HBOX) | **GND** | Niveles ±5 V (MAX3232). Es un DTE |
|
||||||
|
|
||||||
|
**Regla de JP5 (terminación RS-485):** un bus RS-485 se termina **solo en sus dos extremos**. JP5 (puente de soldadura,
|
||||||
|
abierto de fábrica) se cierra únicamente si el HBOX es uno de los dos extremos del bus. En un bus de dos nodos
|
||||||
|
(HBOX + un equipo) se cierran los dos. Nunca cerrar JP5 en un nodo intermedio.
|
||||||
|
|
||||||
|
**Cruce RS-232:** el HBOX es DTE (TX es salida). Contra otro DTE (laptop, PLC con DB9 macho) se cruza:
|
||||||
|
`P16.1 TX → RXD (DB9 pin 2)` · `P16.2 RX ← TXD (DB9 pin 3)` · `P16.3 GND ↔ DB9 pin 5`. Contra un DCE (módem, equipo
|
||||||
|
con DB9 hembra) va directo.
|
||||||
|
|
||||||
|
**Cable a las clemas:** alambre 0.2–1.5 mm² (AWG 24–16), pelado 7 mm, sin estaño en la punta (o con puntera). RS-485
|
||||||
|
con par trenzado (A/B) y el GND por el mismo cable.
|
||||||
|
|
||||||
|
!!! note "Lo que el firmware hace hoy con los puertos"
|
||||||
|
Firmware 0.6.0: **solo prueba de presencia** del SC16IS752 en el POST (`[PASS] SC16IS752 0x4D ACK, SPR rd=0xA5`).
|
||||||
|
No hay tráfico de aplicación, no hay velocidad configurada y el protocolo hacia el equipo del cliente está
|
||||||
|
**por definir**. El auto-test de lazo (loopback) está planeado para **0.6.1**. Parámetros previstos de banco:
|
||||||
|
**9600 8N1** en ambos puertos <!-- VERIFICAR: velocidad y formato de banco de 0.6.1 -->.
|
||||||
|
|
||||||
|
- [ ] `[PASS] SC16IS752` en el POST de la consola.
|
||||||
|
- [ ] JP5 en la posición que pide la instalación (anotar en el acta: abierto / cerrado).
|
||||||
|
- [ ] Si se hizo la prueba con adaptadores: resultado en el [acta Ethernet y puertos serie](../formularios/ethernet-serie.html).
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 6. Paquete de batería — química y JP2
|
||||||
|
|
||||||
|
La química del paquete **la fija la tarjeta**, no el técnico. El LTC4040 lee la posición de **JP2** (pin F2) y con ella
|
||||||
|
decide el voltaje de flotación; si no coincide con el paquete, o no carga o sobrecarga.
|
||||||
|
|
||||||
|
| Tarjeta | Paquete | JP2 (puente de soldadura de 3 pads) | RNTB (R55) / NTC del paquete | Flotación |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| **V5.5** (lote 22-Ago, 15 pzas) | **Li-ion 18650 1S4P** | **1-2** (F2 alto = Li-ion) | 10 k / NTC 10 k | ≈ 4.0–4.1 V |
|
||||||
|
| **V5.6** (ECO 28-Sep) | **LiFePO4 alta temperatura 26650** | **2-3** (F2 bajo = LFP) | **5.6 k** / NTC B3380 | 3.50 V |
|
||||||
|
|
||||||
|
!!! danger "Cruce de química = FALLA"
|
||||||
|
- Paquete **Li-ion** en una tarjeta con **JP2 2-3** (LFP): el cargador flota a 3.50 V → el paquete nunca se llena,
|
||||||
|
autonomía de minutos.
|
||||||
|
- Paquete **LFP** en una tarjeta con **JP2 1-2** (Li-ion): el cargador intenta 4.0 V sobre una celda de 3.6 V máx →
|
||||||
|
**sobrecarga**. No embarcar.
|
||||||
|
|
||||||
|
Antes de conectar P4: **leer JP2 con lupa** (serigrafía V5.6: `JP2 = F2 (Li-ion / LFP)`) y comparar con la etiqueta
|
||||||
|
del paquete. Si no coinciden, la unidad se detiene y se avisa a ingeniería. JP2 **no** se cambia en banco.
|
||||||
|
|
||||||
|
Conexión: P4 = JST XH-3: pin 1 **BAT+**, pin 2 **GND**, pin 3 **NTC** del paquete. Medir en vacío antes de conectar:
|
||||||
|
Li-ion 3.0–4.2 V; LFP 2.8–3.6 V.
|
||||||
|
|
||||||
|
Comprobación en consola (24 V, etapa ON, > 150 s tras el arranque): `STAT … carga=PROVING` → `carga=ON … ltc=CARGANDO`
|
||||||
|
y en el monitor **🔌 CARGANDO**. `vbat` debe subir en la siguiente media hora. Detalle en
|
||||||
|
[prueba de módem en batería — caja 0.6.0](prueba-bateria-modem.md).
|
||||||
|
|
||||||
|
- [ ] Química del paquete = posición de JP2. Anotar ambas en el acta.
|
||||||
|
- [ ] `ltc=CARGANDO` visto en consola.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 7. Checklist final de consola y versiones
|
||||||
|
|
||||||
|
Con 24 V + ignición, etapa ON ≥ 5 min, antena al cielo, batería conectada. Teclear **`s`** y leer la línea `STAT`:
|
||||||
|
|
||||||
|
| Campo | Debe decir | Si no |
|
||||||
|
|---|---|---|
|
||||||
|
| encabezado (tras reset) | `hbox-v5-bringup 0.6.0 built …` | otra versión → re-flashear (tabla abajo) |
|
||||||
|
| `v5=` | `5.2x–5.3x(ok)` (nunca `BAJO` ni `no`) | SD-15B ajustado a ~5.3 V; arnés |
|
||||||
|
| `v5min=` | ≥ 4.9 | riel cae con ráfaga LTE → fuente / SD-15B |
|
||||||
|
| `vbat=` | Li-ion 3.6–4.1 · LFP 3.2–3.5 <!-- VERIFICAR: rango LFP con firmware para V5.6 --> | paquete / P4 |
|
||||||
|
| `chrg=` · `ltc=` · `carga=` | `chg` · `CARGANDO` · `ON` (tras ~150 s) | ver §6 |
|
||||||
|
| `flt=` | `none` | `FAULT` → LTC4040 / NTC del paquete |
|
||||||
|
| `tair=` / `rh=` · `tbat=` · `tmcu=` | valores plausibles (< 45 °C en banco), no `n/d` | I²C: U3 / U4 |
|
||||||
|
| `i2cerr=` | `0` | soldadura U3 / U4 / U13 / U10 |
|
||||||
|
| `stack=` · `modo=` | `ON` · `AUTO` | `MAN` → teclear `A` |
|
||||||
|
| `gga=` · `sats=` | `RTK_FIX` · ≥ 10 | §2 |
|
||||||
|
| `modoB=` · `phlg_aire=` | `ON` · sube cada 30 s | K1 / módem |
|
||||||
|
| `rtcm_age=` | pocos segundos (no `rtcm=none`) | correcciones no llegan → §1 |
|
||||||
|
| `modem=` | **`vivo`** (tras la gracia de 2 min) | `SOSPECHOSO` → módem oscuro: SW4G1 y revisar |
|
||||||
|
| `rec=` | `0` sin `LIMP` | NMEA intermitente: MOD1 / UART1 |
|
||||||
|
| `eth=` (solo build -eth) | `CONECTADO ip=…` con cable; `off` sin 5 V | §4 |
|
||||||
|
|
||||||
|
**V5.6:** el firmware para V5.6 (`MODEM_EN`, `tchg`, `tcell`, `tmodem`) todavía no existe; hasta que se publique, una
|
||||||
|
V5.6 se prueba con el 0.6.0 de V5.5 y los campos nuevos no aparecen. <!-- VERIFICAR: versión y nombre del binario V5.6 cuando se publique -->
|
||||||
|
|
||||||
|
### Firmware vigente por tarjeta (29-sep-2026)
|
||||||
|
|
||||||
|
| Tarjeta | Binario | Versión | Notas |
|
||||||
|
|---|---|---|---|
|
||||||
|
| **V5** (V5.5 y, por ahora, V5.6) | `hbox-v5-bringup_0.6.0.bin` | **0.6.0** | 0.5.9 + gobernador de carga. Build `0.6.0-eth` solo banco |
|
||||||
|
| **V4** | `hbox-tarjetaV4_0.6.0.bin` | **0.6.0** | mismo sketch, `-DHBOX_BOARD_V4`; DFU solo con USB |
|
||||||
|
| **V3** (flota en campo) | `hbox-tarjetaV3_4.0.0.bin` | **4.0.0** | compilado, sin prueba de banco |
|
||||||
|
|
||||||
|
Descargas y SHA-256: [Descargas](../descargas/index.md). Un binario **nunca** se cruza de tarjeta.
|
||||||
|
|
||||||
|
- [ ] `STAT` limpio (tabla anterior) pegado en el acta junto con el encabezado de versión.
|
||||||
|
- [ ] Etiquetas exterior e interior con `HBOX5-Exx-Axxx-Rxxxx` y `H00xx`.
|
||||||
|
- [ ] Interruptor de corte (P11) en **OFF** para almacenar/embarcar.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Historial de revisiones
|
||||||
|
|
||||||
|
| Versión | Fecha | Autor | Cambios |
|
||||||
|
|---|---|---|---|
|
||||||
|
| 1.0 | 2026-09-29 | Helgen Technologies | Primera versión: define «unidad configurada» para V5.5/V5.6 (4G, F9P, identidad H00xx, Ethernet, RS-485/RS-232, química/JP2, checklist de consola). |
|
||||||
@ -0,0 +1,239 @@
|
|||||||
|
---
|
||||||
|
title: HBOX V5 (V5.5 / V5.6) — Prueba de banco de Ethernet y puertos serie (RS-485 / RS-232)
|
||||||
|
tags: [project-drogheda, hardware, hbox, v5, v5.6, ethernet, w5500, rs485, rs232, sc16is752, testing, procedimiento]
|
||||||
|
project: Project Drogheda
|
||||||
|
author: Helgen Technologies
|
||||||
|
date: 2026-09-29
|
||||||
|
version: 1.0
|
||||||
|
status: ACTIVO — obligatoria en al menos una V5.5 ANTES de pedir la V5.6; después, en toda unidad con RJ45 o clemas serie en el panel
|
||||||
|
audience: técnicos de banco
|
||||||
|
---
|
||||||
|
|
||||||
|
# HBOX V5 — Prueba de banco: Ethernet y puertos serie
|
||||||
|
|
||||||
|
**Objetivo:** demostrar en hardware real que el W5500 (Ethernet) y el SC16IS752 con sus transceptores (RS-485 en
|
||||||
|
P15, RS-232 en P16) funcionan. Hasta el 28-sep **Ethernet nunca se había ejercitado en una tarjeta real**; la V5.6
|
||||||
|
copia ese bloque tal cual, así que esta prueba en una V5.5 es condición para ordenar la V5.6.
|
||||||
|
**Duración:** Ethernet 15 min · serie 15 min.
|
||||||
|
**Registro:** [**▶ acta Ethernet y puertos serie**](../formularios/ethernet-serie.html).
|
||||||
|
|
||||||
|
!!! danger "Seguridad eléctrica — las tres reglas"
|
||||||
|
1. **Nunca probar Ethernet con la unidad solo en batería ni solo por USB.** El W5500 se alimenta de `3V3_ETH`, que
|
||||||
|
cuelga del 5 V del sistema: sin 5 V el chip está sin alimentar y el firmware lo deja en reset. En batería el
|
||||||
|
firmware tampoco lo enciende (no valen sus ~130 mA).
|
||||||
|
2. **5 V del sistema ≥ 5.2 V** durante la prueba (SD-15B ajustado a ~5.3 V o fuente de banco a 5.3 V en P2). Con
|
||||||
|
menos, la ráfaga LTE del módem lleva el riel al PFI 4.60 V del LTC4040 y la tarjeta se reinicia a media prueba.
|
||||||
|
3. **Sin batería si se usa fuente de banco en P2** sin 24 V (no hay cargador que gobernar, pero un paquete Li-ion
|
||||||
|
sobre una fuente mal ajustada no se perdona). Lo normal: 24 V al GX16 y el SD-15B interno.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 0. Material
|
||||||
|
|
||||||
|
| Cant. | Ítem |
|
||||||
|
|---|---|
|
||||||
|
| 1 | Unidad V5 ensamblada (tarjeta + simpleRTK2B + módem + antenas) o tarjeta V5 sola + simpleRTK2B (para ver NMEA) |
|
||||||
|
| 1 | Fuente 24 V al GX16 (o fuente 5.3 V / 3 A en P2) |
|
||||||
|
| 1 | Laptop con terminal serie (115200) grabando a archivo, **y** con `nc` (macOS/Linux) o `ncat` (Windows, Nmap) |
|
||||||
|
| 1 | Binario de banco **`hbox-v5-bringup_0.6.0-eth.bin`** (lo compila ingeniería con `-DENABLE_ETH=1`; SHA-256 en su entrega) <!-- VERIFICAR: nombre y SHA-256 del binario -eth publicado --> |
|
||||||
|
| 1 | Cable Ethernet **directo** (cat 5e o mejor), 1–3 m; el W5500 hace Auto-MDIX, no hace falta cruzado |
|
||||||
|
| 1 | Adaptador **USB ↔ RS-485** (con terminales A/B o D+/D−) |
|
||||||
|
| 1 | Adaptador **USB ↔ RS-232** (DB9 macho, chip FTDI/Prolific) + 3 cables con puntera para la clema |
|
||||||
|
| 1 | Multímetro |
|
||||||
|
| — | Destornillador plano 2.5 mm para las clemas Phoenix MC 1,5 |
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## A. Prueba de Ethernet (build `0.6.0-eth`)
|
||||||
|
|
||||||
|
### A1. Preparar la laptop (una vez)
|
||||||
|
|
||||||
|
1. Adaptador Ethernet de la laptop en **IP manual 192.168.7.1**, máscara **255.255.255.0**, sin gateway.
|
||||||
|
(Si en vez de cable directo se usa un switch con DHCP, la unidad tomará la IP del DHCP; entonces la laptop
|
||||||
|
debe estar en esa red y la unidad seguirá buscando el servidor en 192.168.7.1 — por eso el cable directo es lo más simple.)
|
||||||
|
2. Firewall de la laptop: permitir entradas al puerto **5010/TCP** (o desactivarlo durante la prueba).
|
||||||
|
3. Abrir un terminal y dejar escuchando:
|
||||||
|
|
||||||
|
```bash
|
||||||
|
nc -lk 5010 # macOS / Linux
|
||||||
|
ncat -lk 5010 # Windows (Nmap)
|
||||||
|
```
|
||||||
|
|
||||||
|
### A2. Flashear el build de banco
|
||||||
|
|
||||||
|
1. DFU en **J11** (mantener SW2, pulsar y soltar SW1, soltar SW2) — igual que el
|
||||||
|
[procedimiento de flasheo §5](v5-prueba-y-flasheo.md). Solo USB, sin 24 V.
|
||||||
|
2. `dfu-util -a 0 -s 0x08000000:leave -D hbox-v5-bringup_0.6.0-eth.bin` (o STM32CubeProgrammer).
|
||||||
|
3. Terminal serie en J11: la primera línea debe decir **`hbox-v5-bringup 0.6.0-eth`**. La ayuda (`h`) debe listar la
|
||||||
|
tecla `E=Ethernet on/off`.
|
||||||
|
|
||||||
|
!!! warning "Al terminar, regresar la unidad a 0.6.0"
|
||||||
|
El build `-eth` es de banco. Antes de embarcar se vuelve a flashear **`hbox-v5-bringup_0.6.0.bin`** (campo) y se
|
||||||
|
anota en el acta de reflasheo.
|
||||||
|
|
||||||
|
### A3. Secuencia de prueba
|
||||||
|
|
||||||
|
1. Cable Ethernet **entre J10 y la laptop**. Aún sin 24 V: los LEDs de J10 deben estar **apagados** (W5500 sin
|
||||||
|
alimentar por USB — correcto).
|
||||||
|
2. Energizar **24 V + ignición** (P11 en ON). En consola, en los primeros ~15 s:
|
||||||
|
|
||||||
|
| Paso | Línea esperada en consola | Qué significa |
|
||||||
|
|---|---|---|
|
||||||
|
| a | `>>> BOARD OK` · `EVT … STACK ON reason=auto` | tarjeta y etapa bien |
|
||||||
|
| b | `EVT ETH W5500 OK en SPI2 (W5500) mac=02:48:42:xx:xx:xx ip_estatica=192.168.7.2 — esperando cable` | **el chip responde** (`$PHEV … ETH_HW,ok`) |
|
||||||
|
| c | LED de **enlace** de J10 encendido; el de **actividad** parpadea | PHY con enlace |
|
||||||
|
| d | `EVT ETH sin DHCP en 4 s -> IP estatica` (cable directo) **o** `ETH enlace ARRIBA ip=<dhcp> (DHCP)` (switch) | dirección obtenida |
|
||||||
|
| e | `EVT ETH enlace ARRIBA ip=192.168.7.2 (estatica) gw=… -> servidor 192.168.7.1:5010` | listo para conectar |
|
||||||
|
| f | `EVT ETH conectado a 192.168.7.1:5010 (n=1): NMEA + $PHLG + $PHEV en espejo` | **socket abierto** |
|
||||||
|
|
||||||
|
3. En la ventana de `nc` debe aparecer **primero** una línea de identidad y luego el flujo:
|
||||||
|
|
||||||
|
```
|
||||||
|
$PHID,<UID 24 hex>,0.6.0-eth,EinarBoard v5 (HBOX v5),02:48:42:xx:xx:xx,<up_s>*CS
|
||||||
|
$PHLG,0.6.0-eth,RUN,…
|
||||||
|
$GNGGA,…
|
||||||
|
$GNRMC,…
|
||||||
|
```
|
||||||
|
|
||||||
|
(`$PHID` se repite cada 5 min. Con la etapa apagada o sin simpleRTK2B llegan solo `$PHLG`/`$PHEV`.)
|
||||||
|
|
||||||
|
4. Teclear **`s`**: `STAT … eth=CONECTADO ip=192.168.7.2 lineas=N bytes=… drop=0 conn=1`. `lineas` debe subir; `drop`
|
||||||
|
debe quedarse en 0.
|
||||||
|
5. **Prueba de cable:** desconectar el RJ45 10 s → `EVT ETH cable desconectado — esperando enlace`; reconectar →
|
||||||
|
vuelve a `enlace ARRIBA` y `conectado (n=2)` en < 10 s.
|
||||||
|
6. **Prueba de servidor:** cerrar `nc` (Ctrl-C) → `EVT ETH servidor desconectado … reintento en 5 s`; volver a
|
||||||
|
lanzar `nc -lk 5010` → reconecta solo.
|
||||||
|
7. **Tecla `E`:** `E` → `ETH OFF (operador)`, LEDs de J10 apagados; `E` otra vez → toda la secuencia b–f de nuevo.
|
||||||
|
8. **Sin 5 V:** quitar los 24 V (con batería puesta) → `EVT ETH OFF (sin_5V): W5500 en reset` y `STAT … eth=off`.
|
||||||
|
Volver los 24 V → reset del MCU (0.5.9+) y la secuencia completa otra vez.
|
||||||
|
9. Guardar el log de consola **y** la captura de `nc` (`nc -lk 5010 | tee H00xx_eth.txt`). Ambos van al acta.
|
||||||
|
|
||||||
|
### A4. Criterios de aceptación — Ethernet
|
||||||
|
|
||||||
|
| Criterio | PASA si |
|
||||||
|
|---|---|
|
||||||
|
| Hardware | `ETH W5500 OK en SPI2` en cada arranque con 5 V (nunca `NO responde`) |
|
||||||
|
| Enlace | LED de enlace de J10 ON con cable; `enlace ARRIBA` en < 10 s tras conectar el cable |
|
||||||
|
| Dirección | DHCP tomado si hay servidor DHCP; si no, cae a 192.168.7.2 en ≤ 5 s |
|
||||||
|
| Espejo | `$PHID` es la primera línea en `nc`; después NMEA + `$PHLG` continuos ≥ 5 min; `drop=0` |
|
||||||
|
| Recuperación | cable fuera/dentro y servidor caído/arriba se recuperan solos en < 10 s |
|
||||||
|
| No interferencia | mientras Ethernet está conectado: `modoB=ON`, `phlg_aire` sigue subiendo, el monitor sigue viendo la unidad por 4G, `v5min ≥ 4.9` |
|
||||||
|
|
||||||
|
### A5. Árbol de fallas — Ethernet
|
||||||
|
|
||||||
|
| Síntoma | Dónde buscar |
|
||||||
|
|---|---|
|
||||||
|
| `EVT ETH W5500 NO responde en SPI2 … — 3V3_ETH? U11? reintento en 10 s` (`$PHEV … ETH_HW,fail`) | Medir **3V3_ETH** (U12 salida / J10 pin 4 TCT) → 3.3 V. Si 0 V: U12 o su enable, `SYS5V` (P11 cerrado?). Si 3.3 V: SPI2 (PB12 CS, PB13 SCK, PB14 MISO, PB15 MOSI) y **RST PA15**: en V5.5 PA15 no tiene pull-down (flota); la tarjeta debe llevar R112 4.7 k en V5.6. Cristal Y1 25 MHz. Soldadura de U11 (QFN 48) |
|
||||||
|
| `W5500 OK` pero **nunca** `enlace ARRIBA`; LED de enlace apagado | cable (probar otro), el adaptador de la laptop está activo?, **J10** (pines doblados, magnéticos: HR911105A trae los transformadores dentro — un J10 golpeado los rompe), pares TX/RX (J10 1-2 / 3-6) |
|
||||||
|
| `enlace ARRIBA` pero nunca `conectado` (`eth=buscando_srv`) | IP de la laptop ≠ 192.168.7.1/24, `nc` no está escuchando, **firewall** de la laptop, dos adaptadores de red con la misma subred |
|
||||||
|
| `conectado` pero `nc` no muestra nada / `drop` sube | `nc` sin `-k` se cerró tras el primer cliente; la laptop no drena (terminal congelada) |
|
||||||
|
| Se reinicia la tarjeta al conectar Ethernet | riel 5 V: `v5min` < 4.6 → SD-15B / fuente; ver regla 2 de seguridad |
|
||||||
|
| Todo bien con cable directo pero no con switch | el switch da DHCP en otra subred y el servidor sigue siendo 192.168.7.1 → cable directo, o build con `-DETH_SERVER_IP=` de esa red |
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## B. Prueba de puertos serie (P15 RS-485, P16 RS-232)
|
||||||
|
|
||||||
|
### B0. Lo que puede probar cada firmware
|
||||||
|
|
||||||
|
| Firmware | Qué prueba | Cómo |
|
||||||
|
|---|---|---|
|
||||||
|
| **0.6.0 / 0.6.0-eth** (hoy) | presencia del SC16IS752 (registro scratchpad) + **niveles estáticos** de los transceptores | B1 + B2 |
|
||||||
|
| **0.6.1** (planeado; *cuando exista*) | lazo interno A↔B y eco externo por cada puerto a **9600 8N1** | B3 + B4 |
|
||||||
|
|
||||||
|
### B1. Presencia (cualquier 0.6.x)
|
||||||
|
|
||||||
|
Con la tarjeta energizada (USB basta), en consola teclear **`r`** y buscar:
|
||||||
|
|
||||||
|
```
|
||||||
|
[PASS] I2C SC16IS752 U10 @0x4D ACK
|
||||||
|
[PASS] SC16IS752 0x4D ACK, SPR rd=0xA5 (exp A5), LSR=0x60
|
||||||
|
```
|
||||||
|
|
||||||
|
`[FAIL] … no ACK at 0x4D` → U10 sin alimentación / soldadura / dirección (A0, A1 a GND). `SPR rd=` distinto de `A5` →
|
||||||
|
U10 dañado o **Y2** no oscila (debe decir `3.6864`).
|
||||||
|
|
||||||
|
### B2. Niveles estáticos (cualquier 0.6.x, multímetro, sin nada conectado a las clemas)
|
||||||
|
|
||||||
|
| Medir (negro a GND = P15.3 / P16.3) | Esperado | Si no |
|
||||||
|
|---|---|---|
|
||||||
|
| **P16.1 (TX RS-232)** | **−5 a −6.5 V** (marca en reposo del MAX3232) | ≈ 0 V: U15 sin 3V3 o bomba de carga muerta (C1±/C2± = C de U15); ≈ +5 V: T1IN en bajo = U10 en reset |
|
||||||
|
| **P16.2 (RX RS-232)** | ≈ 0 V flotando (R1IN tiene pull-down interno) | — |
|
||||||
|
| **P15.1 (A) y P15.2 (B)** respecto a GND | ambas entre 1 y 3 V; sin JP5 pueden flotar cerca de 3.3/0 según el driver | ambas 0 V con 3V3 presente: U14 sin VCC |
|
||||||
|
| **P15.1 – P15.2** (A – B) con JP5 cerrado | 0 V ± 0.2 (driver desactivado, línea terminada) <!-- VERIFICAR: estado por defecto de SER_DEA (DE/~RE de U14) tras reset del SC16IS752; si el driver arranca activo se leerá ≈ +2 V (marca) --> | ≈ 0 con JP5 abierto también es normal |
|
||||||
|
| **JP5** con la tarjeta apagada, ohms entre P15.1 y P15.2 | JP5 abierto: > 10 kΩ · JP5 cerrado: **≈ 120 Ω** (R82) | — |
|
||||||
|
|
||||||
|
### B3. Lazo interno (cuando exista 0.6.1)
|
||||||
|
|
||||||
|
Cablear **P15 ↔ P16 no** — son eléctricamente distintos. El lazo interno de 0.6.1 conecta TX→RX de cada canal
|
||||||
|
**dentro del SC16IS752** (registro MCR bit 4) y no necesita cable: tecla de consola de 0.6.1 <!-- VERIFICAR: tecla y
|
||||||
|
texto de salida del auto-test de lazo en 0.6.1 --> → `[PASS] SER_LOOP_A` / `[PASS] SER_LOOP_B`. Prueba U10 y el cristal,
|
||||||
|
**no** los transceptores ni las clemas.
|
||||||
|
|
||||||
|
### B4. Eco externo con adaptadores (cuando exista 0.6.1) — 9600 8N1
|
||||||
|
|
||||||
|
Con 0.6.1 en modo eco, todo lo que entra por un puerto sale por el mismo puerto.
|
||||||
|
|
||||||
|
**RS-485 (P15):**
|
||||||
|
|
||||||
|
1. Cerrar **JP5** en la tarjeta *solo si* el adaptador también termina (la mayoría trae 120 Ω conmutable): bus de dos
|
||||||
|
nodos = dos extremos = dos terminaciones. Anotar la posición en el acta.
|
||||||
|
2. Adaptador: **A → P15.1**, **B → P15.2**, **GND → P15.3**. Par trenzado, ≤ 3 m en banco.
|
||||||
|
3. Terminal en el puerto del adaptador a **9600 8N1**, eco local apagado. Enviar `HELGEN-485 0123456789\r\n`
|
||||||
|
diez veces (o un archivo de 1 kB).
|
||||||
|
4. Esperado: cada línea regresa **idéntica**. 10/10 sin caracteres perdidos = PASA.
|
||||||
|
5. Si no vuelve nada: **intercambiar A y B** (muchos adaptadores etiquetan D+/D− al revés). Si sigue sin nada: B2.
|
||||||
|
|
||||||
|
**RS-232 (P16):**
|
||||||
|
|
||||||
|
1. Cable de 3 hilos con puntera: **P16.1 TX → DB9 pin 2 (RXD)** · **P16.2 RX → DB9 pin 3 (TXD)** · **P16.3 GND → DB9 pin 5**.
|
||||||
|
(Cruce DTE↔DTE; sin control de flujo.)
|
||||||
|
2. Terminal en el adaptador a **9600 8N1**. Enviar `HELGEN-232 0123456789\r\n` diez veces.
|
||||||
|
3. Esperado: 10/10 líneas de vuelta idénticas. Basura o nada: revisar cruce (probar pines 2↔3 invertidos) y B2.
|
||||||
|
|
||||||
|
### B5. Criterios de aceptación — puertos serie
|
||||||
|
|
||||||
|
| Prueba | PASA si | Con qué firmware |
|
||||||
|
|---|---|---|
|
||||||
|
| Presencia U10 | `[PASS] SC16IS752 … SPR rd=0xA5` | 0.6.0+ |
|
||||||
|
| Niveles RS-232 | P16.1 en −5…−6.5 V en reposo | 0.6.0+ |
|
||||||
|
| Niveles RS-485 | A y B con nivel (no 0/0), 120 Ω entre A-B solo con JP5 cerrado | 0.6.0+ |
|
||||||
|
| Lazo interno A y B | `[PASS] SER_LOOP_A` y `SER_LOOP_B` | 0.6.1 |
|
||||||
|
| Eco RS-485 | 10/10 líneas idénticas a 9600 8N1 | 0.6.1 |
|
||||||
|
| Eco RS-232 | 10/10 líneas idénticas a 9600 8N1 | 0.6.1 |
|
||||||
|
|
||||||
|
!!! note "Sin 0.6.1, el resultado de serie se registra como «presencia + niveles OK»"
|
||||||
|
Es lo máximo que puede probarse hoy y **basta para ordenar la V5.6** (el bloque serie no cambia entre V5.5 y V5.6).
|
||||||
|
El eco con adaptadores se repite cuando salga 0.6.1 y se agrega al mismo acta.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## C. Cierre
|
||||||
|
|
||||||
|
- [ ] Re-flashear **`hbox-v5-bringup_0.6.0.bin`** (campo) si la unidad se va a embarcar; anotar en el acta de reflasheo.
|
||||||
|
- [ ] Quitar cable Ethernet y adaptadores; tapas ciegas en J10/P15/P16 si el panel no los usa.
|
||||||
|
- [ ] Acta [Ethernet y puertos serie](../formularios/ethernet-serie.html) enviada con los dos logs.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Anexo A — Notas de ingeniería
|
||||||
|
|
||||||
|
- Ethernet en firmware: `ethService()` — `RST` alto → 150 ms → `Ethernet.begin` estático (prueba el chip y lee el
|
||||||
|
PHY) → con cable, DHCP con 4 s de presupuesto (K1 liberado mientras, `relayDisengage("eth_dhcp")`) o estática →
|
||||||
|
`connect()` con timeout 300 ms, reintento 5 s. Escrituras no bloqueantes (`availableForWrite`), descartes en `drop=`.
|
||||||
|
MAC `02:48:42:` + hash del UID. Eventos en banda: `ETH_HW`, `ETH_UP`, `ETH_LINK`, `ETH_CONN`, `ETH_DISC`, `ETH_OFF`.
|
||||||
|
- V5.5 vs V5.6 en este bloque: V5.6 añade **R112 4.7 k pull-down en `ETH_RST` (PA15)** y C90 4.7 µF / C91 10 nF según
|
||||||
|
datasheet. Si una V5.5 arranca con `W5500 NO responde` de forma intermitente, sospechar PA15 flotando antes de que el
|
||||||
|
firmware tome el pin.
|
||||||
|
- SC16IS752: dirección 0x4D (A1 = A0 = GND, modo I²C), IRQ en PB8 (R81 10 k), cristal Y2 3.6864 MHz (`XTAL_FREQ 3686400`
|
||||||
|
→ 9600 = divisor 24). Canal A → U14 SP3485 (DE y ~RE unidos en `SER_DEA`), canal B → U15 MAX3232 (canal 2 sin usar:
|
||||||
|
T2IN a GND, R2IN a GND).
|
||||||
|
- Netlist V5.6 (`p5ntc-after.xml`): P15.1 `RS485_A`, P15.2 `RS485_B`, P15.3 GND; JP5.1 `RS485_T` (R82 120 Ω → A),
|
||||||
|
JP5.2 `RS485_B`; P16.1 `RS232_TX` (T1OUT), P16.2 `RS232_RX` (R1IN), P16.3 GND; J10 1/2 TX±, 3/6 RX±, 4 TCT (3V3_ETH),
|
||||||
|
5 RCT, 7/8 NC, 9–12 LEDs de enlace/actividad.
|
||||||
|
|
||||||
|
## Historial de revisiones
|
||||||
|
|
||||||
|
| Versión | Fecha | Autor | Cambios |
|
||||||
|
|---|---|---|---|
|
||||||
|
| 1.0 | 2026-09-29 | Helgen Technologies | Primera versión: prueba de Ethernet con `0.6.0-eth` (espejo TCP, DHCP/estática, recuperación, árbol de fallas) y de puertos serie (presencia, niveles, lazo y eco 9600 8N1 para 0.6.1). |
|
||||||
Loading…
Reference in New Issue
Block a user