v4 = the live 1.1/Phase-A design (J1 renumbered, blocks M/N/O, HV24, PFI 4.40V). v3-PROD trio = exact as-fabbed state from 9892279 (mirrored J1 as the bench/fleet boards physically are) - do not edit. dru/prl carried to v4. Off-grid warning backlog stays visible-but-muted; real geometry sweep slated for Phase D.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Root cause of 23 ERC errors: vertically-stacked 2-pin parts closer than 15.24mm shared stub columns -> KiCad merged collinear overlapping stubs -> orphaned pins + fused nets (C85-C89 chain shorted C1N/C2P/VP/VN/GND/3V3; RGB chain fused). Regenerated from pre-Phase-A base with grid-snapped origins, one x-column per part, geometry auditor (collinear overlap + T-touch + label-anchor collision checks) now part of the generator. P13 depop made surgical (R61 FB wire preserved). PF10/PF11 added. rjmap LED/TCT nets direct (no alias bridges). Netclass patterns re-applied onto KiCad-canonical pro; note: pro file is vulnerable to open-KiCad resave clobber.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Keystone: gauge moves to PCF8574 on I2C1 -> frees SPI2 for W5500; SC16IS752 dual-UART bridge on I2C gives RS-485 (Modbus RTU) + RS-232/TTL with zero MCU pins. New 3V3_ETH rail from SYS5V (survives stack power-cycles). Carry-over errata state + depop list + phases A-E.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
J1 pads renumbered end-for-end (positions/uuids kept, nets follow numbers, lib id renamed Drogheda:..._RevNum_EJ1 so library-update cannot revert); verified pad-by-pad against the module landing map. R51 287k->270k on board+schematic (PFI trip 4.60->4.40V falling, per 24-Jul bench data). HV24 class (0.5mm clearance) assigned to /24V_IN, 24V, IGN_IN, Q10_GATE after the 23-Jul inner-layer bridge incident. 177 segments/vias ripped on the 11 J1 signal nets + 5 power stubs: reroute pending in the inter-socket channel. NOTE: pre-existing PWR_HI/PWR_MID netclass patterns lack the '/' prefix and likely never matched.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
