Helgen-Services/Drogheda
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Author SHA1 Message Date
Leopoldo Rodríguez
548b69f177 1.1 Phase C1: W5500 datasheet verification — 2 bugs fixed, Ethernet unblocked 
Checked against WIZnet W5500 datasheet v1.1.0 (official pin table):
- CONFIRMED correct: pin 23 RSVD->GND, pin 18 VBG floating, EXRES1 12.4k/1%,
  PMODE[2:0]=111 autoneg via pins 43-45, LINKLED/ACTLED pins 25/27 active-low
  sink topology, TXN/TXP/RXN/RXP order (1/2/5/6), SPI on 32-37
- BUG FIXED: RSVD pins 38-42 were floating; datasheet requires GND. Added
  5 GND stubs on U11 in the schematic + (net GND) on board pads 38-42
- BUG FIXED: TOCAP/1V2O caps were 10uF/4.7uF; datasheet requires 4.7uF/10nF.
  C90 -> 4.7uF, C91 -> 10nF (sch + board values; footprints unchanged)
- R83 board value harmonized to sch's 12.4k/1%
Magjack HR911105A: wiring matches the standard table (TX 1/2, RX 3/6,
TCT pin4->3V3_ETH, RCT pin5->6.8nF, internal Bob Smith). Bench-check with
DMM before flash: pins 4/5 CT assignment + LED anode/cathode on 9-12.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
 2026-07-29 18:12:51 +00:00
Leopoldo Rodríguez
0af0373def 1.1 Phase B: board grown to 155x100 (20mm left), placement for blocks M/N/O 
- Outline left edge 80.19->60.19; MH5/MH6 mounting holes cloned to new corners
- Antenna corridor keepout front-left (notched around MH6) + magjack no-pour/no-via zone
- RJ45 J10 + RS-485 P15 + RS-232 P16 on new left edge behind antenna corridor
- W5500 U11 + 25MHz + terminations between jack and P5; 3V3_ETH buck U12/L8/D11
  in the freed P13/H3 gap under the module (low-profile), bulk caps at load
- SC16IS752 U10 serial cluster behind P15/P16; MAX3232 U15, SP3485 U14
- PCF8574 U13 clear of MOD1 pad ring; RGB JST P14 on right edge (freed P3 slot)
- H4 TTL header moved to front edge (was under module, on D5)
- 24V entry block relocated beside P1 (Q10/C10 in P12 lane, D10/DzG1/Rrp1 pocket);
  old cross-board 24V routing ripped for HV24 re-route
- P3/P13/H3 depopulated; J1/J2/DB pad nets updated (ETH SPI, SER_IRQ, LED flip)
- Fix Phase A miss: SC16IS752 pins 13/14 (I2C SCL/SDA) now wired in sch + board
- Placement verified: 190 footprints, 0 courtyard conflicts, 0 corridor intrusions,
  all new nets 2-ended (verify_phase_b.py)

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
 2026-07-29 04:39:35 +00:00
Leopoldo Rodríguez
ca96c94ad6 HBOX v4: project renamed hbox-watchdog-v4 (199 sch + 113 pcb refs); v3-PROD files restored to as-fabricated as the frozen EinarBoard 1.0 record; ERC endpoint_off_grid muted on v4 
v4 = the live 1.1/Phase-A design (J1 renumbered, blocks M/N/O, HV24, PFI 4.40V). v3-PROD trio = exact as-fabbed state from 9892279 (mirrored J1 as the bench/fleet boards physically are) - do not edit. dru/prl carried to v4. Off-grid warning backlog stays visible-but-muted; real geometry sweep slated for Phase D.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
 2026-07-29 03:34:46 +00:00