The .kicad_dru held one unconditional (min 0.15mm). A custom rule outranks
the netclass table and an unconditional rule matches every pair on the board,
so it was silently overriding the HV24 netclass's 0.5 mm everywhere: the
netclass said 0.5, DRC only ever enforced 0.15.
Rule file, three mutually-exclusive rules so order and specificity agree:
1. neither item HV24 -> 0.15 mm (unchanged)
2. either item HV24 -> 0.50 mm
3. except U2 pad-to-pad (its own land pattern)-> 0.15 mm
Rule 3 covers exactly one pair: U2 (MP1584EN, SOIC-8-EP) pad 7 (24V) to pad 9
(exposed thermal pad, GND) at 0.355 mm. That is the manufacturer's qualified
land pattern, set by the package and not by routing. U2's courtyard contains
9 pads and all 9 belong to U2, so the condition cannot match foreign copper;
the 24 foreign tracks/vias crossing that courtyard are excluded by the
A.Type == 'Pad' test and stay at the full 0.5 mm.
Copper: 13 of the 14 HV24-to-foreign gaps under 0.5 mm were routing, and all
13 are fixed. No component was moved or rotated.
3 width reductions (a narrower track can never reduce a clearance):
479e5357 24V -> U2.7 1.0 -> 0.6 U2's pads are 0.6 tall, so the
pad was already the bottleneck
854214dc FREQ_FAN -> U2.6 1.0 -> 0.6 1.14 mm long, R~0.93 mohm,
~8 mV at 3 A; IPC-2221 gives
~1.9 A at 10 C rise for 0.6 mm
30ed4012 24V -> DzG1.3 1.5 -> 0.8 leaf branch into a BZX84C15
SOT-23 clamp, sub-mA
5 track-vertex moves (never a via centre, never a pad centre):
/3V3_MODEM x3 corridor walks 0.55 mm east off the 24V bus
/USB_CC2 x2 opposite ends of one 6.05 mm segment pivot apart, opening
pad Rrp1.1 and the GND via at the same time
Verification (shapely geometry over every pad/via/track, diffed against the
unedited baseline so nothing pre-existing is miscounted as new):
HV24 inter-item pairs under 0.5 mm 13 -> 0
cross-footprint pairs under 0.15 mm 0 (unchanged)
pairs this edit created 0 at 0.15, 0 at 0.30, 0 at 0.50
per-net connectivity 180/180 nets whole, 0 orphan copper clusters
static DRC 0 violations, byte-identical to the C13 run
fab sweep 0 findings (edge clearance, drills, annular rings, outline)
thinnest new margin 0.5650 mm (pad Rrp1.1 <-> trk 1fed5fbb), looser than
five pre-existing HV24 pairs on this board
/24V_IN and IGN_IN copper byte-identical; 24V differs only in two width tokens
Pour reflow: the 0.5 mm rule widens the zone pullback around HV24 from 0.3 to
0.5 mm. Simulated the refill on all four pours at both values — the anchor
partition is identical (F.Cu 547 anchors / 35 groups, B.Cu 222/2, In1 33/5,
In2 220/7), so pressing B strands nothing. Area loss 115 mm2 on F.Cu, 4.6 mm2
on each of the other three.
Press B to refill zones before running DRC.
v4 = the live 1.1/Phase-A design (J1 renumbered, blocks M/N/O, HV24, PFI 4.40V). v3-PROD trio = exact as-fabbed state from 9892279 (mirrored J1 as the bench/fleet boards physically are) - do not edit. dru/prl carried to v4. Off-grid warning backlog stays visible-but-muted; real geometry sweep slated for Phase D.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
