0b1d542e3b
1.1 Phase A: schematic blocks M/N/O (SC16IS752+RS485+RS232, W5500+MagJack+3V3_ETH buck, PCF8574+RGB), gauge->expander frees SPI2, depop P3/P13/H3
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59 new parts from official KiCad libs (pinouts verified, extends-flattened). Gauge LEDs flipped common-anode (PCF8574 sinks). PB12-15 -> W5500 SPI2; PA15/PB2/PB8 unlocked (ETH_RST/ETH_INT/SER_IRQ). SC16IS752 strapped 0x4D (0x48 collides with TMP102). 220uF VEH5V bulk cap (C78). Netclass patterns slash-fixed; HV24 exclusively owns 24V/ignition nets. RevNum_EJ1 footprint saved to Drogheda.pretty + fp-lib-table. Paper A1. VERIFY flags in Notes: W5500 RSVD/VBG/TOCAP, magjack termination + LED pin order. ERC in KiCad UI pending (Leo).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
2026-07-29 02:17:05 +00:00
19c15e2864
EinarBoard respin WIP: E-J1 pad renumber, PFI 4.40V (R51 270k), HV24 24V clearance class, J1 nets ripped for reroute
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J1 pads renumbered end-for-end (positions/uuids kept, nets follow numbers, lib id renamed Drogheda:..._RevNum_EJ1 so library-update cannot revert); verified pad-by-pad against the module landing map. R51 287k->270k on board+schematic (PFI trip 4.60->4.40V falling, per 24-Jul bench data). HV24 class (0.5mm clearance) assigned to /24V_IN, 24V, IGN_IN, Q10_GATE after the 23-Jul inner-layer bridge incident. 177 segments/vias ripped on the 11 J1 signal nets + 5 power stubs: reroute pending in the inter-socket channel. NOTE: pre-existing PWR_HI/PWR_MID netclass patterns lack the '/' prefix and likely never matched.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
2026-07-25 04:04:12 +00:00
2c3dffa232
2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger
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Electrical/PCB:
- LTC4040 Block B sized to the 12 Ah 1S4P pack (RPROG 825R -> 2.42 A ~ C/5,
RS 8 mR -> 3.1 A input limit, PFI 4.60 V, backup 4.79 V, charge 4.00 V Li-ion
via VSYS-referenced straps) + Block E cutoff (P11) + Block F PA4->VEH5V re-tap
+ Block H fail-safe Modo-B bypass (K1 normally-closed relay) + Block I NTC->PB1.
- CARRIER-BOARD conversion: simpleRTK2B Pro on UNO-pattern female headers (MOD1;
D0/D1=UART1, D2=RX2, D8=TX2, IOREF=3V3, 5V=SW_5V) + 4G NTRIP Master on on-board
XBee socket (J7/J8; VCC=3V3_MODEM via new Block K MP1584 buck off SW_5V - the
HP XBee socket is 3.3 V not 5 V). Board 120x100, placement + GND pour + DRC
baselines. Custom symbols: LTC4040EUFD, AO4406A, SimpleRTK2B_Pro_Socket.
- Fixed duplicated U2, stale no-connects, A4->A3 sheet; ERC 0 errors.
Docs:
- Canonical electrical-design-state + production delta (Block B values table,
5b/5c/5d/5e) + design/rationale/connections/BOM swept to the Jul-2 assumptions
ledger (Conexiones-por-Bloque xlsx).
- Guia de Conexion Protoboard: LaTeX source now maintained in-repo -> v2.1 PDF.
- CircuiTikZ sheet + wiring Beamer: block 11 (NTC->PB1) + guinda ignition legend.
- Client decks: Avance v1.1 (overclaims fixed) + RCA v1.1 (2-jul addendum).
Repo hygiene:
- .gitignore: live rtk-config (SIM/APN/NTRIP creds) now ignored and REMOVED from
tracking (NOTE: rotate those credentials - they exist in prior commits);
KiCad .bak/snapshots/.history, LaTeX intermediates, Office locks ignored+purged.
- Removed rogue .history gitlinks that broke git status.
2026-07-02 22:18:56 -06:00
