- J1/J2 rotated to vertical rows: J2 (outer) x63.77, J1 (inner) x78.77,
y52.8-101.1 — module hugs the front edge full-length, USB end (J1 pad20
/SYS5V) at the top-front corner; antenna exits directly at the front
- Front edge cleared: P15 (RS-485) -> top edge between MH5/MH1, P16 (RS-232)
-> bottom edge west of the modem pad row, H4 TTL -> top strip next to P5
- RJ45 kept at the bottom-left of the front edge (no other edge window fits
a 19x22.3mm magjack) with the no-pour zone moved under it
- Serial cluster re-laid east of the module; W5500 satellites auto-placed
by greedy collision-free placer; 0 pairwise courtyard conflicts (190 fp)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- J1/J2 socket pair translated -43.43mm: rows now x62.0-113.8, USB end
(J1 pad20 /SYS5V) at the left board edge; 49 stale J1/J2 pad stubs ripped
- Ethernet corner rebuilt lower-left: RJ45 J10 on left edge y106-125 inside
relocated MAGJACK_NO_POUR zone, W5500+25MHz+terminations below the serial
stack, clear of the existing R5/R6/R7/D1/C5/C7 LED cluster
- ANT_CORRIDOR_KEEPOUT retired (antenna now exits at the module end itself)
- Rig1 nudged below Rigb1 (was inside J2's new courtyard band), stub ripped
- 3D models: 58 legacy KICAD6/KICAD7 3DMODEL_DIR refs repointed at
KICAD10_3DMODEL_DIR so new parts render in the 3D viewer
- Verified: 190 footprints, 0 pairwise courtyard conflicts, parens balanced
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- Outline left edge 80.19->60.19; MH5/MH6 mounting holes cloned to new corners
- Antenna corridor keepout front-left (notched around MH6) + magjack no-pour/no-via zone
- RJ45 J10 + RS-485 P15 + RS-232 P16 on new left edge behind antenna corridor
- W5500 U11 + 25MHz + terminations between jack and P5; 3V3_ETH buck U12/L8/D11
in the freed P13/H3 gap under the module (low-profile), bulk caps at load
- SC16IS752 U10 serial cluster behind P15/P16; MAX3232 U15, SP3485 U14
- PCF8574 U13 clear of MOD1 pad ring; RGB JST P14 on right edge (freed P3 slot)
- H4 TTL header moved to front edge (was under module, on D5)
- 24V entry block relocated beside P1 (Q10/C10 in P12 lane, D10/DzG1/Rrp1 pocket);
old cross-board 24V routing ripped for HV24 re-route
- P3/P13/H3 depopulated; J1/J2/DB pad nets updated (ETH SPI, SER_IRQ, LED flip)
- Fix Phase A miss: SC16IS752 pins 13/14 (I2C SCL/SDA) now wired in sch + board
- Placement verified: 190 footprints, 0 courtyard conflicts, 0 corridor intrusions,
all new nets 2-ended (verify_phase_b.py)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
v4 = the live 1.1/Phase-A design (J1 renumbered, blocks M/N/O, HV24, PFI 4.40V). v3-PROD trio = exact as-fabbed state from 9892279 (mirrored J1 as the bench/fleet boards physically are) - do not edit. dru/prl carried to v4. Off-grid warning backlog stays visible-but-muted; real geometry sweep slated for Phase D.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Root cause of 23 ERC errors: vertically-stacked 2-pin parts closer than 15.24mm shared stub columns -> KiCad merged collinear overlapping stubs -> orphaned pins + fused nets (C85-C89 chain shorted C1N/C2P/VP/VN/GND/3V3; RGB chain fused). Regenerated from pre-Phase-A base with grid-snapped origins, one x-column per part, geometry auditor (collinear overlap + T-touch + label-anchor collision checks) now part of the generator. P13 depop made surgical (R61 FB wire preserved). PF10/PF11 added. rjmap LED/TCT nets direct (no alias bridges). Netclass patterns re-applied onto KiCad-canonical pro; note: pro file is vulnerable to open-KiCad resave clobber.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Keystone: gauge moves to PCF8574 on I2C1 -> frees SPI2 for W5500; SC16IS752 dual-UART bridge on I2C gives RS-485 (Modbus RTU) + RS-232/TTL with zero MCU pins. New 3V3_ETH rail from SYS5V (survives stack power-cycles). Carry-over errata state + depop list + phases A-E.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
J1 pads renumbered end-for-end (positions/uuids kept, nets follow numbers, lib id renamed Drogheda:..._RevNum_EJ1 so library-update cannot revert); verified pad-by-pad against the module landing map. R51 287k->270k on board+schematic (PFI trip 4.60->4.40V falling, per 24-Jul bench data). HV24 class (0.5mm clearance) assigned to /24V_IN, 24V, IGN_IN, Q10_GATE after the 23-Jul inner-layer bridge incident. 177 segments/vias ripped on the 11 J1 signal nets + 5 power stubs: reroute pending in the inter-socket channel. NOTE: pre-existing PWR_HI/PWR_MID netclass patterns lack the '/' prefix and likely never matched.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
