v6: auditoría completa, plan de corrección, resumen de cambios, revisión final y próximos pasos para ordenar (28-29 sep)

03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Cambios-Resumen_v1.0.md

@@ -0,0 +1,332 @@
+---
+title: "EinarBoard v6 — Cambios de esquemático: resumen de las 3 pasadas"
+tags: [project-drogheda, hardware, hbox, v6, esquematico, cambios, verificacion]
+project: Project Drogheda
+author: Helgen Technologies
+date: 2026-09-28
+version: 1.0
+status: FINAL — esquemático terminado y verificado; falta el layout (Michelle)
+audience: Michelle (layout), Leo, ingenieros
+---
+
+# EinarBoard v6 — Cambios de esquemático: resumen de las 3 pasadas
+
+!!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide"
+    Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios.
+
+**Tarjeta:** `hbox-watchdog-v6` (repo **HBox_PCB**) · **Fecha:** 28-sep-2026 ·
+[Plan de corrección y estado](v6-plan-correccion.md) · [Auditoría completa (español)](v6-auditoria-completa.md) ·
+[original en inglés](v6-full-audit.md)
+
+!!! success "Esquemático terminado y verificado de forma independiente"
+    - **Esquemático final:** `d58a89ba5a5ac46419edf9d68672a8208d825a16387298d0167e21399cd41e7b`
+    - **ERC: 0 errores.** Hay 135 avisos cosméticos, todos explicados (antes eran 166).
+    - **299 piezas montadas**, todas con número LCSC. TP1–TP12 y JP1–JP6 no van en el BOM ni en el CPL.
+    - **El PCB no se tocó** (`6ddec80d…36bf`). Michelle hace *Actualizar PCB desde esquemático*: es el paso 0 de su
+      [lista de trabajo](v6-plan-correccion.md#5-lista-de-trabajo-de-michelle-layout).
+
+## 1. Resumen: tres pasadas
+
+Todo se editó **en el mismo archivo** (`hbox-watchdog-v6.*`), con copia de respaldo antes de cada paso. El método fue el
+mismo en las tres pasadas:
+
+- Antes de guardar se escribe la lista de cambios esperados.
+- Se edita con cortes acotados al nodo del archivo, con una guarda que impide que cambie o desaparezca un UUID existente.
+- Se exporta el netlist y se compara contra lo esperado. **En todos los grupos lo esperado coincidió exactamente con lo obtenido.**
+
+| Pasada | Qué hizo | Resultado | Verificación | Esquemático (sha256) |
+|---|---|---|---|---|
+| **1 · Correcciones de la auditoría** | Todos los Blockers y Majors que tocan esquemático o proyecto, los Minors de la lista D19, las netclasses y reglas DRC (F-01) y la librería (H-04). 37 piezas nuevas, 3 quitadas (D20, D21 y el flag PF15), 17 puestas en DNP | Netlist: 37 agregadas / 3 quitadas / 125 cambios de campo / 22 cambios pin-red / 16 cambios de clase, todo esperado. ERC 0 errores (166 → 134 avisos) | Verificación independiente con scripts propios: **126 ítems, 173 PASS / 0 FAIL**, 15 notas | `ecee9fed…` → `d54e330d…` |
+| **2 · Puertos y sin nueva versión** | Revisó 24 puertos de punta a punta contra hojas de datos y corrigió 7 (RS-485, RS-232, H4, CTS del SC16IS752, LEDs y Bob-Smith de J10, pad de descarga del módem, UART del módem). **H-03** hecho (huella MWSA0804S) y **B-13** hecho (K1 fuera, R148) | Netlist: 8 agregadas / 0 quitadas / 41 campos / 8 pin-red / 0 clases, todo esperado. ERC 0 errores (134) | Revisada por la pasada 3: **26 PASS / 1 FAIL** (la huella de los inductores) | `d54e330d…` → `f73f41a8…` |
+| **3 · Revisión final independiente** | Revisó la pasada 2 con su propio diff y las hojas de datos de los fabricantes. **Corrigió la huella MWSA0804S** (se habían intercambiado dos cotas de Sunlord), **agregó C176** en U28 (N2) y **confirmó los pads de Y3** con la hoja de SCTF (N1, sin cambio) | Netlist: C176 agregado, nada más. ERC 0 errores (134). Conectividad derivada del esquemático = netlist de KiCad (353 redes, 0 diferencias) | — | `f73f41a8…` → **`2b394ef9…`** |
+| **4 · Paquete LFP-HT (igual que V5.6)** | JP2 → `Drogheda:SolderJumper-3_P1.3mm_Bridged23_RoundedPad1.0x1.5mm` (F2 a GND) y R55 10 k → **5.6 k (C23189)**; JP3/JP4 ya coincidían con V5.6 (F1 = 0, F0 = 1). Layout: L-67. | Flotación **3.50 V** LFP (antes 4.00 V Li-ion); ventana de carga ≈ +8…+60 °C con NTC B3380. | Netlist: 0 cambios de pin o de red; lo esperado = lo obtenido. ERC 0 errores (135 avisos). | `d58a89ba…e7b` |
+
+**Total contra la auditoría:** **46 piezas nuevas**, 3 quitadas, 22 puestas en DNP (17 por A-01, 5 por B-13; además
+R145/R146 entran nuevas como DNP). La polaridad del USB_BOOT del módem quedó como aviso: los documentos de SIMCom se
+contradicen, así que hay un procedimiento alterno en banco (TP8–GND).
+
+??? note "Hashes y archivos"
+    | Archivo | Estado final (sha256) |
+    |---|---|
+    | `hbox-watchdog-v6.kicad_sch` | `d58a89ba5a5ac46419edf9d68672a8208d825a16387298d0167e21399cd41e7b` |
+    | `hbox-watchdog-v6.kicad_pro` | `d577aa43076f5f751c291041dbf3054cb93a87facfe9f339ef91b60e073bd6ce` (pasada 1; netclasses) |
+    | `hbox-watchdog-v6.kicad_dru` | `31ce0f4f23e8178b4b5e837b452e7bb8647d446ffd420559049eaaae78100831` (pasada 1) |
+    | `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` | `3f38f26e435c477a7701636d4d5e1c05b4c7bd523e8dd04f9f57128657736313` (H-04) |
+    | `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod` (nueva) | `74528135d4f69617df8570da58700bac3920827a78ec9104c3440be2c5975638` (land corregido) |
+    | `hbox-watchdog-v6.kicad_pcb` | `6ddec80d1c15f79e69dff6c1a850b28345a5d826389f79cee8c61998240b36bf` (**sin tocar**) |
+    | PDF `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf` | `3e073181…4362` |
+
+    Respaldos en la Mac: `kicad/_to_delete/v6-apply-20260928/`, `kicad/_to_delete/v6-ports-20260928/` y
+    `kicad/_to_delete/v6-final-20260928/` (nada se borró).
+
+    **Git (lo corre Leo; desde aquí no se hizo commit):** dentro del submódulo `kicad`, commit de
+    `hbox-watchdog-v6.kicad_sch`, `.kicad_pro`, `.kicad_dru`, `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod`
+    y `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod`; push a Gitea `HBox_PCB`; luego actualizar el gitlink del proyecto
+    padre. Si KiCad está abierto en v6, cerrarlo **sin guardar** antes del *Update PCB*.
+
+---
+
+## 2. Estado final de cada cambio, por bloque
+
+Todo lo de estas tablas está verificado: la pasada 1 por la verificación independiente (126 ítems) y las pasadas 2 y 3
+por la revisión final. **Pasada:** 1 = correcciones de la auditoría · 2 = puertos / sin nueva versión · 3 = revisión final.
+
+### Entrada de 24 V, ignición y ventilador
+
+| Hallazgo | Ref | Estado final | LCSC | Pasada |
+|---|---|---|---|---|
+| A-01 / V1-01 | F2 | Fusible Nano2 de 3 A (0154003.DR), mismo porta-fusible; P1.1 → F2 → `/VIN_FUSED` | C206912 | 1 |
+| V1-01 | D10 | SMBJ33A en `/VIN_FUSED` (salida de F2); con P1 al revés funde F2 | C224019 | 1 |
+| A-01 | D20, D21 | Eliminados; `/VIN_MODEM` unido a `/MAIN5V` | — | 1 |
+| A-01 | Q10, DzG1, Rrp1, C10, C11, C22 | DNP: la rama `/24V` queda sin cargas | — | 1 |
+| A-01 | U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21 | DNP: bloque del ventilador | — | 1 |
+| A-01 | JP1 | Puente de soldadura **puenteado** → `/5V_FAN` = `/VEH5V` | — | 1 |
+| F-02 | **D35** (nuevo) | SMBJ33A de `/IGN_IN` a GND, para ir en P1.3 | C224019 | 1 |
+| F-02 | Rig1 | 22 k sin cambio; se mueve a P1.3 en el layout. `/IGN_IN` = {P1.3, Rig1.1, D35.1} | C88614 | 1 |
+| D-05 | Rigb1 | 2.2 k → relación 0.0833 para leer la ignición por ADC | C4190 | 1 |
+
+### Cargador LTC4040, 5 V, 3V3 e inductores
+
+| Hallazgo | Ref | Estado final | LCSC | Pasada |
+|---|---|---|---|---|
+| A-03 | R50 | 1.43 k 1 % → 1.316–1.483 A de carga | C22840 | 1 |
+| A-04 | R121 | 57.6 k 1 % → U25 en 5.18 / 5.32 / 5.46 V | C23082 | 1 |
+| A-05 | **C161, C162** (nuevos) | 47 µF X7R 1210 en `/MAIN5V` (VSYS de U6) | C5440143 | 1 |
+| A-09 | C78 | 220 µF 16 V polímero | C881921 | 1 |
+| H-02 | R53 | 499 k 1 % (HKR RCT03499KFLF) | C177479 | 1 |
+| H-02b | R56, R57, R58, R85, R87, Rgs1 | 100 k 1 % | C25803 | 1 |
+| A-11 | R56 | Pull-up a `/3V3` → cargador **apagado** sin MCU | C25803 | 1 |
+| A-13 | **R141** (nuevo), red `/PFO` | PFO del LTC4040 → PB10, con 100 k a `/3V3` | C25803 | 1 |
+| F-51 | **U29 + C168** (nuevos) | TMP102 del cargador en **0x48** + 100 nF | C99269, C14663 | 1 |
+| F-51 | **R137, R138, C169** (nuevos) | Toma del NTC: `/NTC` → 100 k → `/NTC_CELL` (PC5) → 120 k + 10 nF a GND | C25803, C25808, C1589 | 1 |
+| A-08 | U17 | TLV1117LV33DCYR, misma huella | C15578 | 1 |
+| H-03 | L2 (DNP), L6, L8, L20 | Huella `Drogheda-v6:IND-SMD_MWSA0804S` (tierra de Sunlord); piezas sin cambio | — | 2 y 3 |
+
+### Módem A7670SA
+
+| Hallazgo | Ref | Estado final | LCSC | Pasada |
+|---|---|---|---|---|
+| A-01 | U20.2, C127, C128 | En `/MAIN5V` | — | 1 |
+| F-03 | **C163, C164, C165** (nuevos) | 2 × 22 µF 0805 + 220 µF polímero en U20.2 | C86817, C881921 | 1 |
+| B-02 | C130, C131 | 220 µF 16 V polímero | C881921 | 1 |
+| B-02 | R116 / C141 / C142 | 113 k / 6.8 nF / 56 pF (compensación para 3.8 V) | C22862, C1542, C1572 | 1 |
+| B-02 | **C166, C167** (nuevos) | 22 µF 0805 en `/VBAT_MODEM` | C86817 | 1 |
+| B-03 | D28 | PESD0402-240 bidireccional, huella 0402 | C1975527 | 1 |
+| B-09 | R132, R133, R134 | 22 Ω | C23345 | 1 |
+| B-09 | **C171** (nuevo) | 100 nF 0402 en J14.C1 (`/SIMB_VDD`) | C1525 | 1 |
+| B-10 | **R142, R143** (nuevos) | 100 k: `/MODEM_STATUS` a GND y `/DIN_4G` a `/3V3` | C25803 | 1 |
+| B-10 | R106 | 1 k | C14676 | 1 |
+| B-15 | R107, R108 | DNP, valor «0R-NEVER-FIT» y nota | — | 1 |
+| F-52 | **U31 + C174** (nuevos) | TMP102 del módem en **0x49** + 100 nF | C99269, C14663 | 1 |
+| G-02 | **U30** (nuevo) | USBLC6-2SC6 en J9 | C7519 | 1 |
+| B-13 | K1, Q6, D6, R40, R41 | DNP: el relé sale del circuito | — | 2 |
+| B-13 | **R148** (nuevo) | 0 Ω de `/USART6_TX` (PC6) a `/DIN_4G`; nunca junto con K1 | C21189 | 2 |
+| P-5 | **TP12** (nuevo) | Pad en `/1V8_MODEM` junto a TP8 (descarga forzada del módem) | — | 2 |
+
+### GNSS ZED-F9P
+
+| Hallazgo | Ref | Estado final | LCSC | Pasada |
+|---|---|---|---|---|
+| C-01 | **U28, R135, R136** (nuevos) | TPS2552 (75 mA) con EN̅ = ANT_OFF + 100 k a GND y FAULT̅ → `/GNSS_ANT_SHORT_N` + 10 k a `/3V3_GNSS`; salida `/ANT_BIAS`; U18.7 sin conectar | C46506, C25803, C25804 | 1 |
+| N2 | **C176** (nuevo) | 100 nF en U28 pin 1 (IN) | C14663 | 3 |
+| C-02 | U21 | TPS7A2033PDBVR (arranque suave), misma huella | C2862740 | 1 |
+| D-01 | **U27 + C170** (nuevos) | 74LVC1G125 de `/DOUT_4G` a U18.26 (`/DOUT_4G_F9P`), VCC = `/3V3_GNSS` | C12518, C14663 | 1 |
+| D-01 | Rdfu1 | 100 k | C25803 | 1 |
+| C-07 | **TP10, TP11** (nuevos) | Pads en SAFEBOOT_N (U18.50) y RESET_N (U18.49) | — | 1 |
+| D-09 | **R144** (nuevo) | 100 k de la base de Q5 a GND | C25803 | 1 |
+
+### MCU y cristales
+
+| Hallazgo | Ref | Estado final | LCSC | Pasada |
+|---|---|---|---|---|
+| D-02 | Y3 | 25 MHz 3225-4P CL 10 pF; símbolo `Crystal_GND24` (pad 1 HSE_IN, pad 3 HSE_OUT, pads 2/4 GND), confirmado con la hoja de SCTF (N1) | C2901684 | 1 y 3 |
+| D-02 | C113, C114 | 12 pF C0G | C38523 | 1 |
+| D-03 | Y4 | FC-135 CL 7 pF, misma huella | C48615 | 1 |
+| D-03 | C115, C116 | 6.8 pF C0G | C1679 | 1 |
+| D-12 | **TP9** (nuevo) | Pad en PA9 (`/USART1_TX`) | — | 1 |
+
+### Ethernet
+
+| Hallazgo | Ref | Estado final | LCSC | Pasada |
+|---|---|---|---|---|
+| E-01 | **R139** (nuevo), red `/ETH_PWR_EN` | EN de U12 → PD2, con 100 k a GND | C25803 | 1 |
+| E-02 | **R140** (nuevo) | 4.7 k de `/ETH_RST` a GND | C23162 | 1 |
+| E-03 | C95, C96 | 33 pF C0G (Y1 se queda) | C1663 | 1 |
+| E-04 | C91 / C90 | 10 nF 0603 / 4.7 µF 0805 | C1589, C1779 | 1 |
+| E-04 | **C172, C173** (nuevos) | 100 nF en AVDD del W5500 | C14663 | 1 |
+| G-03 | J10 | Montado; huella `Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal` | C12074 | 1 |
+| P-3 | J10.11 / J10.12 | LED amarillo corregido: 12 = ánodo (`/ETH_ACT_A`), 11 = cátodo (`/ETH_ACTLED`) | — | 2 |
+| P-3 | J10.8 | A GND (retorno Bob-Smith; plano de Hanrun) | — | 2 |
+
+### Puertos serie (SC16IS752, RS-485, RS-232, H4)
+
+| Hallazgo | Ref | Estado final | LCSC | Pasada |
+|---|---|---|---|---|
+| H-02 | U10 | SC16IS752IPW,128 (I²C 0x4D) | C57156 | 1 |
+| Puertos | U10.2, U10.16 | CTSA̅/CTSB̅ a GND | — | 2 |
+| P-1 | U14 | THVD1410DR, misma huella SOIC-8 | C2671345 | 2 |
+| P-1 | **U32 + C175** (nuevos) | 74LVC1G04: RTSA̅ → `/RS485_DE` (arranca en recepción) + 100 nF | C7827, C14663 | 2 |
+| P-1 | **D39** (nuevo) | SM712 en A/B de P11 | C12067 | 2 |
+| P-4 | **R145, R146** (nuevos, **DNP**) | 390 Ω, opción de polarización del bus | C23151 | 2 |
+| H-01 | U15 | Huella angosta `SOIC-16_3.9x9.9mm` | — | 1 |
+| P-2 | U15 | TRS3232EIDR (ESD IEC) | C308878 | 2 |
+| P-2 | **R147** (nuevo) | 1 k de R1OUT (`/RS232_R1OUT`) a `/SER_RXB` (H4 sin contienda) | C21190 | 2 |
+| G-03 | P11, P12 | Montados; huella `PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal` | C5160226 | 1 |
+
+### Conectores, ESD y limpieza
+
+| Hallazgo | Ref | Estado final | LCSC | Pasada |
+|---|---|---|---|---|
+| G-08 | **D36, D37, D38** (nuevos) | PESD5V0S1BA en `/NRST`, `/NTC_TEMP` y `/NTC2` | C2827694 | 1 |
+| G-04 | **JP6** (nuevo) | Puente de soldadura abierto sobre P5, «CUTOFF_BYPASS» | — | 1 |
+| H-08 | C22, Y2 | Textos de valor «10uF/50V» y «3.6864MHz» | — | 1 |
+| J-04 | Banderas NC y trozos de cable | 23 banderas huérfanas y 4 sobre pines conectados eliminadas; un trozo de cable borrado y otro recortado (sin cambio de red) | — | 1 |
+| J-05 | TP1–TP12, JP1–JP6 | Fuera del BOM y del CPL | — | 2 |
+
+### Reglas del proyecto y librería
+
+| Hallazgo | Archivo | Estado final | Pasada |
+|---|---|---|---|
+| F-01 | `.kicad_pro` | Netclasses por nombre exacto: HV24, PWR_HI, PWR_MODEM, PWR_MID, RF y Default (lista en la [sección F-01](v6-plan-correccion.md#f-01-el-drc-no-veia-ningun-espaciado-de-24-v) del plan) | 1 |
+| F-01 | `.kicad_dru` | Las 5 reglas del verificador 2 (piso 0.15, HV24↔HV24 0.2, HV24 externa 0.3, HV24 interna 0.5, pads de U2/U20/U25 0.15) | 1 |
+| H-04 | `SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` | `LCSC Part` borrado; la copia de U25 en el PCB se refresca en el layout | 1 |
+| H-03 | `IND-SMD_MWSA0804S.kicad_mod` (nueva) | Pads 2.75 × 5.5 mm a ±3.375 mm (separación 4.0 mm), cuerpo 8.8 × 8.2 mm, courtyard 10.0 × 9.0 mm | 2 y 3 |
+| C-01 | Símbolo TPS2552 | Dibujado y embebido en el esquemático (KiCad no lo trae) | 1 |
+
+---
+
+## 3. Delta de layout para Michelle (las tres pasadas juntas)
+
+La lista con casillas, en orden, está en la
+[sección 5 del plan de corrección](v6-plan-correccion.md#5-lista-de-trabajo-de-michelle-layout). Aquí está el resumen
+de lo que cambia en el PCB.
+
+### 3.1 Actualizar el PCB
+
+*Herramientas → Actualizar PCB desde esquemático* con **«Eliminar huellas sin símbolo»** y **«Reemplazar huellas con las
+del esquemático»** marcados. Revisar la lista del diálogo antes de aplicar:
+
+- solo se borran **D20** (D_SMA) y **D21** (SOD-128); PF15 era un flag virtual, sin huella;
+- solo cambian de huella las referencias de la tabla 3.2.
+
+Después, **solo en U25**, *Actualizar huella desde librería* para quitar `LCSC Part` (H-04). **Nunca** la actualización global
+desde librería (L-45). Luego rellenar zonas y correr el DRC con las reglas nuevas.
+
+### 3.2 Huellas que cambian
+
+| Ref | Antes | Ahora | Nota |
+|---|---|---|---|
+| U15 | `SOIC-16W_7.5x10.3mm` | `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm` | TRS3232EIDR; C85–C88 ≤ 3 mm, C89 ≤ 2 mm de U15.16 (L-51) |
+| D28 | SOD-923 | `Diode_SMD:D_0402_1005Metric` | con el re-ruteo LTE de F-06 |
+| Y3 | HC-49SD | `Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm` | pad 1 HSE_IN, pad 3 HSE_OUT, pads 2/4 GND; ≤ 3 mm de PH0/PH1 (máx. 5 mm), sin pistas internas debajo |
+| C91 | 0805 | `C_0603_1608Metric` | ≤ 2 mm de U11.22 |
+| JP1 | puente abierto | `Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm` | puenteado (net-tie) |
+| L2 (DNP), L6, L8, L20 | `Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm` | `Drogheda-v6:IND-SMD_MWSA0804S` | pads 2.75 × 5.5 mm a ±3.375 mm, courtyard 10.0 × 9.0 mm (L-53 corregido por L-63) |
+| U25 | con `LCSC Part` | misma huella, refrescada desde la librería | H-04 |
+
+No cambian: J10 (el apodo de librería se corrigió a `Connector_RJ:`, la misma geometría), P11/P12 (ya eran *Horizontal*
+en el PCB), Y4, F2, U10, U14, U17 y U21.
+
+### 3.3 DNP
+
+- **Pasan a montadas:** J10, P11, P12.
+- **Pasan a DNP:** U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21, Q10, DzG1, Rrp1, C10, C11, C22 (A-01) ·
+  K1, Q6, D6, R40, R41 (B-13).
+- **Nuevas en DNP:** R145, R146 (polarización RS-485).
+
+Las huellas DNP se quedan en la tarjeta. Borrar su cobre `/24V`, `/SW_FAN` y `/BST_FAN` (L-6). En K1 no hay cambio de
+cobre, salvo las dos conexiones de R148 (L-54).
+
+### 3.4 Piezas nuevas (46)
+
+| Ref | Huella | Dónde va |
+|---|---|---|
+| D35 | D_SMB | **en P1.3**; Rig1 a ≤ 3 mm de cobre de P1.3 (F-02) |
+| U28 | SOT-23-6 | junto a L21/C144/C145 en J12; `/ANT_BIAS` ≥ 1 mm de la línea RF con franja GND cosida (C-01, F-06) |
+| R135, R136 | 0603 | en los pines 3 y 4 de U28 |
+| C176 | 0603 | **≤ 2 mm de U28 pin 1**, misma capa, GND con vía ≤ 1 mm (L-64) |
+| C161, C162 | 1210 | ≤ 2 mm de VSYS 1/24 de U6, GND sobre el cobre del EP (A-05/A-02) |
+| C163, C164 | 0805 | ≤ 2–3 mm de U20.2, GND sobre el cobre del EP de U20 (F-03) |
+| C165 | CP_Elec_6.3x7.7 | en U20.2 (F-03) |
+| C166, C167 | 0805 | ≤ 3 mm de L20.2 (B-02) |
+| U29 + C168 | SOT-563 + 0603 | **entre U6 y L6, ≤ 5 mm del EP de U6** (F-51) |
+| R137, R138, C169 | 0603 | R138/C169 junto al pad 25 de U16 (PC5); R137 en cualquier punto de `/NTC` |
+| R139 | 0603 | en U12 pin 2 (EN); pista nueva `/ETH_PWR_EN` al pad 54 de U16 (PD2) |
+| R140 | 0603 | en U11.37 (`/ETH_RST`) |
+| U27 + C170 | SOT-23-5 + 0603 | **en U18.26 (RXD2)**; VCC de `/3V3_GNSS` |
+| U30 | SOT-23-6 | **≤ 3 mm de cobre de los pads de J9**, D± pasando por los pads, vía GND ≤ 1 mm (G-02) |
+| R141 | 0603 | pull-up de `/PFO` cerca del pad 29 de U16 (PB10) |
+| C171 | 0402 | en J14.C1 |
+| R142, R143 | 0603 | en `/MODEM_STATUS` (PC9) y `/DIN_4G`, donde convenga |
+| TP10, TP11 | pad 1.0 mm | cerca de U18 pines 50 (SAFEBOOT_N) y 49 (RESET_N), junto a un pad GND (C-07) |
+| R144 | 0603 | en la base de Q5 |
+| TP9 | pad 1.5 mm | PA9, en la fila de pads de depuración con TP3–TP7 (L-56) |
+| C172, C173 | 0603 | en AVDD 4/8 y 11/21 del W5500 |
+| U31 + C174 | SOT-563 + 0603 | **entre U19 y U20** (F-52) |
+| JP6 | puente de 2 pads, abierto | sobre P5 (`/MAIN5V`–`/SYS5V`), serigrafía «CUTOFF BYPASS» (G-04) |
+| D36, D37, D38 | SOD-323 | ≤ 3 mm de P6.1, P7.1, P8.1, a GND (G-08) |
+| U32 + C175 | SOT-23-5 + 0603 | ≤ 5 mm de U14 pines 2/3; C175 ≤ 2 mm de U32.5 (L-49) |
+| D39 | SOT-23 | ≤ 5 mm de cobre de P11.1/P11.2, A/B en flow-through, pin 3 a GND con 2 vías (L-50) |
+| R145, R146 | 0603 (DNP) | junto a P11 (L-50) |
+| R147 | 0603 | ≤ 3 mm de U15.12; H4.3 del lado de U10 (L-51) |
+| R148 | 0603 | camino más corto U16.37 (PC6) → U23.7 (`/DIN_4G`) (L-54) |
+| TP12 | pad 1.5 mm | a 2.54 mm de TP8, con un contacto GND a ≤ 10 mm (L-55, L-65) |
+
+### 3.5 Redes que cambian de ruteo
+
+- `/VIN_MODEM` desaparece: U20.2, C127 y C128 pasan a **`/MAIN5V`** (≥ 1.5–2 mm hasta U20; borrar la pista de 48 mm de `/VIN_MODEM`).
+- `/VIN_FUSED` gana D10.1: P1.1 → F2 → {D10, Q23.D}; `/24V_IN` = P1.1, F2.1 y Q10.D solamente.
+- `/IGN_IN` = {P1.3, Rig1.1, D35.1}; el tramo largo al MCU es `/IGN_SENSE`.
+- `/ANT_BIAS` (U28.6 → L21.2, C144, C145); U18.7 queda sin conectar; `/GNSS_ANT_OFF` (U18.5 → U28.3, R135);
+  `/GNSS_ANT_SHORT_N` gana U28.4 y R136; `/3V3_GNSS` gana U28.1, U28.5 y C176.
+- `/ETH_PWR_EN` (U12.2, U16.54, R139); U12.2 sale de `/SYS5V`.
+- `/DOUT_4G_F9P` (U27.4 → U18.26); U18.26 sale de `/DOUT_4G`; U27.2 entra a `/DOUT_4G`.
+- `/PFO` (antes `/PFO_TP`: U6.20, TP2, más U16.29 y R141).
+- `/NTC_CELL` (U16.25, R137, R138, C169); `/NTC` gana R137.
+- `/GNSS_SAFEBOOT_N` (U18.50, TP10); `/USART1_TX` (U16.42, TP9).
+- R56.2 pasa de GND a `/3V3`; los pads de Y3 se re-asignan como en 3.2.
+- **Puertos:** `/RS485_DE` nueva (U14.2, U14.3, U32.4) y `/SER_DEA` = {U10.1, U32.2}; D39 en `/RS485_A`/`/RS485_B`;
+  `/RS232_R1OUT` nueva (U15.12, R147.1) y `/SER_RXB` = {U10.24, H4.3, R147.2}; J10.8 → GND, J10.11 → `/ETH_ACTLED`,
+  J10.12 → `/ETH_ACT_A`; U10.2 y U10.16 → GND; R148 entre `/USART6_TX` y `/DIN_4G`; TP12 en `/1V8_MODEM`.
+
+### 3.6 Qué va a mostrar el DRC
+
+En una copia del PCB sin actualizar, con las reglas nuevas: **161 errores de separación**. **149** son proximidades del
+relleno de zonas guardado (se van al rellenar) y **12** son cobre real:
+
+- `/IGN_IN` en In2 contra vía GND 0.250, `/FAN_PWM` 0.291, vía `/5V_FAN` 0.300, `/NTC2` 0.305 y vía `/VEH5V` 0.340 mm.
+  Todos son F-02 y desaparecen al mover Rig1 a P1.3.
+- `/VIN_PROT` contra `/VEH5V`: 0.157 y 0.191 mm en (175.5, 113.8).
+- `/USB_VBUS` contra Q23.1 (`/Q23_GATE`): 0.225 mm.
+- `/SW_PWRIN` contra pista GND: 0.270 mm.
+- `/24V` contra `/COMP_FAN`: 0.290 mm × 2. Es la rama DNP, pero el cobre existe.
+- Clase RF: vía de `/RF_LTE` contra `/PWR_CTRL`, 0.150 mm. Se va con el re-ruteo de F-06.
+
+Ojo: KiCad lista **una sola** violación entre el tramo largo de `/IGN_IN` en In2 y `/VEH5V` (la vía a 0.340 mm), aunque las
+pistas paralelas están a 0.221–0.240 mm. No leer el conteo del DRC como la lista completa; el movimiento de F-02 elimina ese
+tramo de todos modos. Los avisos de `track_width` bajan de 183 a 121. Después del *Update PCB* aparecen elementos HV24
+nuevos en `/VIN_FUSED` junto a D10 y desaparecen los de `/VIN_MODEM`. Comprobar una vez con *Inspeccionar → Resolución de
+separación* que las clases sobrevivieron al guardado.
+
+### 3.7 Pasos de layout nuevos (L-49…L-66)
+
+L-49 dirección RS-485 · L-50 protección RS-485 en P11 · L-51 RS-232/H4 · L-52 J10 · L-53/L-63 land MWSA0804S ·
+L-54 R148 (B-13) · L-55 TP12 · L-56 fila de pads de depuración · L-57 SC16IS752 · L-58 resistencias CC de USB-C ·
+L-59 serigrafía de puertos · L-60 atributos de huella TP/JP · L-61 fiduciales · L-62 revisión de P1 · L-64 C176 ·
+L-65 pads de descarga forzada · L-66 revisión de LEDs de J10. Texto completo y agrupado en la
+[lista de Michelle](v6-plan-correccion.md#5-lista-de-trabajo-de-michelle-layout).
+
+---
+
+## 4. Informes de cada pasada
+
+- **[Pasada 1 — Informe de cambios al esquemático](v6-cambios-esquematico.md)** (en español): cada cambio por hallazgo,
+  pruebas de netlist, ERC, reglas del proyecto, librería, topología de fusible y polaridad, delta de layout y notas de firmware.
+- **[Pasada 2 — Puertos y sin nueva versión](v6-puertos-sin-nueva-version.md)** (inglés): veredicto puerto por puerto, hojas
+  de datos que decidieron los cambios, mapa I²C, cambios con prueba, L-49…L-62, notas de firmware por puerto y la tabla de
+  aceptados permanentemente.
+- **[Pasada 3 — Revisión final](v6-revision-final.md)** (inglés): 27 revisiones de la pasada 2 (26 PASS, 1 FAIL
+  corregido), cierre de N1/N2, avisos, L-63…L-66 y notas de firmware.
+
+La verificación independiente de la pasada 1 (126 ítems revisados uno por uno: 173 PASS / 0 FAIL) no se reproduce aquí;
+su resultado está en la sección 1.

03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Final-Check_v1.0.md

@@ -0,0 +1,223 @@
+---
+title: "EinarBoard v6 — Revisión final independiente (pasada 3, inglés)"
+tags: [project-drogheda, hardware, hbox, v6, esquematico, final-check]
+project: Project Drogheda
+author: Helgen Technologies
+date: 2026-09-28
+version: 1.0
+status: FINAL — pass 3 of 3 (independent check)
+audience: Michelle (layout), Leo, ingenieros
+---
+
+# EinarBoard v6: final independent check of the ports pass, and closure of N1/N2 (v1.0)
+
+!!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide"
+    Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios.
+
+!!! info "Pass 3 of 3 — final independent check"
+    Spanish summary, final state per block and the combined layout delta:
+    **[EinarBoard v6 — Cambios de esquemático: resumen de las 3 pasadas](v6-cambios-resumen.md)**.
+    Checks [pass 2](v6-puertos-sin-nueva-version.md), closes N1/N2 from the verification of [pass 1](v6-cambios-esquematico.md) (Spanish)
+    and fixes the inductor land. Final schematic sha256 `2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933`.
+
+
+**Date:** 2026-09-28 · **Board:** `kicad/hbox-watchdog-v6.*` (HBOX RTK, Helgen Technologies) · **Input:** sch `f73f41a8…27ee` (ports-pass output, verified on the Mac and in the staged copy) · **Baseline for the ports diff:** `apply/netlists/05-final.xml` · **Author:** Claude (final checker, independent of the apply and ports passes) · **Rules followed:** in-place edit with a backup first, span-scoped splices with a UUID multiset guard, expected changes written before editing, semantic netlist proof, `.kicad_pcb` not touched, no git, a unique staged path per commit plus sha256 on the Mac afterwards.
+
+## Resumen (ES)
+
+**Pase de puertos: 26 PASS, 1 FAIL.** Revisé el pase de puertos por mi cuenta: diff propio desde `05-final.xml`, conectividad derivada directamente del `.kicad_sch` (idéntica al netlist de kicad-cli: 353 redes, 0 diferencias) y hojas de datos de los fabricantes. Todos los cambios del esquemático son intencionales y correctos. Confirmé:
+
+- **THVD1410** con el mismo pinout que el SP3485, 3–5,5 V y fail-safe abierto/corto/inactivo.
+- **U32 74LVC1G04** en SOT-23-5 (1 NC, 2 A, 3 GND, 4 Y, 5 VCC). Según NXP, RTS̅ del SC16IS752 queda en ALTO tras el reset, así que el transceptor está en recepción durante el reset, en DFU y sin firmware. EFCR = 0x10 coincide con la tabla 30 de NXP.
+- **SM712** bien orientado (pines 1 y 2 a A/B, pin 3 a GND).
+- **TRS3232E** con el mismo pinout y capacitores de 0,1 µF a 3,3 V.
+- **R147 1 k** y los **CTS̅ a GND**, correctos según NXP.
+- **LED ACT de J10 (11/12) y J10.8 a GND**: confirmados con el **plano de Hanrun** (amarillo con ánodo en 12 y cátodo en 11; P8 = «CHS GND», con la nota «Connect CHS GND to PCB Ground»). El pase de puertos no había podido leer ese plano. Los LED del W5500 son activos en bajo.
+- **B-13**: un solo excitador en `/DIN_4G` (PC6 → R148), sin contienda.
+- **TP1–TP12 y JP1–JP6** fuera del BOM y del CPL.
+- **Los 8 números LCSC** existen, con stock y encapsulado correcto.
+
+**El FAIL es la huella H-03 `IND-SMD_MWSA0804S`.** El pase de puertos intercambió las cotas J y H de Sunlord. La figura 4-1 de la especificación MWSA50230000 define I = largo del pad (2,75), **J = separación entre pads (4,0)** y **H = alto del pad (5,5)**, y los electrodos están sobre la cota **B = 8,8 mm**. La huella tenía pads de 2,75 × 4,0 a ±4,125 mm (separación 5,5) y el cuerpo dibujado girado. **Lo corregí:** pads de 2,75 × 5,5 a ±3,375 mm (separación 4,0, extensión 9,5), cuerpo de 8,8 × 8,2 y courtyard de 10,0 × 9,0. El netlist no cambia (el nombre de la huella es el mismo). Esto sustituye las cifras de L-53.
+
+**N2 cerrado:** se añadió **C176** de 100 nF 0603 (C14663) entre `/3V3_GNSS` y GND, junto a U28 en la hoja, con la nota «≤ 2 mm from U28 pin 1». Lo esperado coincide exactamente con lo obtenido.
+
+**N1 cerrado sin cambio:** la hoja de datos de SCTF (serie 3X, SMD3225-4P) da **1 Xtal, 2 GND, 3 Xtal, 4 GND**, con la misma numeración de vista superior que la huella de KiCad. El mapeo `Crystal_GND24` es correcto. Además, gm_crit = 0,50 mA/V (el F411 admite 1 mA/V) y la CL efectiva queda entre 9 y 11 pF para un cristal de 10 pF.
+
+**ERC:** 0 errores, 134 warnings (igual que antes). Superposiciones 30 → 30 y cruces 9 → 9 (todos preexistentes). **SHA-256 final del esquemático:** `2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933`. Ningún puerto queda bloqueado por el esquemático. Hay dos avisos que no bloquean: RXA flota durante la transmisión RS-485 (se resuelve en firmware), y la polaridad de USB_BOOT del A7670 es contradictoria entre documentos de SIMCom (hay procedimiento alterno en banco). Se añaden L-63…L-66 a la lista de Michelle.
+
+## 0. Summary
+
+| Item | Result |
+|---|---|
+| Ports-pass verification | **26 PASS · 1 FAIL** (the H-03 land pattern; fixed here, §3) |
+| Diff 05-final → ports output (my own code) | 8 added, 0 removed, 8 pin-net changes, 0 net-class changes; every change is on the intended list |
+| Sch-derived connectivity vs kicad-cli netlist | identical (353 nets, 0 partition differences, 0 name mismatches), at start and at the end |
+| N2 | **C176** 100 nF 0603 C14663, `/3V3_GNSS`–GND, beside U28; expected == actual |
+| N1 | **No change**: SCTF datasheet confirms pads 1/3 = crystal, 2/4 = GND |
+| Fixes | **F2**: `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod` land corrected to the Sunlord drawing (no netlist effect) |
+| ERC (kicad-cli via KiCad MCP) | 0 errors, 134 warnings, before and after |
+| Overlaps / wire crossings | 30 → 30 / 9 → 9 (all pre-existing; C176 involved in none) |
+| BOM | 299 fitted real parts, all with LCSC numbers (298 + C176); TP1–TP12 and JP1–JP6 excluded; PF* virtual |
+| **Final sch sha256** | **`2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933`** |
+| Untouched | `.kicad_pcb` `6ddec80d…36bf`, `.kicad_pro` `d577aa43…6ce`, `.kicad_dru` `31ce0f4f…831` |
+
+## 1. Ports-pass verification table
+
+Method: I staged the Mac sch (sha256 `f73f41a8…27ee`, equal to the ports pass's claim and its container copy) and re-exported the netlist with the KiCad MCP (`netlists/00-start.xml`). I wrote my own semantic diff against `apply/netlists/05-final.xml` (`work/fdiff.py`, xml.etree only). I derived connectivity directly from the `.kicad_sch` with the apply-verifier's `schconn.py`/`derive_compare.py` after reading them. I used the manufacturers' datasheets through WebFetch and, for image-only PDFs, rendered them with pdf.js in the Mac's browser pane. The screenshots are in `final/evidence/`. The container and Mac shell proxies block ti.com, nxp.com and lcsc.com (403); I did not route around that.
+
+| # | Item | Intended | Found | Verdict | Evidence / citation |
+|---|---|---|---|---|---|
+| 1 | Completeness of the change set | only the ports/no-respin items | Diff 05-final → current: +C175, D39, R145, R146, R147, R148, TP12, U32; 0 removed; pin changes J10.8/11/12, U10.2/16, U14.2/3, U15.12; field changes on D6, J10, K1, L2/L6/L8/L20, Q6, R40, R41, TP1–TP8, U14, U15; 0 class changes. Nothing else | PASS | `work/diff_apply_to_start.json`; equals `ports/netlists/final.xml` (0 differences) |
+| 2 | U14 → THVD1410DR pinout | = SP3485 (R, RE̅, DE, D, GND, A, B, VCC) | TI D pkg: 1 R, 2 RE̅ (2 MΩ PU), 3 DE (2 MΩ PD), 4 D, 5 GND, 6 A, 7 B, 8 VCC. Netlist: 1 `/SER_RXA`, 2+3 `/RS485_DE`, 4 `/SER_TXA`, 5 GND, 6 `/RS485_A`, 7 `/RS485_B`, 8 `/3V3` | PASS | TI THVD14x0 datasheet, pin functions table |
+| 3 | U14 supply | 3.3 V | "3 V to 5.5 V"; U14.8 on `/3V3`; C84 100 nF on `/3V3` (TI: 100 nF per supply) | PASS | TI datasheet |
+| 4 | U14 fail-safe / ESD claims | open, short, idle; IEC ESD | "failsafe-high when … open-circuit … short-circuit … idle bus"; IEC 61000-4-2 ±18 kV contact, ±25 kV air; HBM ±30 kV; EFT ±4 kV; bus abs max ±18 V; R = Z when RE̅ = H | PASS | TI datasheet §7, function tables |
+| 5 | U32 74LVC1G04 package pinout | DBV: 1 NC, 2 A, 3 GND, 4 Y, 5 VCC | TI DBV table matches; KiCad `SOT-23-5` pads 1-2-3 on the left, 4-5 on the right (standard). Netlist: 2 `/SER_DEA` (U10.1 RTSA̅), 4 `/RS485_DE` (U14.2+3), 5 `/3V3` (+C175), 3 GND, 1 NC | PASS | TI SN74LVC1G04 datasheet; `SOT-23-5.kicad_mod` |
+| 6 | Direction polarity, receive in reset/DFU/no firmware | DE = RE̅ = NOT(RTSA̅) | RTSA̅ HIGH → DE = 0, RE̅ = 0 → receiver on, driver off. RTSA̅ LOW → DE = 1, RE̅ = 1 → transmit | PASS | logic plus items 7 and 8 |
+| 7 | SC16IS752 RTS̅ after reset | HIGH | NXP Table 5 "Output signals after reset": "RTS HIGH"; MCR and EFCR "all bits cleared"; MCR[1] = 0 → "force RTS output to inactive (HIGH)" | PASS | NXP SC16IS752/762 datasheet |
+| 8 | Firmware note EFCR = 0x10 | RTSCON = 1, RTSINVER = 0 | EFCR bit 4 RTSCON "1: transmitter controls RTS pin"; bit 5 RTSINVER "0: RTS = 0 during transmission and RTS = 1 during reception"; §9.1 "asserts the RTS pin (logic 0) once the host writes data … de-asserts (logic 1) once the last bit … has been transmitted". 0x10 is right; bit 0 (9-bit mode) is not needed | PASS | NXP Table 30, §9.1/9.2 |
+| 9 | D39 SM712 orientation | pins 1/2 to the lines, 3 to GND | Semtech: "pins 1 and 2 have a working voltage of 12 volts … connected to the differential data line pairs … pin 3 … 7 volts … connected to ground". Netlist: 1 `/RS485_A`, 2 `/RS485_B`, 3 GND. KiCad `SOT-23` pads 1/2 on one side, 3 opposite | PASS | Semtech SM712 datasheet Rev 6.0 (Mouser copy) |
+| 10 | R145/R146 bias, DNP | 3V3 → A, B → GND, 390 Ω, DNP | R145 `/3V3`–`/RS485_A`, R146 `/RS485_B`–GND, both DNP; A > B idle = logic 1 (THVD1410: V_ID > V_TH+ → R = H). 3.3 × 60/(780 + 60) = 0.236 V with two 120 Ω terminations | PASS | netlist; TI receiver function table |
+| 11 | U15 → TRS3232EIDR pinout | = MAX3232 | TI: 1 C1+, 2 V+, 3 C1−, 4 C2+, 5 C2−, 6 V−, 7 DOUT2, 8 RIN2, 9 ROUT2, 10 DIN2, 11 DIN1, 12 ROUT1, 13 RIN1, 14 DOUT1, 15 GND, 16 VCC; netlist matches pin for pin; narrow SOIC-16 land | PASS | TI TRS3232E datasheet |
+| 12 | U15 charge-pump caps | 0.1 µF at 3.3 V | TI table at 3.3 V ± 0.3 V: C1 = 0.1 µF, C2–C4 = 0.1 µF, "C3 … VCC or GND". C85 C1±, C86 C2±, C87 V+ → GND, C88 V− → GND, C89 VCC, all 100 nF C14663. Unused DIN2 to GND ("connected to VCC or ground") | PASS | TI datasheet |
+| 13 | R147 1 k on R1OUT (H4) | R1OUT → R147 → `/SER_RXB`; H4.3 on the U10 side | `/RS232_R1OUT` = {U15.12, R147.1}; `/SER_RXB` = {U10.24, H4.3, R147.2}. An external TTL driver sees ≤ 3.3 mA of contention; RC ≈ 10 ns | PASS | netlist |
+| 14 | CTSA̅/CTSB̅ tied to GND | GND, auto-CTS off | NXP: CTS̅ LOW = ready; "only affects the transmit and receive operations when Auto-CTS function is enabled via EFR[7]". Tied LOW is the safe choice: it can never block TX, even if auto-CTS gets enabled | PASS | NXP Table 2 |
+| 15 | J10 ACT LED pin 11/12 swap | yellow A = 12, K = 11 | **Hanrun HR911105A drawing, p.1 schematic:** "Yellow LED" with pin 12 on the anode and pin 11 on the cathode; "Green LED" with pin 9 on the anode and pin 10 on the cathode. Netlist: 12 `/ETH_ACT_A` (R97 330 Ω → `/3V3_ETH`), 11 `/ETH_ACTLED` (U11.27); 9 `/ETH_LNK_A` (R96), 10 `/ETH_LINKLED` (U11.25) | PASS | `evidence/hanrun_HR911105A_p1_schematic.jpg` (rendered from lcsc.com/datasheet/C12074.pdf) |
+| 16 | J10.8 → GND | Bob-Smith return | Hanrun: "CHS GND P8", through 1000 pF 2 kV to the 4 × 75 Ω node; note "Connect CHS GND to PCB Ground". P7 = NC. P4/P5 = TX/RX centre taps (J10.4 `/3V3_ETH`, J10.5 `/ETH_RCT`) | PASS | same page |
+| 17 | W5500 LED drive polarity | active-low, so the LEDs light | W5500 v1.1.0: LINKLED (25) "Low: Link is established"; ACTLED (27) "Low: Carrier sense from the active PMD"; VOL 0.4 V at IOL 8 mA. LED current ≈ (3.3 − 2.0)/330 ≈ 4 mA (HR911105A LEDs: Vf 1.8–2.8 V, 20 mA rated) | PASS | WIZnet W5500 datasheet v1.1.0; Hanrun p.2 |
+| 18 | **H-03 footprint `IND-SMD_MWSA0804S` land** | Sunlord recommended land | **Wrong.** Sunlord MWSA-S spec (SPEC No. MWSA50230000) Fig. 4-1 (applies to MWSA0412S–MWSA1265S): **I = pad length along the axis, J = gap between pads, H = pad height across**; electrodes at the **B** ends (D = depth along B, E = height along A). Table 4-1 MWSA0804S: A 8.2±0.3, B 8.8±0.4, C 3.8±0.2, D 1.4±0.3, E 5.0±0.3, I 2.75, J 4.0, H 5.5. The ports pass read J as pad width and H as the gap (and took A as the electrode axis), which gave 2.75 × **4.0** pads with a **5.5** gap at ±4.125 mm. Correct: 2.75 × **5.5** pads with a **4.0** gap at **±3.375 mm** | **FAIL → fixed (F2)** | `evidence/sunlord_MWSA-S_fig4-1_land.jpg`, `…fig4-1_body.jpg`; Table 4-1 row read from the PDF text layer |
+| 19 | H-03 body vs courtyard | body fits the courtyard | The old courtyard (11.5 × 9.7) did enclose the body at maximum tolerance in either orientation, but the F.Fab outline was rotated (8.2 on the pad axis instead of 8.8). Fixed with item 18: body 8.8 × 8.2, courtyard 10.0 × 9.0 (max of pads 9.5 / body 9.2 on x, body 8.5 on y, plus 0.25) | PASS (after F2) | §3 |
+| 20 | B-13 topology | PC6 USART6_TX → R148 → `/DIN_4G` → U23 (B → A) → modem RXD | `/USART6_TX` = {U16.37, R148.1, K1.10 (DNP)}; `/DIN_4G` = {R148.2, R143.2 100 k PU, U23.7 1B, K1.5/6 (DNP), R108.1 (DNP, never-fit)}; U23.5 DIR = GND → "B data to A" (1B input, 1A output); `/DIN_4G_M` = {U23.2, U19.10 **RXD**, R108.2 (DNP)}; U23 VCC(A) = `/1V8_MODEM`, VCC(B) = `/3V3` | PASS | netlist; evidence `ic_pins_U19.csv` (pin 10 RXD) |
+| 21 | Drivers on `/DIN_4G` and neighbouring nets | no two outputs on one net | **Before (05-final):** `/DIN_4G` driven only through K1 COM, from either NC = F9P TXD2 (`/USART1_RX`) or NO = PC6, never both. **After:** `/DIN_4G` has one driver, PC6 via R148; `/USART1_RX` has one driver, F9P TXD2 (U18.27), with PA10 as input and Rdfu1 as PU; `/DIN_4G_M` has one driver, U23.1A; `/BYP_CTRL` (PB5) is now unloaded (R40 DNP); `/KCOIL` and `/Q6_BASE` are all DNP. Fitting K1 together with R148 would put F9P TXD2 against PC6 (both notes say "never") | PASS | §1.1 table |
+| 22 | TP12 (1V8) | 1V8 pad beside TP8 for forced download | TP12 on `/1V8_MODEM` (U19.15 VDD_1V8/_EXTVDD). **SIMCom "A7670 Series Hardware Design V1.00"** (A7670C/E/SA): USB_BOOT pin 6 B-PD; "pull the USB_BOOT pin to 1.8V, then apply VBAT … to enter the download mode". **"A7670 & SIM7070 & A7672X Compatible Design V1.02":** A7670X pin 6 marked "●" = "cannot be pulled up before the module powered up"; "pull up the USB_BOOT pin to 1.8V for A7670". The v6 symbol names the pin `USB_BOOT●`. **Conflict:** "A7672X/A7670X Series Hardware Design V1.03" lists A7670SA and gives USB_BOOT B-PU with "pull the USB_BOOT pin to GND". TP12 matches two SIMCom documents; a GND fallback is recorded (A2, L-65) | PASS (with note A2) | SIMCom documents as cited |
+| 23 | TP1–TP8 out of BOM/CPL | `in_bom no`, `in_pos_files no` | TP1–TP12 and JP1–JP6 all `in_bom no`, `in_pos_files no`, `on_board yes`; none appears in the kicad-cli BOM | PASS | sch flags; `bom_final_ungrouped.csv` |
+| 24 | New/changed LCSC numbers | exist, package, stock | C2671345 THVD1410DR SOIC-8, 8 006 (Extended, **pre-order category**) · C7827 SN74LVC1G04DBVR SOT-23-5, 163 327 · C12067 SM712.TCT SOT-23, 49 238 · C308878 TRS3232EIDR SOIC-16 (narrow), 3 564 · C14663 100 nF 0603 X7R 50 V, Basic, 37.5 M · C23151 390 Ω 0603, Basic, 311 280 · C21190 1 kΩ 0603, Basic, 39.8 M · C21189 0 Ω 0603, Basic, 13.9 M. Inductors unchanged: C17700171 (470), C17700165 (646), C17700167 (1 675) | PASS | `get_jlcpcb_part` (all 11) |
+| 25 | ERC | 0 errors | 0 errors / 134 warnings at start (same families as reported) | PASS | KiCad MCP `run_erc` |
+| 26 | Sch ↔ netlist | derived = exported | 353 = 353 nets, 0 differences, 0 name mismatches (variant MR, −1, wire-interior on) | PASS | `derive_compare.py` |
+| 27 | Overlaps / crossings | not worsened | 30 / 9. The two crossings on U10 (x = 551.18) and the four on U15 pre-date the ports pass (21 wires added, 0 removed, none of them among the crossings) | PASS | MCP checks; wire diff vs `ports/state/00-pre.kicad_sch` |
+
+### 1.1 Drivers per net, before and after (B-13)
+
+| Net | Before (05-final, K1 fitted) | After (current) | Outputs fighting? |
+|---|---|---|---|
+| `/DIN_4G` | K1 COM (5/6), R143 100 k PU, U23.7 input, R108 DNP | **R148 ← PC6** (single driver), R143 PU, U23.7 input; K1 and R108 DNP | No |
+| `/USART6_TX` | U16.37 PC6, K1.10 (NO) | U16.37 PC6, R148.1; K1.10 DNP | No |
+| `/USART1_RX` | U18.27 F9P TXD2, U16.43 PA10 input, Rdfu1 PU, K1.1 (NC) | U18.27, PA10, Rdfu1; K1.1 DNP | No |
+| `/DIN_4G_M` | U23.2 (1A out), U19.10 RXD, R108 DNP | unchanged | No |
+| `/BYP_CTRL` | PB5 → R40 → Q6 → K1 coil | PB5 only (R40 DNP): set it as output LOW or analog in firmware | — |
+
+When the MCU is in reset or DFU, PC6 is Hi-Z and R143 holds `/DIN_4G` HIGH (UART idle). With the modem off, 74LVC2T45 Ioff isolates the A side.
+
+### 1.2 Advisories (not failures; nothing to change in the schematic)
+
+- **A1. RXA floats during RS-485 transmit.** With RE̅ tied to DE, THVD1410 R = Z whenever DE = 1 (TI receiver table), and NXP documents no pull-up on RXA. TI's own typical application ties R straight to the UART RX, so this is not a datasheet violation and does not stop the port. The SP3485 behaved the same way. **Firmware:** after each frame, wait for LSR[6] (TEMT), reset the RX FIFO (FCR[1]), read LSR to clear any error flags raised during TX, and only then arm reception. An alternative is EFCR[1] RXDISABLE while transmitting. A 10 k pull-up on `/SER_RXA` would make this unnecessary, but it is an optional robustness item, not an error, so it was not added.
+- **A2. USB_BOOT polarity conflict in SIMCom documents** (item 22). The bench procedure is to short TP8–TP12 at modem power-on; if the download port does not enumerate on J9, short TP8 to GND instead. L-65 keeps a GND point within reach.
+- **A3. Cosmetic:** pre-existing text crowding at U14 value / R82 / JP5 and C85–C88 on U15 (already in the 30-overlap baseline). No electrical effect.
+- **A4.** The ports report quotes the SM712 at 400 W (8/20 µs, the LCSC description); the Semtech Rev 6.0 sheet lists a higher peak pulse power class. Either value suits a cabinet-internal RS-485 run.
+
+## 2. N1 and N2
+
+### N2: TPS2552 input decoupling (U28)
+TI TPS255x: "Input voltage; connect a 0.1 µF or greater ceramic capacitor from IN to GND as close to the IC as possible." U28 DBV pin 1 = IN = `/3V3_GNSS`. The existing C170 (100 nF on `/3V3_GNSS`) sits elsewhere on the sheet (U27/F9P area), so it does not meet "close to U28".
+
+**Done:** **C176** = 100 nF 0603, LCSC **C14663** (Basic, 37.5 M in stock), pin 1 `/3V3_GNSS`, pin 2 GND. It sits at sheet (457.2, 182.88) rotated 90°, directly above U28, with the sheet note "N2: C176 = U28 IN decap, <=2 mm to U28.1" and a `Note` field that states the layout rule. C176 is the next reference after the highest used (C175); none of the gap numbers exists on the PCB either.
+
+### N1: Y3 pad assignment (SCTF SX3B25.000F1010F30, C2901684)
+**Confirmed from the manufacturer datasheet**: SCTF "3X Series 3.2 × 2.5 mm SMD Crystal" (LCSC copy `2110101030_Shenzhen-SCTF-Elec-SX3B25-000F1010F30_C2901684.pdf`, rendered with pdf.js). The pin table reads **1 Xtal, 2 GND, 3 Xtal, 4 GND**. The top view numbers 1 bottom-left, 2 bottom-right, 3 top-right, 4 top-left, which matches KiCad `Crystal_SMD_3225-4Pin_3.2x2.5mm` (pad 1 at (−1.1, +0.85), 2 at (+1.1, +0.85), 3 at (+1.1, −0.85), 4 at (−1.1, −0.85)). The netlist has Y3.1 `/HSE_IN`, Y3.3 `/HSE_OUT`, Y3.2/Y3.4 GND. **No change.**
+
+Cross-checks from the same sheet: CL 6–20 pF (part code "10" = 10 pF), C0 ≤ 3 pF, ESR ≤ 30 Ω (20–54 MHz), drive level typ 10 / max 100 µW. From ST AN2867: gm_crit = 4 · 30 Ω · (2π · 25 MHz)² · (3 + 10 pF)² = **0.50 mA/V**, against the STM32F411 HSE Gm_crit_max of 1 mA/V (margin 2). C113/C114 = 12 pF give CL_eff = 6 pF + Cstray (3–5 pF) = **9–11 pF** for the 10 pF part. `evidence/sctf_3X_p1_specs.jpg`, `sctf_3X_p2_pinout.jpg`.
+
+## 3. Fixes, with proof
+
+### F1: N2 (schematic)
+- **Expected, written before editing** (`out/F1-N2/expected_written_before_edit.json`): +C176 {100nF, `Capacitor_SMD:C_0603_1608Metric`, `Device:C`, LCSC C14663, fitted, in BOM/CPL, 1:`/3V3_GNSS`, 2:GND}; `/3V3_GNSS` gains C176.1; GND gains C176.2; nothing else.
+- **Edit:** `tools/gF1_n2.py` uses the apply-pass editor (`apply/tools/ops.py`: splice-only, UUID multiset guard). The text diff is **152 lines added, 0 removed or changed**: 1 symbol, 2 wires, 2 labels, 1 text. The C176 field angles were set to 90 to match the sheet's other rotated passives (L6, RS1), patching only the block the script generated.
+- **Actual:** netlist `00-start.xml` → `final.xml`: added 1 (C176, exactly the expected attributes and pins), removed 0, field changes 0, pin changes 0, class changes 0, membership changes as expected. **EXPECTED == ACTUAL.** Sch-derived connectivity also shows only the GND and `/3V3_GNSS` groups changed.
+- Structural checks: orphan NC flags, NC on connected pins, dangling wire ends, dangling labels and unconnected pins without NC all stay at 0 → 0.
+
+### F2: H-03 land pattern (library file `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod`)
+- **Error, with evidence:** item 18 (Sunlord MWSA50230000 Fig. 4-1 and Table 4-1).
+- **New geometry:** pads 1/2 SMD round-rect **2.75 × 5.5 mm** at **x = ∓3.375 mm** (gap 4.0, outer extent 9.5); F.Fab body **8.8 (x) × 8.2 (y)**; F.CrtYd **10.0 × 9.0 mm**; silk lines at y = ±4.21 (≥ 1.4 mm from the pads); Reference/Value at y = ∓5.5. All 11 UUIDs of the old file are kept; the name is unchanged, so L2/L6/L8/L20 keep the same footprint link and **the netlist is unaffected**.
+- **Coverage at the tolerance extremes:** the electrode spans x = 2.9…4.6 mm (B 8.4–9.2, D 1.1–1.7), inside the pad's 2.0…4.75 mm; E ≤ 5.3 mm fits inside H = 5.5 mm. The electrode is fully wetted, with a 0.35 mm toe and a 1.0 mm heel as Sunlord specifies. This land is also closer to the old SRU8028 land (outer ±4.9 mm) than the ports-pass version (±5.5 mm), so it disturbs placement less.
+- Old file backed up; sha256 `dbf53557…a71f` → **`74528135d4f69617df8570da58700bac3920827a78ec9104c3440be2c5975638`**. The KiCad MCP cannot open project-local libraries; the file parses cleanly (sexpdata) in KiCad 9 writer format, and ERC (which checks footprint links) reports 0 errors.
+
+### Hashes and commits
+
+| Step | File | sha256 (Mac, checked after every commit) | Staged path used |
+|---|---|---|---|
+| start | `hbox-watchdog-v6.kicad_sch` | `f73f41a8…27ee` | — (backup `_to_delete/v6-final-20260928/00-pre/`) |
+| F1 (first write) | sch | `889b3c32…1ef` | `/mnt/user-data/outputs/v6final-F1-N2-20260928a/` |
+| F2 | `IND-SMD_MWSA0804S.kicad_mod` | `74528135…5638` | `/mnt/user-data/outputs/v6final-F2-H03-20260928b/` |
+| F1 (fields horizontal, **final**) | sch | **`2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933`** | `/mnt/user-data/outputs/v6final-F1b-N2-20260928c/` |
+| PDF | `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf` | `ae88d524…746b` (old `41241140…91b0` in `00-pre/`) | exported by the KiCad MCP |
+
+The only difference between the two F1 writes is C176's own UUID; C176 was never on the PCB.
+
+## 4. ERC
+
+| State | Errors | Warnings | Overlaps | Crossings |
+|---|---|---|---|---|
+| Start (`f73f41a8`) | 0 | 134 | 30 | 9 |
+| After F1 + F2 (final) | 0 | 134 | 30 | 9 |
+
+## 5. Final state
+
+- **Schematic sha256: `2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933`**
+- Total vs the apply-pass final (`05-final.xml`): +9 parts (C175, C176, D39, R145, R146, R147, R148, TP12, U32), 0 removed, 8 pin-net changes (J10.8/11/12, U10.2/16, U14.2/3, U15.12), 0 net-class changes.
+- Final netlist: `final/netlists/final.xml` (sha256 `7b65595f…607c`; Mac copy `_to_delete/v6-final-20260928/netlists/final-b.xml`).
+
+## 6. Additions to Michelle's layout list (continuing from L-62)
+
+63\. **MWSA0804S land corrected (supersedes the figures in L-53).** L2/L6/L8/L20 now use pads of **2.75 × 5.5 mm at ±3.375 mm** (gap 4.0, outer extent 9.5), courtyard **10.0 × 9.0 mm**, with the body's 8.8 mm side along the pad axis. The land is smaller than the ports-pass version (11.5 × 9.7) and close to the old SRU8028 land, so neighbour spacing is easier than L-53 said. Keep L-11/L-21/L-22/L-23 distances measured to the new pads. If the ports-pass version of this footprint was already pulled into the board, refresh **only these four refs** from the library (L-45).
+
+64\. **C176 (N2):** 0603 **≤ 2 mm from U28 pin 1 (IN)**, on the same layer as U28. Its GND pad goes to the GND plane through a via ≤ 1 mm away, and U28 pin 2 uses the same GND region. Feed `/3V3_GNSS` to U28.1 through the C176 pad (the cap sits between the supply trace and the pin).
+
+65\. **TP8 / TP12 forced-download pads (A2):** TP12 (1V8) at 2.54 mm from TP8 (L-55), plus a **GND contact within 10 mm of TP8**, such as J9's shell tab (SH = GND) or another GND pad. Silk: "BOOT: TP8–1V8 (alt: TP8–GND)".
+
+66\. **J10 LED routing check:** after Update PCB, confirm pad 12 = `/ETH_ACT_A` (to R97) and pad 11 = `/ETH_ACTLED` (to U11.27), per the Hanrun drawing (yellow A = 12, K = 11). Pad 8 = GND per the Hanrun note "Connect CHS GND to PCB Ground" (L-52).
+
+## 7. Firmware notes added (FW 0.7.x `board_v6.h`)
+1. RS-485 RX hygiene (A1): flush the RX FIFO and clear LSR after each transmitted frame (LSR[6] TEMT → FCR[1]), or use EFCR[1] RXDISABLE during TX. Keep EFR[6] (auto-RTS) and EFR[7] (auto-CTS) = 0 while EFCR RTSCON = 1.
+2. PB5 (BYP_CTRL) is unconnected now (R40 DNP): configure it as output LOW or analog.
+3. Modem forced download: try TP8–TP12 (1.8 V) first; if J9 does not enumerate the download port, use TP8–GND (A2).
+
+## 8. Anything that still blocks a port or the order
+**Nothing in the schematic.** Remaining conditions:
+
+- **Layout:** L-49…L-66, especially L-63 (use the corrected MWSA land before routing the switchers) and L-64.
+- **Library pass (optional):** `Drogheda-sym:TPS2552DBV` is still embedded-only (from the apply pass).
+- **Order logistics:** pre-order THVD1410DR (C2671345, JLC pre-order category), U21 and J14; buy the P11/P12 mating plugs.
+- **Bench, first board:** both J10 LEDs light with link up; RS-485 idles in receive during MCU reset and in DFU; RS-485 loopback with EFCR = 0x10 (checking the A1 FIFO handling); RS-232 and H4 checks; J9 download mode (TP8–TP12, then TP8–GND if needed); L6/L8/L20 solder joints inspected on the new land.
+
+## 9. Files
+- This report: `/home/claude/v6audit/final/2026-09-28_Drogheda_EinarBoard-v6_Final-Check_v1.0.md`
+- Final netlist: `final/netlists/final.xml`; start: `netlists/00-start.xml`; intermediate: `netlists/01-N2.xml`
+- Final schematic copy: `final/hbox-watchdog-v6.kicad_sch.final`; footprint: `final/IND-SMD_MWSA0804S.kicad_mod.final`; PDF: `final/hbox-watchdog-v6-schematic.pdf`; BOM: `final/bom_final_ungrouped.csv`
+- Proof: `final/out/F1-N2/` (expected written before the edit, edit log, output), `final/out/F2-H03/`, `final/work/diff_*.json`, `final/work/fdiff.py`
+- Scripts: `final/tools/gF1_n2.py`
+- Datasheet evidence: `final/evidence/` (Hanrun p.1/p.2, Sunlord Fig. 4-1 body and land, SCTF p.1/p.2, sheet crop of U28/C176)
+- Mac backups: `kicad/_to_delete/v6-final-20260928/` (`00-pre/` sch and old PDF, `01-N2/` post and post-b, `02-H03-land/` pre and post footprint, `netlists/`, BOM, new PDF)
+- Git (for Leo; nothing was run here): in the `kicad` submodule commit `hbox-watchdog-v6.kicad_sch` and `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod`, then bump the parent gitlink with `git -c diff.ignoreSubmodules=none commit …`. If KiCad is open on v6, close it without saving before Update PCB.
+
+## 10. F3: LFP-HT backup-pack straps (mirror of V5.6)
+
+**Resumen (ES):** v6 quedó con los mismos estrapes del cargador que V5.6 para el paquete LFP-HT 26650: JP2 puenteado 2-3
+(F2 a GND) y R55 = 5.6 k (C23189). Flotación **3.50 V** (antes 4.00 V Li-ion). Netlist: 0 cambios de pin o de red.
+ERC 0 errores (135 avisos). Esquemático `d58a89ba…e7b`.
+
+**Reason.** On 28-Sep Leo chose a high-temperature LiFePO4 26650 pack for V5.6, and v6 uses the same pack family. v6 was still
+strapped Li-ion (JP2 F2 high, R55 10 k): an LFP pack would have floated at **4.00 V instead of about 3.50 V** (overcharge hazard).
+
+| Ref | V5.6 (reference) | v6 before | v6 after |
+|---|---|---|---|
+| JP2 (F2) | `Jumper:SolderJumper_3_Bridged23`, fp `Drogheda:SolderJumper-3_P1.3mm_Bridged23_RoundedPad1.0x1.5mm`, value `F2:LFP (2-3)` | Bridged12, `F2:Li-ion` | **= V5.6**, Note "LFP-HT (F2 low), same as V5.6" |
+| R55 (RNTB) | 5.6k/1 % 0603, C23189, `/VEH5V`–`/NTC` | 10k/1 %, C25804 | **5.6k/1 %, C23189** |
+| JP3 (F1), JP4 (F0) | F1 = 0, F0 = 1 | same | unchanged |
+
+- **Netlist confirmation:** U6.12 F2 = `/F2_SEL` = {JP2.2}; U6.13 F1 = {JP3.2}; U6.14 F0 = {JP4.2}; U6.17 NTC = {R55.2, P3.3, R137.1}; R55.1 on `/VEH5V` (the RBIAS of the ADI datasheet).
+- **Float voltage** (ADI LTC4040 datasheet, pin-function table): F2 = 0 selects LiFePO4; (F1, F0) = (0, 1) → **3.50 V**.
+- **Charge window** with R55 = 5.6 k and a 10 k B3380 NTC: hot pause **+60 °C**, cold ≈ **+8 °C** on v6 (the F-51 tap R137/R138 shifts the cold trip about 2 °C).
+- **Proof:** expected changes written before the edit; netlist diff: 0 added, 0 removed, 0 pin-net, 0 membership and 0 class changes; only JP2 value/footprint/lib/Note and R55 value/LCSC/Note changed (plus JP2's footprint-filter text, which follows the symbol swap exactly as on V5.6).
+- **ERC:** 0 errors, 135 warnings (+1: the embedded Bridged23 symbol is not in the KiCad library, as on V5.6).
+- **Hashes:** sch `2b394ef9…2f5933` → **`d58a89ba5a5ac46419edf9d68672a8208d825a16387298d0167e21399cd41e7b`**; PDF `3e073181…4362`; PCB `6ddec80d…` untouched.
+- **Layout L-67 (safety):** after Update PCB confirm JP2 is the Bridged23 footprint with copper on pads 2-3 and no 1-2 bridge left; silk "F2: LFP".
+- **Firmware / bench:** measure `/F2_SEL` = 0 V, `/F1_SEL` = 0 V, `/F0_SEL` = MAIN5V on the first board before connecting a pack; rescale the PC5 NTC conversion (RBIAS 5.6 k, β 3380); raise the `CHRG_EN` hot cut in step with +60 °C; LFP-appropriate SoC thresholds or coulomb counting.

03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md

@@ -11,6 +11,12 @@ author: Helgen Technologies
 !!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide"
     Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios.
 
+!!! info "Estado al 28-sep (noche)"
+    Las correcciones de esquemático de esta auditoría **ya están aplicadas y verificadas** de forma independiente
+    (esquemático final `d58a89ba…`, ERC 0 errores; incluye los estrapes del paquete LFP-HT, igual que V5.6); falta el layout. Estado por hallazgo, decisiones y lista de trabajo:
+    [Plan de corrección y estado](v6-plan-correccion.md) · qué cambió en cada pasada:
+    [Cambios de esquemático — resumen de 3 pasadas](v6-cambios-resumen.md).
+
 Responsable: Leo (Helgen Technologies) · Fecha: 2026-09-28 · Versión: 1.0 · Autor: Helgen Technologies (elaborado con asistencia de Claude) · Alcance: auditoría de solo lectura de `03-Architecture-Hardware/kicad/hbox-watchdog-v6.*`; no se modificó ningún archivo de KiCad · Brief: `2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_Agent-Brief_v1.0.md` · Documento compañero: [Pin map MCU v6](v6-pinmap.md) · Lo que se aplicó de esta auditoría: [Informe de cambios al esquemático v6](v6-cambios-esquematico.md)
 
 **Snapshot del diseño (KiCad 10.0.4, versión de archivo de tarjeta 20260206).** Tarjeta: 4 capas, 140.0 × 100.0 mm, 312 huellas, 1999 segmentos de pista, 210 vías, 205/205 nets multi-pad ruteadas. Esquemático: una hoja plana, 328 símbolos en la netlist. Hashes de los archivos en el anexo de trazabilidad.

03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Ports-and-No-Respin_v1.0.md

@@ -0,0 +1,288 @@
+---
+title: "EinarBoard v6 — Puertos y sin nueva versión (pasada 2, inglés)"
+tags: [project-drogheda, hardware, hbox, v6, esquematico, ports]
+project: Project Drogheda
+author: Helgen Technologies
+date: 2026-09-28
+version: 1.0
+status: FINAL — pass 2 of 3 (ports / no new version)
+audience: Michelle (layout), Leo, ingenieros
+---
+
+# EinarBoard v6: ports end to end and the no-v6.1 close-out (v1.0)
+
+!!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide"
+    Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios.
+
+!!! info "Pass 2 of 3 — ports and no new version"
+    Spanish summary, final state per block and the combined layout delta:
+    **[EinarBoard v6 — Cambios de esquemático: resumen de las 3 pasadas](v6-cambios-resumen.md)**.
+    The final independent check ([pass 3](v6-revision-final.md)) passed this pass 26 / 27. The one FAIL was the
+    `IND-SMD_MWSA0804S` land in §4.3 and in L-53: the correct land is pads **2.75 × 5.5 mm at ±3.375 mm**
+    (gap 4.0 mm), courtyard **10.0 × 9.0 mm** (L-63). The schematic hash `f73f41a8…27ee` below was superseded by
+    `2b394ef9…5f33` (C176 added).
+
+
+**Date:** 2026-09-28 · **Board:** `kicad/hbox-watchdog-v6.*` (HBOX RTK, Helgen Technologies) · **Input state:** the schematic after the apply pass (sha256 `d54e330d…`, netlist `apply/netlists/05-final.xml`; a fresh export was identical) · **Author:** Claude (ports and no-respin pass) · **Rules:** edited in place, span-scoped S-expression splices with a UUID guard, `.kicad_pcb` not touched, no git, backups in `kicad/_to_delete/v6-ports-20260928/`.
+
+## Resumen (ES)
+
+Se revisó cada puerto de la v6 corregida, de extremo a extremo (conector → protección → pasivos → transceptor/PHY → pin de MCU o módem → periférico de firmware), contra hojas de datos. **Todos los puertos funcionan como están dibujados después de este pase.** Se encontraron y corrigieron en el esquemático seis defectos que habrían dejado un puerto débil o fallando:
+
+1. **RS-485:** el SP3485 sólo tiene ±2 kV HBM y fail-safe con entradas abiertas; además, con DE/RE̅ atados a RTS̅ del SC16IS752 (que queda en ALTO tras el reset), el transceptor **transmitía y bloqueaba el bus** durante el reset, en DFU o sin firmware. Se cambió U14 por **THVD1410DR** (mismo pinout, ±18 kV IEC, fail-safe con bus abierto, en corto o inactivo). Se añadió **U32 (inversor 74LVC1G04)**, así que el transceptor arranca en recepción. También se añadió **D39 SM712** en P11 y la opción de polarización R145/R146 (DNP).
+2. **RS-232:** el MAX3232 (sin especificación ESD) pasa a **TRS3232EIDR** (mismo pinout, ±8 kV IEC contacto).
+3. **Header TTL H4:** estaba en paralelo directo con la salida R1OUT del transceptor. Se añadió **R147 1 k**, así que un dispositivo TTL puede manejar RXB sin contienda.
+4. **Ethernet J10:** el LED amarillo (ACT) estaba **invertido** (pines 11/12), así que nunca encendía. El pin 8 (retorno del capacitor Bob-Smith de 1000 pF) estaba sin conectar; ahora va a GND.
+5. **SC16IS752:** las entradas CTSA̅/CTSB̅ estaban flotando; ahora van a GND.
+6. **Módem USB (J9):** se añadió **TP12 (1V8)** junto a TP8, para forzar el modo de descarga USB.
+
+USB-C (J9 y J11) ya estaba correcto: CC1/CC2 tenían 5.1 kΩ a GND, D+/D− iban en ambas filas y VBUS no retro-alimenta. No hubo cambios.
+
+Mapa I²C: **sin colisiones**. En el bus: SC7A20 0x18, PCF8574 0x20, SHT40 0x44, TMP102 0x48 y 0x49, SC16IS752 0x4D. Las direcciones posibles de los TMP102 (0x48–0x4B) no incluyen 0x4D.
+
+Cierre de «no v6.1»: **H-03 hecho** (nueva huella `IND-SMD_MWSA0804S` con la tierra recomendada por Sunlord, usada en L2/L6/L8/L20) y **B-13 hecho** (K1 DNP; enlace directo PC6 → DIN_4G con R148 0 Ω). TP1–TP8 salen del BOM y del CPL. Se añaden 14 puntos a la lista de Michelle (L-49…L-62) y se aceptan 20 ítems permanentemente, cada uno con su razón. El único riesgo aceptado a conciencia en la ruta de potencia es **A-10**: no hay protección de sobretensión en VEH5V. La opción OVP del LTC4040 mueve el divisor PFI y cambia la recuperación del modo respaldo, y no puede validarse sin banco. Cada grupo se probó con diff de netlist: **lo esperado coincide exactamente con lo obtenido**. ERC: **0 errores** (134 warnings, igual que antes). SHA-256 final del esquemático: `f73f41a8…27ee`.
+
+## 0. Summary
+
+| Item | Result |
+|---|---|
+| Ports traced | 24 (every J/P/H/SW/TP ref plus the internal modem, GNSS and I²C interfaces) |
+| Port verdicts | 17 ✅ as drawn · 7 🔧 fixed now (RS-485, RS-232, H4, SC16IS752 CTS, Ethernet LEDs + Bob-Smith, modem USB boot pad, modem UART B-13) · 📐 layout items on 11 ports · ⚙ firmware items on 14 ports |
+| USB-C CC | **J9 and J11 both correct:** Rcc1/Rcc2 and R100/R101 = 5.1 kΩ 1 % (C23186) CC→GND; D+ A6/B6 and D− A7/B7 tied; no VBUS back-feed |
+| I²C collisions | **None** (map in §3) |
+| Schematic groups | P1 ports · N1 no-respin · C1 cleanup: **8 parts added, 0 removed, 41 field changes, 8 pin-net changes, 0 net-class changes**. Each group: expected == actual; composed = total, 0 differences |
+| ERC (kicad-cli 10 via KiCad MCP) | 0 errors after every group; warnings 134 → 134 |
+| Overlaps / wire crossings | 30 → 30 / 9 → 9 (all pre-existing; none involve a new part) |
+| BOM | all 298 fitted real parts have an LCSC number (TP1–TP12 and JP1–JP6 are now out of the BOM/CPL; the PF* power flags are virtual) |
+| New library file | `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod` (sha256 `dbf53557…`) |
+| Untouched | `.kicad_pcb` `6ddec80d…`, `.kicad_pro` `d577aa43…`, `.kicad_dru` `31ce0f4f…` |
+| Michelle's list | +14: L-49 … L-62 (§5) |
+| Accepted permanently | 20 items (§7); done now: 17 (§8) |
+
+## 1. Port-by-port verification
+
+Legend: ✅ works as drawn · 🔧 fixed now (schematic) · 📐 layout item added (L-nn) · ⚙ firmware item (§6).
+Datasheets used: TI THVD1410, TI SN65HVD72, MaxLinear SP3485, ADI/Maxim MAX3222-MAX3241, TI TRS3232E, NXP SC16IS752/762, WIZnet W5500 v1.1.0, the KiCad `Connector:RJ45_Hanrun_HR911105A_Horizontal` symbol (drawn from the Hanrun HR911105A sheet; see §1.6), Semtech/Littelfuse SM712, ADI LTC4040 Rev B, Sunlord MWSA-S series spec, and AOS AO4264E. Pin and net evidence comes from `ports/netlists/final.xml` (= `03-cleanup.xml`).
+
+| # | Port | Chain (final) | Checks | Verdict | Evidence |
+|---|---|---|---|---|---|
+| 1 | **RS-485 (P11)** | P11.1 `/RS485_A`, P11.2 `/RS485_B`, P11.3 GND → **D39 SM712** (A/B → GND) · R82 120 Ω + JP5 (open) termination · R145/R146 390 Ω bias (DNP) → **U14 THVD1410DR** (6 A, 7 B, 8 VCC `/3V3` + C84, 5 GND) → 1 RO `/SER_RXA` → U10.4 RXA · 4 DI ← `/SER_TXA` U10.3 TXA · 2 RE̅ + 3 DE ← `/RS485_DE` ← **U32 74LVC1G04** ← `/SER_DEA` ← U10.1 RTSA̅ | A/B polarity: P11.1 = A = U14.6 ✅ · Pinout of THVD1410 D pkg = SP3485 (R, RE̅, DE, D, GND, A, B, VCC) ✅ · RTSA̅ is **HIGH after reset** (NXP DS). With the old direct tie, DE = 1 during reset, DFU and unflashed boards, so the node drove the bus (**bus hog**). U32 inverts it: receive at reset; auto-RS-485 with EFCR RTSCON=1, RTSINVER=0 ✅ · Fail-safe: SP3485 = open inputs only; THVD1410 = open, short and idle bus ✅ · ESD: SP3485 ±2 kV HBM only → THVD1410 ±18 kV IEC contact, ±30 kV HBM, EFT ±4 kV; surge by SM712 (−7/+12 V, 400 W 8/20 µs); THVD1410 bus abs max ±18 V ✅ · Termination by solder jumper (bus ends only) ✅ · 3.3 V supply, logic 3.3 V ✅ · Speed: THVD1410 500 kbps > SC16IS752 max 230.4 kBd at 3.6864 MHz ✅ | 🔧 📐 L-49/L-50/L-59 · ⚙ | `01-ports.xml`: `/RS485_DE` = {U14.2, U14.3, U32.4}; `/SER_DEA` = {U10.1, U32.2}; `/RS485_A` = {P11.1, U14.6, R82.1, D39.1, R145.2} |
+| 2 | **RS-232 (P12)** | P12.1 `/RS232_TX` ← U15.14 T1OUT · P12.2 `/RS232_RX` → U15.13 R1IN · P12.3 GND · **U15 TRS3232EIDR**: C85 C1± (1/3), C86 C2± (4/5), C87 V+ (2)→GND, C88 V− (6)→GND, all 100 nF; C89 100 nF VCC (16) `/3V3`; T1IN (11) ← `/SER_TXB` U10.23 TXB; R1OUT (12) → `/RS232_R1OUT` → **R147 1 k** → `/SER_RXB` U10.24 RXB; T2IN/R2IN → GND, T2OUT/R2OUT NC | Pinout identical to MAX3232 (1 C1+ … 16 VCC) ✅ · Pump caps 0.1 µF at 3.0–3.6 V per both datasheets ✅ · V+ cap to GND allowed ✅ · Unused TX input tied, RX input tied (5 kΩ internal) ✅ · Channel B of U10 ✅ · Direction: board TX on pin 1 (DTE-style, cross to the far end's RX) ✅ · ESD: MAX3232 (non-E) has **no ESD rating** → TRS3232E ±15 kV HBM, **±8 kV IEC contact**, ±15 kV air ✅ | 🔧 📐 L-51/L-59 · ⚙ | `/RS232_R1OUT` = {U15.12, R147.1} |
+| 3 | **TTL UART B (H4)** | H4.1 3V3, H4.2 `/SER_TXB` (U10.23 + U15.11), H4.3 `/SER_RXB` (U10.24 + R147.2), H4.4 GND | Before: H4.3 was hard-wired to U15 R1OUT, so an external TTL TX fought a CMOS output (R1OUT idles HIGH when R1IN is open). With R147: an external driver wins (≤ 3.3 mA, VIL ≈ 0.16 V with a 50 Ω driver); normal RS-232 RX delay 1 k × ~10 pF ≈ 10 ns ✅ · Use H4 **or** P12, not both at once | 🔧 · ⚙ | `/SER_RXB` = {U10.24, H4.3, R147.2} |
+| 4 | **SC16IS752 bridge (U10)** | I2C/SPI̅ (9) = `/3V3` → **I²C mode** · A0 (10), A1 (11) = GND → **0x9A = 7-bit 0x4D** · Y2 3.6864 MHz (C2238) + C82/C83 22 pF on XTAL1/2 (6/7) · IRQ̅ (15) open-drain → R81 10 k → `/3V3`, → U16.61 **PB8** · RESET̅ (5) → R80 10 k → `/3V3` (POR inside; no MCU control) · VDD (8) `/3V3` + C81 · ch A = RS-485, ch B = RS-232/H4 · CTSA̅ (2), CTSB̅ (16) → **GND** (were floating) · GPIO0–7 NC | Address table verified (A1=VSS, A0=VSS → 0x9A) ✅ · Crystal: divisors exact for 9600…230400 ✅ · IRQ̅ is open-drain and needs the pull-up; NXP quotes 1 k for fast edges, but 10 k only slows the de-assert edge (≈ 0.2 µs), which is fine for a level-read EXTI ✅ · POR exists, so R80 is enough; firmware issues IOControl.SRESET after every MCU reset ✅ · I²C max 400 kHz (the bus runs at 100 kHz, see #5) ✅ · Floating CTS inputs removed; GPIOs set to outputs in firmware | ✅ 🔧 (CTS) · 📐 L-57 · ⚙ | `03-cleanup.xml`: U10.2, U10.16 → GND |
+| 5 | **I²C1 bus** | PB6 SCL (U16.58) / PB7 SDA (U16.59), AF4; R30/R31 4.7 k to `/3V3`; U3, U10, U13, U26, U29, U31 | Map in §3: no collision ✅ · PCF8574T (C7605) is a **100 kHz** device, so the whole bus runs at 100 kHz · tr ≈ 0.85 × 4.7 k × ~80 pF ≈ 0.32 µs < 1 µs ✅ · sink 0.7 mA < 3 mA ✅ · ZED-F9P DDC (0x42) **not wired** (U18.44/45 NC), A7670 CI2C NC ✅ | ✅ · ⚙ | nets `/I2C_SCL`, `/I2C_SDA` |
+| 6 | **Ethernet (J10 + U11)** | U11 TXP/TXN (2/1) → J10.1 TD+ / J10.2 TD−, each 49.9 Ω (R92/R93) to `/3V3_ETH`, J10.4 TCT = `/3V3_ETH` · RXP/RXN (6/5) → J10.3 RD+ / J10.6 RD−, R94/R95 49.9 Ω to `/ETH_RCT` = J10.5 RCT + C97 6.8 nF → GND · J10.9 green A ← R96 330 Ω ← `/3V3_ETH`, J10.10 green K → U11.25 LINKLED · **J10.12 yellow A ← R97 330 Ω, J10.11 yellow K → U11.27 ACTLED** · **J10.8 → GND** · J10.7 NC · SH → GND · Y1 25 MHz HC-49 + C95/C96 33 pF · EXRES1 12.4 k 1 % · TOCAP 4.7 µF · 1V2O 10 nF · AVDD 100 nF ×6 + 10 µF/22 µF/100 µF · PMODE[2:0] = 111 via R84 (auto-neg) · RSVD23 → GND, RSVD38–42 NC · SPI2: CS̅ PB12, SCK PB13, MISO PB14, MOSI PB15 (AF5) · INT̅ PC0 · RST̅ PA15 + R140 4.7 k PD · 3V3_ETH from U12 MP1584EN, EN = `/ETH_PWR_EN` PD2 + R139 100 k PD | Terminations and centre taps = W5500 reference topology ✅ · LED polarity: the HR911105A symbol draws the yellow LED anode on pin 12 and cathode on pin 11; v6 had 11 = anode supply and 12 = W5500 ACTLED, so **ACT never lit** → swapped 🔧 · Pin 8 is the Bob-Smith 1000 pF return (symbol pin type power_in); it was NC with a flag, so the unused-pair termination floated (EMI/ESD) → GND 🔧 · Y1 load ≈ 19–20 pF for the CL 20 pF part ✅ · W5500 pin table: TOCAP 4.7 µF, 1V2O 10 nF, EXRES1 12.4 k, RSVD23 → GND, 38–42 NC ✅ · RSTn internal pull-up 62–112 k + PA15 JTDI pull-up vs 4.7 k → ≤ 0.66 V < VIL 0.8 V ✅ · MP1584 EN: 1 µA internal pull-up, 100 k → 0.1 V = off; PD2 3.3 V > 1.5 V = on ✅ · W5500 I/O 5 V-tolerant (no back-power through SPI/RST when 3V3_ETH is off) ✅ · J10 footprint `Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal` = part C12074 ✅ | 🔧 📐 L-52 · ⚙ | `01-ports.xml`: J10.8 GND; `/ETH_ACTLED` = {J10.11, U11.27}; `/ETH_ACT_A` = {J10.12, R97.1} |
+| 7 | **USB-C DFU (J11)** | GCT USB4085-GF-A (C7095263, USB 2.0 Type-C) · CC1 A5 → R100 5.1 k → GND, CC2 B5 → R101 5.1 k → GND · D+ A6+B6 `/DFU_DP` → D14 → U16.45 **PA12** · D− A7+B7 `/DFU_DM` → D15 → U16.44 **PA11** · VBUS A4/A9/B4/B9 `/DFU_VBUS` → D16 · → D13 SS34 → `/LDO_IN` (U17), OR-ed with D12 from SYS5V · SH → GND · BOOT0 = SW2 to 3V3 + R98 10 k PD; PB2 = R99 10 k PD; HSE Y3 25 MHz | Sink Rd on both CC ✅ · flip support ✅ · PA11/PA12 = OTG_FS DM/DP ✅ · VBUS back-feed: D12 blocks VBUS → SYS5V, D13 blocks the board → host; USB powers only the 3V3 domain ✅ · VBUS sensing is not needed (PA9 is TP9): ROM DFU on F411 runs without it; firmware disables it ✅ · PA10 idles high in DFU via Rdfu1 100 k (so the ROM USART1 detector sees no noise) ✅ · ESD D14–D16 PESD5V0S1BA (full speed tolerates their capacitance; V5.5 proven; routing fixed by L-42) ✅ | ✅ · 📐 L-42 (existing), L-58/L-59 · ⚙ | nets `/DFU_*` |
+| 8 | **USB-C modem (J9)** | USB4085 · CC1 A5 → Rcc1 5.1 k, CC2 B5 → Rcc2 5.1 k → GND · D+ A6+B6 `/USB_DP` → U30.3/4 → U19.27 · D− A7+B7 `/USB_DM` → U30.1/6 → U19.28 · VBUS → U30.5 + U19.24 (detect only; feeds no rail) · SH → GND · U19.6 USB_BOOT → TP8, **TP12 = `/1V8_MODEM`** beside it | Rd on both CC ✅ · both D rows tied ✅ · USBLC6-2SC6 (~3.5 pF) suits high speed ✅ · no back-feed path (VBUS only reaches the modem detect pin and the USBLC6 rail pin) ✅ · J9 works only while firmware keeps the modem powered ⚙ · forced download needs VDD_EXT on USB_BOOT at power-on: there was no 1.8 V pad beside TP8 → TP12 🔧 | ✅ 🔧 (TP12) · 📐 L-41/L-43 (existing), L-55/L-58/L-59 · ⚙ | `/1V8_MODEM` gains TP12 |
+| 9 | **P1 24 V + ignition** | DIBO DB128V-5.0-5P (C424683, 5.0 mm, 16 A) on `TerminalBlock_Phoenix_MKDS-1,5-5…Horizontal` · 1 `/24V_IN` → F2 3 A → `/VIN_FUSED` (D10, Q23) · 2 GND · 3 `/IGN_IN` → D35 SMBJ33A + Rig1 22 k → `/IGN_SENSE` (PA5 ADC, ratio 0.0833) · 4 GND · 5 NC | Apply-pass fixes V1-01/A-01/F-02 in place ✅ · pin numbering 1–5 = land 1–5 ✅ · 5.0 mm land fits a KF128-class block; confirm hole/pin and wire-entry side (L-62) | ✅ · 📐 L-62 | `/IGN_IN` = {P1.3, Rig1.1, D35.1} |
+| 10 | **P2 bench 5 V** | XH-2 (C158012) · 1 `/VEH5V`, 2 GND | Bench-only input; no reverse or over-voltage protection (A-10 and A-20c accepted, §7; silk per L-46) | ✅ (bench use) | — |
+| 11 | **P3 battery** | XH-3 (C144394) · 1 `/BAT_PLUS` (L6, U6.23), 2 GND, 3 `/NTC` (R55 10 k to VIN; U6.17; R137 tap → PC5) | 3 A/contact vs 1.4 A charge (R50 1.43 k), backup average 0.6–1 A, LTE-only peaks ≈ 2 A (D9) ✅ | ✅ (G-07 accepted) | — |
+| 12 | **P4 fan** | XH-2 · 1 `/5V_FAN` (= VEH5V via JP1 bridged), 2 `/FAN_RET` → Q2 AO3400A (PA6) + D2 flyback | ✅ | ✅ · ⚙ | — |
+| 13 | **P5 cut-off + JP6** | XH-2 · `/MAIN5V`–`/SYS5V`; JP6 open bypass | ✅ | ✅ | — |
+| 14 | **P6 external reset** | XH-2 · 1 `/NRST` (D36 PESD5V0S1BA, C104 100 nF, SW1, TP5, U16.7), 2 GND | ✅ (renumber hazard handled by silk, L-46) | ✅ | — |
+| 15 | **P7/P8 NTC probes** | XH-2 · `/NTC_TEMP` (R42 10 k to 3V3, C24, D37, PB1 ADC IN9) · `/NTC2` (R126, C157, D38, PC4 IN14) | ✅ | ✅ · ⚙ | — |
+| 16 | **P9 panel LED** | XH-2 · 1 `/LED_A` (R3 120 Ω from 3V3), 2 `/LED_K` → Q4 (PB0); on-board D1 in parallel | Works with a panel LED of Vf ≤ 2.2 V (it shares ≈ 11 mA with D1) | ✅ (usage rule) | — |
+| 17 | **P10 external RGB** | XH-4 · 1 3V3 (common anode), 2–4 cathodes via R89–R91 120 Ω → PCF8574 P4–P6 (sink) | Red about 11 mA; blue/green (Vf about 2.8–3.0 V at 3.3 V) run at a few mA, so they are dimmer. Functional | ✅ | — |
+| 18 | **J12 GNSS antenna** | U.FL (C88374) → `/RF_ANT_GNSS`: D27, C143 DC block → U18.2; bias L21 68 nH ← `/ANT_BIAS` ← U28 TPS2552 (75 mA limit, EN̅ = F9P ANT_OFF, FAULT̅ → PC2) | Apply-pass C-01 in place ✅ | ✅ · 📐 L-30/L-33 (existing) · ⚙ | — |
+| 19 | **J13 LTE antenna** | U.FL → `/RF_ANT_LTE`: D28 PESD0402-240, R118 0 Ω, C146/C147 DNP π → U19.60 | Apply-pass B-03 in place ✅ | ✅ · 📐 L-31 (existing) | — |
+| 20 | **J14 nano-SIM / U22 eSIM** | J14 (C2977286, pre-order) C1 `/SIMB_VDD` (C171) via R131 0 Ω; C2/C3/C7 via R132–R134 22 Ω; ESD D23–D25 on the modem side; U22 + R127–R130 DNP | ✅ (B-09 applied; ESD move per L-38) · SIM detect unused (USIM1_DET NC) | ✅ · ⚙ | — |
+| 21 | **SWD / test pads** | TP3 SWDIO (PA13), TP4 SWCLK (PA14), TP5 NRST, TP6 GND, TP7 3V3, TP9 PA9 TX | Complete SWD set, no connector (D-12) → pads grouped in one row (L-56) | ✅ · 📐 L-56 | — |
+| 22 | **SW1 reset / SW2 BOOT0** | SW1 NRST→GND; SW2 3V3→BOOT0 (R98 PD) | ✅ | ✅ | — |
+| 23 | **Modem UART (internal)** | PC6 USART6_TX → **R148 0 Ω** → `/DIN_4G` (R143 100 k PU) → U23 → modem RXD; modem TXD → U24 → `/DOUT_4G` → R106 1 k → PC7 and U27 → F9P RXD2 | K1 relay path removed (B-13, §4) 🔧 | 🔧 · 📐 L-54 · ⚙ | `/DIN_4G` ∋ R148.2; `/USART6_TX` = {U16.37, R148.1, K1.10 (DNP)} |
+| 24 | **GNSS UARTs (internal)** | USART2 PA2/PA3 ↔ F9P UART1; F9P TXD2 → PA10 (RX-only) + Rdfu1 PU | ✅ (unchanged; `/USART1_RX` no longer reaches K1's contact in practice, since K1 is DNP) | ✅ · ⚙ | — |
+
+### 1.6 Note on the HR911105A LED pin evidence
+The Hanrun PDF could not be read here (image-only on every mirror). The pin mapping comes from KiCad's official symbol `Connector:RJ45_Hanrun_HR911105A_Horizontal`, whose datasheet link points to the LCSC copy of the Hanrun drawing, and from the copy already embedded in the v6 sheet. Both draw the **yellow LED with its anode on pin 12 and cathode on pin 11**, and the **green LED with its anode on pin 9 and cathode on pin 10**. They also both type pin 8 as the power_in return of the 1000 pF Bob-Smith capacitor. The v6 wiring contradicted its own symbol drawing. The original designer's note said "G+/G−/Y+/Y− – VERIFY". Bench check on the first board: both LEDs light with the link up.
+
+## 2. Datasheet facts that decided the fixes
+
+| Part | Fact | Consequence |
+|---|---|---|
+| SP3485 (MaxLinear) | Fail-safe only for open inputs; ESD ±2 kV HBM; no IEC rating | Too weak for a cabled port on port machinery → THVD1410DR |
+| THVD1410 (TI) | SOIC-8 = R, RE̅, DE, D, GND, A, B, VCC; fail-safe open/short/idle; IEC contact ±18 kV, air ±25 kV, HBM ±30 kV; EFT ±4 kV; bus abs max ±18 V; 3–5.5 V; 500 kbps; DE 2 MΩ PD, RE̅ 2 MΩ PU; 100 nF decoupling | Drop-in on U14's land; C84 is its 100 nF |
+| SN74LVC1G04 DBV | 1 NC, 2 A, 3 GND, 4 Y, 5 VCC | U32 on `SOT-23-5` |
+| SC16IS752 (NXP) | A1=VSS, A0=VSS → 0x9A (0x4D) · RTSA̅/RTSB̅ = logic 1 after reset · EFCR[4] RTSCON, EFCR[5] RTSINVER · POR plus RESET̅ · IRQ̅ open-drain · I²C ≤ 400 kbit/s · GPIO inputs after reset | Inverter needed for receive-by-default; firmware SRESET and GPIO direction |
+| MAX3232 (non-E) | No ESD rating; 0.1 µF pump caps at 3.0–3.6 V | → TRS3232E |
+| TRS3232E (TI) | Same 16-pin order as MAX3232; ±15 kV HBM, ±8 kV IEC contact, ±15 kV air; 0.1 µF at 3.3 V | Drop-in on U15's narrow SOIC-16 land (H-01 fixed it in the apply pass) |
+| SM712 | 2 I/O pins + common pin 3; −7/+12 V standoff, 400 W 8/20 µs (Semtech SM712.TCT) | Standard RS-485 surge clamp; matches the THVD1410's ±18 V bus rating |
+| W5500 v1.1.0 | TOCAP 4.7 µF, 1V2O 10 nF, EXRES1 12.4 k 1 %; RSVD23 → GND, RSVD38–42 NC (internal pull-down); RSTn low ≥ 500 µs, internal pull-up; SCSn internal pull-up; 5 V-tolerant I/O; SPI guaranteed ≥ 33.3 MHz | Confirms the apply-pass values and the firmware sequence |
+| LTC4040 Rev B | OVP = MN1 in series VPWR→VIN with IGATE shared with MN2; 6.2 k to OVSNS; 6.1/6.4/6.7 V trip; IGATE pulled to GND in backup; recovery starts when the PFI comparator sees input power; PFI abs max = max(VIN, VBAT, VSYS) + 0.3 V | Why A-10 was **not** applied blind (§7) |
+| Sunlord MWSA-S spec Table 4-1 | MWSA0804S: A 8.2±0.3, B 8.8±0.4, C 3.8±0.2, D 1.4±0.3 (electrode width), E 5.0±0.3 (electrode length); recommended land I 2.75, J 4.0, H 5.5 (typ) | New footprint (§4) |
+
+## 3. I²C address map (I²C1, PB6/PB7, 4.7 k pull-ups to `/3V3`, run at 100 kHz)
+
+| 7-bit address | Device | Ref | Strap | Range the part can take |
+|---|---|---|---|---|
+| 0x18 | SC7A20 accelerometer (INT1 → PB9) | U26 | SDO/SA0 = GND, CS = VDD (I²C) | 0x18–0x19 |
+| 0x20 | PCF8574T I/O expander (battery gauge LEDs, RGB) | U13 | A0–A2 = GND (NXP PCF8574T/3, not the "A" version) | 0x20–0x27 |
+| 0x44 | SHT40-AD1B humidity/temperature | U3 | fixed | 0x44 |
+| 0x48 | TMP102 charger sensor | U29 | ADD0 = GND | 0x48–0x4B |
+| 0x49 | TMP102 modem-area sensor | U31 | ADD0 = V+ | 0x48–0x4B |
+| 0x4D | SC16IS752 dual UART | U10 | A1 = A0 = GND | 0x48–0x57 |
+| (0x42) | ZED-F9P DDC | U18 | **not connected** (pins 44/45 NC) | — |
+
+**No collisions.** Only the SC16IS752 range (0x48–0x57) overlaps the TMP102 range (0x48–0x4B). It sits at 0x4D, outside the four TMP102 values, so no TMP102 strap change can reach it. **No strap change needed.** Bus speed limit: PCF8574 = 100 kHz, so the bus runs at 100 kHz. At that speed the SC16IS752 moves about 10 kB/s in total, which is enough for Modbus RTU at ≤ 38.4 kBd on RS-485 plus RS-232 at ≤ 57.6 kBd (FIFO + IRQ).
+
+## 4. Schematic fixes applied, with proof
+
+Method: the apply-pass editor (`apply/tools/ops.py`: span-scoped splices on the original text, a UUID multiset guard, canonical KiCad node layout). Each group was written as its own script (`ports/tools/gP_ports.py`, `gN_norespin.py`, `gC_cosmetic.py`), with the expected change set written before commit. After each commit to the Mac (unique staged path each time, sha256 checked on the Mac afterwards) the netlist was exported with the KiCad MCP (kicad-cli), diffed semantically with `ndiff.py` and asserted; ERC and the overlap and wire-crossing checks ran after each group.
+
+### 4.1 Hashes
+
+| State | `hbox-watchdog-v6.kicad_sch` sha256 | Backup |
+|---|---|---|
+| Pre (apply-pass final) | `d54e330d189910afd58e18fc7cd498bdb3e6e5b7b3c4472b6cae7f95650b34c4` | `_to_delete/v6-ports-20260928/00-pre/` (+ pro, dru, pretty, old PDF), `01-ports/…pre` |
+| After P1 ports | `26f50aaa7dc7795dcc5aec12b1ed8d8c1a762c09c8d63b0190e36d1078679a0e` | `01-ports/…post`, `02-norespin/…pre` |
+| After N1 no-respin | `3aceff28ac2d91624c37216e2cb83a53f37503452288a86bd52331e211d413c1` | `02-norespin/…post`, `03-cleanup/…pre` |
+| **Final (after C1 cleanup)** | **`f73f41a878655896211b429c6f30d82f13d6e0b7eba78468a6bb0473de8a27ee`** | `03-cleanup/…post`; container `ports/hbox-watchdog-v6.kicad_sch.final` |
+| `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod` (new) | `dbf535570b133bcb05e6ee7861f06e62cb54d554520488650e0b3c5429d5a71f` | new file (nothing overwritten) |
+| Schematic PDF `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf` | `a2c94a49…` → `41241140201f8f19098b1e1c37d3b256b1b6d83df7d338e6204c0fdf0e7191b0` | old copy in `00-pre/`; new copy `ports/hbox-watchdog-v6-schematic.pdf` |
+
+### 4.2 Netlist proof (expected written before commit, asserted after)
+
+| Group | Netlists | Expected (added / removed / field / pin-net / class) | Actual | Result |
+|---|---|---|---|---|
+| P1 ports | `00-baseline` → `01-ports` | 7 / 0 / 11 / 6 / 0 | 7 / 0 / 11 / 6 / 0 | **MATCH** |
+| N1 no-respin | `01-ports` → `02-norespin` | 1 / 0 / 30 / 0 / 0 | 1 / 0 / 30 / 0 / 0 | **MATCH** |
+| C1 cleanup | `02-norespin` → `03-cleanup` | 0 / 0 / 2 / 2 / 0 | 0 / 0 / 2 / 2 / 0 | **MATCH** |
+| **Total** | `00-baseline` → `03-cleanup` | composition of P1+N1+C1 | 8 / 0 / 41 / 8 / 0 | **0 differences** (`ports/netlist_diff_total.md`) |
+
+The 8 pin-net changes: U14.2 and U14.3 `/SER_DEA` → `/RS485_DE`; U15.12 `/SER_RXB` → `/RS232_R1OUT`; J10.8 NC → GND; J10.11 `/ETH_ACT_A` → `/ETH_ACTLED`; J10.12 `/ETH_ACTLED` → `/ETH_ACT_A`; U10.2 and U10.16 NC → GND. No existing symbol changed its UUID (asserted per group). Netlists are in `kicad/_to_delete/v6-ports-20260928/netlists/` and `ports/netlists/` (`final.xml` = `03-cleanup.xml`, sha256 `a5555894…b5b3`).
+
+### 4.3 What changed
+
+| ID | Ref | Change | LCSC (verified: stock / package) |
+|---|---|---|---|
+| P-1 | U14 | SP3485EN (C8963) → **THVD1410DR**, TI; symbol `Interface_UART:SP3485EN` kept (identical pinout); value text `THVD1410` | **C2671345** (8 006 / SOIC-8; JLC "pre-ordered chips") |
+| P-1 | U14.2, U14.3 | `/SER_DEA` → new `/RS485_DE` | — |
+| P-1 | **U32** (new) | SN74LVC1G04DBVR, `74xGxx:74LVC1G04`, `Package_TO_SOT_SMD:SOT-23-5`: 2 `/SER_DEA`, 4 `/RS485_DE`, 5 `/3V3`, 3 GND, 1 NC | **C7827** (163 327 / SOT-23-5) |
+| P-1 | **C175** (new) | 100 nF 0603 at U32 | C14663 (Basic) |
+| P-1 | **D39** (new) | SM712.TCT, `Diode:SM712_SOT23`, `SOT-23`: 1 `/RS485_A`, 2 `/RS485_B`, 3 GND | **C12067** (49 238 / SOT-23) |
+| P-4 | **R145, R146** (new, **DNP**) | 390 Ω 0603: `/3V3`–`/RS485_A`, `/RS485_B`–GND (bias option) | C23151 (Basic, 311 280) |
+| P-2 | U15 | MAX3232ESE+T (C15846) → **TRS3232EIDR**, TI; symbol `Interface_UART:MAX3232` kept; value text `TRS3232E` | **C308878** (3 564 / SOIC-16 narrow) |
+| P-2 | U15.12 | `/SER_RXB` → new `/RS232_R1OUT` | — |
+| P-2 | **R147** (new) | 1 kΩ 0603: `/RS232_R1OUT` → `/SER_RXB` | C21190 (Basic, 39.8 M) |
+| P-3 | J10.11 / J10.12 | labels swapped: 11 = `/ETH_ACTLED` (yellow K), 12 = `/ETH_ACT_A` (yellow A) | — |
+| P-3 | J10.8 | NC flag → wire + GND label (Bob-Smith return) | — |
+| P-5 | **TP12** (new) | `TestPoint_Pad_D1.5mm` on `/1V8_MODEM`, excluded from BOM and CPL | no part |
+| C | U10.2, U10.16 | CTSA̅/CTSB̅ NC flags → GND | — |
+| H-03 | L2 (DNP), L6, L8, L20 | footprint `Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm` → **`Drogheda-v6:IND-SMD_MWSA0804S`** (parts unchanged: C17700171 / C17700165 / C17700171 / C17700167) | — |
+| B-13 | K1, Q6, D6, R40, R41 | → **DNP** (relay and its driver) | — |
+| B-13 | **R148** (new) | 0 Ω 0603: `/USART6_TX` → `/DIN_4G` (never together with K1) | C21189 (Basic, 13.9 M) |
+| J-05 | TP1–TP8 | `in_bom no`, `in_pos_files no` (copper pads, not parts) | — |
+| C | text notes | BLOCK M note (RS-485 direction and EFCR, H4 rule) and BLOCK P note (K1 DNP) updated | — |
+
+**New footprint `IND-SMD_MWSA0804S`** (KiCad 9/10 format, `Drogheda-v6.pretty`): two SMD round-rect pads 2.75 × 4.0 mm (rratio 0.1) at x = ±4.125 mm (inner gap 5.5 mm, outer extent ±5.5 mm); F.Fab body 8.2 × 8.8 mm; F.CrtYd 11.5 × 9.7 mm; silk lines at y = ±4.6 mm between the pads. The pad axis is the body's 8.2 mm A dimension, where the 1.4 mm electrodes sit (the inter-electrode gap of 8.2 − 2 × 1.4 = 5.4 mm matches H = 5.5). Each pad covers 1.35 of the 1.4 mm electrode depth, plus a 1.4 mm toe beyond the body, and 4.0 of the 5.0 mm electrode length. The electrode is now **≈ 77 % wetted plus a toe fillet**, against 55–64 % on the SRU8028 land. The audit's courtyard estimate (9.4 × 9.8 mm) left out the pad overhang; the true courtyard is 11.5 × 9.7 mm (L-53). The KiCad MCP cannot list project-local libraries, but the ERC footprint-link check passed with the new footprint (no `footprint_link_issues`).
+
+### 4.4 ERC (kicad-cli 10 via KiCad MCP)
+0 errors before and after every group; 134 warnings before and after (the same pin-type, library-mismatch and not-in-library families listed in the change report §5). The new symbols (74LVC1G04, SM712_SOT23) are embedded fresh from the KiCad 10 libraries; Device:R and TestPoint are existing cached symbols. Overlaps 30 → 30 and wire crossings 9 → 9: all pre-existing, none involving a new part. I checked the new clusters in the rendered PDF (crops of U10/U14/U32/D39, U15/R147/R145–146, J10, K1/R148, TP12).
+
+## 5. Additions to Michelle's layout list (continue after L-48)
+
+49\. **RS-485 direction (P-1):** U32 (SOT-23-5) + C175 within 5 mm of U14 pins 2/3; C175 ≤ 2 mm from U32.5; `/RS485_DE` ≤ 10 mm; `/SER_DEA` U10.1 → U32.2. C84 ≤ 2 mm from U14.8.
+
+50\. **RS-485 protection at P11 (P-1/P-4):** D39 SM712 ≤ 5 mm of copper from P11.1/P11.2, A/B routed flow-through (P11 → D39 pads → U14), D39.3 to GND with 2 vias ≤ 1 mm; R82 + JP5 beside P11 (termination at the bus end); R145/R146 (DNP 0603) beside P11. Route A/B as a pair (0.3 mm, gap ≤ 0.3 mm), ≥ 0.5 mm from other nets, nothing crossing on the adjacent layer.
+
+51\. **RS-232 / H4 (P-2):** R147 ≤ 3 mm from U15.12; H4.3 connects on the U10 side (`/SER_RXB`), not at U15. U15's pump caps C85–C88 ≤ 3 mm and its decoupler **C89** ≤ 2 mm from U15.16. Correction to L-37: C84 is U14's decoupler, not U15's.
+
+52\. **J10 (P-3):** pin 8 → GND with a ≥ 0.5 mm track to 2 GND vias placed **outside** the MAGJACK_NO_POUR keep-out (no pour under the magnetics). Re-route pins 11/12: J10.12 = `/ETH_ACT_A` (from R97), J10.11 = `/ETH_ACTLED` (to U11.27).
+
+53\. **MWSA0804S land on L2/L6/L8/L20 (H-03):** the footprint swaps to `Drogheda-v6:IND-SMD_MWSA0804S` on *Update PCB from Schematic*. Pads go from 2.0 × 3.2 mm at ±3.9 mm to 2.75 × 4.0 mm at ±4.125 mm; the courtyard is **11.5 × 9.7 mm** (+0.6 mm per side on the pad axis, +0.4–0.6 mm across). Re-check neighbours and keep L-11/L-21/L-22/L-23 distances measured to the new pads. Update only through the schematic sync, never with a global "update footprints from library" (L-45).
+
+54\. **B-13:** place R148 (0603) on the shortest path U16.37 (PC6) → U23.7 (`/DIN_4G`). K1, Q6, D6, R40, R41 are DNP; keep their footprints, with no copper change other than R148's two connections. Silk "K1 XOR R148".
+
+55\. **TP12 beside TP8** (2.54 mm centre spacing) so tweezers can bridge them; both reachable with the lid open.
+
+56\. **Debug pad row (D-12):** TP3 SWDIO, TP4 SWCLK, TP5 NRST, TP6 GND, TP7 3V3, TP9 PA9-TX in one straight row at 2.54 mm pitch, ≤ 30 mm of track from U16, silk labels. A 1×6 pogo clip or header can then be pressed on; no connector part needed.
+
+57\. **SC16IS752 (U10):** Y2 + C82/C83 ≤ 5 mm from U10.6/7, no inner-layer track under them (extends L-39 to Y2); C81 ≤ 2 mm from U10.8.
+
+58\. **USB-C CC resistors:** Rcc1/Rcc2 ≤ 5 mm from J9.A5/B5; R100/R101 ≤ 5 mm from J11.A5/B5.
+
+59\. **Port silkscreen (extends L-46):** P11 "RS-485 A+ B− GND"; P12 "RS-232 TX RX GND"; JP5 "TERM"; R145/R146 "BIAS DNP"; H4 "UART-B TTL 3V3 TX RX GND"; J9 "MODEM USB"; J11 "DFU"; TP8/TP12 "USB_BOOT / 1V8"; P2 "5 V ONLY, BENCH".
+
+60\. **Footprint attributes (J-05):** TP1–TP12 and JP1–JP6 set to SMD and "exclude from BOM/position files" on the board (matches the schematic now); then re-enable the DRC check `footprint_type_mismatch`.
+
+61\. **Fiducials:** three global fiducials (1.0 mm copper, 2.0 mm mask opening) on F.Cu at three corners (LGA U18/U19 and 0.5 mm-pitch parts). The audit listed them as "optional"; no v6.1 means fit them now.
+
+62\. **P1 check:** confirm that the DIBO DB128V-5.0-5P (C424683) pins fit the MKDS-1,5 land's holes (5.0 mm pitch) and that its wire entry faces the harness side of the enclosure. This is a check only; no change is expected.
+
+Order notes for the same pass: pre-order **THVD1410DR C2671345** (JLC pre-order category, like U21 C2862740 and J14 C2977286). P11 and P12 are **pluggable headers** (DEGSON 15EDGRC-3.5-03P): buy the mating plugs (15EDGK-3.5-03P, 2 per board) with the harness, since they are not in the board BOM.
+
+## 6. Firmware notes per port (FW 0.7.x, `board_v6.h`)
+
+1. **SC16IS752 (U10, I²C1 0x4D, 100 kHz):** `BOARD_SER_XTAL_HZ 3686400`; divisor = 3 686 400/(16·baud): 9600 → 24, 19 200 → 12, 38 400 → 6, 57 600 → 4, 115 200 → 2. After every MCU reset write IOControl.SRESET (bit 3), because RESET̅ has no MCU line. Enable the FIFOs. **IODir = 0xFF, IOState = 0x00** (GPIO0–7 as outputs, driven low: no floating inputs). IRQ̅ on **PB8** (EXTI8, falling, no internal pull; R81 is external): service RHR/THR/LSR until IIR says no interrupt pending. CTSA̅/CTSB̅ are tied low, so leave auto-CTS (EFR[7]) off.
+2. **RS-485 (channel A):** **EFCR = 0x10 (RTSCON = 1, RTSINVER = 0).** RTSA̅ goes LOW while transmitting, and U32 turns that into DE = 1; idle and reset leave the transceiver in receive. Never set RTSINVER (with U32 fitted it would invert the logic). Modbus RTU: time the 3.5-character gaps on the MCU; line turnaround is automatic after the last stop bit. Termination (JP5) and bias (R145/R146, DNP) are hardware options only.
+3. **RS-232 (channel B) and H4:** plain 8N1, no flow control. H4 and P12 share channel B: use one at a time. H4 pin 3 can be driven by a TTL device (R147).
+4. **Ethernet (U11, SPI2 PB13/PB14/PB15 AF5, CS̅ PB12 GPIO, INT̅ PC0, RST̅ PA15, power PD2):** at boot drive PA15 LOW and PD2 LOW before anything else. Power-up: SPI pins low → PD2 HIGH → wait ≥ 2 ms for 3V3_ETH → keep RST̅ LOW ≥ 500 µs → release → wait 1 ms (PLL) → SPI mode 0 at ≤ 21 MHz → check VERSIONR = 0x04 → PHYCFGR link. PC0 needs no pull; enable EXTI0 only while PD2 is HIGH. Off / battery: RST̅ LOW, SPI pins LOW or analog, PD2 LOW. LEDs are driven by the PHY (no firmware).
+5. **USB DFU (J11):** ROM DFU (BOOT0 button + NRST) needs HSE 25 MHz (Y3). In the application's USB CDC (u-center passthrough) on OTG_FS PA11/PA12, **disable VBUS sensing** (PA9 is the debug-TX pad, not VBUS).
+6. **Modem USB (J9):** J9 enumerates only while the modem is powered (PC10 MODEM_PWR_EN + PWRKEY sequence). Add a service command that holds the modem on for FOTA/debug. Forced download: short TP8–TP12 at modem power-on (hardware procedure, no firmware).
+7. **Modem UART:** USART6 PC6 TX now reaches the modem **directly through R148** (no K1): drop every BYP_CTRL/Mode-B relay step and keep **PB5 LOW** (driver DNP). PC7 RX via R106 1 k; 115 200 Bd. PC9 STATUS has a hardware pull-down.
+8. **I²C sensors:** 0x18 SC7A20 (INT1 → PB9, EXTI9); 0x20 PCF8574 (P0–P3 battery-gauge LEDs, P4–P6 RGB cathodes on P10, active LOW); 0x44 SHT40; 0x48 TMP102 charger (`tchg`); 0x49 TMP102 modem (`tmodem`). Keep I²C1 at **100 kHz** (PCF8574 limit). The SC7A20 WHO_AM_I read at 0x18 also serves as the v6 board identity check before any v6-only pin is driven (D-08, §7).
+9. **ADC ports:** PB1 IN9 (P7 NTC), PC4 IN14 (P8 NTC2), PC5 IN15 (pack NTC tap), PA5 IN5 ignition (ratio 0.0833), PA4 IN4 5 V sense; compute VDDA from VREFINT.
+10. **Other ports:** P4 fan on PA6 as GPIO on/off (TIM3 stays free for PPS); P9 panel LED on PB0 (Q4); P6 is a hardware reset (no firmware). SIM: no detect line (USIM1_DET NC), so keep SIM hot-swap detection disabled in the modem.
+
+## 7. Accepted permanently
+
+| # | ID | Item | Reason it is safe for the product's life |
+|---|---|---|---|
+| 1 | **A-10** | No over-voltage protection on VEH5V (TPS54360B high-side short, or > 6 V into P2) | It takes a component failure or bench misuse. The field input is the cabinet's regulated, current-limited 24 V (DDR-60G-24, D1), and F2 3 A caps the energy. The datasheet OVP option (MN1 + 6.2 k, sharing IGATE with Q7) also moves the PFI divider to the raw side and changes how backup mode recovers. A mistake there would break normal operation on every board, which is worse than the rare fault it guards against, and it cannot be validated without a bench cycle. P2 gets a "5 V ONLY, BENCH" silk label (L-59). |
+| 2 | D-08 | Board-ID strap | Decision D8: firmware-only. The v6 is identified at boot by the SC7A20 WHO_AM_I at 0x18 (v6-only part) and the F9P answering on USART2, before any v6-only pin is driven. Binary names carry the board (memory rule). PD2 is taken by ETH_PWR_EN and PA9 by the debug pad. |
+| 3 | E-06 (option) | Low-capacitance ESD array between the magjack and U11 | The HR911105A magnetics isolate the cable (1500 Vrms), the WIZnet reference design has no array, and the cabling stays inside the cabinet. J10.8 (Bob-Smith return) is fixed now. |
+| 4 | E-07 | PoE | Not a requirement (Leo: ports must work; no PoE mentioned). The recorded decision is an external splitter. |
+| 5 | A-20a | U12 MP1584EN → AP64350 | U12 is now PD2-gated (E-01), runs only on vehicle power and is proven on V5.5. A swap would need a new compensation/RT design and a different land, which adds risk for no functional gain. |
+| 6 | G-07 | P3 XH-3 → XH-5/VH | 3 A per contact vs 1.4 A charge (R50 1.43 k), 0.6–1 A backup average, and ≈ 2 A LTE-only peaks (D9). XH-3 keeps the fielded 1S4P packs compatible. |
+| 7 | G-06 | P2-only power back-feeds VEH5V → U25 body diode → P1.1 (≈ 4 V) | Benign; with A-01 the Q10/U2 branch is DNP, so nothing on `/24V` is powered. Documented for the bench procedure. |
+| 8 | F-14 (option) | One USBLC6 at J11 instead of D14–D16 | Full-speed USB tolerates the PESD5V0S1BA capacitance (proven on V5.5). The stub problem is solved by routing (L-42). |
+| 9 | G-08 (option) | 100 Ω series on NRST | D36 (PESD5V0S1BA) plus C104 100 nF already clamp and filter the P6 cable; a series R would split `/NRST` for no measurable gain. |
+| 10 | J-03 | Retype `unspecified` library pins | Cosmetic. The warnings were checked net by net (single drivers, no conflicts), pin types do not reach the netlist, BOM or PCB, and the 134-warning baseline is recorded, so a new warning is found by diffing against it. |
+| 11 | J-04 (re-link) | 10 "not found" symbols (+ TPS2552) not copied into a library | Cosmetic. The embedded copies make the schematic self-contained, and pin → pad → net was checked on 25 parts (H-09). Re-linking would change 11 lib_ids for zero electrical effect. |
+| 12 | B-09 (option) | ESD on `/SIM_VDD` (array) | The SIM is inserted once at installation inside the enclosure. Data, CLK and RST have D23–D25 (moved next to J14 by L-38), and VDD has C171 100 nF at J14. |
+| 13 | A-16 | Populate R124/R125 (U25 UVLO) | The board always sees the cabinet's regulated 24 V (D1), so the 4.3–5.8 V input dropout band is never reached in service. |
+| 14 | A-18 (+ R123 option) | U25 compensation | The datasheet example with ≥ 60° phase margin (audit estimate) needs no change; the 0.3 → 2.5 A step is part of bring-up. |
+| 15 | A-19 | ISO 16750-2 load dump | The cabinet DC-DC isolates the board from the alternator bus. SMCJ33A/SMBJ33A survive 36 V/60 min and ISO 7637 fast pulses; F2 opens behind them if a TVS ever shorts. |
+| 16 | A-20b | F1 3 A PPTC now protects only the F9P LDO branch | Harmless and not needed for protection; keeping it avoids a footprint change. |
+| 17 | C-05 (option) | C143 100 nF → 47 pF C0G DC block | 100 nF X7R 0402 is ESL-dominated at L1/L2 (≈ 3–4 Ω); insertion loss < 0.01 dB after a ≥ 25 dB antenna LNA. |
+| 18 | D-06 (option) | D5 BAT54 → BAT54S | verify_2: optional once the SMBJ33A (D35) sits at P1.3 (applied). |
+| 19 | A-03/A-04 (option) | R121/R122 at 0.1 % | 5.18–5.46 V at 1 % meets the LTC4040 VIN ≤ 5.5 V and the governor thresholds; no 0.1 % LCSC parts in the DB. |
+| 20 | A-13 (option) | CLPROG → ADC | No ADC pin is left (PC5 went to the pack NTC). CLPROG stays on TP1 for bench current measurement. |
+
+## 8. Done now
+
+| # | ID | What | Where |
+|---|---|---|---|
+| 1 | P-1 (new) | RS-485 transceiver → THVD1410DR (IEC ESD, fail-safe on open/short/idle bus) | Schematic (U14) |
+| 2 | P-1 (new) | Receive-by-default direction: U32 inverter + C175 | Schematic + L-49 |
+| 3 | P-1 (new) | RS-485 surge TVS D39 SM712 at P11 | Schematic + L-50 |
+| 4 | P-4 (new) | RS-485 bias option R145/R146 (DNP) | Schematic + L-50 |
+| 5 | P-2 (new) | RS-232 transceiver → TRS3232EIDR (IEC ESD) | Schematic (U15) |
+| 6 | P-2 (new) | H4 contention fixed: R147 1 k R1OUT → SER_RXB | Schematic + L-51 |
+| 7 | P-3 (new) | J10 yellow LED polarity (pins 11/12) | Schematic + L-52 |
+| 8 | P-3 / E-06 | J10.8 Bob-Smith return → GND | Schematic + L-52 |
+| 9 | P-5 (new) | TP12 1V8 pad for modem USB forced download | Schematic + L-55 |
+| 10 | C (new) | SC16IS752 CTSA̅/CTSB̅ tied to GND | Schematic |
+| 11 | **H-03** | MWSA0804S footprint per the Sunlord land; L2/L6/L8/L20 re-pointed | Library + schematic + L-53 |
+| 12 | **B-13** | K1 relay path removed: K1/Q6/D6/R40/R41 DNP, R148 0 Ω PC6 → DIN_4G | Schematic + L-54 |
+| 13 | J-05 / H-09 | TP1–TP8 out of the BOM and CPL | Schematic + L-60 |
+| 14 | D-12 (option) | SWD/debug access as one 2.54 mm pad row | L-56 |
+| 15 | FHJ note | Fiducials | L-61 |
+| 16 | L-37 (correction) | U15 decoupler is C89 (not C84) | L-51 |
+| 17 | C | Block notes and value texts updated (no overlap on U14/U15) | Schematic |
+
+Already closed by the apply pass and so not repeated here: every §7.1/§7.2 item, the D19 Minors, F-52 (modem TMP102 0x49), B-15, G-03, G-04, G-08 diodes, and J-04's flag and stub cleanup. Layout-only Minors and Notes (A-14, B-08, E-06 routing, F-14, F-17, F-18, G-05, J-02, C-09, D-15, F-21, A-20c silk) are in Michelle's L-1…L-48 list. Firmware-only Notes (B-14, B-16, C-08, D-13) are in the audit §8 and §6 above.
+
+## 9. Anything that would still stop a port from working
+None found in the schematic after this pass. Conditions that remain:
+
+- **Layout:** L-49…L-62, plus the existing L-30/31/33 (RF), L-41/42/43 (USB) and L-44 (Ethernet pairs), must be done. In particular, the new MWSA land (L-53) must be placed before routing the switchers.
+- **Order logistics:** pre-order THVD1410DR, U21 and J14; buy the P11/P12 mating plugs.
+- **Bench confirmation on the first board:** J10 LINK (green) and ACT (yellow) both light; RS-485 idles in receive during MCU reset and in DFU (DE low); an RS-485 loopback at 9 600 and 115 200 Bd with EFCR = 0x10; RS-232 loopback; an H4 TTL adapter drives RXB with RS-232 idle; J9 enumerates with the modem on, and download mode works with TP8–TP12 shorted.
+
+## 10. Files
+- This report: `/home/claude/v6audit/ports/2026-09-28_Drogheda_EinarBoard-v6_Ports-and-No-Respin_v1.0.md`
+- Final schematic copy: `ports/hbox-watchdog-v6.kicad_sch.final` (sha256 `f73f41a8…27ee`); PDF: `ports/hbox-watchdog-v6-schematic.pdf` and on the Mac `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf` (sha256 `41241140…91b0`)
+- Final netlist: `ports/netlists/final.xml` (= `03-cleanup.xml`); per-group diffs: `ports/out/{P1-ports,N1-norespin,C1-cleanup}/netlist_diff.md`; total: `ports/netlist_diff_total.md`
+- BOM: `ports/bom_final_ungrouped.csv` (also in `_to_delete/v6-ports-20260928/`)
+- Scripts: `ports/tools/` (`gP_ports.py`, `gN_norespin.py`, `gC_cosmetic.py`, `pcommon.py`, `q.py`); footprint source `ports/work/IND-SMD_MWSA0804S.kicad_mod`
+- Mac backups: `kicad/_to_delete/v6-ports-20260928/` (`00-pre/`, `01-ports/`, `02-norespin/`, `03-cleanup/`, `netlists/`, `scratch/`)
+- **Git (for Leo; nothing was run here):** in the `kicad` submodule commit `hbox-watchdog-v6.kicad_sch` and `Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod`, push to Gitea `HBox_PCB`, then bump the parent gitlink (`git -c diff.ignoreSubmodules=none commit …`). If KiCad is open on v6, close it **without saving** before Update PCB.

03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Schematic-Change-Report_v1.0.md

@@ -11,6 +11,11 @@ author: Helgen Technologies
 !!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide"
     Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios.
 
+!!! info "Este informe cubre solo la pasada 1"
+    Este informe cubre la **pasada 1** (correcciones de la auditoría). La **pasada 2** (puertos y sin nueva versión) y la
+    **pasada 3** (revisión final independiente), con el esquemático final `d58a89ba…` (tras la pasada 4: estrapes LFP-HT), están en
+    [Cambios de esquemático — resumen de 3 pasadas](v6-cambios-resumen.md).
+
 Fecha: 2026-09-28 · Proyecto: `kicad/hbox-watchdog-v6.*`, editado en su lugar (D17) · Implementa: [Auditoría completa v6](v6-auditoria-completa.md) §7.1 (Bloqueantes), §7.2 (Mayores), §7.3 Menores según D19, y las reglas de proyecto F-01 / D18 · Decisiones: `DECISIONS.md` D1–D19 (tomadas por delegación de Leo) · Autor: Helgen Technologies (elaborado con asistencia de Claude; ediciones por script sobre el texto S-expression con guarda de UUID; KiCad MCP solo para netlist, ERC, PDF, BOM, DRC y consultas de librería) · Estado: esquemático, reglas de proyecto y librería listos; **`hbox-watchdog-v6.kicad_pcb` no se tocó** (Michelle ejecuta *Update PCB from Schematic*, §10).
 
 Traducido del original en inglés (28-sep-2026).

03-Architecture-Hardware/2026-09-28_v6-audit-attachments/Delegated-Decisions_2026-09-28.md

@@ -0,0 +1,30 @@
+# Decisions for the v6 correction pass — taken by Claude on Leo's delegation (2026-09-28 17:20 CST)
+
+Leo: "if a change can be done at the schematic level we should do that — make the best decisions for me".
+IDs refer to `/home/claude/v6audit/report/2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md` (§5 ranked list, §6 layout list, §7 schematic change list, §8 firmware). Verification files: `findings/verify_1.md`, `findings/verify_2.md`.
+
+| # | Question (report §10) | Decision | Why |
+|---|---|---|---|
+| D1 | Supply context | HBOX input = the cabinet's **regulated 24 V** (Mean Well DDR-60G-24), per the project hard constraint; the board keeps its 9–36 V margin. Ignition = **raw machine ignition, 12 V and 24 V machines** (ICAVE: RTG / Reach Stacker / Empty Handler 24 V; Tractoplana / Montacargas 12 V). | CLAUDE.md §1c + §4 |
+| D2 | Modem supply topology (A-01, B-01, V1-01) | Adopt the verified topology: **U20 fed from `/MAIN5V` only**; D20 and D21 removed (direct connection MAIN5V → U20 VIN); **fan from `/VEH5V`** (U2 fan-buck block DNP, JP1 bridged); the **Q10 `/24V` branch DNP** once it has no loads; **F2 = 3 A (C206912), electrically ahead of D10**. Prerequisites in the same pass: A-04, A-05 (CSYS + 2×47 µF), U20 input caps (2×22 µF + 220 µF), B-02 loop values. | Removes the D21 failure mode and the unfused branch with fewer parts; verify_1 checked U25 ≤ 2.95 A |
+| D3 | R50 | **1.43 kΩ (C22840)**: ≥ 1.3 A at every corner, below the 2.5 A limit | A-03 verified |
+| D4 | U25 set-point | **R121 = 57.6 k (C23082)** → 5.18/5.32/5.46 V; firmware `V5_PFI` → 4.40 V | A-04 |
+| D5 | LTE antenna ESD | **Fit PESD0402-240 (C1975527)** on an 0402 land (keep protection; the antenna cable leaves the box) | B-03 verified |
+| D6 | GNSS antenna bias | **TPS2552DBVR (C46506)**, ILIM→IN (75 mA), ANT_OFF→EN̅, FAULT̅→ANT_SHORT_N | C-01 |
+| D7 | Charger temperature | "Sensor ≤ 10 mm of U6" is **binding**: implement F-51 fully (TMP102 C99269 @0x48 beside U6 + pack-NTC tap to PC5: 100 k C25803 / 120 k C25808 / 10 nF C1589) | R4; lesson F5 |
+| D8 | PD2 | **PD2 = ETH_PWR_EN** (E-01, U12 enable + 100 k pull-down). Board ID = firmware-only (probe the F9P / RTK_STAT behaviour at boot, D-08); PA9 stays the debug-TX pad (D-12) | Hardware power gating beats a strap; ID can be detected |
+| D9 | Battery mode | **LTE-only on battery** (`AT+CNMP=38`); **Ethernet off on battery** | A-05, B-16 |
+| D10 | J10 / P11 / P12 | **Populated** (Ethernet + RS-485/RS-232 are v6 features, EinarBoard 1.1 decisions). Schematic footprints corrected to the ordered parts (P11/P12 right-angle = the PCB's Horizontal footprint; J10 to a library nickname that exists). Michelle clears the PCB DNP flags | G-03 / H-06 |
+| D11 | Enclosure | v6 must fit the **existing V5.5 backplate / standoffs** (v6 brief: "no enclosure rework") → **G-01 = Blocker**: restore V5.5 MH4 and the heatsink-clamp holes (MH11 + partner); L6 moves anyway with A-02 | G-01 |
+| D12 | Fab stackup | **JLC04161H-7628 with impedance control, ENIG, 1 oz inner copper** (and still widen inner power runs per A-07) | F-06, A-07, J-02 |
+| D13 | BOM tool | **Fabrication Toolkit** → delete `LCSC Part` from U25's footprint in `Drogheda-v6.pretty` and on the board | H-04 |
+| D14 | Order quantity | **20 prototypes first**; re-check stock on order day; pre-order J14 (and U18/U19 if going to 100) | H-02, H-02b |
+| D15 | Firmware | Report §8 → **FW 0.7.x `board_v6.h`**; not part of this pass | — |
+| D16 | Minors | Schematic-only value/field Minors from §7.3 are applied **when trivially safe**; the rest go to the layout list or v6.1 | — |
+| D17 | Where to edit | **In place** in `hbox-watchdog-v6.*` (Leo's rule 28-Sep 20:20: iterations of a board are edited in place; old state recoverable from git). Pre-change copies in `kicad/_to_delete/v6-apply-20260928/`. The `.kicad_pcb` is **not** touched (Michelle's file); she runs Update PCB from Schematic | preferences |
+| D18 | Netclasses / DRC rules (F-01) | Applied now in `.kicad_pro` (netclass patterns, RF + PWR_MODEM classes) and `.kicad_dru` (verify_2's corrected rules), so DRC becomes the release gate | F-01 |
+
+## D19 — Scope of the schematic pass (report §7)
+- **All of §7.1 (Blockers) and §7.2 (Majors)** that touch the schematic/project, exactly as listed, with the D-decisions above. G-01 is layout-only (Michelle).
+- **§7.3 Minors applied** (schematic-only, low risk): A-11 (R56 → pull-up, charger OFF by default = safe state), A-13 (PFO → PB10 + 100 k), B-09 (22 Ω + 100 nF), B-10 (pulls + R106 → 1 k), C-07 (test pads), D-02 (Y3 → 3225 C2901684 + 12 pF; Michelle places it ≤ 5 mm from the MCU), D-03 (Y4 CL 7 pF + 6.8 pF), D-05 (Rigb1 → 2.2 k; firmware reads ignition on the ADC), D-09, D-12 (TP9), E-03 (**keep Y1, C95/C96 → 33 pF C1663**; no footprint change), E-04, **F-52 (modem TMP102 at 0x49)**, G-03 (footprints per D10, populated), G-04 (JP_CUT), G-08 (3× ESD), H-08 (value texts), J-04 (orphan NC flags, NC-on-connected flags, wire stubs; re-link missing symbols only if straightforward), B-15 (R107/R108 DNP + "never fit").
+- **§7.3 NOT applied** (→ v6.1 or layout): D-08 (board-ID strap; decided firmware-only), H-03 (MWSA0804S footprint: no land drawing available; V5.5 same pairing works), J-03 (library-wide pin types; cosmetic).

03-Architecture-Hardware/2026-09-28_v6-audit-attachments/Schematic-Change-Report_pass1_EN-original.md

@@ -0,0 +1,419 @@
+# EinarBoard v6 — Schematic change report (v1.0)
+
+**Date:** 2026-09-28 · **Project:** `kicad/hbox-watchdog-v6.*`, edited in place (D17) · **Implements:** `2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md` §7.1 (Blockers), §7.2 (Majors), §7.3 Minors per D19, and F-01 / D18 project rules · **Decisions:** `DECISIONS.md` D1–D19 (taken on Leo's delegation) · **Author:** Claude (scripted span-scoped S-expression edits with a UUID guard; KiCad MCP used only for netlist, ERC, PDF, BOM, DRC, library lookups and a scratch file) · **Status:** schematic, project rules and library done; **`hbox-watchdog-v6.kicad_pcb` not touched** (Michelle runs *Update PCB from Schematic*, §10).
+
+## Resumen (ES)
+
+Se aplicaron al esquemático de v6 todos los Blockers y Majors de la auditoría que son de esquemático, y los Minors de la lista D19. El módem (U20) ahora se alimenta sólo de MAIN5V (D20/D21 eliminados), el ventilador sale de VEH5V (bloque U2 y rama Q10 en DNP) y F2 (3 A) queda antes de D10. Se añadieron limitador de antena GNSS (TPS2552), TVS en ignición, sensores TMP102 del cargador (0x48) y del módem (0x49), buffer U27 hacia el F9P, ESD en J9 y en P6/P7/P8, y se corrigieron valores (R50 1.43 k, R121 57.6 k, compensación de U20, cristales). Cada grupo se comprobó con un diff de netlist: **lo esperado coincide exactamente con lo obtenido** (137 cambios de componentes/campos/pines + 16 cambios de clase de red). ERC: **0 errores** (166 → 134 warnings, todos explicados). El PCB no se tocó; Michelle debe ejecutar *Update PCB* marcando «Delete footprints with no symbols».
+
+## 0. Summary
+
+| Item | Result |
+|---|---|
+| Files edited in place | `hbox-watchdog-v6.kicad_sch`, `hbox-watchdog-v6.kicad_pro` (net classes only), `hbox-watchdog-v6.kicad_dru`, `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` |
+| `hbox-watchdog-v6.kicad_pcb` | **Byte-identical** (sha256 `6ddec80d…` before and after) |
+| Changes applied | Group 1 Blockers: 10 finding IDs · Group 2 Majors: 13 · Group 3 Minors: 19 (D19 list) · Group 4 rules/library: F-01, H-04 |
+| Parts | **37 added** (U27–U31, R135–R144, C161–C174, D35–D38, TP9–TP11, JP6), **3 removed** (D20, D21, PWR_FLAG PF15), **17 set DNP**, 1 symbol swapped (Y3 → `Device:Crystal_GND24`) |
+| Netlist proof | Every group: expected == actual (0 unexpected, 0 missing). Baseline → final: 37 added / 3 removed / 125 field / 22 pin-net / 16 net-class changes; composed group expectations = final netlist with **0 differences** (`netlist_diff_total.md`) |
+| ERC (kicad-cli 10.0.4) | **0 errors** before and after · warnings 166 → 134 (§5) |
+| Overlaps / wire crossings | 30 → 30 overlaps (all pre-existing bbox hits) · 8 → 9 wire crossings (+1 is a tool bbox artefact on U30, checked in the PDF) |
+| BOM | Every populated part has an LCSC number except the pre-existing copper pads TP1–TP8 (unchanged). New pads TP9–TP11 and JP6 are excluded from the BOM |
+| PDF | `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf` (sha256 `a2c94a49…`) |
+
+## 1. Hashes
+
+| File | Before | After |
+|---|---|---|
+| `hbox-watchdog-v6.kicad_sch` | `ecee9fed851f02e74074340bf8361bced7c385b2502b19c368861b9851c2f04a` | `d54e330d189910afd58e18fc7cd498bdb3e6e5b7b3c4472b6cae7f95650b34c4` |
+| `hbox-watchdog-v6.kicad_pro` | `25c57f3936b96a4e31cb5947668c172d318189258d6a5d2fa34d230df8958028` | `d577aa43076f5f751c291041dbf3054cb93a87facfe9f339ef91b60e073bd6ce` |
+| `hbox-watchdog-v6.kicad_dru` | `47538e6cfadc0c53421ff59dadabc0e7f0ad5f11d9e2250618728788080aca1a` | `31ce0f4f23e8178b4b5e837b452e7bb8647d446ffd420559049eaaae78100831` |
+| `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` | `0171be85ff9bf1d27232731a9931ad9d6c3c2bcdee2f5f3558ee94d2566413f9` | `3f38f26e435c477a7701636d4d5e1c05b4c7bd523e8dd04f9f57128657736313` |
+| `hbox-watchdog-v6.kicad_pcb` | `6ddec80d1c15f79e69dff6c1a850b28345a5d826389f79cee8c61998240b36bf` | unchanged |
+
+Pre-flight: sch and pro hashes matched the audit baseline; no `~hbox-watchdog-v6.*.lck` (only the v5 locks exist). No git was run in the mounted folder.
+
+## 2. Changes by finding
+
+Method: every edit is a splice on the original text, scoped to one S-expression node (property value, flag atom, label name, wire point, or a whole node for deletions). Before writing, a guard compares the multiset of UUIDs: no pre-existing UUID may disappear or change except for deliberately deleted items, and no new duplicates may appear. All untouched bytes stay identical. New symbols, wires and labels are written in KiCad's canonical layout; each new part is wired with a 2.54 mm wire to a local label carrying the exact existing net name (local `GND` labels as in the rest of the sheet). The only non-standard library symbol is TPS2552 (§7).
+
+### 2.1 Blockers (§7.1)
+
+| Finding | Ref | From → To | LCSC | Pins / nets |
+|---|---|---|---|---|
+| A-01 | D20 | SS34 (C8678) → **removed** | — | its labels `VIN_MODEM` (K) and `24V` (A) deleted |
+| A-01 | D21 | PMEG3050EP (C50603) → **removed** | — | its labels `VIN_MODEM` (K) and `MAIN5V` (A) deleted |
+| A-01 | PF15 | PWR_FLAG on `/VIN_MODEM` → **removed** with its label | — | the net no longer exists; PF2 already flags `/MAIN5V` |
+| A-01 | U20.2, C127.1, C128.1 | `/VIN_MODEM` → **`/MAIN5V`** (labels renamed) | — | no `VIN_MODEM` label remains (6 of 6 handled) |
+| A-01 | U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21 | fitted → **DNP** | unchanged | fan now from `/VEH5V` via JP1 |
+| A-01 | JP1 | `…SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm` → **`Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`** | no part | `/5V_FAN` = `/VEH5V` in copper (net-tie footprint) |
+| A-01 | Q10, DzG1, Rrp1, C10, C11, C22 | fitted → **DNP** | unchanged | `/24V` loads checked first: {C10, C11, C22, D20, DzG1, Q10, Ren1, U2} + virtual PF6 → nothing left fitted |
+| A-01 + V1-01 | F2 | `2A/125V-NANO2-in-holder` C206910 → **`3A/125V-NANO2-in-holder`**, MPN 0154003.DR, Littelfuse; same holder footprint | **C206912** | P1.1 → F2 → `/VIN_FUSED` |
+| V1-01 | D10 | pin 1 on `/24V_IN` → **`/VIN_FUSED`** | C224019 (unchanged) | `/VIN_FUSED` = {F2.2, D10.1, Q23.2}; topology in §8 |
+| A-03 | R50 | 825R/1% C50214 → **1.43k/1%** | **C22840** | 1.316–1.483 A |
+| B-03 | D28 | ESD9L5.0ST5G C82326, SOD-923 → **PESD0402-240**, `Diode_SMD:D_0402_1005Metric`, Littelfuse | **C1975527** | pin 1 `/RF_ANT_LTE`, pin 2 GND (symbol kept; pins 1/2 map to the 0402 pads) |
+| C-01 | **U28 (new)** | TPS2552DBVR, SOT-23-6 | **C46506** | 1 IN `/3V3_GNSS` · 2 GND · 3 ~EN `/GNSS_ANT_OFF` · 4 ~FAULT `/GNSS_ANT_SHORT_N` · 5 ILIM `/3V3_GNSS` (75 mA) · 6 OUT **`/ANT_BIAS`** |
+| C-01 | **R135 (new)** | 100k, ~EN → GND (antenna ON by default) | C25803 | `/GNSS_ANT_OFF` – GND |
+| C-01 | **R136 (new)** | 10k, FAULT pull-up | C25804 | `/3V3_GNSS` – `/GNSS_ANT_SHORT_N` |
+| C-01 | L21.2, C144.1, C145.1 | `/VCC_RF_GNSS` → **`/ANT_BIAS`** | unchanged | |
+| C-01 | U18.7 VCC_RF | `/VCC_RF_GNSS` → **NC** (label deleted, no-connect flag added) | — | |
+| C-01 | U18.5 ANT_OFF | NC flag → label **`/GNSS_ANT_OFF`** | — | |
+| F-02 | **D35 (new)** | SMBJ33A, `Diode_SMD:D_SMB` (same symbol as D10) | **C224019** | 1 (cathode) `/IGN_IN`, 2 GND; place at P1.3 |
+| F-02 | Rig1 | unchanged (22k C88614); move to P1.3 is layout | — | `/IGN_IN` = {P1.3, Rig1.1, D35.1} |
+| H-01 | U15 | `Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm` → **`Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`** | C15846 (unchanged) | |
+| H-02 | U10 | C729142 (SC16IS762) → **C57156**, MPN SC16IS752IPW,128 (value already SC16IS752IPW; symbol kept) | **C57156** | pinout identical |
+| H-02 | R53 | 499k/1% C131054 → same value, MPN RCT03499KFLF, HKR | **C177479** | |
+| H-04 | U25 | no `LCSC Part` in the schematic symbol; the field comes from the library footprint → removed there (§7) | C524806 | |
+| F-01 | project | net classes + `.kicad_dru` (§6) | — | |
+| G-01 | MH4 + heatsink pair | **not applied** — board-only (§10) | — | |
+
+### 2.2 Majors (§7.2)
+
+| Finding | Ref | From → To | LCSC | Pins / nets |
+|---|---|---|---|---|
+| A-04 | R121 | 53.6k/1% C23074 → **57.6k/1%** | **C23082** | U25 5.18/5.32/5.46 V |
+| A-05 | **C161, C162 (new)** | 47uF X7R 1210 | **C5440143** | `/MAIN5V` – GND (at U6 VSYS 1/24) |
+| A-08 | U17 | AMS1117-3.3 C6186 → **TLV1117LV33DCYR** (TI); symbol `Regulator_Linear:AMS1117-3.3` kept (same 1 GND / 2 OUT / 3 IN, tab = OUT) | **C15578** | pins unchanged |
+| A-09 | C78 | 220uF/10V MVG C2827940 → **220uF/16V polymer**, Lelon OVZ221M1CTR-0608, same CP_Elec_6.3x7.7 | **C881921** | pin 1 `/VEH5V` = + pad |
+| B-02 | C130, C131 | same as C78 → **220uF/16V polymer** | **C881921** | |
+| B-02 | R116 | 14k C22803 → **113k/1%** | **C22862** | |
+| B-02 | C141 | 3.3nF C1536 → **6.8nF** X7R 0402 | **C1542** | |
+| B-02 | C142 | 47pF C1567 → **56pF** C0G 0402 | **C1572** | |
+| B-02 | **C166, C167 (new)** | 22uF 16 V X5R 0805 | **C86817** | `/VBAT_MODEM` – GND (at L20.2) |
+| F-03 | **C163, C164 (new)** | 22uF 16 V 0805 | **C86817** | `/MAIN5V` – GND (at U20.2) |
+| F-03 | **C165 (new)** | 220uF/16V polymer, `Device:C_Polarized`, CP_Elec_6.3x7.7 | **C881921** | 1 (+) `/MAIN5V`, 2 GND |
+| F-51 | **U29 (new)** | TMP102AIDRLR, SOT-563, **I²C 0x48** | **C99269** | 1 SCL `/I2C_SCL` · 2 GND · 3 ALERT NC · 4 ADD0 GND · 5 V+ `/3V3` · 6 SDA `/I2C_SDA` |
+| F-51 | **C168 (new)** | 100nF 0603 | C14663 | `/3V3` – GND |
+| F-51 | **R137 / R138 / C169 (new)** | 100k/1% top · 120k/1% bottom · 10nF 0603 | C25803 · **C25808** · C1589 | `/NTC` → R137 → **`/NTC_CELL`** → R138/C169 → GND |
+| F-51 | U16.25 PC5 | NC flag → label **`/NTC_CELL`** (ADC1_IN15) | — | |
+| C-02 | U21 | AP2112K-3.3 C51118 → **TPS7A2033PDBVR** (TI); symbol `Drogheda-sym:LDO_SOT23-5` kept (its generic 1 VIN / 2 GND / 3 EN / 4 NC / 5 VOUT pinout is the TPS7A20 DBV pinout) | **C2862740** | pins unchanged |
+| E-01 | U12.2 EN | `/SYS5V` → **`/ETH_PWR_EN`** (label renamed; U12.7 VIN stays on `/SYS5V`) | — | |
+| E-01 | U16.54 PD2 | NC flag → label **`/ETH_PWR_EN`** | — | |
+| E-01 | **R139 (new)** | 100k PD | C25803 | `/ETH_PWR_EN` – GND |
+| E-02 | **R140 (new)** | 4.7k | **C23162** | `/ETH_RST` – GND (at U11.37) |
+| D-01 | **U27 (new)** | 74LVC1G125GV,125 (Nexperia), SOT-753 on `Package_TO_SOT_SMD:SOT-23-5` (same SC-74A land) | **C12518** | 1 ~OE GND · 2 A `/DOUT_4G` · 3 GND · 4 Y **`/DOUT_4G_F9P`** · 5 VCC `/3V3_GNSS` |
+| D-01 | **C170 (new)** | 100nF 0603 | C14663 | `/3V3_GNSS` – GND |
+| D-01 | U18.26 RXD2 | `/DOUT_4G` → **`/DOUT_4G_F9P`** | — | PC7/R106 stay on `/DOUT_4G` |
+| D-01 | Rdfu1 | 22k C88614 → **100k** | **C25803** | |
+| G-02 | **U30 (new)** | USBLC6-2SC6, SOT-23-6 | **C7519** | 1,6 `/USB_DM` · 3,4 `/USB_DP` · 5 `/USB_VBUS` · 2 GND |
+| H-02b | R56, R57, R58, R85, R87, Rgs1 | C103211 (100k 5 %) → **C25803** (100k 1 %) | **C25803** | value text kept `100k`. R20/Ren1/Rfreq1 not changed (U2 block is DNP) |
+| V1-01, F-12, F-05, F-06, C-04, A-07, A-02 | — | layout-only → §10 | | |
+
+### 2.3 Minors (D19 list)
+
+| Finding | Ref | From → To | LCSC | Pins / nets |
+|---|---|---|---|---|
+| A-11 | R56.2 | GND → **`/3V3`** (label renamed): CHGOFF pulled up → charger **OFF** without MCU | C25803 | |
+| A-13 | U6.20, TP2.1 | `/PFO_TP` → **`/PFO`** (labels renamed) | — | |
+| A-13 | U16.29 PB10 | NC flag → label **`/PFO`** | — | |
+| A-13 | **R141 (new)** | 100k PU | C25803 | `/3V3` – `/PFO` |
+| B-09 | R132, R133, R134 | 0R C304185 → **22R** | **C23345** | R131 (VDD) stays 0R |
+| B-09 | **C171 (new)** | 100nF 0402 at J14.C1 | **C1525** | **`/SIMB_VDD`** – GND (J14.C1 is on `/SIMB_VDD`, after R131; the report's "(`/SIM_VDD`)" names the modem side) |
+| B-10 | **R142 (new)** | 100k PD | C25803 | `/MODEM_STATUS` – GND |
+| B-10 | **R143 (new)** | 100k PU | C25803 | `/3V3` – `/DIN_4G` |
+| B-10 | R106 | 100R C22775 → **1k** | **C14676** | |
+| C-07 | U18.50 SAFEBOOT_N | NC flag → label **`/GNSS_SAFEBOOT_N`** | — | |
+| C-07 | **TP10, TP11 (new)** | `TestPoint:TestPoint_Pad_D1.0mm`, not in BOM | no part | TP10 `/GNSS_SAFEBOOT_N`, TP11 `/GNSS_RESET_N` |
+| D-02 | Y3 | `Device:Crystal` HC-49SD C14872 → **`Device:Crystal_GND24`**, `Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm`, SCTF SX3B25.000F1010F30 (25 MHz, CL 10 pF, ESR 30 Ω) | **C2901684** | pin 1 `/HSE_IN` · **pin 3 `/HSE_OUT`** · pins 2/4 **GND** (new wire + GND label). Symbol swap needed: a 2-pin symbol on the 4-pad land would have put HSE_OUT on GND pad 2. New pin 3 sits exactly where old pin 2 was, so the `HSE_OUT` label connects unchanged |
+| D-02 | C113, C114 | 15pF C1644 → **12pF** C0G | **C38523** | |
+| D-03 | Y4 | FC-135 CL 12.5 pF C32346 → **FC-135 CL 7 pF** (Epson Q13FC13500002; 7 pF confirmed on distributor listings) | **C48615** | footprint unchanged |
+| D-03 | C115, C116 | 12pF C38523 → **6.8pF** C0G | **C1679** | |
+| D-05 | Rigb1 | 3.3k C22978 → **2.2k** | **C4190** | ratio 0.0833 |
+| D-09 | **R144 (new)** | 100k PD at Q5 base | C25803 | `/BASE_LS` – GND |
+| D-12 | U16.42 PA9 | NC flag → label **`/USART1_TX`** | — | |
+| D-12 | **TP9 (new)** | `TestPoint:TestPoint_Pad_D1.5mm`, not in BOM | no part | `/USART1_TX` |
+| E-03 | C95, C96 | 18pF C1647 → **33pF** C0G (Y1 kept) | **C1663** | |
+| E-04 | C91 | 4.7uF C1779 0805 → **10nF** X7R, `C_0603_1608Metric` | **C1589** | `/ETH_1V2` |
+| E-04 | C90 | 10uF C440198 → **4.7uF** 0805 | **C1779** | `/ETH_TOCAP` |
+| E-04 | **C172, C173 (new)** | 100nF 0603 at AVDD 4/8 and 11/21 | C14663 | `/3V3_ETH` – GND |
+| F-52 | **U31 (new)** | TMP102AIDRLR, **I²C 0x49** (ADD0 → V+) | **C99269** | 1 `/I2C_SCL` · 2 GND · 3 NC · 4 `/3V3` · 5 `/3V3` · 6 `/I2C_SDA` |
+| F-52 | **C174 (new)** | 100nF 0603 | C14663 | `/3V3` – GND |
+| G-03 | P11, P12 | `…MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical` (not in library) → **`Connector_Phoenix_MC:PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal`**; populated (D10) | C5160226 (unchanged) | |
+| G-03 | J10 | `Connector_RJ45:…` (nickname not configured) → **`Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal`**; populated | C12074 (unchanged) | |
+| G-04 | **JP6 (new)** = JP_CUT | `Jumper:SolderJumper_2_Open`, open footprint, value CUTOFF_BYPASS, not in BOM | no part | 1 `/MAIN5V`, 2 `/SYS5V` |
+| G-08 | **D36, D37, D38 (new)** | PESD5V0S1BA, `Diode_SMD:D_SOD-323` (same as D14–D16) | **C2827694** | pin 1 `/NRST` / `/NTC_TEMP` / `/NTC2`, pin 2 GND |
+| H-08 | C22, Y2 | value text "22uF/50V" → **"10uF/50V"**; "1.8432MHz" → **"3.6864MHz"** | unchanged | |
+| B-15 | R107, R108 | value "0R-DNP" → **"0R-NEVER-FIT"** + `Note` field (still DNP) | — | |
+| J-04 | 23 orphan NC flags (x = 453.898 / 484.378) | **deleted** | — | |
+| J-04 | NC flags on U16.37, U16.38, U10.13, U10.14 | **deleted** (pins stay on their nets) | — | |
+| J-04 | wire stubs | **2b755f7f deleted** (the dangling stub over P1.4); **7c1dbfc0 trimmed** from y 219.71 to 218.948 so it ends at its GND label (R52.2 stays on GND); **46f71e27 kept** (it carries P1.4's GND label) and the P1.4 junction kept. See §12 | — | no net change |
+
+## 3. New parts — where they are on the sheet
+
+All new parts sit in free space found with an occupancy map of the sheet (symbols, pins, labels, wires, texts), on the 1.27 mm grid, each cluster with a blue note "v6 audit <ID>: …" stating the physical placement rule. Coordinates are schematic mm (A1 sheet).
+
+| Cluster | Refs | Sheet position | Block it belongs to |
+|---|---|---|---|
+| C-01 | R135, U28, R136 | (402–475, 196) | below U18 / L21 bias-T |
+| F-02 | D35 | (94, 36) | beside P1 |
+| A-05 | C161, C162 | (377–391, 226) | right of C32–C34 |
+| F-03 | C163, C164, C165 | (184–213, 295) | left of U20 |
+| B-02 | C166, C167 | (401–415, 404) | right of U19 (VBAT caps) |
+| F-51 | U29, C168 | (257–287, 141) | above the charger passives (R50/R55) |
+| F-51 | R137, R138, C169 | (264–298, 220) | beside R50/R56 |
+| E-01 | R139 | (674, 217) | at U12 |
+| E-02 | R140 | (692, 60) | at U11 |
+| D-01 | U27, C170 | (268–304, 458) | below U23/U24 |
+| G-02 | U30 | (489, 307) | beside J9 |
+| A-13 | R141 | (218, 246) | near TP1/TP2 |
+| B-09 | C171 | (328, 460) | above J14 |
+| B-10 | R142, R143 | (284–298, 498) | below U24 |
+| C-07 | TP10, TP11 | (522–538, 104) | right of U18 |
+| D-09 | R144 | (137, 113) | at Q5 |
+| D-12 | TP9 | (547, 420) | right of U16 |
+| E-04 | C172, C173 | (730–745, 183) | below C94 |
+| F-52 | U31, C174 | (188–218, 414) | left of U23/U24 (modem block) |
+| G-04 | JP6 | (281, 25) | beside P5 |
+| G-08 | D36 / D37, D38 | (328, 133) / (476–503, 232) | at P6 / near P7–P8 |
+
+## 4. Netlist proof
+
+Netlists exported with kicad-cli through the KiCad MCP after each committed group (`kicad/_to_delete/v6-apply-20260928/netlists/00…05.xml`). `tools/ndiff.py` compares refs, value, footprint, lib_id, every field and property, DNP / BOM / position flags, **ref.pin → net** and net class. The expected change set of each group was written by the edit script *before* the file was committed and asserted against the actual diff.
+
+| Group | Netlist | Expected (added / removed / field / pin-net / class) | Actual | Result |
+|---|---|---|---|---|
+| 1 Blockers | 00-baseline → 01-blockers | 4 / 3 / 38 / 9 / 0 = 54 | 4 / 3 / 38 / 9 / 0 | **MATCH** |
+| 2 Majors | 01 → 02-majors | 17 / 0 / 36 / 4 / 0 = 57 | 17 / 0 / 36 / 4 / 0 | **MATCH** |
+| 3 Minors | 02 → 03-minors | 16 / 0 / 51 / 9 / 0 = 76 | 16 / 0 / 51 / 9 / 0 | **MATCH** (after the J-04 correction, §12) |
+| 4 Project rules | 03 → 04-rules (schematic untouched) | 0 / 0 / 0 / 0 / 16 | 0 / 0 / 0 / 0 / 16 | **MATCH** |
+| 5 Cosmetic (U30 ref text) | 04 → 05-final | 0 | 0 | **MATCH** |
+| **Total** | 00 → 05-final | composition of groups 1–5 | 37 / 3 / 125 / 22 / 16 | **0 differences** in every ref, attribute, pin and class |
+
+Field changes count both `footprint` and the `Footprint` field when a footprint changes. The 22 pin-net changes: U20.2, C127.1, C128.1 → `/MAIN5V`; D10.1 → `/VIN_FUSED`; L21.2, C144.1, C145.1 → `/ANT_BIAS`; U18.7 → NC; U18.5 → `/GNSS_ANT_OFF`; U12.2 → `/ETH_PWR_EN`; U16.54 → `/ETH_PWR_EN`; U16.25 → `/NTC_CELL`; U18.26 → `/DOUT_4G_F9P`; R56.2 → `/3V3`; U6.20, TP2.1 → `/PFO`; U16.29 → `/PFO`; U16.42 → `/USART1_TX`; U18.50 → `/GNSS_SAFEBOOT_N`; Y3.2 → GND, Y3.3 → `/HSE_OUT`, Y3.4 → GND. Full machine list: `netlist_diff_total.md`; per group: `out/0N-*/netlist_diff.md`.
+
+UUIDs: no existing symbol changed UUID (checked per group); the guard also held on every write.
+
+## 5. ERC (kicad-cli 10.0.4 via KiCad MCP)
+
+Per-category counts come from copies with narrowed ERC severities (`kicad/_to_delete/v6-apply-20260928/erc_work/`), because the MCP prints only 30 items. Baseline categories are the audit's (`evidence/erc_summary.md`, same file hash); final categories are from runs on the final file, and they add up to the full run.
+
+| Category | Before | After | Why |
+|---|---|---|---|
+| Errors | 0 | **0** | |
+| pin_to_pin | 104 | 102 | −2 from D21 (unspecified-pin easyeda symbol) removed; new symbols have typed pins |
+| no_connect_dangling | 23 | 0 | J-04 orphan flags deleted |
+| lib_symbol_mismatch | 22 | 21 | Y3 now uses a fresh `Device:Crystal_GND24` copy |
+| lib_symbol_issues (not in library) | 10 | 11 | +1: `Drogheda-sym:TPS2552DBV` is embedded only (§7). The 10 old ones remain (re-link skipped, §9) |
+| footprint_link_issues | 3 | 0 | G-03 (P11, P12, J10) |
+| no_connect_connected | 2 | 0 | J-04 |
+| unconnected_wire_endpoint | 2 | 0 | J-04 (stub deleted / tail trimmed) |
+| All other checks (dangling labels, unconnected pins, power pins, …) | 0 | 0 | |
+| **Total warnings** | **166** | **134** | |
+
+During Group 3 an intermediate run showed 3 errors (label/pin not connected at P1.4 and R52.2) from my first J-04 stub deletion; the netlist diff flagged the same two pins. Both were fixed before continuing (§12).
+
+## 6. Project rules (F-01, D18)
+
+### 6.1 Net classes (`hbox-watchdog-v6.kicad_pro`)
+
+All old patterns were replaced by exact full net names (the un-prefixed duplicates and dead patterns `3V3_MODEM`, `SW3_NODE` are gone). In the final netlist every pattern resolves to a real net.
+
+| Class | Nets | Clearance | Track | Via | Priority |
+|---|---|---|---|---|---|
+| HV24 | `/24V_IN` `/VIN_FUSED` `/VIN_PROT` `/24V` `/IGN_IN` `/Q10_GATE` `/Q23_GATE` `/SW_PWRIN` `/BOOT_PWRIN` `/SW_FAN` `/BST_FAN` | 0.3 (was 0.5) | 1.0 (was 0.5) | 0.8/0.4 | 0 |
+| PWR_HI | `/BAT_PLUS` `/SW_BAT` `/MAIN5V` `/VEH5V` `/SYS5V` `/VIN_SW` | 0.15 (was 0.2) | 1.5 | 0.8/0.4 | 1 |
+| PWR_MODEM (new) | `/VBAT_MODEM` | 0.15 | 1.5 | 0.8/0.4 | 2 |
+| PWR_MID | `/SW_5V` `/SW_IN` `/5V_FAN` `/FAN_RET` | 0.15 (was 0.2) | 0.6 (was 1.0) | 0.8/0.4 | 3 |
+| RF (new) | `/RF_GNSS` `/RF_ANT_GNSS` `/RF_LTE` `/RF_ANT_LTE` | 0.2 (CPWG gap) | 0.3 (CPWG width; final value from JLC's calculator) | 0.6/0.3 (no vias intended) | 4 |
+| Default | everything else, incl. `/3V3_ETH` (moved out of PWR_MID, J-02), `/EN_FAN`, `/EN_PWRIN`, `/SW_MODEM`, `/BST_MODEM` | 0.15 (was 0.2) | 0.2 | 0.6/0.3 | — |
+
+Netlist class changes (16): to HV24 `/VIN_FUSED` `/VIN_PROT` `/24V` `/IGN_IN` `/Q10_GATE` `/Q23_GATE` `/SW_PWRIN` `/BOOT_PWRIN` `/BST_FAN` (from Default) and `/SW_FAN` (from PWR_MID); `/3V3_ETH` PWR_MID → Default; `/VBAT_MODEM` → PWR_MODEM; the four RF nets → RF.
+
+**Decision on the HV24 list (differs from the report table, which predates A-01):** `/VIN_MODEM` no longer exists, and **`/SW_MODEM` and `/BST_MODEM` were left out of HV24**. With A-01, U20 runs from `/MAIN5V` (≤ 5.5 V), so they are 5 V-class switch/boot nodes; in HV24 they would raise false 0.3/0.5 mm errors around U20 (like `/ETH_SW`, they stay Default with the T15 width rule). `/SW_FAN`, `/BST_FAN`, `/24V` and `/Q10_GATE` **stay HV24**: the U2 and Q10 footprints remain on the board as DNP and would carry vehicle voltage if ever fitted.
+
+### 6.2 `.kicad_dru` (verify_2's corrected set, verbatim; replaces "Minimum clearance 1", "HV24 clearance", "HV24 exception: MP1584EN land pattern")
+
+```
+(rule "Floor 0.15 (non-HV24, non-RF)"
+	(condition "A.NetClass != 'HV24' && B.NetClass != 'HV24' && A.NetClass != 'RF' && B.NetClass != 'RF'")
+	(constraint clearance (min 0.15mm))
+)
+(rule "HV24 to HV24"
+	(condition "A.NetClass == 'HV24' && B.NetClass == 'HV24'")
+	(constraint clearance (min 0.2mm))
+)
+(rule "HV24 outer"
+	(layer outer)
+	(condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
+	(constraint clearance (min 0.3mm))
+)
+(rule "HV24 inner"
+	(layer inner)
+	(condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
+	(constraint clearance (min 0.5mm))
+)
+(rule "HV24 IC land patterns"
+	(layer outer)
+	(condition "A.Type == 'Pad' && B.Type == 'Pad' && ((A.memberOfFootprint('U2') && B.memberOfFootprint('U2')) || (A.memberOfFootprint('U20') && B.memberOfFootprint('U20')) || (A.memberOfFootprint('U25') && B.memberOfFootprint('U25')))")
+	(constraint clearance (min 0.15mm))
+)
+```
+
+A 3-line comment header was added above the set. The silkscreen text rule and the three T15 power-width warning rules are unchanged (the T15 rule still names `/VIN_MODEM`, now a dead name; harmless). The U20 clause of the land-pattern rule no longer matches anything after the HV24 decision above; it was kept to stay verbatim with verify_2.
+
+## 7. Library
+
+- **H-04 fixed:** `(property "LCSC Part" "C2071691")` deleted from `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` (one line, span-scoped; the rest of the file is byte-identical). That footprint is shared by U20 (AP64350, C2071691) and U25 (TPS54360B, C524806); both now resolve through their `LCSC` fields. The board copy of U25 still carries the field until Michelle updates the footprint from the library (§10).
+- **Other `LCSC Part` values in `Drogheda-v6.pretty` checked against their users (not stripped):** IND-SMD_L13.5-W12.5 C840531 = L22 ✓ · LCC-LGA-102 C5120257 = U18 ✓ · LGA-124 C18548276 = U19 ✓ · LGA-12 C5126709 = U26 ✓ · RF-SMD_FRF05002 C88374 = J12, J13 ✓ · SMA_L4.4 C113952 = D22 ✓ · VSSOP-8 C730237 = U23, U24 ✓ · SOD-923 C82326 = D27 ✓ (D28 moved to 0402) · **SOD-128 C50603 now unused** (D21 removed). None is wrong.
+- **TPS2552 symbol:** KiCad 10 has no TPS2552 symbol (the MIC2007/2008 SOT-23-6 switches have a different pinout), so `Drogheda-sym:TPS2552DBV` was authored and **embedded in the schematic only**: box symbol, 1 IN power_in, 2 GND power_in, 3 ~EN input, 4 ~FAULT open_collector, 5 ILIM passive, 6 OUT power_out, footprint SOT-23-6, TI datasheet link. `Drogheda-sym.kicad_sym` was not edited (outside this pass's file set; shared with v5), which is the +1 ERC "not found in library" warning. Copy it into the library in a library pass.
+- New library symbols embedded from KiCad 10: `74xGxx:74LVC1G125`, `Power_Protection:USBLC6-2SC6`, `Device:Crystal_GND24`. `Sensor_Temperature:TMP102xxDRL` was already cached in the sheet and is content-identical to the library.
+
+## 8. Reverse-polarity and fusing topology after V1-01 / A-01
+
+```
+P1.1 ─ /24V_IN ─ F2 (3 A Nano2, socketed) ─ /VIN_FUSED ─┬─ D10 SMBJ33A (pad 1 cathode) ─ GND
+                                                        └─ Q23 IRFR5305: D=/VIN_FUSED, S=/VIN_PROT, G=/Q23_GATE
+                                                             D33 zener S→G clamp, R119 gate to GND
+/VIN_PROT ─ D32 SMCJ33A, C149–C151, U25 (TPS54360B) → /VEH5V
+/24V_IN also ─ Q10.D (Q10 branch DNP: /24V carries no fitted part)
+```
+
+- **Correct polarity:** current flows P1 → F2 → Q23 body diode (drain→source), Q23 enhances with its gate pulled to GND (V_GS clamped at −15 V by D33) → /VIN_PROT. D10 and D32 clamp transients; D10 is now behind F2, so a TVS that fails short opens F2 instead of loading the harness.
+- **Reversed P1:** /VIN_FUSED goes negative; Q23's gate (to GND) is positive against its source, so Q23 stays off and its body diode is reverse-biased. D10 forward-conducts GND → /VIN_FUSED through F2 → **F2 blows** (socketed, replaceable). Before V1-01, D10 sat on /24V_IN ahead of F2 and would have carried harness-fuse current.
+- The only unfused copper left on /24V_IN is P1.1 → F2.1 and the Q10.D pad of the DNP Q10. If the Q10 branch is ever re-fitted, move Q10.D to /VIN_FUSED first.
+- U20 now sits on /MAIN5V, upstream of the P5 cutoff (A-01 note): P5 still removes SYS5V → MCU unpowered → R113 holds U20 EN low (µA).
+
+## 9. Skipped items and decisions
+
+**Not applied**
+1. **G-01** (restore MH4 at (193.2, 90.3), heatsink-clamp holes MH11 + partner): board-only mounting holes; Michelle (D11 makes it a Blocker).
+2. **J-04, re-linking the 10 "not found" symbols** (Q_*MOS_G?S ×7, D_Zener_ANK ×2, PCF8574): needs writing their definitions into the shared `Drogheda-sym.kicad_sym` (outside the allowed file set) and swapping 10 lib_ids. Cosmetic; left as warnings. The 22 library mismatches were left alone as the report asks (no bulk update).
+3. **G-08, optional 100 Ω series resistor on NRST:** optional in the report; it would split `/NRST`. Not applied.
+4. **D-08** (board-ID strap), **H-03** (MWSA0804S land), **J-03** (library pin types): excluded by D19.
+5. Layout-only Majors (V1-01 layout, F-12, F-05, F-06, C-04, A-07) and A-02: layout list, §10.
+
+**Decisions taken while applying (beyond the letter of §7)**
+- DNP marking follows the sheet's existing convention (`(dnp yes)` only, as on C146/C147, R107/R108, R124/R125, R127–R130, U22): footprints stay on the board with the DNP attribute, and KiCad leaves DNP parts out of BOM/CPL outputs.
+- U17, U21, U10 kept their symbols (identical pin numbering) and changed fields only; the netlist diff shows value/LCSC/MPN changes only for them.
+- New test pads (TP9–TP11) and JP6 are excluded from BOM and position files (no purchasable part). TP1–TP8 were left as they are.
+- HV24 net list: §6.1. PF15 removal: §2.1. C171 net: §2.3.
+
+## 10. Layout delta for Michelle
+
+Run **Tools → Update PCB from Schematic** on `hbox-watchdog-v6.kicad_pcb` with **"Delete footprints with no symbols" ticked** (earlier runs did not delete removed footprints), and "Update footprints" on so the changed footprints are swapped. Then run DRC (new rules, below).
+
+**New footprints to place (37)**
+
+| Ref | Footprint | Where / constraint (from the audit) |
+|---|---|---|
+| U28 | SOT-23-6 | GNSS bias switch next to L21/C144/C145 at J12; `/ANT_BIAS` ≥ 1 mm from the RF line with a stitched GND strip (F-06); short feed from `/3V3_GNSS` |
+| R135, R136 | 0603 | at U28 pins 3 and 4 |
+| D35 | D_SMB | **at P1.3**; with Rig1 moved to ≤ 3 mm of copper from P1.3 so `/IGN_IN` is ≤ 3 mm on F.Cu and the long run becomes `/IGN_SENSE` (F-02) |
+| C161, C162 | 1210 | ≤ 2 mm from U6 VSYS pins 1/24, GND on the U6 EP copper (A-05/A-02) |
+| C163, C164 | 0805 | ≤ 2–3 mm from U20.2, GND on the U20 EP copper (F-03) |
+| C165 | CP_Elec_6.3x7.7 | at U20.2 (F-03) |
+| C166, C167 | 0805 | ≤ 3 mm from L20.2 (B-02) |
+| U29 + C168 | SOT-563 + 0603 | **between U6 and L6, ≤ 5 mm from the U6 EP** (F-51, R4) |
+| R137, R138, C169 | 0603 | pack-NTC tap: R138/C169 at U16 pad 25 (PC5); R137 anywhere on `/NTC` |
+| R139 | 0603 | at U12 pin 2 (EN); new track `/ETH_PWR_EN` to U16 pad 54 (PD2) |
+| R140 | 0603 | at U11.37 (`/ETH_RST`) |
+| U27 + C170 | SOT-23-5 (SOT-753) + 0603 | **at U18.26 (RXD2)**; VCC from `/3V3_GNSS` |
+| U30 | SOT-23-6 | **≤ 3 mm of copper from the J9 pads**, D+/D− routed through the device pads, GND via ≤ 1 mm (G-02) |
+| R141 | 0603 | `/PFO` pull-up near U16 pad 29 (PB10) |
+| C171 | 0402 | at J14.C1 |
+| R142, R143 | 0603 | on `/MODEM_STATUS` (PC9) and `/DIN_4G`, any convenient spot |
+| TP10, TP11 | TestPoint_Pad_D1.0mm | near U18 pins 50 (SAFEBOOT_N) and 49 (RESET_N), next to a GND pad (C-07) |
+| R144 | 0603 | at Q5 base |
+| TP9 | TestPoint_Pad_D1.5mm | PA9 debug-TX pad next to TP3–TP5 (D-12) |
+| C172, C173 | 0603 | at W5500 AVDD pins 4/8 and 11/21 |
+| U31 + C174 | SOT-563 + 0603 | **between U19 and U20** (F-52) |
+| JP6 | SolderJumper 2-pad, open | across P5 (`/MAIN5V`–`/SYS5V`), silk "CUTOFF BYPASS" (G-04) |
+| D36, D37, D38 | SOD-323 | ≤ 3 mm from P6.1, P7.1, P8.1 to GND (G-08) |
+
+**Removed footprints:** D20 (D_SMA), D21 (SOD-128). (PF15 is a virtual power flag, no footprint.)
+
+**Footprint changes:** U15 → narrow `SOIC-16_3.9x9.9mm` (re-place C84–C88, local reroute) · D28 → `D_0402_1005Metric` (with the F-06 LTE reroute) · Y3 → `Crystal_SMD_3225-4Pin_3.2x2.5mm` (pad 1 HSE_IN, pad 3 HSE_OUT, pads 2/4 GND; ≤ 3–5 mm from PH0/PH1, no inner track under it) · C91 → 0603 · JP1 → Bridged (net-tie) · J10 → `Connector_RJ:` nickname (same geometry) · P11/P12 → Horizontal (already so on the PCB) · U25 → re-pull the footprint from the library so its board copy loses `LCSC Part` (H-04) · Y4 and F2 keep their footprints.
+
+**DNP changes:** set DNP: U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21, Q10, DzG1, Rrp1, C10, C11, C22. **Clear DNP:** J10, P11, P12 (populated per D10).
+
+**Nets that change routing**
+- `/VIN_MODEM` disappears: U20.2, C127, C128 go to **`/MAIN5V`** (≥ 1.5–2 mm all the way to U20; delete the 48 mm `/VIN_MODEM` run, A-01/A-07).
+- `/VIN_FUSED` gains D10.1: P1.1 → F2 → {D10, Q23.D}; `/24V_IN` = P1.1, F2.1, Q10.D only.
+- `/ANT_BIAS` (U28.6 → L21.2, C144, C145); U18.7 is now NC; `/GNSS_ANT_OFF` (U18.5 → U28.3, R135); `/GNSS_ANT_SHORT_N` gains U28.4 and R136.
+- `/ETH_PWR_EN` (U12.2, U16.54, R139); U12.2 leaves `/SYS5V`.
+- `/DOUT_4G_F9P` (U27.4 → U18.26); U18.26 leaves `/DOUT_4G`; U27.2 joins `/DOUT_4G`.
+- `/PFO` (renamed from `/PFO_TP`: U6.20, TP2, plus U16.29 and R141).
+- `/NTC_CELL` (U16.25, R137, R138, C169); `/NTC` gains R137.
+- `/GNSS_SAFEBOOT_N` (U18.50, TP10); `/USART1_TX` (U16.42, TP9).
+- R56.2 moves from GND to `/3V3`; Y3 pads re-netted as above.
+
+**DRC with the new rules (run on a copy of the current, not-yet-updated board):** 161 clearance errors (was 0). **149 of them are zone-fill proximities** (stored fills at 0.15 mm to HV24 and RF nets); a zone refill clears them. **12 are real copper spacings:** `/IGN_IN` on In2 vs GND via 0.250, `/FAN_PWM` 0.291, `/5V_FAN` via 0.300, `/NTC2` 0.305, `/VEH5V` via 0.340 (all F-02, disappear with the P1.3 move); `/VIN_PROT` vs `/VEH5V` 0.157 and 0.191 at (175.5, 113.8); `/USB_VBUS` vs Q23.1 `/Q23_GATE` 0.225; `/SW_PWRIN` vs GND track 0.270; `/24V` vs `/COMP_FAN` 0.290 ×2 (DNP branch, but the copper exists); RF class: `/RF_LTE` via vs `/PWR_CTRL` 0.150 (goes away with the F-06 F.Cu reroute). **Caveat:** KiCad lists only one violation between the long In2 `/IGN_IN` segment and `/VEH5V` (the via at 0.340 mm); the parallel `/VEH5V` 1.0 mm tracks beside it are 0.221–0.240 mm away (recomputed from the track coordinates, matching the audit's 0.221 mm) and are not listed as separate items. So do not read the DRC count as the full list; the F-02 move removes the whole In2 `/IGN_IN` run anyway. `track_width` warnings drop 183 → 121 (`/3V3_ETH` now Default, PWR_MID width 0.6). Other DRC items unchanged (82 lib_footprint_mismatch, 4 lib_footprint_issues, 11 silk_overlap, 2 silk_over_copper, 1 silk_edge). After Update PCB, expect new HV24 items on `/VIN_FUSED` at D10 and removal of the `/VIN_MODEM` ones. Check once with Inspect → Clearance Resolution that the classes survived the GUI save (resync protocol §5).
+
+**Order notes (from the part lookups):** C2862740 (TPS7A2033PDBVR, U21) is listed by JLC under "Pre-ordered Chips": pre-order it into the account like J14. P11/P12 C5160226 stock 512 (enough for 20 boards). Re-check stock on order day (D14).
+
+## 11. Firmware notes (for FW 0.7.x `board_v6.h`, D15)
+
+1. **PD2 = `ETH_PWR_EN`**: U12 (3V3_ETH) enable, R139 100 k pull-down → Ethernet OFF in reset/DFU/battery; drive HIGH only on vehicle power when Ethernet is needed; keep SPI2 and PA15 low while it is off.
+2. **PB10 = `PFO`**: LTC4040 PFO, open-drain, R141 100 k pull-up to 3V3; EXTI10 falling = backup entry (VEH5V < PFI 4.40 V falling / 4.51 V rising). Update `V5_PFI` to 4.40 V.
+3. **PC5 = `NTC_CELL`** (ADC1_IN15): pack NTC through 100 k/120 k (ratio 120/220) + 10 nF; Rntc = R55·Vntc/(VEH5V − Vntc) with VEH5V from PA4; valid only with VEH5V present. Feed `tcell` into `CHG_CELL_HOT/COOL`.
+4. **CHGOFF default:** R56 is now a pull-**up** to 3V3 → PA8 (`CHRG_EN`, drives LTC4040 CHGOFF) high = charger **off** whenever the MCU is not driving. Polarity unchanged: firmware drives PA8 LOW to allow charging.
+5. **Ignition on PA5 (ADC1_IN5), read analog**, no internal pull: Rigb1 = 2.2 k → ratio 2.0 k/24.0 k = **0.0833**: 12 V → 1.00 V, 24 V → 2.00 V, 36 V → 3.00 V, full scale 39.6 V. Add `vign` to `$PHLG`.
+6. **TMP102 at 0x48 = charger sensor (U29)**, **0x49 = modem-area sensor (U31)**; no address clash (0x18 SC7A20, 0x20 PCF8574, 0x44 SHT40, 0x4D SC16IS752). Add `tchg`, `tmodem` to `$PHLG`; shed charge on `tchg` > 85 °C.
+7. GNSS antenna: F9P ANT_OFF now drives TPS2552 ~EN (set `CFG-HW-ANT_CFG_VOLTCTRL` = 1, `SHORTDET` = 1). PC2 `GNSS_ANT_SHORT_N` is driven by TPS2552 ~FAULT (open drain, 10 k to 3V3_GNSS): LOW = short or rail off. PC1 `GNSS_ANT_DETECT` remains undriven (keep hi-Z, infer open antenna from C/N0).
+8. U27 now isolates F9P RXD2: F9P-only power cycles with the modem up become safe on boards that have it; keep the 0.5.5/0.5.6 back-feed rules for PA2/PA10/PC7/PC12. Rdfu1 is 100 k (≤ 27 µA into TXD2 with the F9P off).
+9. `/MODEM_STATUS` (PC9) has a 100 k pull-down and `/DIN_4G` a 100 k pull-up in hardware: no internal pulls needed. R106 is 1 k.
+10. PA9 is a test pad (TP9, `USART1_TX`): usable as a TX-only debug log or ROM USART bootloader.
+11. U25 set-point is now 5.32 V nominal (R121 57.6 k): keep `CHG_RAIL_ON` 5.05 V / `CHG_RAIL_OFF` 4.90 V; compute VDDA from VREFINT.
+12. LSE: Y4 is CL 7 pF → set `LSEMOD` (high drive) before `LSEON`, LSI fallback. HSE is still 25 MHz (new 3225 crystal); `BOARD_SER_XTAL_HZ` = 3 686 400 (Y2 value text now matches).
+13. Battery mode (D9): LTE-only (`AT+CNMP=38`), Ethernet off.
+
+## 12. Incidents and surprises
+
+1. **J-04 wire stubs were not all dangling.** The audit listed three stub UUIDs. Deleting all three broke two connections: at P1.4 the GND label sits at the far end of 46f71e27 (only 2b755f7f is the dangling overhang), and at R52.2 the GND label sits mid-segment on 7c1dbfc0 (only a 0.76 mm tail past the label was dangling). ERC showed 3 new errors and the netlist diff flagged exactly P1.4 and R52.2 as unexpected. Fixed by deleting only 2b755f7f, keeping 46f71e27 and the P1.4 junction, and trimming 7c1dbfc0 to end at its label. Re-verified: expected == actual, ERC 0 errors.
+2. **`device_commit_files` re-sent a cached upload** when a staged path was reused: my second commit of Group 1 wrote the first version. Caught by hashing the Mac file after every commit; from then on every commit used a unique staged path. Every committed state in this report was hash-checked on the Mac.
+3. **Y3 needed a symbol swap**, not a footprint swap: `Device:Crystal` (2 pins) on the 3225-4P land would have put HSE_OUT on GND pad 2. Swapped to `Device:Crystal_GND24` in place (UUIDs kept, pins 3/4 added), proven by the netlist.
+4. **The TPS2552 has no KiCad library symbol** (embedded one authored, §7).
+5. **TPS7A2033PDBVR is in JLC's "Pre-ordered Chips" category** (stock 28 370): pre-order like J14.
+6. One wire-crossing hit on U30 remains: the MCP tool's bounding box for the vertically asymmetric USBLC6 symbol; the PDF shows the VBUS wire leaving the pin outward.
+
+## 13. New LCSC numbers (JLC DB lookup via KiCad MCP, 2026-09-28)
+
+| LCSC | Part | Package | Stock | Type | Used on |
+|---|---|---|---|---|---|
+| C206912 | Littelfuse 0154003.DR 3 A | SMD 9.7×5 (Nano2 holder) | 2 217 | Ext | F2 |
+| C22840 | 1.43 kΩ 1 % | 0603 | 4 965 | Ext | R50 |
+| C1975527 | Littelfuse PESD0402-240 | 0402 | 9 394 | Ext | D28 |
+| C46506 | TI TPS2552DBVR | SOT-23-6 | 3 002 | Ext | U28 |
+| C224019 | Littelfuse SMBJ33A | DO-214AA | 9 624 | Ext | D35 |
+| C57156 | NXP SC16IS752IPW,128 | TSSOP-28 | 2 670 | Ext | U10 |
+| C177479 | HKR RCT03499KFLF 499 k | 0603 | 26 862 | Ext | R53 |
+| C23082 | 57.6 kΩ 1 % | 0603 | 3 673 | Ext | R121 |
+| C5440143 | Samwha 47 µF 16 V X7R | 1210 | 242 640 | Ext | C161, C162 |
+| C15578 | TI TLV1117LV33DCYR | SOT-223 | 26 999 | Ext | U17 |
+| C881921 | Lelon OVZ221M1CTR-0608 220 µF 16 V polymer | 6.3×7.7 | 2 442 | Ext | C78, C130, C131, C165 |
+| C22862 | 113 kΩ 1 % | 0603 | 59 728 | Ext | R116 |
+| C1542 | 6.8 nF 50 V X7R | 0402 | 128 063 | Pref | C141 |
+| C1572 | 56 pF C0G | 0402 | 83 992 | Ext | C142 |
+| C86817 | Murata 22 µF 16 V X5R | 0805 | 4 144 | Ext | C163, C164, C166, C167 |
+| C99269 | TI TMP102AIDRLR | SOT-563 | 34 854 | Ext | U29, U31 |
+| C25808 | 120 kΩ 1 % | 0603 | 773 686 | Basic | R138 |
+| C1589 | 10 nF 50 V X7R | 0603 | 6 584 349 | Ext | C169, C91 |
+| C2862740 | TI TPS7A2033PDBVR | SOT-23-5 | 28 370 | Ext (**pre-order category**) | U21 |
+| C23162 | 4.7 kΩ 1 % | 0603 | 21 915 184 | Basic | R140 |
+| C12518 | Nexperia 74LVC1G125GV,125 | SOT-753 | 5 234 | Ext | U27 |
+| C7519 | ST USBLC6-2SC6 | SOT-23-6 | 1 415 | Ext | U30 |
+| C25803 | 100 kΩ 1 % | 0603 | 10 814 547 | Basic | new pull resistors, Rdfu1, H-02b set |
+| C14663 | 100 nF 50 V X7R | 0603 | 37 493 696 | Basic | C168, C170, C172–C174 |
+| C23345 | 22 Ω 1 % | 0603 | 4 031 533 | Basic | R132–R134 |
+| C1525 | 100 nF 16 V X7R | 0402 | 43 509 060 | Basic | C171 |
+| C14676 | 1 kΩ 5 % | 0603 | 757 955 | Ext | R106 |
+| C2901684 | SCTF SX3B25.000F1010F30 25 MHz CL 10 pF | 3225-4P | 11 076 | Ext | Y3 |
+| C38523 | 12 pF C0G | 0603 | 3 346 489 | Basic | C113, C114 |
+| C48615 | Epson Q13FC13500002 FC-135 CL 7 pF | 3215-2P | 101 342 | Ext | Y4 |
+| C1679 | 6.8 pF C0G | 0603 | 1 445 998 | Pref | C115, C116 |
+| C4190 | 2.2 kΩ 1 % | 0603 | 2 920 710 | Basic | Rigb1 |
+| C1663 | 33 pF C0G | 0603 | 2 808 576 | Basic | C95, C96 |
+| C1779 | 4.7 µF 25 V X5R | 0805 | 4 715 349 | Basic | C90 |
+| C2827694 | PESD5V0S1BA | SOD-323 | 303 975 | Ext | D36–D38 |
+| C25804 | 10 kΩ 1 % | 0603 | (existing Basic) | Basic | R136 |
+
+Final BOM (`kicad/_to_delete/v6-apply-20260928/bom_final*.csv`, kicad-cli): 306 populated BOM lines; only TP1–TP8 have no LCSC (copper pads, as before).
+
+## 14. Files and backups
+
+- Edited in place: `03-Architecture-Hardware/kicad/hbox-watchdog-v6.kicad_sch`, `.kicad_pro`, `.kicad_dru`, `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod`.
+- PDF: `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf`.
+- Backups (nothing deleted): `kicad/_to_delete/v6-apply-20260928/` — `00-pre/` (sch, pro, dru, prl, SO-8 footprint, DRC side-file), `01-blockers/`, `02-majors/`, `03-minors/`, `04-rules/`, `05-final/`, `netlists/00-baseline … 05-final.xml`, `erc_work/` (ERC isolation copies), `drc_work/` (DRC on a board copy with the new rules; report + JSON), `scratch/` (intermediate PDFs, library-extraction file), `bom_final.csv`, `bom_final_ungrouped.csv`.
+- Container: `/home/claude/v6audit/apply/` — this report, `netlist_diff_total.md`, `out/0N-*/` (edit logs, expected sets, per-group diffs), `tools/` (editor, model, diff, group scripts), `drc/`, the PDF.
+- The `.kicad_pcb` is untouched. If KiCad was open on v6 during this pass, close it **without saving** and reopen before Update PCB (resync protocol §5).
+
+**Git (for Leo to run; nothing was committed from here):** commit inside the `kicad` submodule (sch, pro, dru, SO-8 footprint), push to Gitea `HBox_PCB`, then bump the parent gitlink; `_to_delete/` is gitignored.

03-Architecture-Hardware/2026-09-28_v6-audit-attachments/verify_apply.md

@@ -0,0 +1,150 @@
+# EinarBoard v6 — Independent verification of the schematic apply pass (v1.0)
+
+**Date:** 2026-09-28 18:45 CST · **Verifier:** independent Claude agent (read-only, own scripts) · **Object:** `hbox-watchdog-v6.kicad_sch` sha256 `d54e330d…4c4` (the apply pass result, before the ports pass), `.kicad_pro` `d577aa43…`, `.kicad_dru` `31ce0f4f…`, SO-8-EP footprint `3f38f26e…`.
+
+## Result: 173 PASS · 0 FAIL · 15 NOTE
+
+- **Provenance:** the apply pass's baseline netlist equals the audit's evidence netlist; connectivity re-derived directly from the .kicad_sch (own union-find extractor) reproduces `05-final.xml` exactly (353 nets).
+- **Completeness:** all 126 intended items (§7.1, §7.2, D19 Minors) present with the intended value, footprint, LCSC, DNP state and pin→net; no unintended electrical change (only extras: C174 decoupling at U31 and MPN/Manufacturer metadata; the Fabrication Toolkit reads `LCSC` before `MPN`).
+- **Datasheet pinouts (all PASS):** TPS2552DBVR hand-built symbol (TI SLVS841F), 74LVC1G125GV (Nexperia rev 17.1), USBLC6-2SC6 (ST DS4260), TMP102 DRL (TI SBOS397I; 0x48/0x49), PESD0402-240 (bidirectional), SMBJ33A IGN TVS (cathode on /IGN_IN), PESD5V0S1BA ×3, polymer cap polarity, Y3 `Crystal_GND24` ↔ 3225-4P pads.
+- **Pin-compatible swaps (all PASS):** U17 → TLV1117LV33DCYR (TI SBVS160C), U21 → TPS7A2033PDBVR (TI SBVS338H), U10 → SC16IS752IPW (NXP rev 9.1; I²C 0x4D).
+- **Topology (all PASS):** F2 → /VIN_FUSED → {D10, Q23}; reversed P1 forward-biases D10 and blows F2, Q23 stays off; Q10 branch fully DNP with no populated loads on /24V; /VIN_MODEM fully merged into /MAIN5V; JP1 bridged; U20 loop 113 k / 6.8 nF / 56 pF; R50 1.43 k; R121 57.6 k; ETH_PWR_EN → PD2 + 100 k; ETH_RST 4.7 k; U27 drives only U18.26; NTC tap → PC5.
+- **BOM/JLC:** 28 DNP parts flagged; every populated part has an LCSC number; 30 LCSC numbers spot-checked (part, package, stock).
+- **Project rules:** netclass patterns resolve exactly as KiCad's netlist says (no dead patterns); `.kicad_dru` parses and holds verify_2's five rules verbatim; `LCSC Part` removed from the SO-8-EP library footprint.
+- **ERC:** 0 errors, 134 warnings (all pre-existing cosmetic categories).
+
+## Notes acted on afterwards
+- **N1 (Y3 pad map):** confirmed later from the SCTF 3X datasheet (pins 1/3 crystal, 2/4 GND) — no change (Final Check).
+- **N2 (TPS2552 IN bypass):** C176 100 nF (C14663) added at U28 (Final Check).
+- Other notes (N3–N15): symbol graphic of D28, TPS2552 symbol only embedded, HV24 list deviations judged correct, RF class widths are placeholders until the JLC impedance calculator, pre-order C2862740, check DNP/footprints on the board after Update PCB.
+
+## Per-item table (126 rows, generated by the verifier's `make_report.py`)
+
+| # | Finding | Ref / net | Intended (§7 + D19) | Found in `05-final.xml` | Result |
+|---|---|---|---|---|---|
+| I1 | A-01 | D20 | removed | removed | PASS |
+| I2 | A-01 | D21 | removed | removed | PASS |
+| I3 | A-01 | U20 | 2:/MAIN5V | 2:/MAIN5V | PASS |
+| I4 | A-01 | C127 | 1:/MAIN5V | 1:/MAIN5V | PASS |
+| I5 | A-01 | C128 | 1:/MAIN5V | 1:/MAIN5V | PASS |
+| I6 | A-01 | /VIN_MODEM | net absent | absent | PASS |
+| I7 | A-01 | U2 | DNP | DNP | PASS |
+| I8 | A-01 | L2 | DNP | DNP | PASS |
+| I9 | A-01 | Dbk1 | DNP | DNP | PASS |
+| I10 | A-01 | Cbst1 | DNP | DNP | PASS |
+| I11 | A-01 | Rcomp1 | DNP | DNP | PASS |
+| I12 | A-01 | Ccomp1 | DNP | DNP | PASS |
+| I13 | A-01 | Rfreq1 | DNP | DNP | PASS |
+| I14 | A-01 | Ren1 | DNP | DNP | PASS |
+| I15 | A-01 | Ren2 | DNP | DNP | PASS |
+| I16 | A-01 | R20 | DNP | DNP | PASS |
+| I17 | A-01 | R21 | DNP | DNP | PASS |
+| I18 | A-01 | JP1 | SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm; 1:/5V_FAN 2:/VEH5V | fp ok · 1:/5V_FAN 2:/VEH5V | PASS |
+| I19 | A-01 | Q10 | DNP | DNP | PASS |
+| I20 | A-01 | DzG1 | DNP | DNP | PASS |
+| I21 | A-01 | Rrp1 | DNP | DNP | PASS |
+| I22 | A-01 | C10 | DNP | DNP | PASS |
+| I23 | A-01 | C11 | DNP | DNP | PASS |
+| I24 | A-01 | C22 | DNP | DNP | PASS |
+| I25 | A-01/V1-01 | F2 | value ∋ 3A; C206912; Fuseholder_Littelfuse_Nano2_154x; fitted; 1:/24V_IN 2:/VIN_FUSED | LCSC C206912 · val 3A/125V-NANO2-in-holder · fp ok · fitted · 1:/24V_IN 2:/VIN_FUSED | PASS |
+| I26 | V1-01 | D10 | C224019; fitted; 1:/VIN_FUSED 2:GND | LCSC C224019 · fitted · 1:/VIN_FUSED 2:GND | PASS |
+| I27 | V1-01 | Q23 | fitted; 1:/Q23_GATE 2:/VIN_FUSED 3:/VIN_PROT | fitted · 1:/Q23_GATE 2:/VIN_FUSED 3:/VIN_PROT | PASS |
+| I28 | A-03 | R50 | value ∋ 1.43k; C22840; R_0603_1608Metric; 1:/PROG 2:GND | LCSC C22840 · val 1.43k/1% · fp ok · 1:/PROG 2:GND | PASS |
+| I29 | B-03 | D28 | value ∋ PESD0402-240; C1975527; D_0402_1005Metric; 1:/RF_ANT_LTE 2:GND | LCSC C1975527 · val PESD0402-240 · fp ok · 1:/RF_ANT_LTE 2:GND | PASS |
+| I30 | C-01 | U28 | value ∋ TPS2552; C46506; SOT-23-6; fitted; 1:/3V3_GNSS 2:GND 3:/GNSS_ANT_OFF 4:/GNSS_ANT_SHORT_N 5:/3V3_GNSS 6:/ANT_BIAS | LCSC C46506 · val TPS2552DBVR · fp ok · fitted · 1:/3V3_GNSS 2:GND 3:/GNSS_ANT_OFF 4:/GNSS_ANT_SHORT_N 5:/3V3_GNSS 6:/ANT_BIAS | PASS |
+| I31 | C-01 | U18 | 5:/GNSS_ANT_OFF 6:/GNSS_ANT_SHORT_N 7:NC | 5:/GNSS_ANT_OFF 6:/GNSS_ANT_SHORT_N 7:unconnected-(U18-VCC_RF-Pad7) | PASS |
+| I32 | C-01 | R135 | value ∋ 100k; C25803; /GNSS_ANT_OFF↔GND | LCSC C25803 · val 100k · {'1': '/GNSS_ANT_OFF', '2': 'GND'} | PASS |
+| I33 | C-01 | R136 | value ∋ 10k; C25804; /3V3_GNSS↔/GNSS_ANT_SHORT_N | LCSC C25804 · val 10k · {'1': '/3V3_GNSS', '2': '/GNSS_ANT_SHORT_N'} | PASS |
+| I34 | C-01 | L21 | 2:/ANT_BIAS | 2:/ANT_BIAS | PASS |
+| I35 | C-01 | C144 | 1:/ANT_BIAS | 1:/ANT_BIAS | PASS |
+| I36 | C-01 | C145 | 1:/ANT_BIAS | 1:/ANT_BIAS | PASS |
+| I37 | F-02 | D35 | value ∋ SMBJ33A; C224019; D_SMB; fitted; 1:/IGN_IN 2:GND | LCSC C224019 · val SMBJ33A · fp ok · fitted · 1:/IGN_IN 2:GND | PASS |
+| I38 | F-02 | Rig1 | value ∋ 22k; C88614; 1:/IGN_IN 2:/IGN_SENSE | LCSC C88614 · val 22k · 1:/IGN_IN 2:/IGN_SENSE | PASS |
+| I39 | F-02 | /IGN_IN | = {D35.1, P1.3, Rig1.1} | [('D35', '1'), ('P1', '3'), ('Rig1', '1')] | PASS |
+| I40 | H-01 | U15 | C15846; SOIC-16_3.9x9.9mm_P1.27mm | LCSC C15846 · fp ok | PASS |
+| I41 | H-02 | U10 | value ∋ 752; C57156 | LCSC C57156 · val SC16IS752IPW | PASS |
+| I42 | H-02 | R53 | value ∋ 499k; C177479 | LCSC C177479 · val 499k/1% | PASS |
+| I43 | A-04 | R121 | value ∋ 57.6k; C23082; 1:/VEH5V 2:/FB_PWRIN | LCSC C23082 · val 57.6k/1% · 1:/VEH5V 2:/FB_PWRIN | PASS |
+| I44 | A-05 | C161 | value ∋ 47; C5440143; C_1210_3225Metric; fitted; 1:/MAIN5V 2:GND | LCSC C5440143 · val 47uF · fp ok · fitted · 1:/MAIN5V 2:GND | PASS |
+| I45 | A-05 | C162 | value ∋ 47; C5440143; C_1210_3225Metric; fitted; 1:/MAIN5V 2:GND | LCSC C5440143 · val 47uF · fp ok · fitted · 1:/MAIN5V 2:GND | PASS |
+| I46 | A-08 | U17 | value ∋ TLV1117LV33; C15578; 1:GND 2:/3V3 3:/LDO_IN | LCSC C15578 · val TLV1117LV33DCYR · 1:GND 2:/3V3 3:/LDO_IN | PASS |
+| I47 | A-09 | C78 | value ∋ 220; C881921; CP_Elec_6.3x7.7; 1:/VEH5V 2:GND | LCSC C881921 · val 220uF/16V polymer · fp ok · 1:/VEH5V 2:GND | PASS |
+| I48 | B-02 | C130 | value ∋ 220; C881921; CP_Elec_6.3x7.7; 1:/VBAT_MODEM 2:GND | LCSC C881921 · val 220uF/16V polymer · fp ok · 1:/VBAT_MODEM 2:GND | PASS |
+| I49 | B-02 | C131 | value ∋ 220; C881921; CP_Elec_6.3x7.7; 1:/VBAT_MODEM 2:GND | LCSC C881921 · val 220uF/16V polymer · fp ok · 1:/VBAT_MODEM 2:GND | PASS |
+| I50 | B-02 | R116 | value ∋ 113k; C22862 | LCSC C22862 · val 113k/1% | PASS |
+| I51 | B-02 | C141 | value ∋ 6.8n; C1542; C_0402_1005Metric | LCSC C1542 · val 6.8nF · fp ok | PASS |
+| I52 | B-02 | C142 | value ∋ 56p; C1572; C_0402_1005Metric | LCSC C1572 · val 56pF · fp ok | PASS |
+| I53 | B-02 | C166 | value ∋ 22u; C86817; C_0805_2012Metric; 1:/VBAT_MODEM 2:GND | LCSC C86817 · val 22uF · fp ok · 1:/VBAT_MODEM 2:GND | PASS |
+| I54 | B-02 | C167 | value ∋ 22u; C86817; C_0805_2012Metric; 1:/VBAT_MODEM 2:GND | LCSC C86817 · val 22uF · fp ok · 1:/VBAT_MODEM 2:GND | PASS |
+| I55 | F-03 | C163 | value ∋ 22u; C86817; C_0805_2012Metric; 1:/MAIN5V 2:GND | LCSC C86817 · val 22uF · fp ok · 1:/MAIN5V 2:GND | PASS |
+| I56 | F-03 | C164 | value ∋ 22u; C86817; C_0805_2012Metric; 1:/MAIN5V 2:GND | LCSC C86817 · val 22uF · fp ok · 1:/MAIN5V 2:GND | PASS |
+| I57 | F-03 | C165 | value ∋ 220; C881921; CP_Elec_6.3x7.7; 1:/MAIN5V 2:GND | LCSC C881921 · val 220uF/16V polymer · fp ok · 1:/MAIN5V 2:GND | PASS |
+| I58 | F-51 | U29 | value ∋ TMP102; C99269; SOT-563; 1:/I2C_SCL 2:GND 4:GND 5:/3V3 6:/I2C_SDA | LCSC C99269 · val TMP102AIDRLR · fp ok · 1:/I2C_SCL 2:GND 4:GND 5:/3V3 6:/I2C_SDA | PASS |
+| I59 | F-51 | C168 | value ∋ 100n; C14663; /3V3↔GND | LCSC C14663 · val 100nF · {'1': '/3V3', '2': 'GND'} | PASS |
+| I60 | F-51 | R137 | value ∋ 100k; C25803; /NTC↔/NTC_CELL | LCSC C25803 · val 100k/1% · {'1': '/NTC', '2': '/NTC_CELL'} | PASS |
+| I61 | F-51 | R138 | value ∋ 120k; C25808; /NTC_CELL↔GND | LCSC C25808 · val 120k/1% · {'1': '/NTC_CELL', '2': 'GND'} | PASS |
+| I62 | F-51 | C169 | value ∋ 10n; C1589; /NTC_CELL↔GND | LCSC C1589 · val 10nF · {'1': '/NTC_CELL', '2': 'GND'} | PASS |
+| I63 | F-51 | U16 | 25:/NTC_CELL | 25:/NTC_CELL | PASS |
+| I64 | C-02 | U21 | value ∋ TPS7A2033; C2862740; 1:/SW_5V 2:GND 3:/SW_5V 5:/3V3_GNSS | LCSC C2862740 · val TPS7A2033PDBVR · 1:/SW_5V 2:GND 3:/SW_5V 5:/3V3_GNSS | PASS |
+| I65 | E-01 | U12 | 2:/ETH_PWR_EN 7:/SYS5V | 2:/ETH_PWR_EN 7:/SYS5V | PASS |
+| I66 | E-01 | U16 | 54:/ETH_PWR_EN | 54:/ETH_PWR_EN | PASS |
+| I67 | E-01 | R139 | value ∋ 100k; C25803; /ETH_PWR_EN↔GND | LCSC C25803 · val 100k · {'1': '/ETH_PWR_EN', '2': 'GND'} | PASS |
+| I68 | E-02 | R140 | value ∋ 4.7k; C23162; R_0603_1608Metric; /ETH_RST↔GND | LCSC C23162 · val 4.7k · fp ok · {'1': '/ETH_RST', '2': 'GND'} | PASS |
+| I69 | D-01 | U27 | value ∋ 74LVC1G125; C12518; 1:GND 2:/DOUT_4G 3:GND 4:/DOUT_4G_F9P 5:/3V3_GNSS | LCSC C12518 · val 74LVC1G125GV,125 · 1:GND 2:/DOUT_4G 3:GND 4:/DOUT_4G_F9P 5:/3V3_GNSS | PASS |
+| I70 | D-01 | C170 | C14663; /3V3_GNSS↔GND | LCSC C14663 · {'1': '/3V3_GNSS', '2': 'GND'} | PASS |
+| I71 | D-01 | U18 | 26:/DOUT_4G_F9P | 26:/DOUT_4G_F9P | PASS |
+| I72 | D-01 | /DOUT_4G_F9P | = {U18.26, U27.4} | [('U18', '26'), ('U27', '4')] | PASS |
+| I73 | D-01 | Rdfu1 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS |
+| I74 | G-02 | U30 | value ∋ USBLC6; C7519; SOT-23-6; 1:/USB_DM 2:GND 3:/USB_DP 4:/USB_DP 5:/USB_VBUS 6:/USB_DM | LCSC C7519 · val USBLC6-2SC6 · fp ok · 1:/USB_DM 2:GND 3:/USB_DP 4:/USB_DP 5:/USB_VBUS 6:/USB_DM | PASS |
+| I75 | H-02b | R56 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS |
+| I76 | H-02b | R57 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS |
+| I77 | H-02b | R58 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS |
+| I78 | H-02b | R85 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS |
+| I79 | H-02b | R87 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS |
+| I80 | H-02b | Rgs1 | value ∋ 100k; C25803 | LCSC C25803 · val 100k | PASS |
+| I81 | A-11 | R56 | 1:/CHRG_EN 2:/3V3 | 1:/CHRG_EN 2:/3V3 | PASS |
+| I82 | A-13 | R141 | value ∋ 100k; C25803; /3V3↔/PFO | LCSC C25803 · val 100k · {'1': '/3V3', '2': '/PFO'} | PASS |
+| I83 | A-13 | /PFO | = {R141.2, TP2.1, U16.29, U6.20} | [('R141', '2'), ('TP2', '1'), ('U16', '29'), ('U6', '20')] | PASS |
+| I84 | B-09 | R132 | value ∋ 22; C23345; R_0603_1608Metric | LCSC C23345 · val 22R · fp ok | PASS |
+| I85 | B-09 | R133 | value ∋ 22; C23345; R_0603_1608Metric | LCSC C23345 · val 22R · fp ok | PASS |
+| I86 | B-09 | R134 | value ∋ 22; C23345; R_0603_1608Metric | LCSC C23345 · val 22R · fp ok | PASS |
+| I87 | B-09 | C171 | value ∋ 100n; C1525; C_0402_1005Metric; /SIMB_VDD↔GND | LCSC C1525 · val 100nF · fp ok · {'1': '/SIMB_VDD', '2': 'GND'} | PASS |
+| I88 | B-10 | R142 | value ∋ 100k; C25803; /MODEM_STATUS↔GND | LCSC C25803 · val 100k · {'1': '/MODEM_STATUS', '2': 'GND'} | PASS |
+| I89 | B-10 | R143 | value ∋ 100k; C25803; /3V3↔/DIN_4G | LCSC C25803 · val 100k · {'1': '/3V3', '2': '/DIN_4G'} | PASS |
+| I90 | B-10 | R106 | value ∋ 1k; C14676 | LCSC C14676 · val 1k | PASS |
+| I91 | C-07 | TP10 | excl. BOM/pos; 1:/GNSS_SAFEBOOT_N | excl BOM · 1:/GNSS_SAFEBOOT_N | PASS |
+| I92 | C-07 | TP11 | excl. BOM/pos; 1:/GNSS_RESET_N | excl BOM · 1:/GNSS_RESET_N | PASS |
+| I93 | C-07 | /GNSS_SAFEBOOT_N | = {TP10.1, U18.50} | [('TP10', '1'), ('U18', '50')] | PASS |
+| I94 | C-07 | /GNSS_RESET_N | ⊇ {TP11.1, U18.49} | [('R105', '2'), ('TP11', '1'), ('U16', '53'), ('U18', '49')] | PASS |
+| I95 | D-02 | Y3 | value ∋ 25; C2901684; Crystal_SMD_3225-4Pin_3.2x2.5mm; 1:/HSE_IN 2:GND 3:/HSE_OUT 4:GND | LCSC C2901684 · val 25MHz · fp ok · 1:/HSE_IN 2:GND 3:/HSE_OUT 4:GND | PASS |
+| I96 | D-02 | C113 | value ∋ 12p; C38523 | LCSC C38523 · val 12pF | PASS |
+| I97 | D-02 | C114 | value ∋ 12p; C38523 | LCSC C38523 · val 12pF | PASS |
+| I98 | D-03 | Y4 | C48615; Crystal_SMD_3215-2Pin_3.2x1.5mm | LCSC C48615 · fp ok | PASS |
+| I99 | D-03 | C115 | value ∋ 6.8p; C1679 | LCSC C1679 · val 6.8pF | PASS |
+| I100 | D-03 | C116 | value ∋ 6.8p; C1679 | LCSC C1679 · val 6.8pF | PASS |
+| I101 | D-05 | Rigb1 | value ∋ 2.2k; C4190 | LCSC C4190 · val 2.2k | PASS |
+| I102 | D-09 | R144 | value ∋ 100k; C25803; /BASE_LS↔GND | LCSC C25803 · val 100k · {'1': '/BASE_LS', '2': 'GND'} | PASS |
+| I103 | D-12 | TP9 | excl. BOM/pos; 1:/USART1_TX | excl BOM · 1:/USART1_TX | PASS |
+| I104 | D-12 | U16 | 42:/USART1_TX | 42:/USART1_TX | PASS |
+| I105 | E-03 | Y1 | C14872; Crystal_SMD_HC49-SD | LCSC C14872 · fp ok | PASS |
+| I106 | E-03 | C95 | value ∋ 33p; C1663 | LCSC C1663 · val 33pF | PASS |
+| I107 | E-03 | C96 | value ∋ 33p; C1663 | LCSC C1663 · val 33pF | PASS |
+| I108 | E-04 | C91 | value ∋ 10n; C1589; C_0603_1608Metric; 1:/ETH_1V2 | LCSC C1589 · val 10nF · fp ok · 1:/ETH_1V2 | PASS |
+| I109 | E-04 | C90 | value ∋ 4.7u; C1779; C_0805_2012Metric; 1:/ETH_TOCAP | LCSC C1779 · val 4.7uF · fp ok · 1:/ETH_TOCAP | PASS |
+| I110 | E-04 | C172 | value ∋ 100n; C14663; /3V3_ETH↔GND | LCSC C14663 · val 100nF · {'1': '/3V3_ETH', '2': 'GND'} | PASS |
+| I111 | E-04 | C173 | value ∋ 100n; C14663; /3V3_ETH↔GND | LCSC C14663 · val 100nF · {'1': '/3V3_ETH', '2': 'GND'} | PASS |
+| I112 | F-52 | U31 | value ∋ TMP102; C99269; SOT-563; 1:/I2C_SCL 2:GND 4:/3V3 5:/3V3 6:/I2C_SDA | LCSC C99269 · val TMP102AIDRLR · fp ok · 1:/I2C_SCL 2:GND 4:/3V3 5:/3V3 6:/I2C_SDA | PASS |
+| I113 | G-03 | P11 | C5160226; PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal; fitted | LCSC C5160226 · fp ok · fitted | PASS |
+| I114 | G-03 | P12 | C5160226; PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal; fitted | LCSC C5160226 · fp ok · fitted | PASS |
+| I115 | G-03 | J10 | C12074; RJ45_Hanrun_HR911105A_Horizontal; fitted | LCSC C12074 · fp ok · fitted | PASS |
+| I116 | G-04 | JP6 | SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm; excl. BOM/pos; /MAIN5V↔/SYS5V | fp ok · excl BOM · {'1': '/MAIN5V', '2': '/SYS5V'} | PASS |
+| I117 | G-08 | D36 | value ∋ PESD5V0S1BA; C2827694; D_SOD-323; 1:/NRST 2:GND | LCSC C2827694 · val PESD5V0S1BA · fp ok · 1:/NRST 2:GND | PASS |
+| I118 | G-08 | D37 | value ∋ PESD5V0S1BA; C2827694; D_SOD-323; 1:/NTC_TEMP 2:GND | LCSC C2827694 · val PESD5V0S1BA · fp ok · 1:/NTC_TEMP 2:GND | PASS |
+| I119 | G-08 | D38 | value ∋ PESD5V0S1BA; C2827694; D_SOD-323; 1:/NTC2 2:GND | LCSC C2827694 · val PESD5V0S1BA · fp ok · 1:/NTC2 2:GND | PASS |
+| I120 | G-08 | /NRST | ⊇ {P6.1} | [('C104', '1'), ('D36', '1'), ('P6', '1'), ('SW1', '1'), ('TP5', '1'), ('U16', '7')] | PASS |
+| I121 | G-08 | /NTC_TEMP | ⊇ {P7.1} | [('C24', '1'), ('D37', '1'), ('P7', '1'), ('R42', '2'), ('U16', '27')] | PASS |
+| I122 | G-08 | /NTC2 | ⊇ {P8.1} | [('C157', '1'), ('D38', '1'), ('P8', '1'), ('R126', '2'), ('U16', '24')] | PASS |
+| I123 | H-08 | C22 | value ∋ 10uF/50V | val 10uF/50V | PASS |
+| I124 | H-08 | Y2 | value ∋ 3.6864MHz | val 3.6864MHz | PASS |
+| I125 | B-15 | R107 | value ∋ NEVER; DNP | val 0R-NEVER-FIT · DNP | PASS |
+| I126 | B-15 | R108 | value ∋ NEVER; DNP | val 0R-NEVER-FIT · DNP | PASS |

03-Architecture-Hardware/2026-09-29_Drogheda_EinarBoard-V5.6_Datasheet_ES_v1.0.md

@@ -2,7 +2,7 @@
 title: "EinarBoard V5.6 (HBOX V5) — Hoja de datos de ingeniería"
 project: Project Drogheda
 date: 2026-09-29
-version: "1.0"
+version: "1.1"
 status: BORRADOR para revisión de ingeniería — V5.6 con ECO aplicada en esquemático; PCB pendiente de *Update PCB*
 tags: [project-drogheda, hardware, einarboard, v5.6, datasheet, hbox]
 author: Helgen Technologies
@@ -33,7 +33,7 @@ V5.6 = V5.5 (15 pzas, JLC 22-ago-2026) + ECO 27/28-sep: riel del módem en `SYS5
 | Proyecto KiCad | `03-Architecture-Hardware/kicad/hbox-watchdog-v5.*` (V5.5 y V5.6 comparten proyecto; V5.6 = ECO aplicada al esquemático el 28-sep; PCB pendiente de *Update PCB from Schematic*; etiqueta git `v5.5-as-fabbed` guarda el estado del lote anterior) | Informe de cambios §9 |
 | MCU | U16 **STM32F411RET6** LQFP-64 soldado (ya no hay Blackpill en zócalo) · HSE Y3 25 MHz · LSE Y4 32.768 kHz · SYSCLK 96 MHz, USB 48 MHz | `board_v5.h`, `.ino` |
 | Módulos en zócalo | **MOD1** simpleRTK2B (u-blox ZED-F9P, formato UNO) · **J7/J8** 4G NTRIP Master (formato XBee, paso 2.00 mm) | netlist |
-| Firmware | `hbox_v5_bringup` **0.6.0** (`hbox-v5-bringup_0.6.0.bin`), consola USB CDC en J11 | `README.md` |
+| Firmware | `hbox_v5_bringup` **0.6.1** (`hbox-v5-bringup_0.6.1.bin`), consola USB CDC en J11. Umbrales de batería de Li-ion (flotación 4.00 V, corte 3.40 V, LEDs, monitor): con el paquete LFP-HT hace falta un build propio con flotación 3.50 V y esos umbrales recalculados (0.7.0 en la ECO, §H) | `README.md` |
 | Lote V5.5 | 15 pzas, JLCPCB 22-ago-2026 | FACTS / procedimiento v5 |
 | Lote V5.6 | Por pedir (semana del 29-sep-2026); BOM 94 LCSC comprobados para 30 tarjetas | Informe §10 |
 | Componentes / nets | 252 componentes · 237 nets en la netlist V5.6 | netlist |
@@ -255,13 +255,13 @@ Pinout completo pin a pin (generado de la netlist): [Pinout de arneses y conecto
 | USB J11 / J9 | 5 V | — | 5.5 V; ESD PESD5V0S1BA (J11) / USBLC6-2SC6 (J9) | netlist |
 | Bus RS-485 | — | — | Terminación 120 Ω opcional (JP5); SP3485 ±7 V modo común (datasheet) | netlist |
 
-## 9. Interfaz de firmware (`hbox_v5_bringup` 0.6.0)
+## 9. Interfaz de firmware (`hbox_v5_bringup` 0.6.1)
 
 | Ítem | Valor |
 |---|---|
-| Consola | USB CDC en **J11**, 115200 (el baud no importa en CDC), líneas CR+LF. Primera línea: `hbox_v5_bringup 0.6.0 built …`, luego `board=EinarBoard v5 (HBOX v5)` |
+| Consola | USB CDC en **J11**, 115200 (el baud no importa en CDC), líneas CR+LF. Primera línea: `hbox-v5-bringup 0.6.1 built …`, luego `board=EinarBoard v5 (HBOX v5)` |
-| Compilación | `arduino-cli` STM32duino 3.x, FQBN `GenF4:pnum=GENERIC_F411RETX,usb=CDCgen,xserial=generic,rtlib=nanofp`, `-DHSE_VALUE=25000000UL`; variante Ethernet de banco `-DENABLE_ETH=1` (0.6.0-eth); `-DENABLE_CHARGE=0` = cargador siempre OFF (0.5.x) |
+| Compilación | `arduino-cli` STM32duino 3.x, FQBN `GenF4:pnum=GENERIC_F411RETX,usb=CDCgen,xserial=generic,rtlib=nanofp`, `-DHSE_VALUE=25000000UL`; variante Ethernet de banco `-DENABLE_ETH=1` (0.6.1-eth); `-DENABLE_CHARGE=0` = cargador siempre OFF (0.5.x) |
-| Flasheo | DFU por J11: SW2 pulsado → SW1 pulsar/soltar → soltar SW2 → `dfu-util -a 0 -s 0x08000000:leave -D hbox-v5-bringup_0.6.0.bin` (o STM32CubeProgrammer, USB, `0x08000000`) |
+| Flasheo | DFU por J11: SW2 pulsado → SW1 pulsar/soltar → soltar SW2 → `dfu-util -a 0 -s 0x08000000:leave -D hbox-v5-bringup_0.6.1.bin` (o STM32CubeProgrammer, USB, `0x08000000`) |
 | Modo por defecto | **AUTO** (flash byte `0x5A` = MANUAL): la etapa se enciende sola 3 s después de haber 5 V en P2; respaldo continuo en batería; reset del MCU al volver el 5 V tras ≥ 10 s de respaldo |
 | Watchdog | IWDG 16 s |
 
@@ -287,16 +287,16 @@ Pinout completo pin a pin (generado de la netlist): [Pinout de arneses y conecto
 | `LSE_Y4` | LSERDY = 1 (Y4 32.768 kHz) |
 | `I2C` ×4 | ACK de PCF8574 0x20, SHT40 0x44, TMP102 0x48, SC16IS752 0x4D (+ escaneo 0x08–0x77) <!-- VERIFICAR: 0.6.0 no incluye U18 0x49 en la lista; añadir en 0.6.x --> |
 | `TMP102` / `SHT40` | Lectura entre −20 y +85 °C |
-| `SC16IS752` | Registro *scratchpad* lee lo escrito (sin *loopback* de canal todavía; previsto 0.6.1) |
+| `SC16IS752` | Registro *scratchpad* lee lo escrito (sin *loopback* de canal todavía; previsto en un build posterior, no en 0.6.1) |
 | `GAUGE_WALK` | Visual: DB1→DB4 y luego R, G, B |
 | `ADC` / `DIN` | Informativos: `vbat v5 ntc mcu` y `ign chrg fault ser_irq eth_int` |
 | Resultado | `---- RESULT: n PASS / m FAIL ----` → `>>> BOARD OK` o `>>> BOARD CHECK FAILED` |
 
 ### 9.3 Línea `STAT` (cada 5 s)
 
-`STAT up= vbat= v5=(ok|BAJO|no) ign= chrg= flt= tntc= tbat= tair= rh= tmcu= i2cerr= stack= modo= fan= rec= [LIMP] [backup=] [duty=…] carga=FASE [+CALIENTE][+OP] pin= ltc= cortes= modoB= relay= phlg_aire= v5min= vbatmin= bkp= mrst= [eth=… ip= lineas= bytes= drop= conn=] [t_on= nmea= bad= gga= sats= hdop= age= rtcm_age= sta= rtcm_last= sag5= sagb= flat= modem=]`
+`STAT up= vbat= v5=(ok|BAJO|no) ign= chrg= flt= tntc= tbat= tair= rh= tmcu= i2cerr= stack= modo= fan= rec= [LIMP] [backup=] [duty=…] carga=FASE [+CALIENTE][+OP] pin= ltc= cortes=n(duro/sost) media= duty= cargado= [caida=] vdda= modoB= relay= phlg_aire= v5min= vbatmin= bkp= mrst= [eth=… ip= lineas= bytes= drop= conn=] [t_on= nmea= bad= gga= sats= hdop= age= rtcm_age= sta= rtcm_last= sag5= sagb= flat= modem=]`
 
-Fases del gobernador de carga (`carga=`): `HOLDOFF` (< 120 s tras boot/STACK ON) · `NOTRUN` · `BATT` · `WAIT` (riel 4.90–5.05 V) · `PROVING n/30s` · `ON` · `SHED` · `COOLDOWN faltan s`. Umbrales: arranque ≥ 5.05 V estable 30 s, corte < 4.90 V (muestra rápida), enfriamiento 60 s → 30 min, celda ≥ 45 °C inhibe.
+Fases del gobernador de carga (`carga=`, 0.6.1): `HOLDOFF` (< 120 s tras boot/STACK ON) · `NOTRUN` · `PWRCYC` · `BATT` · `WAIT` (riel bajo 5.05 V, o espera tras una caída sin corriente de carga) · `PROVING n/30s` · `ON` · `SHED` (3 s mientras se clasifica un corte) · `COOLDOWN faltan s` (tras un corte contado). Umbrales: arranque con la media de 200 ms ≥ 5.05 V durante 30 s; corte DURO con una muestra rápida < 4.70 V, SOSTENIDO con la media de 200 ms < 4.90 V durante 1 s o < 4.85 V; enfriamiento 60 s → 30 min (se duplica por corte contado); celda ≥ 45 °C inhibe. PFI real 4.40 V. Detalle: [notas de versión](../descargas/notas-de-version.md).
 
 ### 9.4 Trama `$PHLG` (cada 10 s en consola, cada 30 s en banda; checksum XOR)
 
@@ -342,5 +342,6 @@ Fuente: Informe de cambios §1 (tabla antes → después), §2–§3 (partes y p
 | Versión | Fecha | Cambios |
 |---|---|---|
 | 1.0 | 2026-09-29 | Primera versión (V5.6 con ECO en esquemático; PCB pendiente) |
+| 1.1 | 2026-09-29 | Firmware 0.6.1: consola, `STAT`, fases y umbrales del gobernador de carga; el lazo serie no está en 0.6.1; con paquete LFP-HT hace falta otro build (flotación 3.50 V y umbrales de batería de LFP). |
 
 Ver también: [manual V5](../manuales/manual-tarjeta-V5.md) · [pinout V5.6](v56-pinout.md) · [informe de cambios](v56-cambios-esquematico.md) · [ECO](v56-eco.md) · [instrucciones de layout](v56-layout-instrucciones.md).

03-Architecture-Hardware/2026-09-29_Drogheda_EinarBoard-v6_Proximos-Pasos-Pedido_v1.0.md

@@ -0,0 +1,184 @@
+---
+title: "EinarBoard v6 — Próximos pasos para ordenar (29-sep-2026)"
+tags: [project-drogheda, hardware, hbox, v6, pcb, pedido, jlcpcb, proximos-pasos]
+project: Project Drogheda
+author: Helgen Technologies
+date: 2026-09-29
+version: 1.0
+status: ACTIVO — camino crítico al pedido de v6
+audience: Leo, Michelle (layout), compras
+---
+
+# EinarBoard v6 — Próximos pasos para ordenar (29-sep-2026)
+
+!!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide"
+    Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios.
+
+Esta página es la versión corta: **qué falta, en qué orden, quién lo hace y cuánto tarda**. Las cifras de cada paso
+(anchos, distancias, número de vías, piezas) están en el [Plan de corrección y estado](v6-plan-correccion.md).
+
+!!! danger "Hoy todavía no se puede ordenar: el PCB no tiene ninguna corrección"
+    - **Esquemático: listo y verificado** (`d58a89ba…e7b`, ERC 0 errores). Todos los puertos revisados de punta a punta.
+    - **PCB: sin actualizar.** `hbox-watchdog-v6.kicad_pcb` sigue igual que el 28-sep a las 11:36 (`6ddec80d…`). No se ha
+      hecho *Actualizar PCB desde esquemático* ni el layout de las correcciones.
+    - Si se ordena así, la tarjeta sale con los 11 Blockers: rama de 24 V sin fusible, ignición a 0.22 mm de 5 V en
+      capa interna (la geometría del corto del 23-jul), RS-232 imposible de soldar, cargador LTC4040 sin disipar,
+      JP2 en Li-ion con paquete LFP, entre otros. Eso obliga a otra versión, que es justo lo que no queremos.
+    - **Fecha realista de pedido: viernes 2-oct** si Michelle trabaja en esto desde hoy (jueves 1-oct si todo sale a la
+      primera). Son estimaciones; el detalle está en la tabla de abajo.
+
+---
+
+## 1. Camino crítico
+
+| # | Paso | Quién | Tiempo estimado | Listo cuando |
+|---|---|---|---|---|
+| 1 | [Subir los cambios de v6 a git y publicar el sitio](#paso-1-leo-subir-a-git-y-publicar-hoy) | Leo | 15 min | Michelle hace `git pull` y ve el esquemático `d58a89ba…` |
+| 2 | [Pre-órdenes y compras](#paso-2-compras-hoy-en-paralelo) (en paralelo) | Leo / compras | 30 min hoy; las piezas pre-ordenadas suelen tardar unos días hábiles en quedar disponibles en JLC | THVD1410DR, TPS7A2033PDBVR y J14 en «Pre-ordered» de la cuenta |
+| 3 | [Actualizar el PCB y colocar las piezas nuevas](#paso-3-michelle-actualizar-el-pcb) | Michelle | 3–4 h | Paso 0 de su lista cerrado |
+| 4 | [Layout de las correcciones](#paso-4-michelle-layout-en-este-orden) | Michelle | 2–2.5 días | Lista L-1…L-67 cerrada |
+| 5 | [Rellenar zonas y DRC](#paso-5-michelle-drc-la-puerta-de-salida) | Michelle | 2–4 h | **0 errores de separación**, 0 sin conectar |
+| 6 | [Re-auditoría del PCB](#paso-6-claude-re-auditoria-del-pcb) | Claude | 1–2 h después del push | GO por escrito en este sitio |
+| 7 | [Archivos y pedido](#paso-7-leo-archivos-y-pedido) | Leo | 1 h | Pedido en JLC |
+
+El paso 1 bloquea todo lo demás: **sin él, Michelle no puede traer el esquemático corregido.**
+El paso 2 no depende de nadie y es lo que más tarda en llegar, así que conviene hacerlo hoy.
+
+---
+
+## Paso 1 — Leo: subir a git y publicar (hoy)
+
+Los cambios de v6 de la noche del 28-sep **no están en ningún commit**: el último commit de `HBox_PCB` es de la V5.6
+(`b1e1677`), y el sitio se publicó antes de que existieran las páginas de v6. Los comandos, en este orden:
+
+```bash
+# 1) Repo de KiCad (HBox_PCB): solo los archivos de v6
+cd ~/Documents/Claude/Projects/Drogheda/03-Architecture-Hardware/kicad
+git add hbox-watchdog-v6.kicad_sch hbox-watchdog-v6.kicad_pro hbox-watchdog-v6.kicad_dru \
+  Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod
+git commit -m "v6: correcciones de auditoría, puertos, revisión final y estrapes LFP (sch d58a89ba)"
+git push helgen main
+
+# 2) Sitio (hbox-docs)
+cd ../../hbox-docs
+git status
+git add -A && git commit -m "v6: próximos pasos, plan de corrección, cambios, puertos, revisión final, auditoría EN"
+git push
+
+# 3) Repo padre (Drogheda): fuentes, PDF del esquemático y los dos submódulos
+cd ..
+git add 03-Architecture-Hardware/2026-09-2*_Drogheda_EinarBoard-v6_*.md 03-Architecture-Hardware/pinmap-v6.md \
+  03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf 03-Architecture-Hardware/2026-09-28_v6-audit-attachments \
+  03-Architecture-Hardware/kicad hbox-docs
+git -c diff.ignoreSubmodules=none commit -m "v6: auditoría, correcciones de esquemático y próximos pasos (fuentes + gitlinks)"
+git push helgen main
+
+# 4) Publicar el sitio
+cd hbox-docs && ./scripts/deploy.sh
+```
+
+Después, avisar a Michelle con la liga a esta página.
+
+---
+
+## Paso 2 — Compras hoy, en paralelo
+
+- [ ] **Pre-órdenes en la cuenta de JLC** (categoría «Pre-ordered»; sin esto JLC no las coloca):
+      **THVD1410DR (C2671345)**, **TPS7A2033PDBVR (C2862740)** y **J14 (C2977286)**.
+      Si el pedido llega a ≳ 100 tarjetas: pre-ordenar también U18 (ZED-F9P) y U19 (A7670SA).
+- [ ] **Conectores hembra de P11/P12:** DEGSON **15EDGK-3.5-03P, 2 por tarjeta** (no van en el BOM de la tarjeta).
+- [ ] **Paquete de respaldo para las pruebas:** LFP-HT 26650 4P con NTC 10 k **B3380**, el mismo de V5.6.
+- [ ] **Cotizar el PCB** para tener costo y tiempo listos: 4 capas, 1.6 mm, **JLC04161H-7628 con control de impedancia**,
+      **ENIG**, **cobre interno 1 oz**, rayos X en U18/U19, vías tapadas bajo U18/U19.
+- [ ] **Cantidad:** 20 prototipos (decisión D14 del plan).
+
+---
+
+## Paso 3 — Michelle: actualizar el PCB
+
+Detalle completo: [paso 0 de la lista de Michelle](v6-plan-correccion.md#5-lista-de-trabajo-de-michelle-layout).
+
+1. `git pull` en `HBox_PCB`. Si KiCad tenía la v6 abierta, **cerrar sin guardar** antes del pull.
+2. Abrir `hbox-watchdog-v6` y correr *Herramientas → Actualizar PCB desde esquemático* con
+   **«Eliminar huellas sin símbolo»** marcado (así desaparecen D20 y D21) y reemplazando las huellas que cambiaron:
+   U15 (SOIC-16 angosto), D28 (0402), Y3 (3225 de 4 pads), JP1 (Bridged), **JP2 (Bridged23, LFP)**, J10/P11/P12 (ya
+   poblados), L2/L6/L8/L20 (`Drogheda-v6:IND-SMD_MWSA0804S`).
+3. Colocar las **46 piezas nuevas** junto a su bloque. La lista con su lugar está en el
+   [resumen de cambios](v6-cambios-resumen.md).
+4. Revisar que queden **35 piezas DNP**, y que U25 ya no tenga el campo `LCSC Part` (refrescar su huella desde la librería).
+
+---
+
+## Paso 4 — Michelle: layout, en este orden
+
+Los números L-x son los de la [lista de trabajo](v6-plan-correccion.md#5-lista-de-trabajo-de-michelle-layout),
+donde está cada cifra. El orden va de lo que más riesgo tiene a lo que menos.
+
+| Orden | Bloque de la lista | Pasos | Por qué va en este lugar | Tiempo estimado |
+|---|---|---|---|---|
+| 1 | A · Reglas DRC y stackup | L-1…L-4 | Sin esto el DRC no ve los errores de 24 V | 0.5 h |
+| 2 | B · Entrada de 24 V e ignición | L-5…L-10, L-62 | Seguridad: fusible primero, rama sin fusible fuera, ignición lejos de 5 V (corto del 23-jul) | 2 h |
+| 3 | C · Cargador LTC4040 e inductores | L-11…L-19, L-53/L-63, **L-67** | Lección F5 (cargador caliente, carga lenta) y **JP2 en LFP** (si no, sobrecarga a 4.00 V) | 4 h |
+| 4 | D · Reguladores conmutados | L-20…L-23 | Lazos calientes y vías en los pads térmicos | 2 h |
+| 5 | E + F · Módem, RF y GNSS | L-30…L-36, L-54, L-55, L-65, L-33, L-64, L-34 | Líneas RF a 50 Ω, módem estable en batería, antena GNSS protegida | 4 h |
+| 6 | I · Tierras y vías | L-24…L-29, L-35 | Que el LTE no desensibilice al GNSS; disipación del módem y del F9P | 3 h |
+| 7 | G + H · Puertos, cristales y Ethernet | L-49…L-52, L-56, L-57, L-39, L-44, L-66, L-47 | **Todos los puertos funcionan** (RS-485, RS-232, Ethernet) | 3 h |
+| 8 | J · Conectores y barrenos | L-40…L-43, L-58 | Que entre en la placa base de la V5.5 (MH4 y abrazadera) y los USB | 2 h |
+| 9 | K · Serigrafía | L-46, L-59 | Legible para ensamble y campo | 1.5 h |
+| 10 | L · Cierre | L-47, L-60, L-61 | Atributos de huella y fiduciales | 1 h |
+
+**Total estimado: 23 h de layout**, más el DRC del paso 5.
+
+!!! tip "Cómo acelerar sin saltarse nada"
+    - **Subir avances a git** después de los bloques B y C (y después de E + F). Claude revisa cada avance mientras
+      Michelle sigue con el siguiente bloque. Así los errores salen el mismo día y la re-auditoría final es corta.
+    - **No repartir el mismo archivo `.kicad_pcb` entre dos personas.** KiCad no combina bien dos ediciones del PCB.
+    - Dejar la serigrafía (bloque K) para el final: es lo único que se puede hacer rápido.
+
+---
+
+## Paso 5 — Michelle: DRC, la puerta de salida
+
+- [ ] Rellenar **todas** las zonas.
+- [ ] DRC con las reglas nuevas (ya están en `.kicad_dru`): **0 errores de separación**, **0 sin conectar**.
+- [ ] Cerrar la aceptación completa de **L-48** (en la lista de Michelle).
+- [ ] `git push` del PCB.
+
+---
+
+## Paso 6 — Claude: re-auditoría del PCB
+
+Con el PCB subido, Claude revisa (1–2 h):
+
+- esquemático ↔ PCB sincronizados: 46 piezas nuevas colocadas, 28 DNP, huellas correctas;
+- las medidas de cada Blocker: ignición y 24 V a ≥ 0.5 mm en capas internas, `/SW_BAT` ≥ 2 mm, 9 vías en el pad de U6,
+  vías bajo U18/U19, impedancia de las líneas RF, MH4 en su lugar, **JP2 puenteado 2-3**, U25 sin `LCSC Part`;
+- DRC propio con las reglas nuevas.
+
+El resultado se publica aquí como **GO / NO-GO** con la lista de lo que falte.
+
+---
+
+## Paso 7 — Leo: archivos y pedido
+
+- [ ] BOM y CPL con **Fabrication Toolkit**. Revisar que la línea de U25 diga **C524806 (TPS54360B)**, y que TP1–TP12 y
+      JP1–JP6 no aparezcan.
+- [ ] Opciones del PCB como en la cotización del paso 2 (stackup con control de impedancia, ENIG, 1 oz interno, rayos X,
+      vías tapadas).
+- [ ] Revisar rotaciones en la vista previa de JLC y el stock en el carrito.
+- [ ] Ordenar **20 prototipos**.
+
+---
+
+## Lo que NO detiene el pedido
+
+- **Firmware 0.7.x (`board_v6.h`):** hace falta para probar las tarjetas, no para ordenarlas. Se puede empezar hoy con
+  la [sección 6 del plan](v6-plan-correccion.md) y el [mapa de pines](v6-pinmap.md).
+- **Lo aceptado permanentemente** (20 puntos, sección 9 del plan): ya está decidido y documentado.
+
+## Ligas
+
+- [Plan de corrección y estado](v6-plan-correccion.md): decisiones, estado por hallazgo, puertos, lista completa de
+  Michelle con cifras, lista de liberación (GO).
+- [Cambios de esquemático: resumen de las 4 pasadas](v6-cambios-resumen.md): qué cambió y dónde van las piezas nuevas.
+- [Mapa de pines MCU v6](v6-pinmap.md) · [Auditoría completa](v6-auditoria-completa.md) ([inglés](v6-full-audit.md)).

03-Architecture-Hardware/manuales/index.md

@@ -2,21 +2,21 @@
 title: "Manuales por tarjeta"
 project: Project Drogheda
 date: 2026-09-29
-version: "1.1"
+version: "1.2"
 tags: [project-drogheda, hardware, einarboard, manual, indice]
 author: Helgen Technologies
 ---
 
 # Manuales por tarjeta
 
-Cada manual cubre cómo reconocer la tarjeta, conectores, puentes, botones, LEDs, flasheo y limitaciones. El binario lleva la tarjeta en el nombre; reglas en [Descargas](../descargas/index.md#firmware-del-hbox-que-binario-va-en-que-tarjeta).
+Cada manual cubre cómo reconocer la tarjeta, conectores, puentes, botones, LEDs, flasheo y limitaciones. El binario lleva la tarjeta en el nombre; reglas en [Descargas](../descargas/index.md#firmware-del-hbox-que-binario-va-en-que-tarjeta); qué cambia entre versiones, en las [notas de versión](../descargas/notas-de-version.md).
 
 | Tarjeta | Nombre | Estado (sep-2026) | Firmware | Proyecto KiCad | Manual |
 |---|---|---|---|---|---|
 | V3 | EinarBoard 1.0 (Blackpill en zócalo) | 10 pzas jul-2026; 3 unidades en campo (RTK-003/006/014); registro congelado | `hbox-tarjetaV3_4.0.0.bin` | `hbox-watchdog-v3-PROD` | [Manual V3](manual-tarjeta-V3.md) |
-| V4 | EinarBoard 2.0 (Blackpill + Ethernet + serie) | Fabricada ago-2026; en prueba con 0.6.0 | `hbox-tarjetaV4_0.6.0.bin` | `hbox-watchdog-v4` | [Manual V4](manual-tarjeta-V4.md) |
+| V4 | EinarBoard 2.0 (Blackpill + Ethernet + serie) | Fabricada ago-2026; en prueba con 0.6.1 | `hbox-tarjetaV4_0.6.1.bin` | `hbox-watchdog-v4` | [Manual V4](manual-tarjeta-V4.md) |
-| V5.5 | EinarBoard 4.0 (serigrafía) / HBOX v5, MCU soldado | 15 pzas 22-ago-2026; en ensamble y campo | `hbox-v5-bringup_0.6.0.bin` | `hbox-watchdog-v5` (tag `v5.5-as-fabbed`) | [Manual V5](manual-tarjeta-V5.md) |
+| V5.5 | EinarBoard 4.0 (serigrafía) / HBOX v5, MCU soldado | 15 pzas 22-ago-2026; en ensamble y campo | `hbox-v5-bringup_0.6.1.bin` | `hbox-watchdog-v5` (tag `v5.5-as-fabbed`) | [Manual V5](manual-tarjeta-V5.md) |
-| V5.6 | HBOX v5 + ECO 27/28-sep (módem controlado por MCU, LFP, sensores) | Esquemático cerrado; PCB en layout; pedido pendiente | `hbox-v5-bringup_0.6.0.bin` (0.6.x para las funciones nuevas) | `hbox-watchdog-v5` | [Manual V5](manual-tarjeta-V5.md) §9 |
+| V5.6 | HBOX v5 + ECO 27/28-sep (módem controlado por MCU, LFP, sensores) | Esquemático cerrado; PCB en layout; pedido pendiente | `hbox-v5-bringup_0.6.1.bin` solo con paquete Li-ion; firmware propio de V5.6 previsto en 0.7.0 | `hbox-watchdog-v5` | [Manual V5](manual-tarjeta-V5.md) §9 |
 | v6 | GNSS + 4G a bordo | En diseño; no pedir | — | `hbox-watchdog-v6` | [Manual v6](manual-tarjeta-v6.md) |
 
 Documentos de ingeniería: [Tarjetas y hardware](../hardware/index.md).
@@ -27,3 +27,4 @@ Documentos de ingeniería: [Tarjetas y hardware](../hardware/index.md).
 |---|---|---|
 | 1.0 | 2026-09-29 | Primera versión. |
 | 1.1 | 2026-09-29 | Edición breve; estado V5.6 alineado con la portada. |
+| 1.2 | 2026-09-29 | Firmware vigente 0.6.1 en V4 y V5.5 (V5.6 solo con paquete Li-ion); enlace a las notas de versión. |

03-Architecture-Hardware/manuales/manual-tarjeta-V4.md

@@ -2,7 +2,7 @@
 title: "Manual de tarjeta — EinarBoard V4 (EinarBoard 2.0)"
 project: Project Drogheda
 date: 2026-09-29
-version: "1.1"
+version: "1.2"
 tags: [project-drogheda, hardware, einarboard, v4, manual, tecnicos, blackpill]
 author: Helgen Technologies
 audience: técnicos de banco y de campo
@@ -19,7 +19,7 @@ Blackpill en zócalo + Ethernet y puertos serie. Es el diseño de la V5 con el M
 | Tamaño | 155 × 100 mm (20 mm más ancha que la V3, lado derecho) |
 | MCU | WeAct Blackpill STM32F411CEU6 en zócalos J1/J2 (J1 con pads renumerados: corrige la errata E-J1 de la V3) |
 | Fabricación | JLCPCB, orden preparada 02/03-ago-2026 (lote Y5) <!-- VERIFICAR: número de tarjetas fabricadas y fecha de entrega --> |
-| Firmware | `hbox-tarjetaV4_0.6.0.bin` (mismo sketch `hbox_v5_bringup` compilado con `-DHBOX_BOARD_V4` para Blackpill). SHA-256 `1458470bbdd95b49…` |
+| Firmware | `hbox-tarjetaV4_0.6.1.bin` (mismo sketch `hbox_v5_bringup` compilado con `-DHBOX_BOARD_V4` para Blackpill). SHA-256 `ef43a901ae9a875e…`. Cambios por versión: [notas de versión](../descargas/notas-de-version.md) |
 | Paquete | Li-ion 18650 1S4P · JP2 en 1-2 (`F2:Li-ion`) · R55 10 k |
 
 <!-- foto: vista superior V4 con Blackpill sentado, RJ45 arriba-izquierda, clemas P15/P16 abajo, P14 a la derecha -->
@@ -79,7 +79,7 @@ Puente de reset del módem (necesario para que el MCU resetee el módem): diodo
 
 ## 5. Flasheo
 
-Solo el USB-C del Blackpill, nada en P2 (con el W5500 alimentado, `ETH_INT` = PB2 = BOOT1 puede impedir el DFU). KEY (BOOT0) + NRST (o SW1) → `0483:DF11`. Solo `hbox-tarjetaV4_…` ([Descargas](../descargas/index.md#firmware-del-hbox-que-binario-va-en-que-tarjeta)). La consola debe decir `board=EinarBoard v4 (HBOX v4)`; si dice `v5`, es el binario equivocado. Procedimiento: [V4 — flasheo](../procedimientos/v4-prueba-fw-0.5.6.md#flasheo-de-060).
+Solo el USB-C del Blackpill, nada en P2 (con el W5500 alimentado, `ETH_INT` = PB2 = BOOT1 puede impedir el DFU). KEY (BOOT0) + NRST (o SW1) → `0483:DF11`. Solo `hbox-tarjetaV4_…` ([Descargas](../descargas/index.md#firmware-del-hbox-que-binario-va-en-que-tarjeta)). La consola debe decir `board=EinarBoard v4 (HBOX v4)`; si dice `v5`, es el binario equivocado. Procedimiento: [V4 — flasheo](../procedimientos/v4-prueba-fw-0.5.6.md#flasheo).
 
 ## 6. Consola y autotest
 
@@ -101,12 +101,12 @@ Iguales a la V5 (mismo firmware): teclas `h l r s t i g v P Y n A B M R C`, lín
 ## 8. Limitaciones conocidas (iguales a V5.5)
 
 - Módem oscuro en batería: no arranca sobre el boost; solo SW4G1 (o el puente 0.5.6 + `M`) o los 24 V lo reviven. Firmware ≥ 0.5.9: sin ciclos de etapa en batería; reset del MCU al volver el 5 V.
-- Cargador: apagado en firmware < 0.6.0; el gobernador de 0.6.0 lo habilita con 24 V y riel estable.
+- Cargador: apagado en firmware < 0.6.0; desde 0.6.0 un gobernador lo habilita con 24 V y riel estable, y 0.6.1 ya no lo corta por las ráfagas del módem. Con cable o fuente débiles hasta P2 la carga avanza despacio o se estanca ([límite de la ruta de 5 V](../descargas/notas-de-version.md#el-limite-de-la-ruta-de-5-v)).
 - Ethernet y serie sin prueba en hardware real.
 
 ## 9. Procedimientos relacionados
 
-[V4 — preparación y prueba con firmware 0.6.0](../procedimientos/v4-prueba-fw-0.5.6.md) · [Política de ventilador (banco)](../procedimientos/fan-policy-bench-test.md) · [Acta V4](../formularios/v4.html) · [Reflasheo de unidades](../procedimientos/reflasheo-unidades.md) · [Prueba módem en batería](../procedimientos/prueba-bateria-modem.md) · [Manual V5](manual-tarjeta-V5.md).
+[V4 — preparación y prueba con firmware 0.6.1](../procedimientos/v4-prueba-fw-0.5.6.md) · [Política de ventilador (banco)](../procedimientos/fan-policy-bench-test.md) · [Acta V4](../formularios/v4.html) · [Reflasheo de unidades](../procedimientos/reflasheo-unidades.md) · [Prueba módem en batería](../procedimientos/prueba-bateria-modem.md) · [Manual V5](manual-tarjeta-V5.md).
 
 ## Historial de revisiones
 
@@ -114,5 +114,6 @@ Iguales a la V5 (mismo firmware): teclas `h l r s t i g v P Y n A B M R C`, lín
 |---|---|---|
 | 1.0 | 2026-09-29 | Primera versión. |
 | 1.1 | 2026-09-29 | Edición breve; puente y flasheo remiten al procedimiento V4 (el manual listaba 1N5819, que el procedimiento prohíbe). |
+| 1.2 | 2026-09-29 | Firmware 0.6.1. |
 
 Versiones anteriores en git.

03-Architecture-Hardware/manuales/manual-tarjeta-V5.md

@@ -2,7 +2,7 @@
 title: "Manual de tarjeta — EinarBoard V5 (V5.5 y V5.6)"
 project: Project Drogheda
 date: 2026-09-29
-version: "1.1"
+version: "1.2"
 tags: [project-drogheda, hardware, einarboard, v5, v5.5, v5.6, manual, tecnicos]
 author: Helgen Technologies
 audience: técnicos de banco y de campo
@@ -16,7 +16,7 @@ Valores de ingeniería: [hoja de datos V5.6](../hardware/v56-datasheet.md). Pin
 |---|---|---|
 | Estado | 15 tarjetas fabricadas (JLCPCB, 22-ago-2026), en ensamble y en campo | Esquemático listo (ECO 27/28-sep); PCB y pedido pendientes |
 | Proyecto KiCad | `kicad/hbox-watchdog-v5.*` (etiqueta git `v5.5-as-fabbed`) | `kicad/hbox-watchdog-v5.*` (ECO aplicada) |
-| Firmware | `hbox-v5-bringup_0.6.0.bin` | `hbox-v5-bringup_0.6.0.bin` (0.6.x añadirá el control del módem) |
+| Firmware | `hbox-v5-bringup_0.6.1.bin` | `hbox-v5-bringup_0.6.1.bin` solo con paquete Li-ion; el firmware propio de V5.6 (control del módem, paquete LFP) está previsto en 0.7.0 |
 | Paquete de batería | Li-ion 18650 1S4P · JP2 en 1-2 · R55 10 k | LFP-HT 26650 · JP2 en 2-3 · R55 5.6 k · NTC B3380 |
 
 ## 1. Identificación
@@ -93,7 +93,7 @@ V5.5 igual al [pinout V5.6](../hardware/v56-pinout.md) salvo lo listado en §9.
 
 ## 6. Flasheo
 
-DFU por J11, solo USB, sin P1/P2 ni batería: mantén SW2, pulsa y suelta SW1, suelta SW2 (`STM32 BOOTLOADER`, `0483:DF11`). Procedimiento completo: [prueba y flasheo §5](../procedimientos/v5-prueba-y-flasheo.md#5-flasheo-por-usb-dfu-j11-5-min). Binario: [Descargas](../descargas/index.md). La consola debe decir `hbox_v5_bringup 0.6.0` y `board=EinarBoard v5 (HBOX v5)`.
+DFU por J11, solo USB, sin P1/P2 ni batería: mantén SW2, pulsa y suelta SW1, suelta SW2 (`STM32 BOOTLOADER`, `0483:DF11`). Procedimiento completo: [prueba y flasheo §5](../procedimientos/v5-prueba-y-flasheo.md#5-flasheo-por-usb-dfu-j11-5-min). Binario: [Descargas](../descargas/index.md). La consola debe decir `hbox-v5-bringup 0.6.1` y `board=EinarBoard v5 (HBOX v5)`.
 
 Nunca flashees `blackpillrtkcode` (V3) en una V5: usa PB12–PB15 como LEDs y en la V5 son el SPI del W5500.
 
@@ -150,14 +150,14 @@ En V5.6 el escaneo I²C (`i`) muestra además 0x49 (U18, sensor del módem).
 
 ## 10. Ethernet y puertos serie
 
-- Ethernet (J10): solo con el build de banco `0.6.0-eth`; DHCP o `192.168.7.2/24`, TCP a `192.168.7.1:5010` con NMEA + `$PHLG` + `$PHEV` + `$PHID`. Tecla `E`.
+- Ethernet (J10): solo con el build de banco `0.6.1-eth` (el `0.6.0-eth` se bloqueaba 4–5 s cada 5 s con cable directo y sin DHCP); DHCP o `192.168.7.2/24`, TCP a `192.168.7.1:5010` con NMEA + `$PHLG` + `$PHEV` + `$PHID`. Tecla `E`.
-- RS-485 (P15) / RS-232 (P16): 0.6.0 solo comprueba que el SC16IS752 responde; loopback previsto en 0.6.1.
+- RS-485 (P15) / RS-232 (P16): 0.6.0 y 0.6.1 solo comprueban que el SC16IS752 responde; el lazo (loopback) queda para un build posterior (0.6.1 salió como arreglo del cargador).
 - Procedimiento: [Ethernet y puertos serie](../procedimientos/v5-prueba-ethernet-serie.md), obligatorio en una V5.5 antes de pedir la V5.6.
 
 ## 11. Limitaciones de la V5.5
 
 - Módem oscuro en batería: si el módem se apaga en batería (ciclo de etapa, brown-out) no arranca sobre el boost del LTC4040; solo lo reviven SW4G1 o los 24 V. Por eso el firmware ≥ 0.5.9 nunca cicla la etapa en batería y resetea el MCU al volver el 5 V ([hallazgos](../procedimientos/prueba-bateria-modem.md#3-hallazgos-2527-sep)).
-- Hasta 0.5.9 el cargador estaba apagado por firmware. 0.6.0 carga con 24 V, etapa ON > 120 s y riel ≥ 5.05 V, y corta bajo 4.90 V. Reflashea unidades con firmware anterior.
+- Hasta 0.5.9 el cargador estaba apagado por firmware. Desde 0.6.0 carga con 24 V, etapa ON > 120 s y riel ≥ 5.05 V. 0.6.0, con la ruta de 5 V justa, cortaba la carga en cada ráfaga del módem; 0.6.1 la corta solo si el riel no la sostiene (media de 200 ms bajo 4.90 V durante 1 s o bajo 4.85 V, o una muestra bajo 4.70 V). Reflashea unidades con firmware anterior ([notas de versión](../descargas/notas-de-version.md)).
 - La consola no sabe si el módem está vivo: `modem=vivo|SOSPECHOSO|?` es una inferencia por RTCM y caídas del riel.
 - Ethernet y serie no se han probado en hardware real (sep-2026).
 - Y2: la pieza dice 3.6864; el esquemático V5.6 dice `1.8432MHz` <!-- VERIFICAR el campo Value en KiCad; la pieza LCSC C2238 es de 3.6864 MHz -->.
@@ -170,5 +170,6 @@ Procedimientos V5: [Producción](../produccion/index.md) · [Taller](../taller/i
 |---|---|---|
 | 1.0 | 2026-09-29 | Primera versión (V5.5 fabricada + V5.6 en esquemático). |
 | 1.1 | 2026-09-29 | Edición breve; flasheo, química/JP2 y JP5 remiten a su procedimiento. |
+| 1.2 | 2026-09-29 | Firmware 0.6.1: cargador, Ethernet de banco `0.6.1-eth`; el lazo serie no está en 0.6.1; en V5.6, 0.6.1 solo con paquete Li-ion. |
 
 Versiones anteriores en git.

03-Architecture-Hardware/pinmap-v6.md

@@ -11,7 +11,13 @@ author: Helgen Technologies
 !!! warning "EinarBoard v6 (`hbox-watchdog-v6`): en diseño, no se pide"
     Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios.
 
-Prosa y encabezados en español; la tabla de 64 pines y el borrador de `board_v6.h` se dejan en inglés (fuente directa para firmware). Fuente: `findings/pinmap-v6.md` de la [auditoría completa v6](v6-auditoria-completa.md) (§4), mismo snapshot del 2026-09-28. La tabla describe **la v6 tal como está dibujada**. Las filas marcadas ▶ audit llevan la consecuencia a nivel de pin de un hallazgo verificado de forma independiente, o de la asignación de pines libres que ambas verificaciones aceptan. Nada de esto se ha aplicado al esquemático (ver el [informe de cambios v6](v6-cambios-esquematico.md) para lo que sí se aplicó); las notas «▶ audit» dicen qué cambia si se adopta la corrección.
+!!! info "Los cambios «▶ audit» ya se aplicaron al esquemático (28-sep)"
+    Los cambios de pin marcados «▶ audit» **ya se aplicaron** al esquemático y están verificados. Los principales:
+    **PD2** = `ETH_PWR_EN` (R139 100 k a GND) · **PB10** = `PFO` (R141 100 k a `/3V3`) · **PC5** = `NTC_CELL` (toma del
+    NTC del paquete) · **PA9** = pad de depuración TP9 · **PC6** → RX del módem directo por **R148** 0 Ω (K1 DNP) ·
+    **CHGOFF** (PA8) apagado por defecto con el pull-up R56. Detalle: [Cambios de esquemático — resumen de 3 pasadas](v6-cambios-resumen.md).
+
+Prosa y encabezados en español; la tabla de 64 pines y el borrador de `board_v6.h` se dejan en inglés (fuente directa para firmware). Fuente: `findings/pinmap-v6.md` de la [auditoría completa v6](v6-auditoria-completa.md) (§4), mismo snapshot del 2026-09-28. La tabla describe **la v6 tal como está dibujada**. Las filas marcadas ▶ audit llevan la consecuencia a nivel de pin de un hallazgo verificado de forma independiente, o de la asignación de pines libres que ambas verificaciones aceptan. Desde el 28-sep, los cambios de esquemático de las filas ▶ audit ya están aplicados y verificados, salvo el strap de identificación de D-08 (la tarjeta se identifica por firmware); lo que es de layout, como mover Rig1 a P1.3, sigue pendiente (ver el [informe de cambios v6](v6-cambios-esquematico.md) y el [resumen de las 3 pasadas](v6-cambios-resumen.md)).
 
 **Correcciones aplicadas al texto original (v1.0, 2026-09-28):**
 

06-Testing-Validation/2026-09-29_Drogheda_HBOX-V5_Configuracion-de-Unidad_ES_v1.0.md

@@ -4,7 +4,7 @@ tags: [project-drogheda, hardware, hbox, v5, v5.6, configuracion, ntrip, etherne
 project: Project Drogheda
 author: Helgen Technologies
 date: 2026-09-29
-version: 1.1
+version: 1.2
 status: ACTIVO — toda unidad V5.5 / V5.6 antes de embarcar o de reinstalar
 audience: técnicos de banco
 ---
@@ -24,7 +24,7 @@ Una unidad está configurada cuando cumple las siete filas:
 | 1 | Módem 4G | Parámetros cargados (APN, caster, mountpoint, ID de estación) y registrado en Telcel | 1 |
 | 2 | simpleRTK2B (ZED-F9P) | Configuración Helgen en flash; RTK FIX (`fix=4`) con cielo | 2 |
 | 3 | Identidad | Aparece en el monitor como `H00xx` con posición y Salud | 3 |
-| 4 | Ethernet (si lo lleva) | Enlace y espejo TCP probados con `0.6.0-eth` | 4 |
+| 4 | Ethernet (si lo lleva) | Enlace y espejo TCP probados con el build de banco `0.6.1-eth` | 4 |
 | 5 | Puertos serie (si los lleva) | `[PASS] SC16IS752` y niveles correctos en P15/P16 | 4 |
 | 6 | Paquete de batería | Química = JP2; `ltc=CARGANDO` | 5 |
 | 7 | Firmware y consola | Versión vigente y `STAT` limpio | 6 |
@@ -116,5 +116,6 @@ V5.6: su firmware (`MODEM_EN`, `tchg`, `tcell`, `tmodem`) aún no existe; hasta
 |---|---|---|
 | 1.0 | 2026-09-29 | Primera versión: define "unidad configurada" para V5.5/V5.6. |
 | 1.1 | 2026-09-29 | Edición breve. Parámetros del módem → Descargas; Ethernet/serie y JP5 → prueba de Ethernet y serie; química/JP2 → ensamble §2; tabla de firmware → Descargas. |
+| 1.2 | 2026-09-29 | Ethernet con el build de banco 0.6.1-eth. |
 
 Versiones anteriores en git.

06-Testing-Validation/2026-09-29_Drogheda_HBOX-V5_Prueba-Ethernet-y-Puertos-Serie_ES_v1.0.md

@@ -4,7 +4,7 @@ tags: [project-drogheda, hardware, hbox, v5, v5.6, ethernet, w5500, rs485, rs232
 project: Project Drogheda
 author: Helgen Technologies
 date: 2026-09-29
-version: 1.1
+version: 1.2
 status: ACTIVO — obligatoria en al menos una V5.5 antes de pedir la V5.6; después, en toda unidad con RJ45 o clemas serie
 audience: técnicos de banco
 ---
@@ -15,14 +15,14 @@ audience: técnicos de banco
     - Para quién: técnicos de banco.
     - Cuándo: al menos una V5.5 antes de pedir la V5.6 (Ethernet nunca se había probado en tarjeta real y la V5.6 copia el bloque); después, toda unidad V5.5/V5.6 con RJ45 o clemas serie en el panel, dentro de la [configuración de la unidad](v5-configuracion-unidad.md).
     - Tiempo: Ethernet 15 min · serie 15 min.
-    - Necesitas: unidad V5 ensamblada (o tarjeta + simpleRTK2B para ver NMEA); 24 V al GX16 (o 5.3 V / 3 A en P2); laptop con terminal serie a 115200 grabando y `nc` (macOS/Linux) o `ncat` (Windows); binario de banco `hbox-v5-bringup_0.6.0-eth.bin` (lo compila ingeniería con `-DENABLE_ETH=1` y entrega su SHA-256) <!-- VERIFICAR: nombre y SHA-256 del binario -eth publicado -->; cable Ethernet directo cat 5e de 1–3 m (el W5500 hace Auto-MDIX); adaptadores USB-RS485 y USB-RS232 (DB9 macho) con 3 cables con puntera; multímetro; desarmador plano 2.5 mm; [acta Ethernet y puertos serie](../formularios/ethernet-serie.html).
+    - Necesitas: unidad V5 ensamblada (o tarjeta + simpleRTK2B para ver NMEA); 24 V al GX16 (o 5.3 V / 3 A en P2); laptop con terminal serie a 115200 grabando y `nc` (macOS/Linux) o `ncat` (Windows); binario de banco `hbox-v5-bringup_0.6.1-eth.bin` (lo compila ingeniería con `-DENABLE_ETH=1` y entrega su SHA-256; no uses el `0.6.0-eth`: con cable directo y sin DHCP se bloqueaba 4–5 s cada 5 s) <!-- VERIFICAR: nombre y SHA-256 del binario -eth publicado -->; cable Ethernet directo cat 5e de 1–3 m (el W5500 hace Auto-MDIX); adaptadores USB-RS485 y USB-RS232 (DB9 macho) con 3 cables con puntera; multímetro; desarmador plano 2.5 mm; [acta Ethernet y puertos serie](../formularios/ethernet-serie.html).
 
 !!! warning "Reglas"
     1. Nunca pruebes Ethernet solo en batería ni solo por USB: el W5500 cuelga de `3V3_ETH`, que sale del 5 V del sistema. Sin 5 V el firmware lo deja en reset.
     2. 5 V del sistema ≥ 5.2 V (SD-15B o fuente a ~5.3 V). Con menos, la ráfaga LTE lleva el riel al PFI 4.60 V del LTC4040 y la tarjeta se reinicia.
     3. Con fuente de banco en P2 y sin 24 V, sin paquete de batería. Lo normal: 24 V al GX16 y el SD-15B interno.
 
-## A. Ethernet (build `0.6.0-eth`)
+## A. Ethernet (build `0.6.1-eth`)
 
 ### A1. Laptop (una vez)
 
@@ -38,10 +38,10 @@ audience: técnicos de banco
 ### A2. Flasheo del build de banco
 
 1. DFU por J11, solo USB, sin 24 V ([flasheo §5](v5-prueba-y-flasheo.md#5-flasheo-por-usb-dfu-j11-5-min)).
-2. `dfu-util -a 0 -s 0x08000000:leave -D hbox-v5-bringup_0.6.0-eth.bin` o STM32CubeProgrammer.
+2. `dfu-util -a 0 -s 0x08000000:leave -D hbox-v5-bringup_0.6.1-eth.bin` o STM32CubeProgrammer.
-3. Terminal en J11: primera línea `hbox-v5-bringup 0.6.0-eth`; la ayuda (`h`) lista `E=Ethernet on/off`.
+3. Terminal en J11: primera línea `hbox-v5-bringup 0.6.1-eth`; la ayuda (`h`) lista `E=Ethernet on/off`.
 
-El build `-eth` es solo de banco: al terminar reflashea `hbox-v5-bringup_0.6.0.bin` (ver C).
+El build `-eth` es solo de banco: al terminar reflashea el binario V5 vigente de [Descargas](../descargas/index.md) (hoy `hbox-v5-bringup_0.6.1.bin`; ver C).
 
 ### A3. Secuencia
 
@@ -60,8 +60,8 @@ El build `-eth` es solo de banco: al terminar reflashea `hbox-v5-bringup_0.6.0.b
 3. En `nc` llega primero la identidad y luego el flujo. `$PHID` se repite cada 5 min; con la etapa apagada o sin simpleRTK2B solo llegan `$PHLG`/`$PHEV`.
 
     ```
-    $PHID,<UID 24 hex>,0.6.0-eth,EinarBoard v5 (HBOX v5),02:48:42:xx:xx:xx,<up_s>*CS
+    $PHID,<UID 24 hex>,0.6.1-eth,EinarBoard v5 (HBOX v5),02:48:42:xx:xx:xx,<up_s>*CS
-    $PHLG,0.6.0-eth,RUN,…
+    $PHLG,0.6.1-eth,RUN,…
     $GNGGA,…
     $GNRMC,…
     ```
@@ -101,8 +101,8 @@ El build `-eth` es solo de banco: al terminar reflashea `hbox-v5-bringup_0.6.0.b
 
 | Firmware | Prueba | Secciones |
 |---|---|---|
-| 0.6.0 / 0.6.0-eth | Presencia del SC16IS752 y niveles estáticos | B1, B2 |
+| 0.6.0 y 0.6.1 (y sus `-eth`) | Presencia del SC16IS752 y niveles estáticos | B1, B2 |
-| 0.6.1 (planeado) | Lazo interno y eco externo a 9600 8N1 | B3, B4 |
+| Build con lazo serie (planeado; no es 0.6.1) | Lazo interno y eco externo a 9600 8N1 | B3, B4 |
 
 ### B1. Presencia (0.6.x)
 
@@ -125,11 +125,11 @@ Tarjeta energizada (USB basta). Teclea `r` y busca:
 | P15.1 – P15.2 con JP5 cerrado | 0 V ± 0.2 (driver desactivado, línea terminada) <!-- VERIFICAR: estado por defecto de SER_DEA (DE/~RE de U14) tras reset del SC16IS752; si el driver arranca activo se leerá ≈ +2 V (marca) --> | ≈ 0 con JP5 abierto también es normal |
 | Ohms P15.1–P15.2, tarjeta apagada | JP5 abierto > 10 kΩ · cerrado ≈ 120 Ω (R82) | — |
 
-### B3. Lazo interno (0.6.1)
+### B3. Lazo interno (build con lazo, planeado)
 
-No cablees P15 con P16: son eléctricamente distintos. El lazo de 0.6.1 une TX→RX de cada canal dentro del SC16IS752 (MCR bit 4), sin cable: tecla de consola de 0.6.1 <!-- VERIFICAR: tecla y texto de salida del auto-test de lazo en 0.6.1 --> → `[PASS] SER_LOOP_A` / `[PASS] SER_LOOP_B`. Prueba U10 y el cristal, no los transceptores ni las clemas.
+No cablees P15 con P16: son eléctricamente distintos. El lazo une TX→RX de cada canal dentro del SC16IS752 (MCR bit 4), sin cable: tecla de consola del build con lazo <!-- VERIFICAR: tecla y texto de salida del auto-test de lazo cuando exista ese build --> → `[PASS] SER_LOOP_A` / `[PASS] SER_LOOP_B`. Prueba U10 y el cristal, no los transceptores ni las clemas.
 
-### B4. Eco externo con adaptadores (0.6.1, 9600 8N1)
+### B4. Eco externo con adaptadores (build con lazo, 9600 8N1)
 
 En modo eco, lo que entra por un puerto sale por el mismo.
 
@@ -154,10 +154,10 @@ RS-232 (P16):
 | Presencia U10 | `[PASS] SC16IS752 … SPR rd=0xA5` | 0.6.0+ |
 | Niveles RS-232 | P16.1 en −5…−6.5 V en reposo | 0.6.0+ |
 | Niveles RS-485 | A y B con nivel (no 0/0); 120 Ω A-B solo con JP5 cerrado | 0.6.0+ |
-| Lazo interno | `SER_LOOP_A` y `SER_LOOP_B` en PASS | 0.6.1 |
+| Lazo interno | `SER_LOOP_A` y `SER_LOOP_B` en PASS | build con lazo |
-| Eco RS-485 / RS-232 | 10/10 idénticas a 9600 8N1 | 0.6.1 |
+| Eco RS-485 / RS-232 | 10/10 idénticas a 9600 8N1 | build con lazo |
 
-Sin 0.6.1 el resultado se registra como "presencia + niveles OK". Basta para ordenar la V5.6 (el bloque serie no cambia). El eco se agrega al mismo acta cuando salga 0.6.1.
+Hasta que salga el build con lazo el resultado se registra como "presencia + niveles OK". Basta para ordenar la V5.6 (el bloque serie no cambia). El eco se agrega al mismo acta cuando salga ese build.
 
 ## Conexión en la instalación
 
@@ -173,16 +173,16 @@ Sin 0.6.1 el resultado se registra como "presencia + niveles OK". Basta para ord
 
 ## C. Cierre
 
-- [ ] Si la unidad se embarca, reflashea `hbox-v5-bringup_0.6.0.bin` y anótalo en el [acta de reflasheo](../formularios/reflasheo.html).
+- [ ] Si la unidad se embarca, reflashea el binario V5 vigente (`hbox-v5-bringup_0.6.1.bin`) y anótalo en el [acta de reflasheo](../formularios/reflasheo.html).
 - [ ] Retira cable y adaptadores; tapas ciegas en J10/P15/P16 que el panel no use.
 - [ ] Envía el [acta Ethernet y puertos serie](../formularios/ethernet-serie.html) con los dos logs.
 
 ## Anexo — notas de ingeniería
 
-- `ethService()`: `RST` alto → 150 ms → `Ethernet.begin` estático (prueba el chip y lee el PHY) → con cable, DHCP con 4 s (K1 liberado mientras, `relayDisengage("eth_dhcp")`) o estática → `connect()` con timeout 300 ms, reintento 5 s. Escrituras no bloqueantes (`availableForWrite`); descartes en `drop=`. MAC `02:48:42:` + hash del UID. Eventos en banda: `ETH_HW`, `ETH_UP`, `ETH_LINK`, `ETH_CONN`, `ETH_DISC`, `ETH_OFF`.
+- `ethService()`: `RST` alto → 150 ms → `Ethernet.begin` estático (prueba el chip y lee el PHY) → con cable, DHCP con 4 s (K1 liberado mientras, `relayDisengage("eth_dhcp")`) o estática → `connect()` con timeout 300 ms, reintento 5 s. Desde 0.6.1-eth: nunca `Ethernet.maintain()` tras un connect fallido (sin lease, la librería re-corría el DHCP entero: 4–5 s bloqueado cada 5 s); renovación del lease una vez por minuto solo si hubo DHCP; el cargador se pausa durante el DHCP; W5500 ausente: reintento cada 10 min tras 3 fallos. Escrituras no bloqueantes (`availableForWrite`); descartes en `drop=`. MAC `02:48:42:` + hash del UID. Eventos en banda: `ETH_HW`, `ETH_UP`, `ETH_LINK`, `ETH_CONN`, `ETH_DISC`, `ETH_OFF`.
 - Defaults del build: DHCP, y si no hay respuesta en 4 s estática 192.168.7.2/24 (`-DETH_DHCP=0`, `-DETH_IP=192,168,1,50`); servidor 192.168.7.1:5010, reintento 5 s (`-DETH_SERVER_IP=`, `-DETH_SERVER_PORT=`); activo solo con 5 V, nunca en batería ni por USB. IP y servidor son banderas de compilación: otro valor = otro `.bin` de ingeniería. No hay build de campo con Ethernet y el servidor htracker no escucha el espejo; la unidad reporta por 4G.
 - V5.6 añade R112 4.7 k pull-down en `ETH_RST` (PA15) y C90 4.7 µF / C91 10 nF. `W5500 NO responde` intermitente en V5.5: sospecha PA15 flotando antes de que el firmware tome el pin.
-- SC16IS752: 0x4D (A1 = A0 = GND, I²C), IRQ en PB8 (R81 10 k), Y2 3.6864 MHz (`XTAL_FREQ 3686400` → 9600 = divisor 24). Canal A → U14 SP3485 (DE y ~RE unidos en `SER_DEA`); canal B → U15 MAX3232 (canal 2 sin usar: T2IN y R2IN a GND). En 0.6.0 no hay tráfico de aplicación y el protocolo con el equipo del cliente está por definir.
+- SC16IS752: 0x4D (A1 = A0 = GND, I²C), IRQ en PB8 (R81 10 k), Y2 3.6864 MHz (`XTAL_FREQ 3686400` → 9600 = divisor 24). Canal A → U14 SP3485 (DE y ~RE unidos en `SER_DEA`); canal B → U15 MAX3232 (canal 2 sin usar: T2IN y R2IN a GND). En 0.6.0 y 0.6.1 no hay tráfico de aplicación y el protocolo con el equipo del cliente está por definir.
 - Netlist V5.6 (`p5ntc-after.xml`): P15.1 `RS485_A`, P15.2 `RS485_B`, P15.3 GND; JP5.1 `RS485_T` (R82 120 Ω → A), JP5.2 `RS485_B`; P16.1 `RS232_TX` (T1OUT), P16.2 `RS232_RX` (R1IN), P16.3 GND; J10 1/2 TX±, 3/6 RX±, 4 TCT (3V3_ETH), 5 RCT, 7/8 NC, 9–12 LEDs.
 
 ## Historial de revisiones
@@ -191,5 +191,6 @@ Sin 0.6.1 el resultado se registra como "presencia + niveles OK". Basta para ord
 |---|---|---|
 | 1.0 | 2026-09-29 | Primera versión: Ethernet con `0.6.0-eth` y puertos serie (presencia, niveles, lazo y eco para 0.6.1). |
 | 1.1 | 2026-09-29 | Edición breve; recibe de la configuración de la unidad la tabla de conexión, la regla de JP5 y los defaults de Ethernet. |
+| 1.2 | 2026-09-29 | Build de banco 0.6.1-eth (el 0.6.0-eth se bloqueaba sin DHCP). Lazo y eco serie: build posterior (0.6.1 salió como arreglo del cargador). |
 
 Versiones anteriores en git.