# Verification 2 — Layout/EMC (F), BOM (H), ERC/DRC (J), MCU/connectors (D/G)

!!! warning "Designators from before 22-Oct (T43)"
    This document keeps the designators the board had on its date. Since 22-Oct (T43) the V5.6, V5.7 and v6 carry new ones, and several old names now belong to another part: on the v6, U6 is now the A7670SA modem (was U19) and the LTC4040 is U17 (was U6). To read it against today's board, use the [old → new table](https://drogheda.helgen.online/hardware/designadores-t43-22oct/#8-tablas-viejo-nuevo) (in Spanish); parts already gone by 22-Oct are not in it.

Verifier 2, 2026-09-28. Scope: F-01, F-02, H-01, H-02 (Blockers); F-03…F-09, F-12, F-13, H-03, H-04, J-01, J-02, D-01, D-06, G-01, G-02 (Majors); D-02.
Method: my own scripts in `work/verifier2/` (`load_pcb.py` sexpdata zone-fill parser, `geom.py` pad/track/via → shapely, `hv24_gaps.py`, `vias_cnt.py`, `fcu_islands.py`, `in1cross.py`, `rfpar.py`, `z0.py`, `widths.py`). Primary sources: `src/*.kicad_pro/.kicad_dru/.kicad_pcb`, v6/V5.5/V5.6 netlists, `src/v5_current/…v5.kicad_pcb` (= V5.6 PCB, carries the V5.5 layout), evidence CSVs, JLC DB (`get_jlcpcb_part`), datasheets (cited per item), Fabrication-Toolkit source (GitHub `bennymeg/Fabrication-Toolkit@master`).

## Summary table

| ID | Auditor severity | Verdict | Verified severity | One-line reason |
|---|---|---|---|---|
| F-01 | Blocker | CONFIRMED-WITH-CORRECTION | **Blocker** | Only `/24V_IN` is HV24 and a 0.15 mm catch-all overrides every class. The proposed `.kicad_dru` has a hole: HV24↔HV24 pairs fall through to the 0.5 mm class value, which adds 4 false errors. Corrected rule set below. |
| F-02 | Blocker | CONFIRMED | **Blocker** | `/IGN_IN` runs 106.47 mm on In2 at 0.221 mm from `/VEH5V`. That is the 23-Jul geometry (0.20–0.25 mm on In2) again. |
| H-01 | Blocker | CONFIRMED-WITH-CORRECTION | **Blocker** | MAX3232ESE+ = 16 Narrow SO, placed on the SOIC-16W land (rows 9.3 mm apart). V5.5 did **not** have this: its PCB uses the narrow SOIC-16 land. v6 is a regression from re-syncing footprints from the schematic. |
| H-02 | Blocker | CONFIRMED-WITH-CORRECTION | **Blocker (order gate), U10 + R53 only** | R53 C131054 has 6 in stock against a 20-piece minimum, so it cannot be bought at any quantity. U10 has 15. The swaps are exact drop-ins. C103211, U19, U18 and J14 become a Major "re-check at order". |
| F-03 | Major | CONFIRMED | Major | U25's input-cap GND is on a 270 mm² F.Cu island. U25's EP and D34's anode are on the 3766 mm² island, whose nearest via is 30 mm away. |
| F-04 | Major | CONFIRMED | Major | 69 GND vias on the board. 1 via under U19, 0 under U18. The 3766 mm² east pour has 5 vias. (B-04 rates this Blocker; I rate it Major. See merges.) |
| F-05 | Major | CONFIRMED | Major | In1 is 18.8 % void and carries 1571.9 mm of tracks from 49 nets. USB, crystal, SIM and I²C lines cross slots or run broadside over foreign tracks. |
| F-06 | Major | CONFIRMED-WITH-CORRECTION | Major | LTE feed: 22.14 mm on In1, 2 vias, 1 fence via. GNSS bias line: minimum gap 0.274 mm over 3.3 mm and ≤ 0.5 mm over 13.4 mm, not "16.7 mm at 0.27". Impedance re-derived. |
| F-07 | Major | CONFIRMED | Major | C128's GND reaches U20's EP through a 0.25 mm neck between pin 1 and pin 2 (gaps 0.225/0.195 mm). EP has 0 vias. |
| F-08 | Major | CONFIRMED | Major (moot if U2 deleted, A-01) | U2 VIN (pin 7) to C11/C22/C10: 20.75/18.33/17.04 mm. |
| F-09 | Major | CONFIRMED-WITH-CORRECTION | Major | The auditor's Cin distance (1.77 mm) was measured to U12 **pin 2 = EN**. To VIN (pin 7) it is **6.40 mm**. D11 is 11.92 mm away and R87 25.9 mm. |
| F-12 | Major | CONFIRMED | Major | 69 GND vias (V5.5: 165), 10 of 35 20-mm cells empty, 2 vias along the edge. The via target is corrected to ≥ 400 (auditor: 500–600). |
| F-13 | Major | CONFIRMED-WITH-CORRECTION | Major (U6 EP part = A-02 Blocker) | 0 EP vias on U6/U25/U20/U2/U12. Correct the proposed fix: a board-wide "thru_hole_only" makes 23 × 0402 pads solid (tombstone risk). Use pad-level solid instead. |
| H-03 | Major | SEVERITY-CHANGE | **Minor** | Same part/land pairing on L2/L6/L7/L8 of 15 assembled V5.5 boards that work. Joint area is ≈ 55–64 % of the electrode, which is ample in strength. Change the footprint, not the part. |
| H-04 | Major (A-15 Minor) | SEVERITY-CHANGE | **Blocker** | Fabrication Toolkit (the tool the 25-Sep pre-fab audit prescribes) reads `LCSC Part` **before** `LCSC`. The BOM would order AP64350 (40 V) for U25 behind a 53 V clamp. |
| J-01 | Major | CONFIRMED (duplicate) | → F-01 | Same root cause as F-01. Merged. |
| J-02 | Major | CONFIRMED-WITH-CORRECTION | Major (copper → A-02/A-07/B-08) | 6 nets are really under-sized (BAT_PLUS, MAIN5V, VEH5V, SW_BAT, VIN_SW, VBAT_MODEM). VIN_MODEM is only a 0.1 mm neck. JLC's standard inner copper is 0.5 oz, which makes the inner runs worse than the auditor stated. |
| D-01 | Major (C-06 Minor) | CONFIRMED-WITH-CORRECTION | Major | U24 drives 3.3 V into an unpowered F9P RXD2 (ZED-F9P abs max VCC + 0.5 V). The 10 k series-R alternative is not enough. Use the Nexperia gate C12518 (Ioff), not the clone. |
| D-06 | Major | SEVERITY-CHANGE | **Blocker** (merged into F-02) | Same net and same geometry as F-02; this repeats the paid-for lesson. |
| G-01 | Major (Blocker if V5.5 standoffs) | CONFIRMED-WITH-CORRECTION | **Blocker unless Leo confirms a re-drilled backplate** | V5.5 MH4 (193.2, 90.3) is missing and L6 covers that point. The design brief says "no enclosure rework". The planned MH11 heatsink-clamp holes are also missing. |
| G-02 | Major | CONFIRMED | Major | `/USB_DP/DM/VBUS` = J9 + U19 only. USBLC6-2SC6 C7519 checked (SOT-23-6, 1415 in stock). |
| D-02 | Minor/Major-cond. | CONFIRMED | Minor | Y3 is 8.32/11.30 mm (pad edge) from PH0/PH1. The gm margin is thin only at max ESR. Leo graded ECO §E.6 🟡 and V5.5 starts in the field. |

Counts: 10 CONFIRMED, 9 CONFIRMED-WITH-CORRECTION, 3 SEVERITY-CHANGE, 0 REFUTED, 0 CANNOT-VERIFY. H-03's exact Sunlord land letters could not be read from the drawing (see its note).

**Severity calibration note on R5.** ECO §0 R5 is "the EMC list of the second batch" (ECO §E), and Leo graded its items himself: 🔴 SW_BAT and BAT_PLUS; 🟠 fan FB divider, Cin loops < 3 mm, DFU ESD and J9 ESD; 🟡 crystals ≤ 5 mm and stitching cells. I kept those grades: 🔴 → Blocker, 🟠 → Major, 🟡 → Minor. The only exception is stitching (F-12). v6 puts an LTE PA and a GNSS receiver on the board, which V5.5 did not have, so I keep F-12 at Major.

## Per-item notes

### F-01 Netclasses and custom rules
- **Re-derived.** `.kicad_pro` `netclass_patterns` (parsed with json): HV24 = `/24V_IN`, `24V`, `IGN_IN`, `Q10_GATE`. KiCad netclass patterns are anchored wildcard/regex matches against the full name, so the three un-prefixed patterns match nothing. The netlist `class` attribute (KiCad's own resolution, parsed from `src/netlists/v6-netlist.xml`) gives: HV24 = {`/24V_IN`} only; PWR_HI = 6 nets; PWR_MID = 6 nets (incl. `/3V3_ETH`); Default = 338 nets. The Default set includes `/24V`, `/IGN_IN`, `/Q10_GATE`, `/VIN_PROT`, `/VIN_FUSED`, `/VIN_MODEM`, `/Q23_GATE`, `/SW_PWRIN`, `/BOOT_PWRIN`, `/SW_MODEM`, `/BST_MODEM`, `/BST_FAN`, `/VBAT_MODEM`, `/RF_LTE` and `/RF_GNSS`. There are no RF or PWR_MODEM classes.
- **Rule precedence.** The rule `"Minimum clearance 1"`, `(min 0.15mm)`, has condition `A.NetClass != 'HV24' && B.NetClass != 'HV24'`, no layer clause and no type clause. KiCad turns netclass values into implicit rules and appends custom rules after them. The last matching rule wins; it does not take the max (JeffYoung, KiCad forum "Netclass clearance override by custom rules"). So this rule replaces Default/PWR 0.2 mm for every non-HV24 pair.
- **Zone clearance.** KiCad's zone-properties documentation (8.0) says "if two clearance values are in conflict, the larger clearance value will be used". The stored fills contradict that:
  - My shapely measurement of the fill gives 0.1505 mm to every non-HV24 net (for example the `/24V` In1 1.5 mm track and `P1.3` `/IGN_IN` on In1/In2) and 0.5005 mm to `/24V_IN`.
  - All 5 zones have `(connect_pads (clearance 0.3))` in the file.
  - DRC reports 0 clearance items.

  So in KiCad 10.0.4 the custom rule does override the zone field in practice. The corrected fix below does not depend on either interpretation, because it states every value explicitly.
- **Differences from the auditor's claim.** The facts are confirmed. The proposed `.kicad_dru` is syntactically valid KiCad DRC language (`(layer outer)`/`(layer inner)`, `A.NetClass`, `A.Type == 'Pad'`, `memberOfFootprint()`, `(constraint clearance (min …))`), but it misses one case. A pair where both nets are HV24 matches neither "HV24 outer/inner" (`B.NetClass != 'HV24'`) nor the floor rule, so it falls through to the HV24 netclass value of 0.5 mm. On today's copper that produces 4 false errors:
  - `/BST_MODEM` C129.1 ↔ `/SW_MODEM` 0.180 mm (bootstrap, ≈ 5 V difference)
  - `/BST_FAN` Cbst1.1 ↔ `/SW_FAN` 0.285 mm
  - `/Q23_GATE` D33.1 ↔ `/VIN_PROT` 0.388 mm
  - `/SW_FAN` ↔ `/VIN_MODEM` 0.400 mm
- **Corrected fix** (netclass table as the auditor gave it; the rule order matters because later rules win):
  ```
  (rule "Floor 0.15 (non-HV24, non-RF)"
    (condition "A.NetClass != 'HV24' && B.NetClass != 'HV24' && A.NetClass != 'RF' && B.NetClass != 'RF'")
    (constraint clearance (min 0.15mm)))
  (rule "HV24 to HV24"
    (condition "A.NetClass == 'HV24' && B.NetClass == 'HV24'")
    (constraint clearance (min 0.2mm)))
  (rule "HV24 outer"
    (layer outer)
    (condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
    (constraint clearance (min 0.3mm)))
  (rule "HV24 inner"
    (layer inner)
    (condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
    (constraint clearance (min 0.5mm)))
  (rule "HV24 IC land patterns"
    (layer outer)
    (condition "A.Type == 'Pad' && B.Type == 'Pad' && ((A.memberOfFootprint('U2') && B.memberOfFootprint('U2')) || (A.memberOfFootprint('U20') && B.memberOfFootprint('U20')) || (A.memberOfFootprint('U25') && B.memberOfFootprint('U25')))")
    (constraint clearance (min 0.15mm)))
  ```
  Notes on the rule set:
  - RF pairs resolve through the netclass implicit rules, where the larger class value wins, so the RF class clearance becomes the CPWG gap. Set HV24's class clearance to 0.3 mm so any fall-through is sane.
  - Change the HV24 net list if A-01 is adopted: U2 deleted takes out `/SW_FAN` and `/BST_FAN`; U20 moved to MAIN5V takes out `/VIN_MODEM`.
  - The IPC basis stands. IPC-2221B Table 6-1, 51–100 V row: B1 internal 0.1 mm, B4 external coated 0.13 mm, A6 0.13 mm. The 0.5 mm inner value is a defect/CAF margin taken from the 23-Jul lesson, not a dielectric requirement.
  - Check: after the change, run KiCad Inspect → Clearance Resolution on one `/24V` ↔ GND-zone pair and one GND-zone ↔ Default pair, then refill and run DRC.
- **Remeasured worst inner-layer gaps** (non-zone copper; `hv24_gaps.py`):

  | layer | gap (mm) | pair |
  |---|---|---|
  | In2 | 0.221 | `/IGN_IN` ↔ `/VEH5V` 1.0 mm track |
  | In2 | 0.250 | `/IGN_IN` ↔ GND via |
  | In2 | 0.291 | `/IGN_IN` ↔ `/FAN_PWM` |
  | In2 | 0.300 | `/IGN_IN` ↔ `/5V_FAN` via |
  | In1 | 0.305 | `/IGN_IN` via ↔ `/NTC2` |
  | In1 | 0.500 | `/24V_IN` ↔ `/SW_5V` |

  The zone gap to all 24 V nets except `/24V_IN` is 0.1505 mm. Outer layer: 12 pairs below 0.3 mm (worst `/SW_MODEM`–GND 0.150, `/VIN_MODEM`–GND 0.150, `/VIN_PROT`–`/VEH5V` 0.162). These match the auditor.

### F-02 `/IGN_IN` on In2 (primary of merge M-B; absorbs D-06, F-16)
- **Re-derived.**
  - Routing: 4.08 mm F.Cu plus 106.47 mm In2, all 0.5 mm wide, with 1 via at (127.6, 50.75). P1.3 is at (177.5, 135.0) and Rig1.1 at (123.55, 50.675).
  - Gap to `/VEH5V`: 0.2214 mm on In2, to track segment (147.85, 66.95).
  - 23-Jul geometry (`docs/memory/drogheda-einarboard-short-incident.md`): `/24V_IN` on In2 at 0.202–0.25 mm from MAIN5V/VEH5V, **and `VEH5V↔IGN_IN` at 0.2 mm on In2**. v6 is within 0.02 mm of that geometry, on the same net pair.
  - The incident's root cause was still "suspected" when the memory was written. Even so, the corrective action ("24V-to-LV ≥ 0.5–1 mm, keep 24 V off inner layers next to LV") is written into the audit brief §4-A.
- **Rating.** Blocker: it repeats a paid-for lesson, a failure would damage hardware (vehicle-fused 24 V onto LTC4040 VIN, 6 V class), and an inner-layer defect cannot be inspected or reworked. D-06's Major under-rates it.
- **Fix check.**
  - Rig1 (22 k 0603, C88614) goes ≤ 3 mm of copper from P1.3. The 106 mm run then becomes `/IGN_SENSE`, limited to (36 V − 5 V)/22 k = 1.4 mA (2.5 mA at 58 V) into any bridged 5 V net. C9 at the MCU keeps τ = (22 k ∥ 2.87 k) × 100 nF = 0.25 ms.
  - Add D-06's SMBJ33A (C224019, Littelfuse, DO-214AA, 9624 in stock; VR 33 V, VC 53.3 V at 11.3 A) at P1.3. It also clamps negative ISO 7637 pulses at about −1 V, which removes D-06's −27 mA PA5 injection. BAT54S becomes optional.
  - Rig1 at 58 V dissipates 0.13 W for the 400 ms load dump. An 0603 thick-film part (75 V max working voltage, 2.5× short-time overload) is acceptable once the TVS is fitted; 1206 is optional.
  - The In1 IGN via next to `/NTC2` goes away with the reroute.
  - Conflict (≤ 3 mm vs ≤ 5 mm): use ≤ 3 mm of copper.
- **F-16 (sub-item, Minor).** `/24V_IN` on In1 is 27.11 mm of 1.5 mm track at exactly 0.500 mm from `/SW_5V`. Move it to F.Cu along the south edge, or keep ≥ 1.0 mm from LV (the upper end of Leo's rule). The `/24V` In1 track (12.75 mm) with a 0.15 mm zone gap re-pours to 0.5 mm under F-01.

### H-01 U15 package vs land
- **Re-derived.**
  - JLC DB: C15846 = MAX3232ESE+T, package "SOIC-16". Compare C7605 PCF8574T, which the DB lists as "SOIC-16-300mil".
  - Maxim/ADI datasheet 19-0273 Rev 10 (5/19), Ordering Information: "MAX3232ESE+ −40 °C to +85 °C 16 Narrow SO S16+5"; "MAX3232EWE+ … 16 Wide SO".
  - v6 PCB U15: `SOIC-16W_7.5x10.3mm`, pads 2.05 × 0.6 mm, pad-row centres at x = 117.3 and 126.6 (9.3 mm apart). A narrow SO lead tip reaches ±3.0–3.1 mm, and the inner pad edge is at ±3.625 mm, so the leads end 0.5–0.6 mm short of the pads. The joint cannot form.
- **History, corrected.**
  - V5.5 as-fabbed netlist and V5.6 netlist: U15 footprint field = SOIC-16W, the same stale field.
  - The **V5 PCB** (`src/v5_current/…v5.kicad_pcb`, identical to the V5.6 PCB, which carries the V5.5 layout; U15 is placed in it) uses `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`, pads 1.95 × 0.6 at ±2.475 mm. That is the correct narrow land.
  - So V5.5 boards were built on the right land, and the auditor's statement "the same combination is in V5.5 as fabbed" is wrong. v6 regressed when its PCB footprints were rebuilt from the schematic (02-Sep fresh-layout baseline, `drogheda-v6-resync-protocol`).
  - A sweep of every LCSC part common to the V5 and v6 PCBs shows U15 is the **only** carried-over part whose footprint changed.
- **Fix.** Option (b): set `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm` in the v6 schematic **and** PCB, keep C15846 (genuine Maxim, 4873 in stock), and re-place C84–C88 against U15. Also fix the stale field in the V5.x schematic so a future Update-PCB cannot repeat this. C19268179 is a TECH PUBLIC clone; use it only as an alternate. Option (a), the wide part C118514 with 30 in stock, is not recommended.

### H-02 Stock
- **Re-queried** (JLC DB snapshot):

  | ref | LCSC | stock | note |
  |---|---|---|---|
  | U10 | C729142 (SC16IS762IPW) | 15 | — |
  | R53 | C131054 | 6 | first price break 20+, so JLC's 20-piece minimum cannot be met at any board quantity |
  | 9 refs | C103211 (RALEC 100 k **5 %**) | 702 | 9 per board → 78 boards maximum |
  | U19 | C18548276 (A7670SA) | 96 | — |
  | U18 | C5120257 (ZED-F9P-04B) | 104 | — |
  | J14 | C2977286 | 10 890 | category "Pre-ordered Products", so it must be pre-ordered into the JLC account |
- **Drop-in check.**
  - C57156 SC16IS752IPW,128: same TSSOP-28, same pinout and registers. U10 runs in **I²C mode** (pin 9 = 3V3, `ic_pins_U10.csv`); in I²C mode the 752 and 762 are identical, and they differ only in SPI/IrDA top speed. The value field already says 752. 2670 in stock. ✅
  - C177479 HKR RCT03499KFLF: 499 k, 1 %, 100 ppm, 0603, 100 mW, 75 V. The same rating as YAGEO RC0603FR-07499KL. 26 862 in stock. ✅
  - C25803 UNI-ROYAL 100 k 1 % (Basic, 10.8 M) replaces the 5 % C103211. That is an upgrade: R87 sets 3V3_ETH, R20 sets the fan output. ✅
- **Rating.** Blocker only as an order gate for U10/R53 (both swaps are free and carry no design risk). C103211, U19, U18 and J14: Major, re-check on order day against the order quantity.

### F-03 U25 hot loop (merge M-D)
- **Re-derived** (`fcu_islands.py`):
  - F.Cu GND copper (pour + GND pads + GND tracks) forms 55 pieces.
  - U25.9 (EP), U25.7 and D34.2 sit on piece "east", 3766 mm² with 5 GND vias. The nearest on-piece via is 29.5–30.4 mm from the EP and 37.9 mm from D34.2.
  - C149.2, C150.2 and C151.2 sit on the 270 mm² U6 piece (5 vias, nearest 9.4–11.4 mm).
  - C150.1 → U25.2 = 2.88 mm; D34.1 → U25.8 = 4.28 mm; L22.1 → U25.8 = 13.75 mm.
  - The auditor's "nearest GND via 28 mm" is correct as an on-island figure. Straight-line, the nearest GND via is 14.4 mm, but it sits on another island.
- **Fix.** See the M-D layout instruction below.

### F-04 Module grounds (merge M-C)
- **Re-derived** (`vias_cnt.py`):
  - U19: 39 GND pads, of which 20 are 2.1 × 2.1 mm centre pads. 1 GND via under the courtyard, 4 in a 5 mm ring.
  - U18: 56 GND pads, 0 vias under the courtyard, 5 in the ring.
  - East piece: pour points to the nearest GND via have median 10.4 mm, p90 19.8 mm, maximum 29.5 mm.
- **Rating.** Confirmed Major. I disagree with B-04's Blocker. No R1–R5 item is violated outright, there is no V5.5 field precedent for an on-board modem, and there is no damage path. It is still a zero-BOM-cost must-do alongside the Blockers.

### F-05 In1 plane
- **Re-derived** (`in1cross.py`):
  - In1 fill is 11 370.5 mm²: 18.8 % void against 14 000 mm², or 17.4 % against the 139 × 99 mm usable area.
  - In1 carries 1571.9 mm of tracks from 49 nets.
  - Length of each F.Cu net over In1 voids:

    | net | length over void | notes |
    |---|---|---|
    | USB_DP / USB_DM | 10.4 / 9.7 mm | directly over `/24V_IN` and `/SW_5V` |
    | I2C_SDA | 25.2 mm | 14.2 mm directly over `/SER_TXB` |
    | ETH_XO | 8.3 mm | 6.95 mm over `/ETH_RST` |
    | NRST | 21.1 mm | 7.2 mm over `/USART6_RX` |
    | DFU_DM | 13.2 mm | — |
    | SIMB_CLK | 9.1 mm | 5.8 mm over `/SW_5V` |
    | DOUT_4G_M | 13.1 mm | — |
    | RF_GNSS / RF_ANT_* | 0 mm ✅ | — |
- **Correction to the fix (scope).** A full "In1 = plane" re-layout is ideal. The minimum is to clear In1 under the USB pairs, the crystals and their lines, all switch nodes, VBAT_MODEM/the RF area, SIM, and the three broadside parallels listed above. Acceptance: ≤ 3 In1 islands, and no critical net over a void longer than 1 mm.

### F-06 RF feeds (merge M-E; absorbs B-05, C-05)
- **Re-derived.**
  - `/RF_LTE` = 4.01 mm F.Cu + 22.14 mm In1. `/RF_ANT_LTE` = 5.62 mm F.Cu.
  - GND vias within 3.5 mm of the 31.5 mm LTE path: 1. Within 3.5 mm of the 27.2 mm GNSS path: 2.
  - GNSS bias line `/VCC_RF_GNSS` beside `/RF_GNSS` (`rfpar.py`): minimum edge gap 0.274 mm; 3.25 mm of run at ≤ 0.3 mm, 13.4 mm at ≤ 0.5 mm, 17.9 mm within 1 mm. The auditor's "16.7 mm at 0.27 mm" overstates it; BCE's "≈ 0.46 mm for 10 mm" is closer.
- **Impedance** (`z0.py`, Hammerstad-Jensen with thickness correction; CPWG by conformal mapping without thickness).

  Assumed stackup **JLC04161H-7628**: L1–L2 7628 prepreg 0.2104 mm, εr 4.4; core 1.065 mm; outer 1 oz, inner 0.5 oz.

  | geometry | JLC04161H-7628 | file stackup (0.48 mm, εr 4.5) |
  |---|---|---|
  | 0.5 mm microstrip | **42.1 Ω** (εeff 3.41) | 66.6 Ω |
  | CPWG 0.5 mm / 0.15 mm gap (as built) | 41.0 Ω | — |
  | CPWG 0.30 / 0.20 | 56.6 Ω bare | — |
  | CPWG 0.35 / 0.20 | 52.1 Ω bare | — |

  BCE's FD solver gives 53.3 Ω bare and 48.4 Ω masked for 0.30/0.20; closed forms read 2–4 Ω high. The In1 LTE section is ≈ 30–47 Ω, varying with F.Cu coverage, which agrees with BCE's 32.5/47.1 Ω.
- **Fix, conflict resolved.** Start from CPWG w 0.30 mm / gap 0.20 mm on F.Cu over solid In1 and finalise in JLC's calculator with impedance control ordered. Via fence ≤ 3 mm pitch (λg/20 = 3.1 mm at 2.69 GHz, εeff 3.2), ≤ 1 mm from the gap edge, 2 vias per U.FL GND pad. Keep `/VCC_RF_GNSS` ≥ 1 mm from the RF line, with a stitched GND strip between. Set the real stackup in Board Setup.

### F-07 U20 GND neck (merge M-D; = B-06)
- **Re-derived.** The GND track (0.25 mm) runs C128.2 (142.5, 60.93) → (143.525, 61.955) → (145.3225, 61.955) → (151.02, 62.1) and joins the EP (147.5, 63.205; 3.2 × 2.5 mm). At y = 61.955 it passes between U20.1 (y 61.305, pad 0.6 mm wide) and U20.2 (y 62.575). Gaps: 0.225 mm to pin 1 and 0.195 mm to pin 2.
- **Fix.** Confirmed. C128 and C127 GND pads go on solid F.Cu bonded to the EP, with EP vias (see M-C).

### F-08 U2 input caps
- **Re-derived.** U2.7 (MP1584 VIN) to C11 = 20.75 mm, C22 = 18.33 mm, C10 = 17.04 mm. Dbk1 6.51 mm. The EP (solid) has 0 vias and its nearest GND via is 19.7 mm away.
- **Fix.** Confirmed. The item is moot if A-01 deletes U2.

### F-09 U12 (correction)
- **Re-derived.** U12 is an MP1584EN: pin 2 = EN (tied to `/SYS5V`), pin 7 = VIN.
  - C101.1 → U12.7 = **6.40 mm** (A-06 had this right; FHJ's 1.77 mm was measured to EN).
  - D11 → U12.1 = 11.92 mm; L8 = 15.10 mm; R87 (FB top) = 25.9 mm.
  - C101.2 is on the 224 mm² piece and D11.2 on the 178 mm² piece.
- **Why it matters.** This is the same R5 🟠 item that was 8.5 mm on V5.5, and it is still > 3 mm.

### F-12 Stitching (merge M-C)
- **Re-derived.**
  - GND vias per 20 mm cell, rows from y 40.32:
    ```
    [0,5,4,3,0,1,0]
    [2,3,4,4,4,0,2]
    [2,1,2,3,0,1,3]
    [0,2,2,2,0,2,4]
    [4,5,0,2,2,0,0]
    ```
    That is 10 of 35 cells empty. GND vias within 3 mm of the edge: 2.
  - My grid matches the auditor's exactly.
- **Target, corrected.** 480 mm of perimeter at 5 mm pitch needs ≈ 96 vias. The 7890 mm² of F.Cu GND copper at 1 via per 25 mm² needs ≈ 316. Target **≥ 400**, not 500–600.

### F-13 EP vias and pad connection (primary of merge M-C)
- **Re-derived.**
  - All 5 zones use default thermal relief (gap 0.5, spoke 0.5).
  - Pad-level solid overrides exist only on U6.25, U2.9, U12.9, U11.9, U11.29 and JP1–JP5.
  - Vias inside the EP: 0 on U6, U25, U20, U2 and U12.
- **Correction.** A board-wide `(connect_pads thru_hole_only …)` would make the 23 × 0402 and 142 × 0603 GND pads solid, which is a tombstoning risk. Instead set pad-level `zone_connect` solid on the EPs, all U18/U19 GND pads, D34/Dbk1/D11 anodes and the buck Cin/Cout GND pads. Keep the zone default thermal (≥ 2 spokes) for small passives.
- **Via arrays, corrected for fit** (0.3 mm drill / 0.6 mm pad at 1.0 mm pitch):
  - U25 and U20 EPs are 3.2 × 2.5 mm. A 3 × 3 array at 1.0 mm pitch needs 2.6 mm, so it does **not** fit the 2.5 mm side (F-03's claim is wrong). Use 2 × 3 = 6, or 2 × 4 = 8 at 0.8 mm pitch with 0.3/0.5 vias.
  - U6 EP is 2.65 × 3.65 mm: 3 × 3 at 0.9 × 1.2 mm fits and meets ECO D2's ≥ 9.
  - U2 and U12 EPs are 2.29 × 3.0 mm: 2 × 3 fits.

### H-03 MWSA0804S on the SRU8028 land
- **Re-derived.**
  - Land: pads 2.0 (along the axis) × 3.2 mm at ±3.9 mm, spanning 2.9–4.9 mm from centre (KiCad `L_Bourns-SRU8028`, also confirmed from the GitHub library copy).
  - Sunlord MWSA-S spec Table 4-1 row MWSA0804S: A 8.2 ± 0.3, B 8.8 ± 0.4, C 3.8 ± 0.2, D 1.4 ± 0.3, E 5.0 ± 0.3; land I 2.75 / J 4.0 / H 5.5 (typ).
  - The figure that defines H/I/J could not be read: the LCSC, Digikey and alfatec PDFs are blocked from this sandbox or render text only.
  - Electrode overlap is 86–100 % along the axis (depending on whether the 8.2 or the 8.8 side carries the electrodes) × 64 % across (3.2 / 5.0), so **55–64 %** of the electrode area is wetted.
- **Rating.** V5.5 used exactly this pairing on L2, L6, L7 and L8 (V5 PCB: C17700165/C17700171 on `L_Bourns-SRU8028`), and 15 boards were assembled and run. Pad area per joint is ≈ 3.8 mm²; SAC shear strength at ≈ 30 MPa gives ≈ 100 N against ≈ 0.1 N/g inertial load, so strength is not the problem. The V5.5 "modem dark on battery" was root-caused to back-feed and UVLO (FW 0.5.5/0.5.6), not to inductor joints. **Minor.**
- **Fix.** Change the footprint, not the part. The SRU8028-class Bourns parts have lower Isat than MWSA0804S-2R2 for L6. Build `Drogheda-v6:IND-SMD_MWSA0804S` from the LCSC drawing (Leo or Michelle can open it) while L6/L20 are being re-placed anyway (A-02/M-D).

### H-04 U25 `LCSC Part`
- **Re-derived.**
  - v6 PCB fields: 14 footprints carry `LCSC Part`, all inherited from the easyeda `Drogheda-v6.pretty` footprints. U25 is the only one whose value differs from `LCSC` (C2071691 vs C524806).
  - Source: `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` line 12, `(property "LCSC Part" "C2071691")`. U20 and U25 share this footprint.
  - Fabrication-Toolkit `plugins/process.py::_get_mpn_from_footprint` builds its key list as `['LCSC Part #','LCSC Part', …]` + fallback `['LCSC', …]` and returns the first non-empty field.
  - The 25-Sep pre-fab audit says "Generate BOM/CPL from the board … (Fabrication Toolkit)", and the V5.5 `production/` folder is the toolkit's output folder.
- **Consequence.** U25 would be ordered as the AP64350. It is pin-compatible (1 BST, 2 VIN, 3 EN, 4 RT/CLK, 5 FB, 6 COMP, 7 GND, 8 SW) with the same 0.8 V FB, so it passes the bench and then fails at the first transient above 40 V. **Blocker** (damage risk).
- **Fix.** Delete `LCSC Part` from U25 on the board **and** from the library footprint, or delete it from all 10 `Drogheda-v6.pretty` footprints. Alternatively generate the BOM from the schematic (`kicad-cli`); `evidence/bom.csv` is correct.

### J-01
- Same root cause as F-01. Merged (M-A).

### J-02 Track widths
- **Sampled.** All 16 flagged nets, `widths.py`. Criterion: IPC-2221 k = 0.048 (≈ IPC-2152 baseline) at ΔT 20 °C; outer 1 oz; **inner 0.5 oz** (JLC04161H default, not the file's 1 oz). Design currents: BAT_PLUS/SW_BAT 4.2 A (backup), MAIN5V/VEH5V/VIN_SW 2.5 A, VBAT_MODEM 2 A, VIN_MODEM 1.8 A, SYS5V 0.8 A, fans ≤ 0.3 A, SW_5V/SW_IN 0.25 A, 3V3_ETH 0.15 A.
- **Length under capacity:**

  | net | length under capacity | notes |
  |---|---|---|
  | BAT_PLUS | 123 mm | incl. 69.9 mm of In2 1.0 mm ≈ 1.45 A |
  | MAIN5V | 111 mm | — |
  | VEH5V | 102 mm | incl. In2 1.0 mm 66.6 mm |
  | SW_BAT | 12.9 mm | all of it |
  | VIN_SW | 26 mm | — |
  | VBAT_MODEM | 12.5 mm | — |
  | VIN_MODEM | 0.1 mm | neck only, and bursts are RMS-light |
  | 3V3_ETH, fan nets, SW_5V, SW_IN, SYS5V, VIN_PROT, VIN_FUSED | 0 mm | benign |

  So **6 nets are real**, carrying 63 DRC hits (vs the auditor's 59 with VIN_MODEM counted). The conclusion stands and is stronger for the inner layers.
- **Fix.** The copper is owned by A-02 (SW_BAT/BAT_PLUS, R5 🔴, Blocker), A-07 (VEH5V/VIN_SW/MAIN5V) and B-08 (VBAT_MODEM). Either order 1 oz inner copper or widen inner runs by 1.65×. J-02's residual item (relax T15 for the benign nets) is Minor.

### D-01 F9P back-power via U24 (merge M-G; absorbs C-06)
- **Re-derived.**
  - `/DOUT_4G` = {U24.7 (1B), R106.1, R107.2 DNP, U18.26 RXD2}. U24 has VCCA = `/1V8_MODEM`, VCCB = `/3V3` (always on) and DIR = VCCA.
  - `/3V3_GNSS` = U21 out plus U18.33/34 only.
  - ZED-F9P-04B datasheet UBX-21044850 R05 Table 14: input pin voltage −0.5 … VCC + 0.5 V for VCC ≤ 3.1 V. At VCC = 0, a 3.3 V push-pull high exceeds that by 2.8 V.
  - The 74LVC2T45's VCC isolation protects the modem side only (U23), not U24's B output into a dead load.
  - Same mechanism as the V5.5 FW 0.5.5 lesson (CHANGELOG: an idle-high UART held the simpleRTK2B/modem rails up through ESD diodes, so no POR), now built into hardware.
- **Rating.** Major, not Blocker: firmware sequencing (modem off before F9P off, never F9P-only cycles with the modem up) avoids it, as the ECO A sequence does.
- **Fix check.**
  - The 10 k series-R alternative injects ≈ 0.28 mA. That is the same order as the leakage that held the V5.5 modem rail at ≈ 1 V (0.5.6: `3V3_MODEM = 0.99 V`), so it does not reliably protect the F9P's 20–8000 µs/V ramp.
  - Use the gate: **C12518 Nexperia 74LVC1G125GV,125** (SOT-753; pin 1 OE, 2 A, 3 GND, 4 Y, 5 VCC; datasheet Rev 17.1: "IOFF circuitry provides partial Power-down mode operation", IOFF ±2 µA max). Power it from `/3V3_GNSS`, OE tied to GND, with 100 nF C14663. C3040595 is a TECH PUBLIC clone and should not be relied on for Ioff.
  - Keep PC7/R106 on `/DOUT_4G`. Moving U24's VCCB to `/3V3_GNSS` is not an option: MODEM_STATUS and the RTCM tap would die with the F9P off (R2).
  - Rdfu1 22 k → 100 k (C25803) still leaves ≈ 27 µA into U18.27. Bench-check `/3V3_GNSS` with PA1 low and the modem on: it must read < 0.3 V.

### D-06
- Merged into F-02 (M-B). Rated Blocker there.

### G-01 Mounting holes
- **Re-derived.**
  - V5 PCB holes: MH5 (65.2, 45.3), MH6 (65.2, 135.3), MH4 (193.2, 90.3), MH7/9/10/11 (M2.5 shield/heatsink).
  - v6 holes: MH5, MH6, MH7 (195.2, 45.3), MH8 (195.2, 135.3).
  - At (193.2, 90.3) on v6: the L6 courtyard contains the point (0.0 mm), L6.2 `/BAT_PLUS` pad centre is 2.44 mm away, R133 is 1.75 mm away.
  - Design brief v1.0: "Keep 140.000 × 100.000 mm — no enclosure rework". Memory `drogheda-v6-zed-f9p-integration`: "MH4/5/6 (enclosure) and MH11 (heatsink clamp) survive". Phase-2 delta: "KEEP MH11 and add one partner near U19".
  - **Also missing:** MH11 at (168.3, 84.6), which now sits 0.6 mm from the U19 courtyard, and its partner. These are the modem heatsink clamp holes for thermal gate T1.
- **Rating.** Blocker unless Leo confirms a new backplate. The documented intent was to reuse the V5.5 enclosure.
- **Fix.** Restore MH4 at (193.2, 90.3). L6 has to move anyway (A-02: ≤ 5 mm from U6). Decide on the heatsink-clamp pair near U19. Keep a ≥ 4 mm copper-free radius or use nylon washers.
- **Input needed from Leo:** the backplate hole pattern.

### G-02 J9 ESD (merge M-F; absorbs B-07's ESD part and F-14's J9 part)
- **Re-derived.** Nets are as stated, with no protection device.
- **Fix check.** C7519 USBLC6-2SC6 (ST, SOT-23-6L, 1415 in stock). Pinout: 1/6 I/O1 → USB_DM, 3/4 I/O2 → USB_DP, 5 VBUS, 2 GND. Routing conflict resolved: ≤ 3 mm of copper from the J9 pads, flow-through, with GND via ≤ 1 mm. The pair-split part of B-07 goes to F-17 (Minor).

### D-02 HSE crystal
- **Re-derived.**
  - Y3 pad edge to U16.5/U16.6 = 8.32/11.30 mm. DG's 10.30/14.21 mm are pad-centre figures.
  - C14872: CL 20 pF, **−20…+70 °C** rating.
  - gm_crit = 4·ESR·(2πf)²·(C0 + CL)² = 1.21 mA/V (ESR 40 Ω, C0 5 pF, CL_eff 12.5 pF) to 2.37 mA/V (C0 7 pF, CL_eff 17.5 pF), against Gm_crit_max 1 mA/V. It passes at typical ESR.
- **Rating.** Minor (Leo's 🟡).
- **Fix check.**
  - C2901684 (SCTF 3225, CL 10 pF, ESR 30 Ω, −40…+85 °C, 11 076 in stock) with 12 pF C38523 gives 0.46 mA/V ✅.
  - Preferred: **C9006** (YXC 3225, CL 12 pF, **Basic**, 528 k in stock, −40…+85 °C) with 15 pF (C1644) gives CL_eff ≈ 11.5 pF and ≈ 0.77 mA/V at ESR 40 Ω. Confirm its ESR on the LCSC PDF.
  - The −20…+70 °C rating of C14872 in a sealed port box is a further reason to swap it.

## Duplicates / merges proposed

| Merge | Primary | Absorbs | Severity | Single fix |
|---|---|---|---|---|
| **M-A 24 V rules** | F-01 | J-01, F-15 (outer spots become DRC findings), B-12 (netclass part) | Blocker | Netclass table plus the corrected `.kicad_dru` above, then refill and DRC as the gate. Re-check that the classes survive every GUI save. |
| **M-B 24 V on inner layers** | F-02 | D-06, F-16 | Blocker | Rig1 ≤ 3 mm from P1.3, plus SMBJ33A C224019 at P1.3. `/24V_IN` In1 run moved to F.Cu, or ≥ 1.0 mm from LV. |
| **M-C Ground vias / pad connection** | F-13 | F-04, F-12, B-04, C-03, A-06 (EP/via part) | Major (U6 EP → A-02 Blocker) | Layout instruction L1–L6 below. |
| **M-D Buck hot loops** | F-03 | F-07, B-06, F-08, F-09, A-06 (loop part) | Major | Layout instruction L7 below. |
| **M-E RF feeds** | F-06 | B-05, C-05 | Major | CPWG 0.30/0.20 on F.Cu over solid In1, fence ≤ 3 mm, real stackup, impedance control. |
| **M-F J9 ESD** | G-02 | B-07 (ESD), F-14 (J9 part) | Major | USBLC6-2SC6 C7519 ≤ 3 mm from J9, flow-through. |
| **M-G F9P back-power** | D-01 | C-06 | Major | 74LVC1G125 C12518 on `/3V3_GNSS` at U18.26; Rdfu1 → 100 k. |
| **M-H Power copper** | A-02 / A-07 / B-08 | J-02 | per owner | Widen/pour the 6 nets; 1 oz inner or 1.65× width on inner layers. |
| **M-I U25 BOM field** | H-04 | A-15 | Blocker | Delete `LCSC Part` (board + library). |

**Layout instruction for Michelle (M-C/M-D), quantified:**
- **L1 EP vias** (0.3 mm drill / 0.6 mm pad, tented on B.Cu, or JLC via-in-pad filled and capped):
  - U6: 3 × 3 = 9 at 0.9 × 1.2 mm (ECO D2)
  - U25, U20: 2 × 3 = 6 at 1.0 mm (8 at 0.8 mm with 0.3/0.5 mm vias)
  - U2, U12: 2 × 3 = 6
  - Every EP pad gets `zone_connect` solid.
- **L2 U19 A7670SA:** one via in each gap between adjacent 2.1 mm centre GND pads (1.7 mm gap, leaving 0.55 mm clearance) plus a via ring on the perimeter GND pads. **≥ 30, target 40**, tented, never in pads.
- **L3 U18 ZED-F9P:** vias at the diagonal interstitial points of the 2.1 mm-pitch GND array. 0.3/0.6 mm vias leave 0.41 mm to the pad corners. **≥ 24.** All GND pads of U18 and U19 solid.
- **L4 Stitching:**
  - Every F.Cu GND island ≥ 20 mm² gets ≥ 2 vias.
  - No F.Cu GND pour point more than 5 mm from a GND via (today: median 10.4 mm, maximum 29.5 mm in the east pour).
  - Edge fence at ≤ 5 mm pitch within 1.5 mm of the edge clearance, ≈ 96 vias.
  - Board total **≥ 400 GND vias** (today 69, V5.5 165). Acceptance: 0 empty 20 mm cells.
- **L5 RF:** fence ≤ 3 mm pitch on both sides of RF_LTE/RF_ANT_LTE and RF_GNSS/RF_ANT_GNSS, ≤ 1 mm from the gap edge. 2 vias ≤ 1 mm from each U.FL GND pad (J12, J13) and at D28.
- **L6 Small passives:** leave them on thermal relief (23 × 0402), not solid.
- **L7 Hot loops** (U25, U20, U12, and U2 if it stays):
  - Cin (VIN and GND pads) ≤ 2 mm from the IC VIN and GND/EP pins. The Cin GND, the diode anode (D34/D11/Dbk1) and the EP on **one solid F.Cu area**, with no GND neck narrower than 1 mm.
  - ≥ 2 vias ≤ 1 mm from each Cin GND pad.
  - Catch diode ≤ 3 mm from SW. Inductor ≤ 5 mm from SW. SW copper ≤ 25 mm².
  - FB divider ≤ 3 mm from the FB pin, with nothing on In1 under the SW copper.
  - Acceptance: each input loop ≤ 1 cm² (Copper Plan §2); today U25 ≈ 3.1 cm².

## Fix conflicts resolved
1. **F-02 ≤ 3 mm vs D-06 ≤ 5 mm (Rig1).** Use ≤ 3 mm of copper, and add the D-06 TVS.
2. **Severity, F-02 Blocker vs D-06 Major.** Blocker.
3. **H-04 Major vs A-15 Minor.** Blocker (Fabrication Toolkit key order is proven in the source).
4. **F-04 Major vs B-04 Blocker.** Major. The U6 EP is the Blocker part, owned by A-02.
5. **D-01 Major vs C-06 Minor.** Major. The gate (C12518) replaces the series-R option.
6. **EP via counts** (F-03 "3 × 3 at 1.0 mm", A-06 "4 × 2", F-13 "3 × 3").
   - U25/U20: 6 at 1.0 mm, or 8 at 0.8 mm. 3 × 3 at 1.0 mm does not fit 2.5 mm.
   - U6: 9.
7. **Stitching count** (F-12 500–600). ≥ 400 with the acceptance criteria above.
8. **CPWG geometry** (F-06 0.30–0.35/0.20–0.25; B-05 0.30/0.20). 0.30/0.20 as the starting point (FD solver 48.4 Ω masked), finalised in the JLC calculator.
9. **J9 ESD distance** (G-02 ≤ 3 mm, B-07 ≤ 5 mm). ≤ 3 mm.
10. **Proposed `.kicad_dru`** (FHJ). Add the HV24↔HV24 rule, or 4 false errors will appear.

## Anything else you noticed
- **U12 Cin (F-09):** the auditor measured to the EN pin. The real VIN loop is 6.40 mm, so R5 🟠 item 4 is still open on U12. A-06's figure was right.
- **H-01 is a regression, not a legacy defect.** The V5.x schematics still carry the stale SOIC-16W field. Fix the field in both v6 and V5.x so a future Update-PCB on V5.6 does not break the working V5.5 land.
- **Inner copper weight.** JLC04161H-7628 ships 0.5 oz inner by default, while the file stackup says 1 oz everywhere. That lowers inner-layer current capacity by ≈ 40 % (A-07/J-02). Order 1 oz inner or widen. Record it with the stackup decision (F-06).
- **Zone clearance field 0.3 mm is not honoured by the current fills** (0.1505 mm measured). After M-A, verify with Inspect → Clearance Resolution that the GND pour keeps the intended gap to RF (CPWG gap) and to HV24.
- No REFUTED items and no new Blocker beyond the severity changes above (H-04 ↑Blocker, D-06 ↑Blocker, G-01 Blocker-conditional).

## Inputs needed from Leo
1. Backplate/enclosure hole pattern: are the V5.5 standoffs (incl. (193.2, 90.3)) reused, and is the modem heatsink clamp still planned (MH11 + partner)? (G-01)
2. BOM tool for the JLC order: Fabrication Toolkit (board fields) or kicad-cli (schematic fields)? H-04 is a Blocker in either case until the field is deleted.
3. Stackup and copper: JLC04161H-7628 with impedance control, and 1 oz inner? (F-06, J-02)
4. Order quantity: this decides whether C103211, U19 and U18 limit the order (H-02).