# EinarBoard v6 — Schematic change report (v1.0)

!!! warning "Tarjeta: EinarBoard **v6** — proyecto KiCad `hbox-watchdog-v6` (EN DISEÑO, no se pide todavía) / Board: v6, in design"
    Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. **No es la V5.6** que se manda a fabricar esta semana (`hbox-watchdog-v5`, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios.


**Date:** 2026-09-28 · **Project:** `kicad/hbox-watchdog-v6.*`, edited in place (D17) · **Implements:** `2026-09-28_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md` §7.1 (Blockers), §7.2 (Majors), §7.3 Minors per D19, and F-01 / D18 project rules · **Decisions:** `DECISIONS.md` D1–D19 (taken on Leo's delegation) · **Author:** Claude (scripted span-scoped S-expression edits with a UUID guard; KiCad MCP used only for netlist, ERC, PDF, BOM, DRC, library lookups and a scratch file) · **Status:** schematic, project rules and library done; **`hbox-watchdog-v6.kicad_pcb` not touched** (Michelle runs *Update PCB from Schematic*, §10).

## Resumen (ES)

Se aplicaron al esquemático de v6 todos los Blockers y Majors de la auditoría que son de esquemático, y los Minors de la lista D19. El módem (U20) ahora se alimenta sólo de MAIN5V (D20/D21 eliminados), el ventilador sale de VEH5V (bloque U2 y rama Q10 en DNP) y F2 (3 A) queda antes de D10. Se añadieron limitador de antena GNSS (TPS2552), TVS en ignición, sensores TMP102 del cargador (0x48) y del módem (0x49), buffer U27 hacia el F9P, ESD en J9 y en P6/P7/P8, y se corrigieron valores (R50 1.43 k, R121 57.6 k, compensación de U20, cristales). Cada grupo se comprobó con un diff de netlist: **lo esperado coincide exactamente con lo obtenido** (137 cambios de componentes/campos/pines + 16 cambios de clase de red). ERC: **0 errores** (166 → 134 warnings, todos explicados). El PCB no se tocó; Michelle debe ejecutar *Update PCB* marcando «Delete footprints with no symbols».

## 0. Summary

| Item | Result |
|---|---|
| Files edited in place | `hbox-watchdog-v6.kicad_sch`, `hbox-watchdog-v6.kicad_pro` (net classes only), `hbox-watchdog-v6.kicad_dru`, `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` |
| `hbox-watchdog-v6.kicad_pcb` | **Byte-identical** (sha256 `6ddec80d…` before and after) |
| Changes applied | Group 1 Blockers: 10 finding IDs · Group 2 Majors: 13 · Group 3 Minors: 19 (D19 list) · Group 4 rules/library: F-01, H-04 |
| Parts | **37 added** (U27–U31, R135–R144, C161–C174, D35–D38, TP9–TP11, JP6), **3 removed** (D20, D21, PWR_FLAG PF15), **17 set DNP**, 1 symbol swapped (Y3 → `Device:Crystal_GND24`) |
| Netlist proof | Every group: expected == actual (0 unexpected, 0 missing). Baseline → final: 37 added / 3 removed / 125 field / 22 pin-net / 16 net-class changes; composed group expectations = final netlist with **0 differences** (`netlist_diff_total.md`) |
| ERC (kicad-cli 10.0.4) | **0 errors** before and after · warnings 166 → 134 (§5) |
| Overlaps / wire crossings | 30 → 30 overlaps (all pre-existing bbox hits) · 8 → 9 wire crossings (+1 is a tool bbox artefact on U30, checked in the PDF) |
| BOM | Every populated part has an LCSC number except the pre-existing copper pads TP1–TP8 (unchanged). New pads TP9–TP11 and JP6 are excluded from the BOM |
| PDF | `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf` (sha256 `a2c94a49…`) |

## 1. Hashes

| File | Before | After |
|---|---|---|
| `hbox-watchdog-v6.kicad_sch` | `ecee9fed851f02e74074340bf8361bced7c385b2502b19c368861b9851c2f04a` | `d54e330d189910afd58e18fc7cd498bdb3e6e5b7b3c4472b6cae7f95650b34c4` |
| `hbox-watchdog-v6.kicad_pro` | `25c57f3936b96a4e31cb5947668c172d318189258d6a5d2fa34d230df8958028` | `d577aa43076f5f751c291041dbf3054cb93a87facfe9f339ef91b60e073bd6ce` |
| `hbox-watchdog-v6.kicad_dru` | `47538e6cfadc0c53421ff59dadabc0e7f0ad5f11d9e2250618728788080aca1a` | `31ce0f4f23e8178b4b5e837b452e7bb8647d446ffd420559049eaaae78100831` |
| `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` | `0171be85ff9bf1d27232731a9931ad9d6c3c2bcdee2f5f3558ee94d2566413f9` | `3f38f26e435c477a7701636d4d5e1c05b4c7bd523e8dd04f9f57128657736313` |
| `hbox-watchdog-v6.kicad_pcb` | `6ddec80d1c15f79e69dff6c1a850b28345a5d826389f79cee8c61998240b36bf` | unchanged |

Pre-flight: sch and pro hashes matched the audit baseline; no `~hbox-watchdog-v6.*.lck` (only the v5 locks exist). No git was run in the mounted folder.

## 2. Changes by finding

Method: every edit is a splice on the original text, scoped to one S-expression node (property value, flag atom, label name, wire point, or a whole node for deletions). Before writing, a guard compares the multiset of UUIDs: no pre-existing UUID may disappear or change except for deliberately deleted items, and no new duplicates may appear. All untouched bytes stay identical. New symbols, wires and labels are written in KiCad's canonical layout; each new part is wired with a 2.54 mm wire to a local label carrying the exact existing net name (local `GND` labels as in the rest of the sheet). The only non-standard library symbol is TPS2552 (§7).

### 2.1 Blockers (§7.1)

| Finding | Ref | From → To | LCSC | Pins / nets |
|---|---|---|---|---|
| A-01 | D20 | SS34 (C8678) → **removed** | — | its labels `VIN_MODEM` (K) and `24V` (A) deleted |
| A-01 | D21 | PMEG3050EP (C50603) → **removed** | — | its labels `VIN_MODEM` (K) and `MAIN5V` (A) deleted |
| A-01 | PF15 | PWR_FLAG on `/VIN_MODEM` → **removed** with its label | — | the net no longer exists; PF2 already flags `/MAIN5V` |
| A-01 | U20.2, C127.1, C128.1 | `/VIN_MODEM` → **`/MAIN5V`** (labels renamed) | — | no `VIN_MODEM` label remains (6 of 6 handled) |
| A-01 | U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21 | fitted → **DNP** | unchanged | fan now from `/VEH5V` via JP1 |
| A-01 | JP1 | `…SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm` → **`Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm`** | no part | `/5V_FAN` = `/VEH5V` in copper (net-tie footprint) |
| A-01 | Q10, DzG1, Rrp1, C10, C11, C22 | fitted → **DNP** | unchanged | `/24V` loads checked first: {C10, C11, C22, D20, DzG1, Q10, Ren1, U2} + virtual PF6 → nothing left fitted |
| A-01 + V1-01 | F2 | `2A/125V-NANO2-in-holder` C206910 → **`3A/125V-NANO2-in-holder`**, MPN 0154003.DR, Littelfuse; same holder footprint | **C206912** | P1.1 → F2 → `/VIN_FUSED` |
| V1-01 | D10 | pin 1 on `/24V_IN` → **`/VIN_FUSED`** | C224019 (unchanged) | `/VIN_FUSED` = {F2.2, D10.1, Q23.2}; topology in §8 |
| A-03 | R50 | 825R/1% C50214 → **1.43k/1%** | **C22840** | 1.316–1.483 A |
| B-03 | D28 | ESD9L5.0ST5G C82326, SOD-923 → **PESD0402-240**, `Diode_SMD:D_0402_1005Metric`, Littelfuse | **C1975527** | pin 1 `/RF_ANT_LTE`, pin 2 GND (symbol kept; pins 1/2 map to the 0402 pads) |
| C-01 | **U28 (new)** | TPS2552DBVR, SOT-23-6 | **C46506** | 1 IN `/3V3_GNSS` · 2 GND · 3 ~EN `/GNSS_ANT_OFF` · 4 ~FAULT `/GNSS_ANT_SHORT_N` · 5 ILIM `/3V3_GNSS` (75 mA) · 6 OUT **`/ANT_BIAS`** |
| C-01 | **R135 (new)** | 100k, ~EN → GND (antenna ON by default) | C25803 | `/GNSS_ANT_OFF` – GND |
| C-01 | **R136 (new)** | 10k, FAULT pull-up | C25804 | `/3V3_GNSS` – `/GNSS_ANT_SHORT_N` |
| C-01 | L21.2, C144.1, C145.1 | `/VCC_RF_GNSS` → **`/ANT_BIAS`** | unchanged | |
| C-01 | U18.7 VCC_RF | `/VCC_RF_GNSS` → **NC** (label deleted, no-connect flag added) | — | |
| C-01 | U18.5 ANT_OFF | NC flag → label **`/GNSS_ANT_OFF`** | — | |
| F-02 | **D35 (new)** | SMBJ33A, `Diode_SMD:D_SMB` (same symbol as D10) | **C224019** | 1 (cathode) `/IGN_IN`, 2 GND; place at P1.3 |
| F-02 | Rig1 | unchanged (22k C88614); move to P1.3 is layout | — | `/IGN_IN` = {P1.3, Rig1.1, D35.1} |
| H-01 | U15 | `Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm` → **`Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`** | C15846 (unchanged) | |
| H-02 | U10 | C729142 (SC16IS762) → **C57156**, MPN SC16IS752IPW,128 (value already SC16IS752IPW; symbol kept) | **C57156** | pinout identical |
| H-02 | R53 | 499k/1% C131054 → same value, MPN RCT03499KFLF, HKR | **C177479** | |
| H-04 | U25 | no `LCSC Part` in the schematic symbol; the field comes from the library footprint → removed there (§7) | C524806 | |
| F-01 | project | net classes + `.kicad_dru` (§6) | — | |
| G-01 | MH4 + heatsink pair | **not applied** — board-only (§10) | — | |

### 2.2 Majors (§7.2)

| Finding | Ref | From → To | LCSC | Pins / nets |
|---|---|---|---|---|
| A-04 | R121 | 53.6k/1% C23074 → **57.6k/1%** | **C23082** | U25 5.18/5.32/5.46 V |
| A-05 | **C161, C162 (new)** | 47uF X7R 1210 | **C5440143** | `/MAIN5V` – GND (at U6 VSYS 1/24) |
| A-08 | U17 | AMS1117-3.3 C6186 → **TLV1117LV33DCYR** (TI); symbol `Regulator_Linear:AMS1117-3.3` kept (same 1 GND / 2 OUT / 3 IN, tab = OUT) | **C15578** | pins unchanged |
| A-09 | C78 | 220uF/10V MVG C2827940 → **220uF/16V polymer**, Lelon OVZ221M1CTR-0608, same CP_Elec_6.3x7.7 | **C881921** | pin 1 `/VEH5V` = + pad |
| B-02 | C130, C131 | same as C78 → **220uF/16V polymer** | **C881921** | |
| B-02 | R116 | 14k C22803 → **113k/1%** | **C22862** | |
| B-02 | C141 | 3.3nF C1536 → **6.8nF** X7R 0402 | **C1542** | |
| B-02 | C142 | 47pF C1567 → **56pF** C0G 0402 | **C1572** | |
| B-02 | **C166, C167 (new)** | 22uF 16 V X5R 0805 | **C86817** | `/VBAT_MODEM` – GND (at L20.2) |
| F-03 | **C163, C164 (new)** | 22uF 16 V 0805 | **C86817** | `/MAIN5V` – GND (at U20.2) |
| F-03 | **C165 (new)** | 220uF/16V polymer, `Device:C_Polarized`, CP_Elec_6.3x7.7 | **C881921** | 1 (+) `/MAIN5V`, 2 GND |
| F-51 | **U29 (new)** | TMP102AIDRLR, SOT-563, **I²C 0x48** | **C99269** | 1 SCL `/I2C_SCL` · 2 GND · 3 ALERT NC · 4 ADD0 GND · 5 V+ `/3V3` · 6 SDA `/I2C_SDA` |
| F-51 | **C168 (new)** | 100nF 0603 | C14663 | `/3V3` – GND |
| F-51 | **R137 / R138 / C169 (new)** | 100k/1% top · 120k/1% bottom · 10nF 0603 | C25803 · **C25808** · C1589 | `/NTC` → R137 → **`/NTC_CELL`** → R138/C169 → GND |
| F-51 | U16.25 PC5 | NC flag → label **`/NTC_CELL`** (ADC1_IN15) | — | |
| C-02 | U21 | AP2112K-3.3 C51118 → **TPS7A2033PDBVR** (TI); symbol `Drogheda-sym:LDO_SOT23-5` kept (its generic 1 VIN / 2 GND / 3 EN / 4 NC / 5 VOUT pinout is the TPS7A20 DBV pinout) | **C2862740** | pins unchanged |
| E-01 | U12.2 EN | `/SYS5V` → **`/ETH_PWR_EN`** (label renamed; U12.7 VIN stays on `/SYS5V`) | — | |
| E-01 | U16.54 PD2 | NC flag → label **`/ETH_PWR_EN`** | — | |
| E-01 | **R139 (new)** | 100k PD | C25803 | `/ETH_PWR_EN` – GND |
| E-02 | **R140 (new)** | 4.7k | **C23162** | `/ETH_RST` – GND (at U11.37) |
| D-01 | **U27 (new)** | 74LVC1G125GV,125 (Nexperia), SOT-753 on `Package_TO_SOT_SMD:SOT-23-5` (same SC-74A land) | **C12518** | 1 ~OE GND · 2 A `/DOUT_4G` · 3 GND · 4 Y **`/DOUT_4G_F9P`** · 5 VCC `/3V3_GNSS` |
| D-01 | **C170 (new)** | 100nF 0603 | C14663 | `/3V3_GNSS` – GND |
| D-01 | U18.26 RXD2 | `/DOUT_4G` → **`/DOUT_4G_F9P`** | — | PC7/R106 stay on `/DOUT_4G` |
| D-01 | Rdfu1 | 22k C88614 → **100k** | **C25803** | |
| G-02 | **U30 (new)** | USBLC6-2SC6, SOT-23-6 | **C7519** | 1,6 `/USB_DM` · 3,4 `/USB_DP` · 5 `/USB_VBUS` · 2 GND |
| H-02b | R56, R57, R58, R85, R87, Rgs1 | C103211 (100k 5 %) → **C25803** (100k 1 %) | **C25803** | value text kept `100k`. R20/Ren1/Rfreq1 not changed (U2 block is DNP) |
| V1-01, F-12, F-05, F-06, C-04, A-07, A-02 | — | layout-only → §10 | | |

### 2.3 Minors (D19 list)

| Finding | Ref | From → To | LCSC | Pins / nets |
|---|---|---|---|---|
| A-11 | R56.2 | GND → **`/3V3`** (label renamed): CHGOFF pulled up → charger **OFF** without MCU | C25803 | |
| A-13 | U6.20, TP2.1 | `/PFO_TP` → **`/PFO`** (labels renamed) | — | |
| A-13 | U16.29 PB10 | NC flag → label **`/PFO`** | — | |
| A-13 | **R141 (new)** | 100k PU | C25803 | `/3V3` – `/PFO` |
| B-09 | R132, R133, R134 | 0R C304185 → **22R** | **C23345** | R131 (VDD) stays 0R |
| B-09 | **C171 (new)** | 100nF 0402 at J14.C1 | **C1525** | **`/SIMB_VDD`** – GND (J14.C1 is on `/SIMB_VDD`, after R131; the report's "(`/SIM_VDD`)" names the modem side) |
| B-10 | **R142 (new)** | 100k PD | C25803 | `/MODEM_STATUS` – GND |
| B-10 | **R143 (new)** | 100k PU | C25803 | `/3V3` – `/DIN_4G` |
| B-10 | R106 | 100R C22775 → **1k** | **C14676** | |
| C-07 | U18.50 SAFEBOOT_N | NC flag → label **`/GNSS_SAFEBOOT_N`** | — | |
| C-07 | **TP10, TP11 (new)** | `TestPoint:TestPoint_Pad_D1.0mm`, not in BOM | no part | TP10 `/GNSS_SAFEBOOT_N`, TP11 `/GNSS_RESET_N` |
| D-02 | Y3 | `Device:Crystal` HC-49SD C14872 → **`Device:Crystal_GND24`**, `Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm`, SCTF SX3B25.000F1010F30 (25 MHz, CL 10 pF, ESR 30 Ω) | **C2901684** | pin 1 `/HSE_IN` · **pin 3 `/HSE_OUT`** · pins 2/4 **GND** (new wire + GND label). Symbol swap needed: a 2-pin symbol on the 4-pad land would have put HSE_OUT on GND pad 2. New pin 3 sits exactly where old pin 2 was, so the `HSE_OUT` label connects unchanged |
| D-02 | C113, C114 | 15pF C1644 → **12pF** C0G | **C38523** | |
| D-03 | Y4 | FC-135 CL 12.5 pF C32346 → **FC-135 CL 7 pF** (Epson Q13FC13500002; 7 pF confirmed on distributor listings) | **C48615** | footprint unchanged |
| D-03 | C115, C116 | 12pF C38523 → **6.8pF** C0G | **C1679** | |
| D-05 | Rigb1 | 3.3k C22978 → **2.2k** | **C4190** | ratio 0.0833 |
| D-09 | **R144 (new)** | 100k PD at Q5 base | C25803 | `/BASE_LS` – GND |
| D-12 | U16.42 PA9 | NC flag → label **`/USART1_TX`** | — | |
| D-12 | **TP9 (new)** | `TestPoint:TestPoint_Pad_D1.5mm`, not in BOM | no part | `/USART1_TX` |
| E-03 | C95, C96 | 18pF C1647 → **33pF** C0G (Y1 kept) | **C1663** | |
| E-04 | C91 | 4.7uF C1779 0805 → **10nF** X7R, `C_0603_1608Metric` | **C1589** | `/ETH_1V2` |
| E-04 | C90 | 10uF C440198 → **4.7uF** 0805 | **C1779** | `/ETH_TOCAP` |
| E-04 | **C172, C173 (new)** | 100nF 0603 at AVDD 4/8 and 11/21 | C14663 | `/3V3_ETH` – GND |
| F-52 | **U31 (new)** | TMP102AIDRLR, **I²C 0x49** (ADD0 → V+) | **C99269** | 1 `/I2C_SCL` · 2 GND · 3 NC · 4 `/3V3` · 5 `/3V3` · 6 `/I2C_SDA` |
| F-52 | **C174 (new)** | 100nF 0603 | C14663 | `/3V3` – GND |
| G-03 | P11, P12 | `…MC_1,5_3-G-3.5_1x03_P3.50mm_Vertical` (not in library) → **`Connector_Phoenix_MC:PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal`**; populated (D10) | C5160226 (unchanged) | |
| G-03 | J10 | `Connector_RJ45:…` (nickname not configured) → **`Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal`**; populated | C12074 (unchanged) | |
| G-04 | **JP6 (new)** = JP_CUT | `Jumper:SolderJumper_2_Open`, open footprint, value CUTOFF_BYPASS, not in BOM | no part | 1 `/MAIN5V`, 2 `/SYS5V` |
| G-08 | **D36, D37, D38 (new)** | PESD5V0S1BA, `Diode_SMD:D_SOD-323` (same as D14–D16) | **C2827694** | pin 1 `/NRST` / `/NTC_TEMP` / `/NTC2`, pin 2 GND |
| H-08 | C22, Y2 | value text "22uF/50V" → **"10uF/50V"**; "1.8432MHz" → **"3.6864MHz"** | unchanged | |
| B-15 | R107, R108 | value "0R-DNP" → **"0R-NEVER-FIT"** + `Note` field (still DNP) | — | |
| J-04 | 23 orphan NC flags (x = 453.898 / 484.378) | **deleted** | — | |
| J-04 | NC flags on U16.37, U16.38, U10.13, U10.14 | **deleted** (pins stay on their nets) | — | |
| J-04 | wire stubs | **2b755f7f deleted** (the dangling stub over P1.4); **7c1dbfc0 trimmed** from y 219.71 to 218.948 so it ends at its GND label (R52.2 stays on GND); **46f71e27 kept** (it carries P1.4's GND label) and the P1.4 junction kept. See §12 | — | no net change |

## 3. New parts — where they are on the sheet

All new parts sit in free space found with an occupancy map of the sheet (symbols, pins, labels, wires, texts), on the 1.27 mm grid, each cluster with a blue note "v6 audit <ID>: …" stating the physical placement rule. Coordinates are schematic mm (A1 sheet).

| Cluster | Refs | Sheet position | Block it belongs to |
|---|---|---|---|
| C-01 | R135, U28, R136 | (402–475, 196) | below U18 / L21 bias-T |
| F-02 | D35 | (94, 36) | beside P1 |
| A-05 | C161, C162 | (377–391, 226) | right of C32–C34 |
| F-03 | C163, C164, C165 | (184–213, 295) | left of U20 |
| B-02 | C166, C167 | (401–415, 404) | right of U19 (VBAT caps) |
| F-51 | U29, C168 | (257–287, 141) | above the charger passives (R50/R55) |
| F-51 | R137, R138, C169 | (264–298, 220) | beside R50/R56 |
| E-01 | R139 | (674, 217) | at U12 |
| E-02 | R140 | (692, 60) | at U11 |
| D-01 | U27, C170 | (268–304, 458) | below U23/U24 |
| G-02 | U30 | (489, 307) | beside J9 |
| A-13 | R141 | (218, 246) | near TP1/TP2 |
| B-09 | C171 | (328, 460) | above J14 |
| B-10 | R142, R143 | (284–298, 498) | below U24 |
| C-07 | TP10, TP11 | (522–538, 104) | right of U18 |
| D-09 | R144 | (137, 113) | at Q5 |
| D-12 | TP9 | (547, 420) | right of U16 |
| E-04 | C172, C173 | (730–745, 183) | below C94 |
| F-52 | U31, C174 | (188–218, 414) | left of U23/U24 (modem block) |
| G-04 | JP6 | (281, 25) | beside P5 |
| G-08 | D36 / D37, D38 | (328, 133) / (476–503, 232) | at P6 / near P7–P8 |

## 4. Netlist proof

Netlists exported with kicad-cli through the KiCad MCP after each committed group (`kicad/_to_delete/v6-apply-20260928/netlists/00…05.xml`). `tools/ndiff.py` compares refs, value, footprint, lib_id, every field and property, DNP / BOM / position flags, **ref.pin → net** and net class. The expected change set of each group was written by the edit script *before* the file was committed and asserted against the actual diff.

| Group | Netlist | Expected (added / removed / field / pin-net / class) | Actual | Result |
|---|---|---|---|---|
| 1 Blockers | 00-baseline → 01-blockers | 4 / 3 / 38 / 9 / 0 = 54 | 4 / 3 / 38 / 9 / 0 | **MATCH** |
| 2 Majors | 01 → 02-majors | 17 / 0 / 36 / 4 / 0 = 57 | 17 / 0 / 36 / 4 / 0 | **MATCH** |
| 3 Minors | 02 → 03-minors | 16 / 0 / 51 / 9 / 0 = 76 | 16 / 0 / 51 / 9 / 0 | **MATCH** (after the J-04 correction, §12) |
| 4 Project rules | 03 → 04-rules (schematic untouched) | 0 / 0 / 0 / 0 / 16 | 0 / 0 / 0 / 0 / 16 | **MATCH** |
| 5 Cosmetic (U30 ref text) | 04 → 05-final | 0 | 0 | **MATCH** |
| **Total** | 00 → 05-final | composition of groups 1–5 | 37 / 3 / 125 / 22 / 16 | **0 differences** in every ref, attribute, pin and class |

Field changes count both `footprint` and the `Footprint` field when a footprint changes. The 22 pin-net changes: U20.2, C127.1, C128.1 → `/MAIN5V`; D10.1 → `/VIN_FUSED`; L21.2, C144.1, C145.1 → `/ANT_BIAS`; U18.7 → NC; U18.5 → `/GNSS_ANT_OFF`; U12.2 → `/ETH_PWR_EN`; U16.54 → `/ETH_PWR_EN`; U16.25 → `/NTC_CELL`; U18.26 → `/DOUT_4G_F9P`; R56.2 → `/3V3`; U6.20, TP2.1 → `/PFO`; U16.29 → `/PFO`; U16.42 → `/USART1_TX`; U18.50 → `/GNSS_SAFEBOOT_N`; Y3.2 → GND, Y3.3 → `/HSE_OUT`, Y3.4 → GND. Full machine list: `netlist_diff_total.md`; per group: `out/0N-*/netlist_diff.md`.

UUIDs: no existing symbol changed UUID (checked per group); the guard also held on every write.

## 5. ERC (kicad-cli 10.0.4 via KiCad MCP)

Per-category counts come from copies with narrowed ERC severities (`kicad/_to_delete/v6-apply-20260928/erc_work/`), because the MCP prints only 30 items. Baseline categories are the audit's (`evidence/erc_summary.md`, same file hash); final categories are from runs on the final file, and they add up to the full run.

| Category | Before | After | Why |
|---|---|---|---|
| Errors | 0 | **0** | |
| pin_to_pin | 104 | 102 | −2 from D21 (unspecified-pin easyeda symbol) removed; new symbols have typed pins |
| no_connect_dangling | 23 | 0 | J-04 orphan flags deleted |
| lib_symbol_mismatch | 22 | 21 | Y3 now uses a fresh `Device:Crystal_GND24` copy |
| lib_symbol_issues (not in library) | 10 | 11 | +1: `Drogheda-sym:TPS2552DBV` is embedded only (§7). The 10 old ones remain (re-link skipped, §9) |
| footprint_link_issues | 3 | 0 | G-03 (P11, P12, J10) |
| no_connect_connected | 2 | 0 | J-04 |
| unconnected_wire_endpoint | 2 | 0 | J-04 (stub deleted / tail trimmed) |
| All other checks (dangling labels, unconnected pins, power pins, …) | 0 | 0 | |
| **Total warnings** | **166** | **134** | |

During Group 3 an intermediate run showed 3 errors (label/pin not connected at P1.4 and R52.2) from my first J-04 stub deletion; the netlist diff flagged the same two pins. Both were fixed before continuing (§12).

## 6. Project rules (F-01, D18)

### 6.1 Net classes (`hbox-watchdog-v6.kicad_pro`)

All old patterns were replaced by exact full net names (the un-prefixed duplicates and dead patterns `3V3_MODEM`, `SW3_NODE` are gone). In the final netlist every pattern resolves to a real net.

| Class | Nets | Clearance | Track | Via | Priority |
|---|---|---|---|---|---|
| HV24 | `/24V_IN` `/VIN_FUSED` `/VIN_PROT` `/24V` `/IGN_IN` `/Q10_GATE` `/Q23_GATE` `/SW_PWRIN` `/BOOT_PWRIN` `/SW_FAN` `/BST_FAN` | 0.3 (was 0.5) | 1.0 (was 0.5) | 0.8/0.4 | 0 |
| PWR_HI | `/BAT_PLUS` `/SW_BAT` `/MAIN5V` `/VEH5V` `/SYS5V` `/VIN_SW` | 0.15 (was 0.2) | 1.5 | 0.8/0.4 | 1 |
| PWR_MODEM (new) | `/VBAT_MODEM` | 0.15 | 1.5 | 0.8/0.4 | 2 |
| PWR_MID | `/SW_5V` `/SW_IN` `/5V_FAN` `/FAN_RET` | 0.15 (was 0.2) | 0.6 (was 1.0) | 0.8/0.4 | 3 |
| RF (new) | `/RF_GNSS` `/RF_ANT_GNSS` `/RF_LTE` `/RF_ANT_LTE` | 0.2 (CPWG gap) | 0.3 (CPWG width; final value from JLC's calculator) | 0.6/0.3 (no vias intended) | 4 |
| Default | everything else, incl. `/3V3_ETH` (moved out of PWR_MID, J-02), `/EN_FAN`, `/EN_PWRIN`, `/SW_MODEM`, `/BST_MODEM` | 0.15 (was 0.2) | 0.2 | 0.6/0.3 | — |

Netlist class changes (16): to HV24 `/VIN_FUSED` `/VIN_PROT` `/24V` `/IGN_IN` `/Q10_GATE` `/Q23_GATE` `/SW_PWRIN` `/BOOT_PWRIN` `/BST_FAN` (from Default) and `/SW_FAN` (from PWR_MID); `/3V3_ETH` PWR_MID → Default; `/VBAT_MODEM` → PWR_MODEM; the four RF nets → RF.

**Decision on the HV24 list (differs from the report table, which predates A-01):** `/VIN_MODEM` no longer exists, and **`/SW_MODEM` and `/BST_MODEM` were left out of HV24**. With A-01, U20 runs from `/MAIN5V` (≤ 5.5 V), so they are 5 V-class switch/boot nodes; in HV24 they would raise false 0.3/0.5 mm errors around U20 (like `/ETH_SW`, they stay Default with the T15 width rule). `/SW_FAN`, `/BST_FAN`, `/24V` and `/Q10_GATE` **stay HV24**: the U2 and Q10 footprints remain on the board as DNP and would carry vehicle voltage if ever fitted.

### 6.2 `.kicad_dru` (verify_2's corrected set, verbatim; replaces "Minimum clearance 1", "HV24 clearance", "HV24 exception: MP1584EN land pattern")

```
(rule "Floor 0.15 (non-HV24, non-RF)"
	(condition "A.NetClass != 'HV24' && B.NetClass != 'HV24' && A.NetClass != 'RF' && B.NetClass != 'RF'")
	(constraint clearance (min 0.15mm))
)
(rule "HV24 to HV24"
	(condition "A.NetClass == 'HV24' && B.NetClass == 'HV24'")
	(constraint clearance (min 0.2mm))
)
(rule "HV24 outer"
	(layer outer)
	(condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
	(constraint clearance (min 0.3mm))
)
(rule "HV24 inner"
	(layer inner)
	(condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
	(constraint clearance (min 0.5mm))
)
(rule "HV24 IC land patterns"
	(layer outer)
	(condition "A.Type == 'Pad' && B.Type == 'Pad' && ((A.memberOfFootprint('U2') && B.memberOfFootprint('U2')) || (A.memberOfFootprint('U20') && B.memberOfFootprint('U20')) || (A.memberOfFootprint('U25') && B.memberOfFootprint('U25')))")
	(constraint clearance (min 0.15mm))
)
```

A 3-line comment header was added above the set. The silkscreen text rule and the three T15 power-width warning rules are unchanged (the T15 rule still names `/VIN_MODEM`, now a dead name; harmless). The U20 clause of the land-pattern rule no longer matches anything after the HV24 decision above; it was kept to stay verbatim with verify_2.

## 7. Library

- **H-04 fixed:** `(property "LCSC Part" "C2071691")` deleted from `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod` (one line, span-scoped; the rest of the file is byte-identical). That footprint is shared by U20 (AP64350, C2071691) and U25 (TPS54360B, C524806); both now resolve through their `LCSC` fields. The board copy of U25 still carries the field until Michelle updates the footprint from the library (§10).
- **Other `LCSC Part` values in `Drogheda-v6.pretty` checked against their users (not stripped):** IND-SMD_L13.5-W12.5 C840531 = L22 ✓ · LCC-LGA-102 C5120257 = U18 ✓ · LGA-124 C18548276 = U19 ✓ · LGA-12 C5126709 = U26 ✓ · RF-SMD_FRF05002 C88374 = J12, J13 ✓ · SMA_L4.4 C113952 = D22 ✓ · VSSOP-8 C730237 = U23, U24 ✓ · SOD-923 C82326 = D27 ✓ (D28 moved to 0402) · **SOD-128 C50603 now unused** (D21 removed). None is wrong.
- **TPS2552 symbol:** KiCad 10 has no TPS2552 symbol (the MIC2007/2008 SOT-23-6 switches have a different pinout), so `Drogheda-sym:TPS2552DBV` was authored and **embedded in the schematic only**: box symbol, 1 IN power_in, 2 GND power_in, 3 ~EN input, 4 ~FAULT open_collector, 5 ILIM passive, 6 OUT power_out, footprint SOT-23-6, TI datasheet link. `Drogheda-sym.kicad_sym` was not edited (outside this pass's file set; shared with v5), which is the +1 ERC "not found in library" warning. Copy it into the library in a library pass.
- New library symbols embedded from KiCad 10: `74xGxx:74LVC1G125`, `Power_Protection:USBLC6-2SC6`, `Device:Crystal_GND24`. `Sensor_Temperature:TMP102xxDRL` was already cached in the sheet and is content-identical to the library.

## 8. Reverse-polarity and fusing topology after V1-01 / A-01

```
P1.1 ─ /24V_IN ─ F2 (3 A Nano2, socketed) ─ /VIN_FUSED ─┬─ D10 SMBJ33A (pad 1 cathode) ─ GND
                                                        └─ Q23 IRFR5305: D=/VIN_FUSED, S=/VIN_PROT, G=/Q23_GATE
                                                             D33 zener S→G clamp, R119 gate to GND
/VIN_PROT ─ D32 SMCJ33A, C149–C151, U25 (TPS54360B) → /VEH5V
/24V_IN also ─ Q10.D (Q10 branch DNP: /24V carries no fitted part)
```

- **Correct polarity:** current flows P1 → F2 → Q23 body diode (drain→source), Q23 enhances with its gate pulled to GND (V_GS clamped at −15 V by D33) → /VIN_PROT. D10 and D32 clamp transients; D10 is now behind F2, so a TVS that fails short opens F2 instead of loading the harness.
- **Reversed P1:** /VIN_FUSED goes negative; Q23's gate (to GND) is positive against its source, so Q23 stays off and its body diode is reverse-biased. D10 forward-conducts GND → /VIN_FUSED through F2 → **F2 blows** (socketed, replaceable). Before V1-01, D10 sat on /24V_IN ahead of F2 and would have carried harness-fuse current.
- The only unfused copper left on /24V_IN is P1.1 → F2.1 and the Q10.D pad of the DNP Q10. If the Q10 branch is ever re-fitted, move Q10.D to /VIN_FUSED first.
- U20 now sits on /MAIN5V, upstream of the P5 cutoff (A-01 note): P5 still removes SYS5V → MCU unpowered → R113 holds U20 EN low (µA).

## 9. Skipped items and decisions

**Not applied**
1. **G-01** (restore MH4 at (193.2, 90.3), heatsink-clamp holes MH11 + partner): board-only mounting holes; Michelle (D11 makes it a Blocker).
2. **J-04, re-linking the 10 "not found" symbols** (Q_*MOS_G?S ×7, D_Zener_ANK ×2, PCF8574): needs writing their definitions into the shared `Drogheda-sym.kicad_sym` (outside the allowed file set) and swapping 10 lib_ids. Cosmetic; left as warnings. The 22 library mismatches were left alone as the report asks (no bulk update).
3. **G-08, optional 100 Ω series resistor on NRST:** optional in the report; it would split `/NRST`. Not applied.
4. **D-08** (board-ID strap), **H-03** (MWSA0804S land), **J-03** (library pin types): excluded by D19.
5. Layout-only Majors (V1-01 layout, F-12, F-05, F-06, C-04, A-07) and A-02: layout list, §10.

**Decisions taken while applying (beyond the letter of §7)**
- DNP marking follows the sheet's existing convention (`(dnp yes)` only, as on C146/C147, R107/R108, R124/R125, R127–R130, U22): footprints stay on the board with the DNP attribute, and KiCad leaves DNP parts out of BOM/CPL outputs.
- U17, U21, U10 kept their symbols (identical pin numbering) and changed fields only; the netlist diff shows value/LCSC/MPN changes only for them.
- New test pads (TP9–TP11) and JP6 are excluded from BOM and position files (no purchasable part). TP1–TP8 were left as they are.
- HV24 net list: §6.1. PF15 removal: §2.1. C171 net: §2.3.

## 10. Layout delta for Michelle

Run **Tools → Update PCB from Schematic** on `hbox-watchdog-v6.kicad_pcb` with **"Delete footprints with no symbols" ticked** (earlier runs did not delete removed footprints), and "Update footprints" on so the changed footprints are swapped. Then run DRC (new rules, below).

**New footprints to place (37)**

| Ref | Footprint | Where / constraint (from the audit) |
|---|---|---|
| U28 | SOT-23-6 | GNSS bias switch next to L21/C144/C145 at J12; `/ANT_BIAS` ≥ 1 mm from the RF line with a stitched GND strip (F-06); short feed from `/3V3_GNSS` |
| R135, R136 | 0603 | at U28 pins 3 and 4 |
| D35 | D_SMB | **at P1.3**; with Rig1 moved to ≤ 3 mm of copper from P1.3 so `/IGN_IN` is ≤ 3 mm on F.Cu and the long run becomes `/IGN_SENSE` (F-02) |
| C161, C162 | 1210 | ≤ 2 mm from U6 VSYS pins 1/24, GND on the U6 EP copper (A-05/A-02) |
| C163, C164 | 0805 | ≤ 2–3 mm from U20.2, GND on the U20 EP copper (F-03) |
| C165 | CP_Elec_6.3x7.7 | at U20.2 (F-03) |
| C166, C167 | 0805 | ≤ 3 mm from L20.2 (B-02) |
| U29 + C168 | SOT-563 + 0603 | **between U6 and L6, ≤ 5 mm from the U6 EP** (F-51, R4) |
| R137, R138, C169 | 0603 | pack-NTC tap: R138/C169 at U16 pad 25 (PC5); R137 anywhere on `/NTC` |
| R139 | 0603 | at U12 pin 2 (EN); new track `/ETH_PWR_EN` to U16 pad 54 (PD2) |
| R140 | 0603 | at U11.37 (`/ETH_RST`) |
| U27 + C170 | SOT-23-5 (SOT-753) + 0603 | **at U18.26 (RXD2)**; VCC from `/3V3_GNSS` |
| U30 | SOT-23-6 | **≤ 3 mm of copper from the J9 pads**, D+/D− routed through the device pads, GND via ≤ 1 mm (G-02) |
| R141 | 0603 | `/PFO` pull-up near U16 pad 29 (PB10) |
| C171 | 0402 | at J14.C1 |
| R142, R143 | 0603 | on `/MODEM_STATUS` (PC9) and `/DIN_4G`, any convenient spot |
| TP10, TP11 | TestPoint_Pad_D1.0mm | near U18 pins 50 (SAFEBOOT_N) and 49 (RESET_N), next to a GND pad (C-07) |
| R144 | 0603 | at Q5 base |
| TP9 | TestPoint_Pad_D1.5mm | PA9 debug-TX pad next to TP3–TP5 (D-12) |
| C172, C173 | 0603 | at W5500 AVDD pins 4/8 and 11/21 |
| U31 + C174 | SOT-563 + 0603 | **between U19 and U20** (F-52) |
| JP6 | SolderJumper 2-pad, open | across P5 (`/MAIN5V`–`/SYS5V`), silk "CUTOFF BYPASS" (G-04) |
| D36, D37, D38 | SOD-323 | ≤ 3 mm from P6.1, P7.1, P8.1 to GND (G-08) |

**Removed footprints:** D20 (D_SMA), D21 (SOD-128). (PF15 is a virtual power flag, no footprint.)

**Footprint changes:** U15 → narrow `SOIC-16_3.9x9.9mm` (re-place C84–C88, local reroute) · D28 → `D_0402_1005Metric` (with the F-06 LTE reroute) · Y3 → `Crystal_SMD_3225-4Pin_3.2x2.5mm` (pad 1 HSE_IN, pad 3 HSE_OUT, pads 2/4 GND; ≤ 3–5 mm from PH0/PH1, no inner track under it) · C91 → 0603 · JP1 → Bridged (net-tie) · J10 → `Connector_RJ:` nickname (same geometry) · P11/P12 → Horizontal (already so on the PCB) · U25 → re-pull the footprint from the library so its board copy loses `LCSC Part` (H-04) · Y4 and F2 keep their footprints.

**DNP changes:** set DNP: U2, L2, Dbk1, Cbst1, Rcomp1, Ccomp1, Rfreq1, Ren1, Ren2, R20, R21, Q10, DzG1, Rrp1, C10, C11, C22. **Clear DNP:** J10, P11, P12 (populated per D10).

**Nets that change routing**
- `/VIN_MODEM` disappears: U20.2, C127, C128 go to **`/MAIN5V`** (≥ 1.5–2 mm all the way to U20; delete the 48 mm `/VIN_MODEM` run, A-01/A-07).
- `/VIN_FUSED` gains D10.1: P1.1 → F2 → {D10, Q23.D}; `/24V_IN` = P1.1, F2.1, Q10.D only.
- `/ANT_BIAS` (U28.6 → L21.2, C144, C145); U18.7 is now NC; `/GNSS_ANT_OFF` (U18.5 → U28.3, R135); `/GNSS_ANT_SHORT_N` gains U28.4 and R136.
- `/ETH_PWR_EN` (U12.2, U16.54, R139); U12.2 leaves `/SYS5V`.
- `/DOUT_4G_F9P` (U27.4 → U18.26); U18.26 leaves `/DOUT_4G`; U27.2 joins `/DOUT_4G`.
- `/PFO` (renamed from `/PFO_TP`: U6.20, TP2, plus U16.29 and R141).
- `/NTC_CELL` (U16.25, R137, R138, C169); `/NTC` gains R137.
- `/GNSS_SAFEBOOT_N` (U18.50, TP10); `/USART1_TX` (U16.42, TP9).
- R56.2 moves from GND to `/3V3`; Y3 pads re-netted as above.

**DRC with the new rules (run on a copy of the current, not-yet-updated board):** 161 clearance errors (was 0). **149 of them are zone-fill proximities** (stored fills at 0.15 mm to HV24 and RF nets); a zone refill clears them. **12 are real copper spacings:** `/IGN_IN` on In2 vs GND via 0.250, `/FAN_PWM` 0.291, `/5V_FAN` via 0.300, `/NTC2` 0.305, `/VEH5V` via 0.340 (all F-02, disappear with the P1.3 move); `/VIN_PROT` vs `/VEH5V` 0.157 and 0.191 at (175.5, 113.8); `/USB_VBUS` vs Q23.1 `/Q23_GATE` 0.225; `/SW_PWRIN` vs GND track 0.270; `/24V` vs `/COMP_FAN` 0.290 ×2 (DNP branch, but the copper exists); RF class: `/RF_LTE` via vs `/PWR_CTRL` 0.150 (goes away with the F-06 F.Cu reroute). **Caveat:** KiCad lists only one violation between the long In2 `/IGN_IN` segment and `/VEH5V` (the via at 0.340 mm); the parallel `/VEH5V` 1.0 mm tracks beside it are 0.221–0.240 mm away (recomputed from the track coordinates, matching the audit's 0.221 mm) and are not listed as separate items. So do not read the DRC count as the full list; the F-02 move removes the whole In2 `/IGN_IN` run anyway. `track_width` warnings drop 183 → 121 (`/3V3_ETH` now Default, PWR_MID width 0.6). Other DRC items unchanged (82 lib_footprint_mismatch, 4 lib_footprint_issues, 11 silk_overlap, 2 silk_over_copper, 1 silk_edge). After Update PCB, expect new HV24 items on `/VIN_FUSED` at D10 and removal of the `/VIN_MODEM` ones. Check once with Inspect → Clearance Resolution that the classes survived the GUI save (resync protocol §5).

**Order notes (from the part lookups):** C2862740 (TPS7A2033PDBVR, U21) is listed by JLC under "Pre-ordered Chips": pre-order it into the account like J14. P11/P12 C5160226 stock 512 (enough for 20 boards). Re-check stock on order day (D14).

## 11. Firmware notes (for FW 0.7.x `board_v6.h`, D15)

1. **PD2 = `ETH_PWR_EN`**: U12 (3V3_ETH) enable, R139 100 k pull-down → Ethernet OFF in reset/DFU/battery; drive HIGH only on vehicle power when Ethernet is needed; keep SPI2 and PA15 low while it is off.
2. **PB10 = `PFO`**: LTC4040 PFO, open-drain, R141 100 k pull-up to 3V3; EXTI10 falling = backup entry (VEH5V < PFI 4.40 V falling / 4.51 V rising). Update `V5_PFI` to 4.40 V.
3. **PC5 = `NTC_CELL`** (ADC1_IN15): pack NTC through 100 k/120 k (ratio 120/220) + 10 nF; Rntc = R55·Vntc/(VEH5V − Vntc) with VEH5V from PA4; valid only with VEH5V present. Feed `tcell` into `CHG_CELL_HOT/COOL`.
4. **CHGOFF default:** R56 is now a pull-**up** to 3V3 → PA8 (`CHRG_EN`, drives LTC4040 CHGOFF) high = charger **off** whenever the MCU is not driving. Polarity unchanged: firmware drives PA8 LOW to allow charging.
5. **Ignition on PA5 (ADC1_IN5), read analog**, no internal pull: Rigb1 = 2.2 k → ratio 2.0 k/24.0 k = **0.0833**: 12 V → 1.00 V, 24 V → 2.00 V, 36 V → 3.00 V, full scale 39.6 V. Add `vign` to `$PHLG`.
6. **TMP102 at 0x48 = charger sensor (U29)**, **0x49 = modem-area sensor (U31)**; no address clash (0x18 SC7A20, 0x20 PCF8574, 0x44 SHT40, 0x4D SC16IS752). Add `tchg`, `tmodem` to `$PHLG`; shed charge on `tchg` > 85 °C.
7. GNSS antenna: F9P ANT_OFF now drives TPS2552 ~EN (set `CFG-HW-ANT_CFG_VOLTCTRL` = 1, `SHORTDET` = 1). PC2 `GNSS_ANT_SHORT_N` is driven by TPS2552 ~FAULT (open drain, 10 k to 3V3_GNSS): LOW = short or rail off. PC1 `GNSS_ANT_DETECT` remains undriven (keep hi-Z, infer open antenna from C/N0).
8. U27 now isolates F9P RXD2: F9P-only power cycles with the modem up become safe on boards that have it; keep the 0.5.5/0.5.6 back-feed rules for PA2/PA10/PC7/PC12. Rdfu1 is 100 k (≤ 27 µA into TXD2 with the F9P off).
9. `/MODEM_STATUS` (PC9) has a 100 k pull-down and `/DIN_4G` a 100 k pull-up in hardware: no internal pulls needed. R106 is 1 k.
10. PA9 is a test pad (TP9, `USART1_TX`): usable as a TX-only debug log or ROM USART bootloader.
11. U25 set-point is now 5.32 V nominal (R121 57.6 k): keep `CHG_RAIL_ON` 5.05 V / `CHG_RAIL_OFF` 4.90 V; compute VDDA from VREFINT.
12. LSE: Y4 is CL 7 pF → set `LSEMOD` (high drive) before `LSEON`, LSI fallback. HSE is still 25 MHz (new 3225 crystal); `BOARD_SER_XTAL_HZ` = 3 686 400 (Y2 value text now matches).
13. Battery mode (D9): LTE-only (`AT+CNMP=38`), Ethernet off.

## 12. Incidents and surprises

1. **J-04 wire stubs were not all dangling.** The audit listed three stub UUIDs. Deleting all three broke two connections: at P1.4 the GND label sits at the far end of 46f71e27 (only 2b755f7f is the dangling overhang), and at R52.2 the GND label sits mid-segment on 7c1dbfc0 (only a 0.76 mm tail past the label was dangling). ERC showed 3 new errors and the netlist diff flagged exactly P1.4 and R52.2 as unexpected. Fixed by deleting only 2b755f7f, keeping 46f71e27 and the P1.4 junction, and trimming 7c1dbfc0 to end at its label. Re-verified: expected == actual, ERC 0 errors.
2. **`device_commit_files` re-sent a cached upload** when a staged path was reused: my second commit of Group 1 wrote the first version. Caught by hashing the Mac file after every commit; from then on every commit used a unique staged path. Every committed state in this report was hash-checked on the Mac.
3. **Y3 needed a symbol swap**, not a footprint swap: `Device:Crystal` (2 pins) on the 3225-4P land would have put HSE_OUT on GND pad 2. Swapped to `Device:Crystal_GND24` in place (UUIDs kept, pins 3/4 added), proven by the netlist.
4. **The TPS2552 has no KiCad library symbol** (embedded one authored, §7).
5. **TPS7A2033PDBVR is in JLC's "Pre-ordered Chips" category** (stock 28 370): pre-order like J14.
6. One wire-crossing hit on U30 remains: the MCP tool's bounding box for the vertically asymmetric USBLC6 symbol; the PDF shows the VBUS wire leaving the pin outward.

## 13. New LCSC numbers (JLC DB lookup via KiCad MCP, 2026-09-28)

| LCSC | Part | Package | Stock | Type | Used on |
|---|---|---|---|---|---|
| C206912 | Littelfuse 0154003.DR 3 A | SMD 9.7×5 (Nano2 holder) | 2 217 | Ext | F2 |
| C22840 | 1.43 kΩ 1 % | 0603 | 4 965 | Ext | R50 |
| C1975527 | Littelfuse PESD0402-240 | 0402 | 9 394 | Ext | D28 |
| C46506 | TI TPS2552DBVR | SOT-23-6 | 3 002 | Ext | U28 |
| C224019 | Littelfuse SMBJ33A | DO-214AA | 9 624 | Ext | D35 |
| C57156 | NXP SC16IS752IPW,128 | TSSOP-28 | 2 670 | Ext | U10 |
| C177479 | HKR RCT03499KFLF 499 k | 0603 | 26 862 | Ext | R53 |
| C23082 | 57.6 kΩ 1 % | 0603 | 3 673 | Ext | R121 |
| C5440143 | Samwha 47 µF 16 V X7R | 1210 | 242 640 | Ext | C161, C162 |
| C15578 | TI TLV1117LV33DCYR | SOT-223 | 26 999 | Ext | U17 |
| C881921 | Lelon OVZ221M1CTR-0608 220 µF 16 V polymer | 6.3×7.7 | 2 442 | Ext | C78, C130, C131, C165 |
| C22862 | 113 kΩ 1 % | 0603 | 59 728 | Ext | R116 |
| C1542 | 6.8 nF 50 V X7R | 0402 | 128 063 | Pref | C141 |
| C1572 | 56 pF C0G | 0402 | 83 992 | Ext | C142 |
| C86817 | Murata 22 µF 16 V X5R | 0805 | 4 144 | Ext | C163, C164, C166, C167 |
| C99269 | TI TMP102AIDRLR | SOT-563 | 34 854 | Ext | U29, U31 |
| C25808 | 120 kΩ 1 % | 0603 | 773 686 | Basic | R138 |
| C1589 | 10 nF 50 V X7R | 0603 | 6 584 349 | Ext | C169, C91 |
| C2862740 | TI TPS7A2033PDBVR | SOT-23-5 | 28 370 | Ext (**pre-order category**) | U21 |
| C23162 | 4.7 kΩ 1 % | 0603 | 21 915 184 | Basic | R140 |
| C12518 | Nexperia 74LVC1G125GV,125 | SOT-753 | 5 234 | Ext | U27 |
| C7519 | ST USBLC6-2SC6 | SOT-23-6 | 1 415 | Ext | U30 |
| C25803 | 100 kΩ 1 % | 0603 | 10 814 547 | Basic | new pull resistors, Rdfu1, H-02b set |
| C14663 | 100 nF 50 V X7R | 0603 | 37 493 696 | Basic | C168, C170, C172–C174 |
| C23345 | 22 Ω 1 % | 0603 | 4 031 533 | Basic | R132–R134 |
| C1525 | 100 nF 16 V X7R | 0402 | 43 509 060 | Basic | C171 |
| C14676 | 1 kΩ 5 % | 0603 | 757 955 | Ext | R106 |
| C2901684 | SCTF SX3B25.000F1010F30 25 MHz CL 10 pF | 3225-4P | 11 076 | Ext | Y3 |
| C38523 | 12 pF C0G | 0603 | 3 346 489 | Basic | C113, C114 |
| C48615 | Epson Q13FC13500002 FC-135 CL 7 pF | 3215-2P | 101 342 | Ext | Y4 |
| C1679 | 6.8 pF C0G | 0603 | 1 445 998 | Pref | C115, C116 |
| C4190 | 2.2 kΩ 1 % | 0603 | 2 920 710 | Basic | Rigb1 |
| C1663 | 33 pF C0G | 0603 | 2 808 576 | Basic | C95, C96 |
| C1779 | 4.7 µF 25 V X5R | 0805 | 4 715 349 | Basic | C90 |
| C2827694 | PESD5V0S1BA | SOD-323 | 303 975 | Ext | D36–D38 |
| C25804 | 10 kΩ 1 % | 0603 | (existing Basic) | Basic | R136 |

Final BOM (`kicad/_to_delete/v6-apply-20260928/bom_final*.csv`, kicad-cli): 306 populated BOM lines; only TP1–TP8 have no LCSC (copper pads, as before).

## 14. Files and backups

- Edited in place: `03-Architecture-Hardware/kicad/hbox-watchdog-v6.kicad_sch`, `.kicad_pro`, `.kicad_dru`, `Drogheda-v6.pretty/SO-8_L4.9-W3.9-P1.27-LS6.0-BL-EP.kicad_mod`.
- PDF: `03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf`.
- Backups (nothing deleted): `kicad/_to_delete/v6-apply-20260928/` — `00-pre/` (sch, pro, dru, prl, SO-8 footprint, DRC side-file), `01-blockers/`, `02-majors/`, `03-minors/`, `04-rules/`, `05-final/`, `netlists/00-baseline … 05-final.xml`, `erc_work/` (ERC isolation copies), `drc_work/` (DRC on a board copy with the new rules; report + JSON), `scratch/` (intermediate PDFs, library-extraction file), `bom_final.csv`, `bom_final_ungrouped.csv`.
- Container: `/home/claude/v6audit/apply/` — this report, `netlist_diff_total.md`, `out/0N-*/` (edit logs, expected sets, per-group diffs), `tools/` (editor, model, diff, group scripts), `drc/`, the PDF.
- The `.kicad_pcb` is untouched. If KiCad was open on v6 during this pass, close it **without saving** and reopen before Update PCB (resync protocol §5).

**Git (for Leo to run; nothing was committed from here):** commit inside the `kicad` submodule (sch, pro, dru, SO-8 footprint), push to Gitea `HBox_PCB`, then bump the parent gitlink; `_to_delete/` is gitignored.