EinarBoard v6 Copper Plan

Placement companion for the 140 × 100 re-layout — every capacitor's owner, what clusters together, and the EMC order of work. Cap ownership below is computed from the board netlist, not from memory.

Before placing anything: run Update PCB from Schematic once more. The NTC2 label was sitting on PA7 (TIMEPULSE) and merged the nets — it is fixed in the schematic (commit ba70f62), and the sync re-nets P18/R126/C157 to a clean /NTC2. Tick “delete footprints with no symbol” in that dialog.

Known leftovers from the auto-clustering: ~54 small courtyard overlaps, nearly all against the legacy V5 regulator families that kept their old spots — L2/D2 (under U19's new outline), L6/DB2/DB3/Q2/Dbk1 near U25, C40, R40/R41 at Y3. Drag those few aside first and the board is clean.

§0Three laws that decide EMC at placement time

Loop area is the antenna

Emission scales with the area of each switching current loop. A hot loop closed in 1 cm² is ~20 dB quieter than the same loop at 10 cm². Placement fixes this; routing can't rescue a bad placement.

Smallest cap closest

A capacitor filters up to the frequency its trace inductance allows. Order banks by descending value toward the pin: bulk → 10 µF → 100 nF → pF, with the pF parts within 2–3 mm.

Aggressors far from victims

Four switchers, one LTE transmitter, one −167 dBm GNSS receiver on one board. Distance and an unbroken In1 ground plane are the only broadband shields you get for free.

§1Floorplan as clustered (NW ETH · NE LTE · SW GNSS · SE power)

The clustered state after commit c7d2552 — your anchors kept (J10, P1, U18, U16, U6, U15, K1, connectors), 160 support parts packed by family. Fine-tune freely inside each region; keep the diagonal.

§2Vehicle power entry — U25 TPS54360B hot loop

Chain order along the copper, left to right from P1: F2 → Q23 (with R119, D33 beside its gate) → D32 SMCJ33A → input caps → U25 → D34/L22 → output caps. D10 stays glued to P1 pin 1.

Loudest loop on the board: C149/C150 (+) → U25 VIN ⟶ U25 SW → D34 cathode ⟶ D34 anode → C149/C150 (−). This is a non-synchronous buck, so the input loop carries the full di/dt. Put C149/C150 within 2–3 mm of U25 pins 2/7, D34 directly across from them, and close the loop over solid ground. Under 1 cm² or do it again.

Ref	Value	Belongs to	Placement
C149 C150	2.2 µF/100 V	U25 VIN	2–3 mm from pins 2/7; the hot loop
C151	100 µF/50 V	input bulk	right behind C149/C150
C152	100 nF	U25 BOOT	directly across pins 1–8
C153 C154	47 µF/16 V	5 V output	at L22 output; FB tap (R121) here, not at the inductor
D34	B560C	catch diode	anode ground ties straight into C149/C150 ground
D32	SMCJ33A	surge clamp	between Q23 and the input caps, short fat ties
R120 · R123 C155 C156 · R121 R122 · R124 R125	RT · COMP · FB · UVLO (DNP)	U25 analog side	cluster at pins 3–6, opposite the SW node; keep FB thin and away from L22

24 V rail housekeeping: C10/C22 bulk near Q10, C11 100 nF at the load side. Keep the whole entry block in one corner so the dirty 24 V copper never crosses the board.

§3Battery backup — U6 LTC4040 kelvin

Ref	Value	Belongs to	Placement
C30 C31 C78	10 µF · 2.2 µF · 220 µF	VEH5V input	at U6 input pins, after RS1
C32 C33 C34	47 µF ×2 · 10 µF	MAIN5V output	at U6/Q7 output side
C35	22 µF	BAT_PLUS	near P4; `/SW_BAT` ≥ 2 mm polygon, `/BAT_PLUS` ≥ 1.5 mm — the blackout path, a hard v6 requirement

RS1 (10 mΩ) is a Kelvin part: the LTC4040 sense pins must tap the pad faces themselves, not the power trace. Place RS1 immediately at U6 with L22's output feeding it directly.

§4LTE island — U20 buck + U19 A7670SA hot loop

Second hot loop: C127/C128 → U20 VIN/GND. Synchronous buck, so the input loop is the loud one — C127 10 µF within 2–3 mm of U20 pin 2, C128 1 µF even closer. C129 boot across BOOT–SW, L20 right at SW with a minimal SW pour.

The VBAT bank is a one-direction gradient into pins 55/56/57 — largest farthest, smallest touching the module:

Ref	Value	Order	Placement
C130 C131	220 µF/10 V ×2	far end	the ≥300 µF droop reservoir (2.8 A bursts, ≤300 mV sag)
C132 → C133 → C134	22 µF → 1 µF → 100 nF	middle	stepping toward the module
C135 C136	33 pF · 10 pF	at the pins	within 2–3 mm of pins 55/56/57 — these keep TX harmonics off VBAT
D22	SMAJ5.0A	at the bank	across VBAT near C130/C131

VBAT copper ≥ 3 mm wide the whole way. Around the module: C125 at pin 15 (1V8 out); U22 SIM within 5 mm of pins 30–33 with C126 at its VCC pad and D23–D25 PESD at the SIM pads; U23/U24 level shifters between U19 and the MCU side, each with its supply pair (C137/C139 on 1V8, C138/C140 on 3V3) at the pins; Q20–Q22 near the control pins they drive. J13 U.FL at the board edge; the DNP pi network C146/C147 (+ its series element) sits inline in the 50 Ω run right at the connector, D28 ESD at the connector ground side.

§5GNSS island — U18 ZED-F9P + U21 LDO quiet

Ref	Value	Belongs to	Placement
C119	10 µF	U21 input (SW_5V)	at the LDO input pin
C120 C124	10 µF ×2	3V3_GNSS	one at U21 output, one at U18's main VCC entry
C121 C122 C123	100 nF ×3	U18 VCC pins	one per supply pin, at the pin
C144 C145	100 nF · 100 pF	VCC_RF / bias tee	at L21's feed side — the antenna supply injection
C143	100 nF RF	DC block	inline in the 50 Ω run between L21 tap and J12
D27	ESD9L (≤0.5 pF)	J12	at the connector, stub-less tap on the RF line

This corner is the victim: no switcher, no inductor, no fast digital within ~25 mm (U25 sits ~95 mm away in the SE, the fan buck ~130 mm NE — keep it that way); nothing but solid In1 ground under the module and the RF run. TIMEPULSE to the MCU is the one digital line that leaves — route it away from the RF path.

§6MCU core — U16 analog care

Ref	Value	Belongs to	Placement
C111	4.7 µF	VCAP1	≤ 3 mm from the pin — the core regulator, non-negotiable
C109 C112	100 nF · 1 µF	VDDA	at the VDDA pin, on the quiet side, away from the switchers
C105–C108 + C110	100 nF ×4 + 4.7 µF	VDD pins	one 100 nF per VDD pin, bulk nearby
C104	100 nF	NRST	at the pin, with P10 reset routed clean
Y3 + C113 C114	HSE + 15 pF	crystal	tight triangle at the pins, local ground, ≥10 mm from any inductor
Y4 + C115 C116	LSE 32 kHz + 12 pF	crystal	even tighter — high-impedance oscillator, guard with ground
C5 C7 C9 C24 C157	100 nF ×5	ADC sense filters	with their dividers (R42, R126…) at the MCU pins, not at the jacks — the wire filters at the pin

§7The rest of the families

Ethernet (U11/U12, Y1, C90–C103): one block, U11 close to J10 (magnetics are inside the HR911105A), crystal + 18 pF at the pins, the 3V3_ETH locals (C92–C94, C98, C102, C103) around U11. Keep the RJ45 pair region free of other routes.
RS232 (U15): C85–C88 are charge-pump flying caps — they carry the pump current, so they sit hard against U15; C84 100 nF at its supply pin. P16 at the edge.
UART bridge (U10, Y2, C82/C83): crystal caps at the pins, block near the MCU.
Fan buck (U2, Cbst1, Ccomp1, C23): a third switcher — treat like §4's loop, and park it in the noisy quarter near the power entry, away from GNSS.
Accelerometer (U26, C158/C159 at VDD/VDDIO, C160 bulk): ≤ 10 mm from a mounting hole, on stiff board — it should feel the chassis, not board flex.
Rail sprinkles (Cu3 Cu4 C80 C81 C89 C105+…): every 100 nF on 3V3 pairs with one IC's power pin — when you move an IC, its 100 nF moves with it. C118 22 µF is the 3V3 bulk at the regulator.
NTC channels: pullup + filter (R42+C24, R126+C157) at the MCU; P12/P18 jacks at the harness edge.

§8Separation rules

Keep apart	Min	Why
GNSS island ↔ any switcher L / SW node	25 mm	−167 dBm receiver vs. dV/dt fields
GNSS RF run ↔ LTE RF run	opposite ends	desense is risk #1; antennas ≥ 20 cm at the enclosure
Any crystal ↔ any inductor	10 mm	magnetic pickup into the oscillator
ADC sense traces ↔ SW nodes	5 mm + ground between	tntc/vbat readings ride on µV
USB pairs (J9/J11) ↔ switchers	route as 90 Ω pairs, short	eye + radiated emissions
U26 accel ↔ mounting hole	≤ 10 mm (close!)	chassis coupling, not board flex

§9Order of work from here

Update PCB from Schematic (NTC2 re-net), then fine-tune inside the §1 regions. Field wiring now enters mostly along the north edge + P1 at the SE corner — keep each connector beside its block, and its TVS/filter parts right at the jack, so cable common-mode currents stay off the board core.
Say the word and I re-add the four zones — F.Cu GND pour, In1 GND (unbroken, especially under both RF runs and the crystals), In2 3V3, B.Cu GND — plus a stitching-via plan: 5 mm grid around RF, via fence along the board edge.
Route in this order: ① both 50 Ω RF runs (CPWG on F.Cu over In1, JLC7628 ≈ 0.35/0.25 mm — confirm in the JLC calculator and order controlled impedance) · ② the two hot loops and VBAT ≥ 3 mm · ③ /SW_BAT ≥ 2 mm + /BAT_PLUS ≥ 1.5 mm with via farms · ④ USB and ETH pairs · ⑤ sense lines · ⑥ everything else.
Refill zones, full DRC, then the G2 external review checkpoint before ordering.
Bench items carried forward: measure U21's 3V3_GNSS rise (F9P ramp window), verify U25's EP against the TI DDA drawing, and the DzG1 jumper check on the fabbed v5.5 boards.

EinarBoard HBOX v6 · Helgen · updated 03-Sep-2026 to the clustered layout (commits ba70f62 · c7d2552).