- Outline left edge 80.19->60.19; MH5/MH6 mounting holes cloned to new corners
- Antenna corridor keepout front-left (notched around MH6) + magjack no-pour/no-via zone
- RJ45 J10 + RS-485 P15 + RS-232 P16 on new left edge behind antenna corridor
- W5500 U11 + 25MHz + terminations between jack and P5; 3V3_ETH buck U12/L8/D11
in the freed P13/H3 gap under the module (low-profile), bulk caps at load
- SC16IS752 U10 serial cluster behind P15/P16; MAX3232 U15, SP3485 U14
- PCF8574 U13 clear of MOD1 pad ring; RGB JST P14 on right edge (freed P3 slot)
- H4 TTL header moved to front edge (was under module, on D5)
- 24V entry block relocated beside P1 (Q10/C10 in P12 lane, D10/DzG1/Rrp1 pocket);
old cross-board 24V routing ripped for HV24 re-route
- P3/P13/H3 depopulated; J1/J2/DB pad nets updated (ETH SPI, SER_IRQ, LED flip)
- Fix Phase A miss: SC16IS752 pins 13/14 (I2C SCL/SDA) now wired in sch + board
- Placement verified: 190 footprints, 0 courtyard conflicts, 0 corridor intrusions,
all new nets 2-ended (verify_phase_b.py)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Leopoldo Rodríguez
0af0373def