Drogheda/03-Architecture-Hardware
Leopoldo Rodríguez 449588649a C13: clear the last KiCad 10 DRC error - stranded GND_POUR_FCU island (EinarBoard 2.0)
Leo's post-C12 DRC run left exactly one error:

  [unconnected_items] Zone 'GND_POUR_FCU' [GND] on F.Cu <-> Zone 'GND_POUR_FCU' [GND] on F.Cu

KiCad prints only the zone anchor (60.1917, 40.3231) for both endpoints, so the
report cannot localise the stranded island. Located it analytically instead.

Root cause: U11 pad 9 [GND] @ (91.1275, 55.7600). It is the only GND item on the
board whose item-only connectivity cluster never reaches the In2.Cu GND plane
(two independent fill-independent proofs agree: layer-reach and In2-anchor). An
island survives KiCad's isolated-island removal only if some item props it up,
so pad 9 was propping up a GND_POUR_FCU island that touches nothing else.
island_removal_mode cannot fix that - it needs copper.

Pad 9 is fenced on all four sides (LQFP-48 lead ring, pad 8's westward /3V3_ETH
escape, pad 10's eastward /ETH_RSET escape, the /ETH_RXP chain under the body).
A 0.05mm grid router reached only 227 of 20883 legal cells and found no way to
touch existing GND copper without a via, so a through via is mandatory. A
0.005mm sweep of every legal via site in that pocket picked the best one on the
board's existing drill inventory - no third drill size added.

  + F.Cu GND track w0.3  (91.1275,55.7600) -> (90.1000,55.7600) -> (89.9950,55.8900)
  + F.Cu-B.Cu GND via 0.6/0.3 @ (89.9950,55.8900)
  * U11 pad 9 -> (zone_connect 2)

Both track legs hold +0.2000mm clearance - the structural ceiling for a 0.3mm
track between 0.3mm leads on 0.5mm pitch. The via holds +0.1758mm copper and
+2.9705mm hole. The site sits inside GND_POUR_FCU, GND_POUR_BCU, P3V3_PLANE_IN1
and GND_PLANE_IN2 and outside MAGJACK_NO_POUR, with the nearest In2 signal
copper 1.10mm away, so the barrel lands on solid In2 GND plane.

zone_connect 2 mirrors the landed C12 treatment of pad 29: pads 8 and 10 each
knock 0.5mm of pour out around themselves, covering the whole pad-9 lane
(0.10mm tall < min_thickness 0.25), so the pour cannot reach pad 9 in any
connect mode. Solid mode removes the pad from the minimum-spoke test rather
than leaving a starved thermal behind.

Verified on the output file:
  drc_c12.py   0 hard clearance violations, same 49 sub-epsilon marginals as C12
  proof_c13.py 0 GND clusters without an In2 GND-plane anchor (was 1)
  fcu_only.py  0 F.Cu-only GND clusters (was 1 = pad 9)
  24V / /24V_IN / IGN_IN copper byte-identical (45 segments)
  segments 1984->1986  vias 351->352  zones 5->5  footprints 189->189

Backup: .mcp-backups/hbox-watchdog-v4.kicad_pcb.pre-C13 (md5 042efd5d)
Pushed:  md5 94d36711d60985eef109913fcee36b09, 3502885 bytes

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
2026-08-01 02:08:00 +00:00
..
CAD-Files auto-sync 2026-07-13 18:00 2026-07-13 18:00:15 -06:00
circuitikz-wiring auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
EinarBoard-Manual sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
Guia-Conexion-Protoboard auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
kicad C13: clear the last KiCad 10 DRC error - stranded GND_POUR_FCU island (EinarBoard 2.0) 2026-08-01 02:08:00 +00:00
Manual-Instalacion-Operacion Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
4G-USB-Reset-LED-addition.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
0007-1000_Assembly_Guide.pdf auto-sync 2026-07-11 18:00 2026-07-11 18:00:15 -06:00
2026-07-06_Drogheda_EinarBoard-1.0-PreFab-Audit_v1.0.md sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
2026-07-08_Drogheda_4G-Modem-Alternatives_v1.0.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
2026-07-24_Drogheda_EinarBoard-1.1_Design-Brief_v1.0.md EinarBoard 1.1 design brief: locked decisions (RS-485+RS-232 via SC16IS752, on-board W5500 Ethernet, RGB status LED, board growth) + execution phases 2026-07-29 01:58:39 +00:00
Assembly-BOM-Split.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
BOM-master.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
bom.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
cabinet-electrical-bom.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.png 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.svg 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_EinarBoard-1.0_Tabla-Conexiones-Externas_v1.0.pdf auto-sync 2026-07-23 18:00 2026-07-23 18:00:14 -06:00
Drogheda_Guia-Cableado-Proto-Watchdog-v3_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v2.2.pdf auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.0.pdf auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.1.pdf auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
Drogheda-BOM-Maestro.xlsx Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda-Manual-Instalacion-Operacion.pdf Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-v3-pinned-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
firmware-review-v2.3-EinarBoard.md Firmware review: v2.3 as EinarBoard 1.0 production candidate (2026-07-24) 2026-07-24 01:27:20 +00:00
firmware-review.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
hardware-respec-and-pcb-brief.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
harness-connector-pinout.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
JLCPCB-Order-Guide.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
LCSC-search-list.md auto-sync 2026-07-07 18:00 2026-07-07 18:00:12 -06:00
Socket-Pinout-Silkscreen.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
watchdog-connections-rationale.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-connections.xlsx 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-electrical-design-state.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
watchdog-health-telemetry.md add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-LISTA-DE-COMPRAS-ES.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-pcb-v3-blockdiagram.svg auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-bom.xlsx add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-pcb-v3-design.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-pcb-v3-kicad-guide.md auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-routing-status.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
watchdog-production-schematic-delta.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-proto-bench-bringup-v3.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-protoboard-BOM-3boards.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-protoboard-bringup.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-schematic.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00