d4795539e7
T0 hbox-watchdog-v6.{sch,pcb,pro,dru} forked from v5.5 @ e6ac8cc (new files on main,
same precedent as v4 -> v5). All internal project refs renamed, paren-balanced.
T1 Deleted the simpleRTK2B Pro socket (MOD1), both XBee sockets (J7/J8) and the modem
reset button (SW4G1) from schematic and PCB, plus the 25 on-pin labels that carried
their connectivity. The schematic has ZERO wires - connectivity is labels on pins -
so no wire/junction surgery was needed.
T2 Relay K1 pin 10 (NO contact) moves from PA9 /USART1_TX to PC6 /USART6_TX, giving the
MCU ownership of the modem RX line while K1 de-energised still feeds the receiver's
GGA straight to the modem (MCU-dead fail-safe). PA9 freed -> no_connect. USART6_RX
added on PC7. Retired /USART1_TX copper ripped (7 items).
Verified: /USART6_TX = U16.37 + K1.10 | /USART1_RX = U16.43 + Rdfu1.1 + K1.1 | PA9 free.
Nets awaiting T3/T4 silicon: /DOUT_4G, /MODEM_RST, /GNSS_TX, /GNSS_RX, /USART6_RX.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
135 lines
5.6 KiB
Python
135 lines
5.6 KiB
Python
#!/usr/bin/env python3
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"""v6 T2 - move K1 pin 10 (relay NO) from PA9 /USART1_TX to PC6 /USART6_TX.
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This is the one-net change that lets the MCU own the modem's RX line (AT commands,
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byte-exact GGA forwarding, $PHLG injection) while keeping the MCU-dead fail-safe:
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de-energised, K1's NC contact still feeds the receiver's GGA straight to the modem.
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Schematic (label-only connectivity):
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- rename USART1_TX @ (513.588, 182.372) -> USART6_TX [K1 pin 10]
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- delete USART1_TX @ (518.16, 416.56) + add a no_connect [U16 PA9, now free]
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- add USART6_TX @ (482.6, 431.8) [U16 PC6]
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- add USART6_RX @ (482.6, 434.34) [U16 PC7]
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PCB:
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- K1 pad 10 /USART1_TX -> /USART6_TX
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- U16 pad 37 -> /USART6_TX ; pad 38 -> /USART6_RX ; pad 42 -> unconnected
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- rip all copper on the retired /USART1_TX net (it joined PA9 to K1.10)
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Usage: python3 2026-08-24_v6_T2_k1_to_pc6.py [--apply]
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"""
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import re, sys, os, shutil, uuid
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KI = os.path.join(os.path.dirname(os.path.abspath(__file__)), '..', '03-Architecture-Hardware', 'kicad')
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SCH = os.path.join(KI, 'hbox-watchdog-v6.kicad_sch')
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PCB = os.path.join(KI, 'hbox-watchdog-v6.kicad_pcb')
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APPLY = '--apply' in sys.argv
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def span_from(text, i):
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d = 0; instr = False; esc = False; j = i
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while j < len(text):
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ch = text[j]
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if esc: esc = False
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elif ch == '\\': esc = True
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elif ch == '"': instr = not instr
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elif not instr:
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if ch == '(': d += 1
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elif ch == ')':
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d -= 1
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if d == 0: return j + 1
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j += 1
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raise ValueError('unbalanced')
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def find_label(text, name, x, y):
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for m in re.finditer(r'\(label "' + re.escape(name) + r'"\s*\n\s*\(at ([-\d.]+) ([-\d.]+) (\d+)\)', text):
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if abs(float(m.group(1)) - x) < 0.01 and abs(float(m.group(2)) - y) < 0.01:
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return m.start(), span_from(text, m.start()), int(m.group(3))
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return None
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def mklabel(name, x, y, rot, justify):
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return ('\n\t(label "%s"\n\t\t(at %s %s %d)\n\t\t(effects\n\t\t\t(font\n\t\t\t\t(size 1.27 1.27)\n'
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'\t\t\t)\n\t\t\t(justify %s)\n\t\t)\n\t\t(uuid "%s")\n\t)') % (name, x, y, rot, justify, uuid.uuid4())
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def mknc(x, y):
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return '\n\t(no_connect\n\t\t(at %s %s)\n\t\t(uuid "%s")\n\t)' % (x, y, uuid.uuid4())
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sch = open(SCH, encoding='utf-8').read()
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log = []
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# 1. K1 pin 10 label -> USART6_TX
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hit = find_label(sch, 'USART1_TX', 513.588, 182.372)
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if not hit: sys.exit('K1.10 USART1_TX label not found')
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a, b, rot = hit
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sch = sch[:a] + sch[a:b].replace('"USART1_TX"', '"USART6_TX"', 1) + sch[b:]
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log.append(' rename USART1_TX -> USART6_TX @ (513.588, 182.372) [K1 pin 10 / relay NO]')
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# 2. U16 PA9 label -> gone, no_connect in its place
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hit = find_label(sch, 'USART1_TX', 518.16, 416.56)
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if not hit: sys.exit('U16 PA9 USART1_TX label not found')
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a, b, rot = hit
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sch = sch[:a] + mknc('518.16', '416.56') + sch[b:]
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log.append(' delete USART1_TX @ (518.16, 416.56) -> no_connect [U16 PA9, freed -> test point later]')
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# 3+4. new labels on PC6 / PC7 (left column of U16: rot 180, justify right bottom)
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anchor = sch.find('\n\t(label "ETH_INT"')
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ins = span_from(sch, anchor + 1)
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add = mklabel('USART6_TX', '482.6', '431.8', 180, 'right bottom') + \
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mklabel('USART6_RX', '482.6', '434.34', 180, 'right bottom')
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sch = sch[:ins] + add + sch[ins:]
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log.append(' add USART6_TX @ (482.6, 431.8) [U16 PC6 / USART6_TX]')
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log.append(' add USART6_RX @ (482.6, 434.34) [U16 PC7 / USART6_RX]')
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# ---------------- PCB ----------------
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pcb = open(PCB, encoding='utf-8').read()
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plog = []
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def set_pad_net(text, ref, pad, newnet):
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m = re.search(r'\n\t\(footprint (?:(?!\n\t\(footprint ).)*?\(property "Reference" "' + re.escape(ref) + r'"(?:(?!\n\t\(footprint ).)*', text, re.S)
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if not m: raise ValueError('footprint %s not found' % ref)
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seg = m.group(0)
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pm = re.search(r'\(pad "' + re.escape(pad) + r'"(?:(?!\(pad ").)*?\(net "([^"]*)"\)', seg, re.S)
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if not pm: raise ValueError('pad %s.%s not found' % (ref, pad))
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old = pm.group(1)
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newseg = seg[:pm.start(1)] + newnet + seg[pm.end(1):]
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plog.append(' %-5s pad %-3s %-34s -> %s' % (ref, pad, old, newnet))
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return text[:m.start()] + newseg + text[m.end():]
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pcb = set_pad_net(pcb, 'K1', '10', '/USART6_TX')
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pcb = set_pad_net(pcb, 'U16', '37', '/USART6_TX')
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pcb = set_pad_net(pcb, 'U16', '38', '/USART6_RX')
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pcb = set_pad_net(pcb, 'U16', '42', 'unconnected-(U16-PA9-Pad42)')
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# rip retired /USART1_TX copper
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cuts = []
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for kw in ('\n\t(segment', '\n\t(via'):
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for m in re.finditer(re.escape(kw), pcb):
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e = span_from(pcb, m.start() + 1)
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if '(net "/USART1_TX")' in pcb[m.start():e]:
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cuts.append((m.start(), e))
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for a, b in sorted(cuts, reverse=True):
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pcb = pcb[:a] + pcb[b:]
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plog.append(' ripped %d copper items on the retired /USART1_TX net' % len(cuts))
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print('--- SCHEMATIC ---'); print('\n'.join(log))
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print('--- PCB ---'); print('\n'.join(plog))
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def bal(t):
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d = 0; instr = False; esc = False
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for ch in t:
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if esc: esc = False; continue
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if ch == '\\': esc = True; continue
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if ch == '"': instr = not instr; continue
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if instr: continue
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if ch == '(': d += 1
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elif ch == ')': d -= 1
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return d
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print('\nparen balance sch=%s pcb=%s' % (bal(sch), bal(pcb)))
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if not APPLY:
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print('\nDRY RUN - nothing written. Re-run with --apply.')
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sys.exit(0)
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if bal(sch) or bal(pcb): sys.exit('REFUSING: paren imbalance')
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shutil.copy2(SCH, SCH + '.T2bak'); shutil.copy2(PCB, PCB + '.T2bak')
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open(SCH, 'w', encoding='utf-8').write(sch)
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open(PCB, 'w', encoding='utf-8').write(pcb)
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print('\nAPPLIED. Backups: *.T2bak')
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