Drogheda/03-Architecture-Hardware/2026-09-02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html

<title>EinarBoard v6 Copper Plan</title>
<link rel="stylesheet" href="https://fonts.googleapis.com/css2?family=Archivo:wght@500;600;700&family=IBM+Plex+Sans:ital,wght@0,400;0,500;0,600;1,400&family=IBM+Plex+Mono:wght@400;500&display=swap">
<style>
:root{
  --paper:#faf8f4; --ink:#1d1c19; --ink2:#5a564d; --line:#e2ddd2;
  --copper:#a4611f; --copper-soft:#f3e7d6; --plane:#33586e; --plane-soft:#e3ebf0;
  --crit:#a63b2a; --crit-soft:#f6e5e1; --ok:#43704c;
  --card:#ffffff; --mono-bg:#f0ece3;
}
:root:not([data-theme="light"]){ }
@media (prefers-color-scheme: dark){
  :root:not([data-theme="light"]){
    --paper:#191b1e; --ink:#e3ded4; --ink2:#a09a8d; --line:#33363b;
    --copper:#d99b52; --copper-soft:#2e2519; --plane:#8fb4c9; --plane-soft:#1f2a31;
    --crit:#e08373; --crit-soft:#33211d; --ok:#8fbf98;
    --card:#1f2226; --mono-bg:#25282d;
  }
}
:root[data-theme="dark"]{
  --paper:#191b1e; --ink:#e3ded4; --ink2:#a09a8d; --line:#33363b;
  --copper:#d99b52; --copper-soft:#2e2519; --plane:#8fb4c9; --plane-soft:#1f2a31;
  --crit:#e08373; --crit-soft:#33211d; --ok:#8fbf98;
  --card:#1f2226; --mono-bg:#25282d;
}
body{background:var(--paper);color:var(--ink);font:400 15.5px/1.55 "IBM Plex Sans",system-ui,sans-serif;margin:0}
.wrap{max-width:900px;margin:0 auto;padding:40px 22px 80px}
h1,h2,h3{font-family:"Archivo",system-ui,sans-serif;text-wrap:balance;margin:0}
h1{font-size:30px;font-weight:700;letter-spacing:-.01em}
.sub{color:var(--ink2);margin:6px 0 0;max-width:64ch}
h2{font-size:19px;font-weight:600;margin:44px 0 6px;padding-top:14px;border-top:2px solid var(--copper)}
h2 .no{color:var(--copper);font-family:"IBM Plex Mono",monospace;font-size:14px;font-weight:500;margin-right:8px}
h3{font-size:15.5px;font-weight:600;margin:20px 0 4px}
p{margin:8px 0;max-width:72ch}
code,.rf{font-family:"IBM Plex Mono",monospace;font-size:.92em;background:var(--mono-bg);padding:1px 5px;border-radius:3px;white-space:nowrap}
.lead{font-size:16.5px}
table{border-collapse:collapse;width:100%;margin:10px 0;font-size:14px}
th{font-family:"Archivo",sans-serif;font-size:11.5px;text-transform:uppercase;letter-spacing:.07em;color:var(--ink2);text-align:left;padding:6px 10px 6px 0;border-bottom:1px solid var(--ink2)}
td{padding:6px 10px 6px 0;border-bottom:1px solid var(--line);vertical-align:top}
td:first-child{font-family:"IBM Plex Mono",monospace;font-size:13px;white-space:nowrap}
.tblwrap{overflow-x:auto}
.loop{background:var(--copper-soft);border-left:3px solid var(--copper);padding:10px 14px;margin:12px 0;border-radius:0 6px 6px 0}
.loop b:first-child{color:var(--copper)}
.warn{background:var(--crit-soft);border-left:3px solid var(--crit);padding:10px 14px;margin:12px 0;border-radius:0 6px 6px 0}
.warn b:first-child{color:var(--crit)}
.note{background:var(--plane-soft);border-left:3px solid var(--plane);padding:10px 14px;margin:12px 0;border-radius:0 6px 6px 0}
.laws{display:grid;grid-template-columns:repeat(auto-fit,minmax(240px,1fr));gap:12px;margin:18px 0}
.law{background:var(--card);border:1px solid var(--line);border-radius:8px;padding:14px 16px}
.law b{display:block;font-family:"Archivo",sans-serif;font-size:14px;margin-bottom:4px;color:var(--copper)}
.law p{font-size:13.5px;margin:0;color:var(--ink2)}
figure{margin:16px 0}
figcaption{font-size:12.5px;color:var(--ink2);margin-top:6px}
svg text{font-family:"IBM Plex Mono",monospace}
ol.steps{counter-reset:s;list-style:none;padding:0;margin:14px 0}
ol.steps li{counter-increment:s;padding:10px 0 10px 44px;position:relative;border-bottom:1px solid var(--line);max-width:76ch}
ol.steps li::before{content:counter(s,decimal-leading-zero);position:absolute;left:0;top:10px;font-family:"IBM Plex Mono",monospace;color:var(--copper);font-weight:500}
ul{padding-left:20px}
li{margin:4px 0}
.tag{font-family:"Archivo",sans-serif;font-size:10.5px;text-transform:uppercase;letter-spacing:.08em;padding:2px 7px;border-radius:99px;border:1px solid var(--copper);color:var(--copper);white-space:nowrap}
.tag.q{border-color:var(--plane);color:var(--plane)}
.d{font-family:"Archivo",sans-serif;font-size:10px;font-weight:600;letter-spacing:.05em;padding:1px 6px;border-radius:99px;white-space:nowrap}
.d1{background:var(--crit-soft);color:var(--crit)}
.d2{background:var(--copper-soft);color:var(--copper)}
.d3{background:var(--plane-soft);color:var(--plane)}
tr.own td{font-family:"Archivo",sans-serif;font-size:12.5px;font-weight:600;text-transform:uppercase;letter-spacing:.06em;color:var(--copper);border-bottom:2px solid var(--copper);padding-top:18px;white-space:normal}
a{color:var(--plane)}
</style>
<div class="wrap">
<h1>EinarBoard v6 Copper Plan</h1>
<p class="sub">Placement companion for the 140 × 100 re-layout — every capacitor's owner, what clusters together, and the EMC order of work. Cap ownership below is computed from the board netlist, not from memory.</p>

<div class="note"><b>Connector renumber (03-Sep, commit <code>b007c7c</code>):</b> P-refs now follow function order — <code>P1</code> 24V · <code>P2</code> 5V bench · <code>P3</code> battery (was P4) · <code>P4</code> fan (was P6) · <code>P5</code> cutoff (was P11) · <code>P6</code> reset (was P10) · <code>P7</code> NTC probe 1 (was P12) · <code>P8</code> NTC probe 2 (was P18) · <code>P9</code> panel LED (was P8) · <code>P10</code> RGB (was P14) · <code>P11</code> RS485 (was P15) · <code>P12</code> RS232 (was P16). ⚠ v5 field docs say "P12 = NTC" — in v6 that name is the RS232 port; update harness docs. The NTC2 net fix is applied and synced.</div>
<div class="note"><b>Known leftovers from the auto-clustering:</b> ~54 small courtyard overlaps, nearly all against the legacy V5 regulator families that kept their old spots — <code>L2</code>/<code>D2</code> (under U19's new outline), <code>L6</code>/<code>DB2</code>/<code>DB3</code>/<code>Q2</code>/<code>Dbk1</code> near U25, <code>C40</code>, <code>R40</code>/<code>R41</code> at Y3. Drag those few aside first and the board is clean.</div>

<h2><span class="no">§0</span>Three laws that decide EMC at placement time</h2>
<div class="laws">
  <div class="law"><b>Loop area is the antenna</b><p>Emission scales with the area of each switching current loop. A hot loop closed in 1 cm² is ~20 dB quieter than the same loop at 10 cm². Placement fixes this; routing can't rescue a bad placement.</p></div>
  <div class="law"><b>Smallest cap closest</b><p>A capacitor filters up to the frequency its trace inductance allows. Order banks by descending value <i>toward</i> the pin: bulk → 10 µF → 100 nF → pF, with the pF parts within 2–3 mm.</p></div>
  <div class="law"><b>Aggressors far from victims</b><p>Four switchers, one LTE transmitter, one −167 dBm GNSS receiver on one board. Distance and an unbroken In1 ground plane are the only broadband shields you get for free.</p></div>
</div>

<h2><span class="no">§1</span>Floorplan as clustered (NW ETH · NE LTE · SW GNSS · SE power)</h2>
<figure>
<svg viewBox="0 0 700 500" style="max-width:100%;height:auto" role="img" aria-label="Current floorplan of the 140 by 100 mm board">
  <rect x="30" y="40" width="630" height="450" fill="none" stroke="var(--ink)" stroke-width="2"/>
  <text x="30" y="28" font-size="12" fill="var(--ink2)">140 × 100 mm · as clustered on 03-Sep (commit c7d2552) · N = top of the KiCad screen</text>
  <!-- NW ETH -->
  <rect x="32" y="42" width="200" height="130" fill="var(--plane-soft)"/>
  <text x="42" y="64" font-size="13" fill="var(--plane)">NW — ETHERNET</text>
  <text x="42" y="81" font-size="11" fill="var(--ink2)">J10 RJ45 · U11/U12 · Y1</text>
  <text x="42" y="96" font-size="11" fill="var(--ink2)">C90–C103 · J11 USB-DFU</text>
  <!-- NE LTE -->
  <rect x="440" y="42" width="218" height="200" fill="var(--copper-soft)"/>
  <text x="452" y="64" font-size="13" fill="var(--copper)">NE — LTE ISLAND</text>
  <text x="452" y="81" font-size="11" fill="var(--ink2)">U20 buck+L20 · VBAT bank</text>
  <text x="452" y="96" font-size="11" fill="var(--ink2)">U19 A7670SA · K1 · shifters</text>
  <text x="452" y="111" font-size="11" fill="var(--ink2)">J13 U.FL → NE corner</text>
  <!-- MCU -->
  <rect x="250" y="90" width="170" height="150" fill="none" stroke="var(--line)" stroke-dasharray="5 4"/>
  <text x="335" y="115" font-size="13" text-anchor="middle" fill="var(--ink)">MCU U16</text>
  <text x="335" y="132" font-size="11" text-anchor="middle" fill="var(--ink2)">crystals · VCAP · VDDA</text>
  <text x="335" y="147" font-size="11" text-anchor="middle" fill="var(--ink2)">sense RCs · U10/Y2 below</text>
  <!-- SW GNSS -->
  <rect x="32" y="255" width="200" height="233" fill="var(--plane-soft)"/>
  <text x="42" y="277" font-size="13" fill="var(--plane)">SW — GNSS ISLAND</text>
  <text x="42" y="294" font-size="11" fill="var(--ink2)">U21 LDO · C119–C124</text>
  <text x="42" y="309" font-size="11" fill="var(--ink2)">U18 F9P · L21 bias tee</text>
  <text x="42" y="324" font-size="11" fill="var(--ink2)">C143/144/145 · D27 · J12 → W edge</text>
  <text x="42" y="345" font-size="11" fill="var(--ink2)">U26 accel at MH6 (SW hole)</text>
  <text x="42" y="366" font-size="11" fill="var(--crit)">quiet corner — no switchers</text>
  <!-- SE power -->
  <rect x="440" y="290" width="218" height="198" fill="var(--copper-soft)"/>
  <text x="452" y="312" font-size="13" fill="var(--copper)">SE — POWER ENTRY</text>
  <text x="452" y="329" font-size="11" fill="var(--ink2)">P1 24V · F2 Q23 D32 · 24V parts</text>
  <text x="452" y="344" font-size="11" fill="var(--ink2)">U25 + L22 + C149–C154</text>
  <text x="452" y="359" font-size="11" fill="var(--ink2)">U6 LTC4040 + RS1 · fan U2 above</text>
  <text x="452" y="374" font-size="11" fill="var(--ink2)">J9 USB · RS232 U15 just west</text>
  <!-- diagonal separation -->
  <line x1="235" y1="370" x2="500" y2="130" stroke="var(--crit)" stroke-dasharray="6 5"/>
  <text x="368" y="262" font-size="11" text-anchor="middle" fill="var(--crit)" transform="rotate(-42 368 262)">GNSS ↔ LTE on the diagonal · antennas ≥ 20 cm at the enclosure</text>
</svg>
<figcaption>The clustered state after commit <code>c7d2552</code> — your anchors kept (J10, P1, U18, U16, U6, U15, K1, connectors), 160 support parts packed by family. Fine-tune freely inside each region; keep the diagonal.</figcaption>
</figure>

<h2><span class="no">§2</span>Vehicle power entry — U25 TPS54360B <span class="tag">hot loop</span></h2>
<p>Chain order along the copper, left to right from P1: <code>F2</code> → <code>Q23</code> (with <code>R119</code>, <code>D33</code> beside its gate) → <code>D32</code> SMCJ33A → input caps → <code>U25</code> → <code>D34</code>/<code>L22</code> → output caps. <code>D10</code> stays glued to P1 pin 1.</p>
<div class="loop"><b>Loudest loop on the board:</b> C149/C150 (+) → U25 VIN ⟶ U25 SW → D34 cathode ⟶ D34 anode → C149/C150 (−). This is a non-synchronous buck, so the input loop carries the full di/dt. Put <code>C149</code>/<code>C150</code> within 2–3 mm of U25 pins 2/7, D34 directly across from them, and close the loop over solid ground. Under 1 cm² or do it again.</div>
<div class="tblwrap"><table>
<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
<tr><td>C149 C150</td><td>2.2 µF/100 V</td><td>U25 VIN</td><td>2–3 mm from pins 2/7; the hot loop</td></tr>
<tr><td>C151</td><td>100 µF/50 V</td><td>U25 input bulk</td><td>right behind C149/C150</td></tr>
<tr><td>C152</td><td>100 nF</td><td>U25 BOOT</td><td>directly across pins 1–8</td></tr>
<tr><td>C153 C154</td><td>47 µF/16 V</td><td>U25 5 V output</td><td>at L22 output; FB tap (R121) here, not at the inductor</td></tr>
<tr><td>D34</td><td>B560C</td><td>U25 catch diode</td><td>anode ground ties straight into C149/C150 ground</td></tr>
<tr><td>D32</td><td>SMCJ33A</td><td>U25 input surge clamp</td><td>between Q23 and the input caps, short fat ties</td></tr>
<tr><td>R120 · R123 C155 C156 · R121 R122 · R124 R125</td><td>RT · COMP · FB · UVLO (DNP)</td><td>U25 analog side</td><td>cluster at pins 3–6, opposite the SW node; keep FB thin and away from L22</td></tr>
</table></div>
<p>24 V rail housekeeping: <code>C10</code>/<code>C22</code> bulk near Q10, <code>C11</code> 100 nF at the load side. Keep the whole entry block in one corner so the dirty 24 V copper never crosses the board.</p>

<h2><span class="no">§3</span>Battery backup — U6 LTC4040 <span class="tag q">kelvin</span></h2>
<div class="tblwrap"><table>
<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
<tr><td>C30 C31 C78</td><td>10 µF · 2.2 µF · 220 µF</td><td>U6 VEH5V input</td><td>at U6 input pins, after RS1</td></tr>
<tr><td>C32 C33 C34</td><td>47 µF ×2 · 10 µF</td><td>U6 MAIN5V output</td><td>at U6/Q7 output side</td></tr>
<tr><td>C35</td><td>22 µF</td><td>U6 BAT pin → P3</td><td>near P3; <code>/SW_BAT</code> ≥ 2 mm polygon, <code>/BAT_PLUS</code> ≥ 1.5 mm — the blackout path, a hard v6 requirement</td></tr>
</table></div>
<div class="note"><b>RS1 (10 mΩ) is a Kelvin part:</b> the LTC4040 sense pins must tap the pad faces themselves, not the power trace. Place RS1 immediately at U6 with L22's output feeding it directly.</div>

<h2><span class="no">§4</span>LTE island — U20 buck + U19 A7670SA <span class="tag">hot loop</span></h2>
<div class="loop"><b>Second hot loop:</b> C127/C128 → U20 VIN/GND. Synchronous buck, so the input loop is the loud one — C127 10 µF within 2–3 mm of U20 pin 2, C128 1 µF even closer. C129 boot across BOOT–SW, L20 right at SW with a minimal SW pour.</div>
<p>The VBAT bank is a one-direction gradient into pins 55/56/57 — largest farthest, smallest touching the module:</p>
<div class="tblwrap"><table>
<tr><th>Ref</th><th>Value</th><th>Order</th><th>Placement</th></tr>
<tr><td>C130 C131</td><td>220 µF/10 V ×2</td><td>U19 VBAT · far end</td><td>the ≥300 µF droop reservoir (2.8 A bursts, ≤300 mV sag)</td></tr>
<tr><td>C132 → C133 → C134</td><td>22 µF → 1 µF → 100 nF</td><td>U19 VBAT · middle</td><td>stepping toward the module</td></tr>
<tr><td>C135 C136</td><td>33 pF · 10 pF</td><td>U19 pins 55/56/57</td><td>within 2–3 mm — these keep TX harmonics off VBAT</td></tr>
<tr><td>D22</td><td>SMAJ5.0A</td><td>U19 VBAT bank</td><td>across VBAT near C130/C131</td></tr>
</table></div>
<p>VBAT copper ≥ 3 mm wide the whole way. Around the module: <code>C125</code> at pin 15 (1V8 out); <code>U22</code> SIM within 5 mm of pins 30–33 with <code>C126</code> at its VCC pad and <code>D23–D25</code> PESD at the SIM pads; <code>U23</code>/<code>U24</code> level shifters between U19 and the MCU side, each with its supply pair (<code>C137</code>/<code>C139</code> on 1V8, <code>C138</code>/<code>C140</code> on 3V3) at the pins; <code>Q20–Q22</code> near the control pins they drive. <code>J13</code> U.FL at the board edge; the DNP pi network <code>C146</code>/<code>C147</code> (+ its series element) sits inline in the 50 Ω run right at the connector, <code>D28</code> ESD at the connector ground side.</p>

<h2><span class="no">§5</span>GNSS island — U18 ZED-F9P + U21 LDO <span class="tag q">quiet</span></h2>
<div class="tblwrap"><table>
<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
<tr><td>C119</td><td>10 µF</td><td>U21 input (SW_5V)</td><td>at the LDO input pin</td></tr>
<tr><td>C120 C124</td><td>10 µF ×2</td><td>U21 out → U18 VCC</td><td>one at U21 output, one at U18's main VCC entry</td></tr>
<tr><td>C121 C122 C123</td><td>100 nF ×3</td><td>U18 VCC pins</td><td>one per supply pin, at the pin</td></tr>
<tr><td>C144 C145</td><td>100 nF · 100 pF</td><td>U18 VCC_RF · L21 bias tee</td><td>at L21's feed side — the antenna supply injection</td></tr>
<tr><td>C143</td><td>100 nF RF</td><td>J12 RF line (DC block)</td><td>inline in the 50 Ω run between L21 tap and J12</td></tr>
<tr><td>D27</td><td>ESD9L (≤0.5 pF)</td><td>J12</td><td>at the connector, stub-less tap on the RF line</td></tr>
</table></div>
<p>This corner is the victim: no switcher, no inductor, no fast digital within ~25 mm (U25 sits ~95 mm away in the SE, the fan buck ~130 mm NE — keep it that way); nothing but solid In1 ground under the module and the RF run. <code>TIMEPULSE</code> to the MCU is the one digital line that leaves — route it away from the RF path.</p>

<h2><span class="no">§6</span>MCU core — U16 <span class="tag q">analog care</span></h2>
<div class="tblwrap"><table>
<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
<tr><td>C111</td><td>4.7 µF</td><td>U16 VCAP1</td><td>≤ 3 mm from the pin — the core regulator, non-negotiable</td></tr>
<tr><td>C109 C112</td><td>100 nF · 1 µF</td><td>U16 VDDA</td><td>at the VDDA pin, on the quiet side, away from the switchers</td></tr>
<tr><td>C105–C108 + C110</td><td>100 nF ×4 + 4.7 µF</td><td>U16 VDD pins</td><td>one 100 nF per VDD pin, bulk nearby</td></tr>
<tr><td>C104</td><td>100 nF</td><td>U16 NRST</td><td>at the pin, with the P6 reset jack routed clean</td></tr>
<tr><td>Y3 + C113 C114</td><td>HSE + 15 pF</td><td>U16 OSC pins</td><td>tight triangle at the pins, local ground, ≥10 mm from any inductor</td></tr>
<tr><td>Y4 + C115 C116</td><td>LSE 32 kHz + 12 pF</td><td>U16 OSC32 pins</td><td>even tighter — high-impedance oscillator, guard with ground</td></tr>
<tr><td>C5 C7 C9 C24 C157</td><td>100 nF ×5</td><td>U16 ADC pins</td><td>with their dividers (R42, R126…) at the MCU pins, not at the jacks — the wire filters at the pin</td></tr>
</table></div>

<h2><span class="no">§7</span>The rest of the families</h2>
<ul>
<li><b>Ethernet</b> (<code>U11</code>/<code>U12</code>, <code>Y1</code>, <code>C90–C103</code>): one block, U11 close to J10 (magnetics are inside the HR911105A), crystal + 18 pF at the pins, the 3V3_ETH locals (<code>C92–C94</code>, <code>C98</code>, <code>C102</code>, <code>C103</code>) around U11. Keep the RJ45 pair region free of other routes.</li>
<li><b>RS232</b> (<code>U15</code>): <code>C85–C88</code> are charge-pump flying caps — they carry the pump current, so they sit hard against U15; <code>C84</code> 100 nF at its supply pin. P12 (RS232 jack) at the edge.</li>
<li><b>UART bridge</b> (<code>U10</code>, <code>Y2</code>, <code>C82</code>/<code>C83</code>): crystal caps at the pins, block near the MCU.</li>
<li><b>Fan buck</b> (<code>U2</code>, <code>Cbst1</code>, <code>Ccomp1</code>, <code>C23</code>): a third switcher — treat like §4's loop, and park it in the noisy quarter near the power entry, away from GNSS.</li>
<li><b>Accelerometer</b> (<code>U26</code>, <code>C158</code>/<code>C159</code> at VDD/VDDIO, <code>C160</code> bulk): ≤ 10 mm from a mounting hole, on stiff board — it should feel the chassis, not board flex.</li>
<li><b>Rail sprinkles</b> (<code>Cu3</code> <code>Cu4</code> <code>C80</code> <code>C81</code> <code>C89</code> <code>C105+</code>…): every 100 nF on 3V3 pairs with one IC's power pin — when you move an IC, its 100 nF moves with it. <code>C118</code> 22 µF is the 3V3 bulk at the regulator.</li>
<li><b>NTC channels</b>: pullup + filter (<code>R42</code>+<code>C24</code> → P7, <code>R126</code>+<code>C157</code> → P8) at the MCU; <code>P7</code>/<code>P8</code> jacks at the harness edge.</li>
</ul>

<h2><span class="no">§8</span>Master proximity table — every discrete, its owner designator, and how close</h2>
<p>Computed from the current board netlist (post-rename, all 300 footprints), then hand-corrected where the netlist heuristic picked a connected-but-wrong owner (ESD parts belong at connectors, ADC filters at the MCU, comp caps at their regulator). Distance classes:</p>
<p><span class="d d1">🔴 GLUED ≤3 mm</span> loop-critical — same pad ground, no via between &nbsp; <span class="d d2">🟠 CLOSE ≤5 mm</span> at the pin, short direct trace &nbsp; <span class="d d3">🔵 BLOCK ≤15 mm</span> same cluster, routing order free</p>
<div class="tblwrap"><table>
<tr><th>Ref</th><th>Value</th><th>Glue to</th><th></th><th>Why</th></tr>

<tr class="own"><td colspan="5">P1 — 24 V entry (SE corner)</td></tr>
<tr><td>D10</td><td>SMBJ33A</td><td>P1 pin 1 (24V_IN)</td><td><span class="d d1">🔴</span></td><td>surge clamp at the jack, before anything else</td></tr>
<tr><td>Rig1</td><td>22k</td><td>P1 ignition pin</td><td><span class="d d1">🔴</span></td><td>series element right at the jack</td></tr>
<tr><td>F2</td><td>2 A slow 1812</td><td>P1 → Q23</td><td><span class="d d3">🔵</span></td><td>first element in the chain</td></tr>
<tr><td>Q23</td><td>IRFR5305</td><td>F2 output</td><td><span class="d d3">🔵</span></td><td>reverse-polarity FET, chain order</td></tr>
<tr><td>R119 D33</td><td>100k · BZX84C15</td><td>Q23 G–S pads</td><td><span class="d d1">🔴</span></td><td>gate bias + 15 V clamp across the FET itself</td></tr>
<tr><td>D32</td><td>SMCJ33A</td><td>between Q23 and C149/C150</td><td><span class="d d2">🟠</span></td><td>clamps the line before the buck sees it</td></tr>
<tr><td>Q10</td><td>IRFR5305</td><td>P1 24 V branch</td><td><span class="d d3">🔵</span></td><td>legacy 24 V rail FET (feeds U2 + K1)</td></tr>
<tr><td>Rrp1 DzG1</td><td>10k · BZX84C15</td><td>Q10 G–S pads</td><td><span class="d d1">🔴</span></td><td>gate network — the part behind the v5.5 jumper check</td></tr>
<tr><td>C10 C22</td><td>47 µF/50 V · 22 µF/50 V</td><td>Q10 load side (/24V)</td><td><span class="d d3">🔵</span></td><td>24 V rail bulk</td></tr>

<tr class="own"><td colspan="5">U25 — TPS54360B vehicle buck</td></tr>
<tr><td>C149 C150</td><td>2.2 µF/100 V</td><td>U25 pins 2/7 (VIN–GND)</td><td><span class="d d1">🔴</span></td><td>THE hot loop of the board</td></tr>
<tr><td>D34</td><td>B560C</td><td>U25 SW + C149 ground</td><td><span class="d d1">🔴</span></td><td>closes the hot loop</td></tr>
<tr><td>C151</td><td>100 µF/50 V</td><td>behind C149/C150</td><td><span class="d d2">🟠</span></td><td>input bulk</td></tr>
<tr><td>C152</td><td>100 nF</td><td>U25 BOOT (pins 1–8)</td><td><span class="d d1">🔴</span></td><td>boot flyer</td></tr>
<tr><td>L22</td><td>10 µH SRP1265A</td><td>U25 SW pin</td><td><span class="d d2">🟠</span></td><td>minimal SW copper</td></tr>
<tr><td>C153 C154</td><td>47 µF/16 V</td><td>L22 output pad</td><td><span class="d d2">🟠</span></td><td>VEH5V output caps; FB taps here</td></tr>
<tr><td>R121 R122</td><td>53.6k · 10.2k</td><td>U25 FB pin, tap at C153</td><td><span class="d d2">🟠</span></td><td>thin trace, away from L22's field</td></tr>
<tr><td>R123 C155 C156</td><td>13k · 6.8 nF · 39 pF</td><td>U25 COMP pin</td><td><span class="d d2">🟠</span></td><td>compensation — quiet side, short ground</td></tr>
<tr><td>R120</td><td>162k</td><td>U25 RT pin</td><td><span class="d d2">🟠</span></td><td>frequency-set, short ground</td></tr>
<tr><td>R124 R125</td><td>UVLO (DNP)</td><td>U25 EN pin</td><td><span class="d d2">🟠</span></td><td>divider lands here if fitted</td></tr>

<tr class="own"><td colspan="5">U6 — LTC4040 battery backup (+P3)</td></tr>
<tr><td>RS1</td><td>10 mΩ 1%</td><td>U6 sense pins</td><td><span class="d d1">🔴</span></td><td>Kelvin — sense routes from the pad faces</td></tr>
<tr><td>L6</td><td>2.2 µH/8 A</td><td>U6 SW pins</td><td><span class="d d1">🔴</span></td><td>charger/boost loop tight</td></tr>
<tr><td>C30 C31 C78</td><td>10 µF · 2.2 µF · 220 µF</td><td>U6 VIN, after RS1</td><td><span class="d d2">🟠</span></td><td>VEH5V bank at the input pins</td></tr>
<tr><td>C32 C33 C34</td><td>47 µF ×2 · 10 µF</td><td>U6 MAIN5V output / Q7</td><td><span class="d d2">🟠</span></td><td>output bank</td></tr>
<tr><td>C35</td><td>22 µF</td><td>U6 BAT pin → P3</td><td><span class="d d2">🟠</span></td><td>on the wide /BAT_PLUS copper</td></tr>
<tr><td>Q7</td><td>AO4406A</td><td>U6 gate/PowerPath side</td><td><span class="d d2">🟠</span></td><td>the blackout switch</td></tr>
<tr><td>R50</td><td>825R 1%</td><td>U6 PROG pin</td><td><span class="d d1">🔴</span></td><td>precision current-program R</td></tr>
<tr><td>R51 R52</td><td>270k · 100k</td><td>U6 PFI pin</td><td><span class="d d2">🟠</span></td><td>power-fail divider</td></tr>
<tr><td>R53 R54</td><td>499k · 100k</td><td>U6 FB pin</td><td><span class="d d2">🟠</span></td><td>boost feedback</td></tr>
<tr><td>R55</td><td>10k 1%</td><td>U6 NTC pin</td><td><span class="d d2">🟠</span></td><td>pack-thermistor divider (probe enters at P3)</td></tr>
<tr><td>JP2 JP3 JP4</td><td>F-straps</td><td>U6 F0/F1/F2 pins</td><td><span class="d d3">🔵</span></td><td>logic straps</td></tr>
<tr><td>R56 R57 R58</td><td>100k ×3</td><td>U6 ↔ U16 route</td><td><span class="d d3">🔵</span></td><td>status/enable pulls, anywhere on the line</td></tr>
<tr><td>TP1 TP2</td><td>CLPROG · PFO</td><td>U6 block edge</td><td><span class="d d3">🔵</span></td><td>probe access</td></tr>

<tr class="own"><td colspan="5">U2 — MP1584 fan buck (+P4)</td></tr>
<tr><td>C11</td><td>100 nF</td><td>U2 VIN pin</td><td><span class="d d1">🔴</span></td><td>non-sync input loop (C10/C22 bulk behind)</td></tr>
<tr><td>Dbk1</td><td>SS34</td><td>U2 SW + input ground</td><td><span class="d d1">🔴</span></td><td>catch diode — same loop</td></tr>
<tr><td>Cbst1</td><td>10 nF</td><td>U2 BOOT–SW</td><td><span class="d d1">🔴</span></td><td>boot flyer</td></tr>
<tr><td>L2</td><td>10 µH</td><td>U2 SW</td><td><span class="d d2">🟠</span></td><td>minimal SW copper</td></tr>
<tr><td>C23</td><td>22 µF/16 V</td><td>L2 output → P4</td><td><span class="d d2">🟠</span></td><td>5V_FAN output cap</td></tr>
<tr><td>R20 R21</td><td>100k · 19.1k</td><td>U2 FB, tap at C23</td><td><span class="d d2">🟠</span></td><td>feedback divider</td></tr>
<tr><td>Rcomp1 Ccomp1</td><td>40.2k · 2.2 nF</td><td>U2 COMP pin</td><td><span class="d d2">🟠</span></td><td>compensation</td></tr>
<tr><td>Rfreq1</td><td>100k</td><td>U2 FREQ pin</td><td><span class="d d2">🟠</span></td><td>frequency-set</td></tr>
<tr><td>Ren1 Ren2</td><td>100k · 20k</td><td>U2 EN pin</td><td><span class="d d3">🔵</span></td><td>enable divider</td></tr>
<tr><td>D2</td><td>SS34</td><td>P4 pins</td><td><span class="d d1">🔴</span></td><td>flyback right at the fan jack</td></tr>
<tr><td>Q2 Rgs1</td><td>AO3400A · 100k</td><td>P4 return · Rgs1 on Q2 G–S</td><td><span class="d d2">🟠</span></td><td>low-side switch at the jack, G–S resistor glued</td></tr>
<tr><td>Q5 Rg1</td><td>MMBT3904 · 100R</td><td>Q2 gate</td><td><span class="d d3">🔵</span></td><td>gate driver stage</td></tr>
<tr><td>JP1</td><td>0R</td><td>P4 5V_FAN link</td><td><span class="d d3">🔵</span></td><td>current-measure link</td></tr>

<tr class="own"><td colspan="5">U20 — AP64350 modem buck</td></tr>
<tr><td>C127 C128</td><td>10 µF · 1 µF</td><td>U20 VIN pin 2</td><td><span class="d d1">🔴</span></td><td>sync input loop — 1 µF closest of all</td></tr>
<tr><td>C129</td><td>100 nF</td><td>U20 BOOT–SW</td><td><span class="d d1">🔴</span></td><td>boot flyer</td></tr>
<tr><td>L20</td><td>4.7 µH/5 A</td><td>U20 SW</td><td><span class="d d2">🟠</span></td><td>minimal SW copper</td></tr>
<tr><td>D21</td><td>PMEG3050EP</td><td>U20 VIN feed</td><td><span class="d d2">🟠</span></td><td>input ORing</td></tr>
<tr><td>D20</td><td>SS34</td><td>24 V → U20 input branch</td><td><span class="d d3">🔵</span></td><td>feed diode</td></tr>
<tr><td>R110 R111</td><td>75k · 20k</td><td>U20 FB pin</td><td><span class="d d2">🟠</span></td><td>feedback divider</td></tr>
<tr><td>R116 C141 C142</td><td>14k · 3.3 nF · 47 pF</td><td>U20 COMP pin</td><td><span class="d d2">🟠</span></td><td>compensation</td></tr>
<tr><td>R117</td><td>200k 1%</td><td>U20 RT pin</td><td><span class="d d2">🟠</span></td><td>frequency-set</td></tr>
<tr><td>R113</td><td>100k</td><td>U20 EN pin</td><td><span class="d d3">🔵</span></td><td>enable pull</td></tr>

<tr class="own"><td colspan="5">U19 — A7670SA modem (+U22 SIM · U23/U24 · K1 · J13)</td></tr>
<tr><td>C135 C136</td><td>33 pF · 10 pF</td><td>U19 pins 55/56/57</td><td><span class="d d1">🔴</span></td><td>TX-harmonic filters — the closest of the bank</td></tr>
<tr><td>C134 C133 C132</td><td>100 nF → 1 µF → 22 µF</td><td>stepping back from those pins</td><td><span class="d d2">🟠</span></td><td>the gradient</td></tr>
<tr><td>C130 C131</td><td>220 µF/10 V ×2</td><td>far end of U19's VBAT bank</td><td><span class="d d3">🔵</span></td><td>≥300 µF burst reservoir</td></tr>
<tr><td>D22</td><td>SMAJ5.0A</td><td>at C130/C131</td><td><span class="d d2">🟠</span></td><td>VBAT clamp</td></tr>
<tr><td>R112</td><td>1k</td><td>U19 VBAT side</td><td><span class="d d3">🔵</span></td><td>bleed/monitor</td></tr>
<tr><td>C125</td><td>2.2 µF</td><td>U19 pin 15 (1V8 out)</td><td><span class="d d1">🔴</span></td><td>LDO output cap</td></tr>
<tr><td>U22</td><td>SIM (fp TBD)</td><td>U19 pins 30–33, ≤5 mm</td><td><span class="d d2">🟠</span></td><td>unshielded SIM bus</td></tr>
<tr><td>C126</td><td>100 nF</td><td>U22 VCC pad</td><td><span class="d d1">🔴</span></td><td>SIM supply</td></tr>
<tr><td>D23 D24 D25</td><td>PESD5V0S1BA</td><td>U22 SIM pads</td><td><span class="d d1">🔴</span></td><td>ESD at the socket, not mid-route</td></tr>
<tr><td>U23 U24</td><td>74LVC2T45</td><td>between U19 and U16</td><td><span class="d d3">🔵</span></td><td>level shifters sit on the path</td></tr>
<tr><td>C137 C139</td><td>100 nF</td><td>U23/U24 1V8 pins</td><td><span class="d d1">🔴</span></td><td>supply pair, one each</td></tr>
<tr><td>C138 C140</td><td>100 nF</td><td>U23/U24 3V3 pins</td><td><span class="d d1">🔴</span></td><td>supply pair, one each</td></tr>
<tr><td>Q20 R114</td><td>2N7002 · 100k</td><td>U19 PWRKEY side</td><td><span class="d d3">🔵</span></td><td>open-drain driver</td></tr>
<tr><td>Q21 R115</td><td>2N7002 · 100k</td><td>U19 RESET side</td><td><span class="d d3">🔵</span></td><td>open-drain driver</td></tr>
<tr><td>R109 Q22 Rmled1 D4G1</td><td>NETLIGHT chain</td><td>U19 netlight pin → LED at a visible spot</td><td><span class="d d3">🔵</span></td><td>status LED driver</td></tr>
<tr><td>R106 R107 R108</td><td>100R · 0R ×2</td><td>U23/U24 line ends</td><td><span class="d d3">🔵</span></td><td>UART series elements</td></tr>
<tr><td>TP8</td><td>USB_BOOT</td><td>U19 BOOT pin</td><td><span class="d d3">🔵</span></td><td>probe access</td></tr>
<tr><td>R118 C146 C147</td><td>0R · DNP pi</td><td>inline in the 50 Ω run, U19 RF pad → J13</td><td><span class="d d1">🔴</span></td><td>matching seats — zero stubs</td></tr>
<tr><td>D28</td><td>ESD9L</td><td>J13</td><td><span class="d d1">🔴</span></td><td>at the connector, stub-less</td></tr>
<tr><td>D6</td><td>1N4148W</td><td>K1 coil pins</td><td><span class="d d1">🔴</span></td><td>flyback across the coil</td></tr>
<tr><td>Q6 R2 C101</td><td>MMBT3904 · 10k · 22 µF</td><td>K1 coil side</td><td><span class="d d2">🟠</span></td><td>relay driver + coil supply cap</td></tr>

<tr class="own"><td colspan="5">U18 — ZED-F9P GNSS (+U21 LDO · J12)</td></tr>
<tr><td>C121 C122 C123</td><td>100 nF ×3</td><td>U18 VCC pins, one each</td><td><span class="d d1">🔴</span></td><td>per-pin decouplers</td></tr>
<tr><td>C120 C124</td><td>10 µF ×2</td><td>U21 output · U18 VCC entry</td><td><span class="d d1">🔴</span></td><td>LDO stability + local bulk</td></tr>
<tr><td>C119</td><td>10 µF</td><td>U21 input pin</td><td><span class="d d1">🔴</span></td><td>LDO input</td></tr>
<tr><td>C3 C40</td><td>47 µF · 22 µF</td><td>SW_5V feed near U21</td><td><span class="d d2">🟠</span></td><td>upstream bulk</td></tr>
<tr><td>Q1</td><td>AO3401A</td><td>upstream of U21 on SW_5V</td><td><span class="d d3">🔵</span></td><td>rail switch</td></tr>
<tr><td>R105</td><td>10k</td><td>U18 pull-up</td><td><span class="d d3">🔵</span></td><td>strap</td></tr>
<tr><td>L21 C144 C145</td><td>68 nH · 100 nF · 100 pF</td><td>bias-tee tap on the 50 Ω run</td><td><span class="d d1">🔴</span></td><td>antenna supply injection</td></tr>
<tr><td>C143</td><td>100 nF RF</td><td>inline, L21 tap → J12</td><td><span class="d d1">🔴</span></td><td>DC block</td></tr>
<tr><td>D27</td><td>ESD9L ≤0.5 pF</td><td>J12</td><td><span class="d d1">🔴</span></td><td>at the connector, stub-less</td></tr>

<tr class="own"><td colspan="5">U16 — STM32 MCU (+Y3/Y4 · J11/J9 USB · sense jacks)</td></tr>
<tr><td>C111</td><td>4.7 µF</td><td>U16 VCAP1 pin</td><td><span class="d d1">🔴</span></td><td>core regulator — non-negotiable</td></tr>
<tr><td>R104</td><td>10R</td><td>U16 VDDA feed</td><td><span class="d d1">🔴</span></td><td>analog supply filter element</td></tr>
<tr><td>C109 C112</td><td>100 nF · 1 µF</td><td>U16 VDDA pin, behind R104</td><td><span class="d d1">🔴</span></td><td>analog decoupling</td></tr>
<tr><td>C105 C106 C107 C108</td><td>100 nF ×4</td><td>one per U16 VDD pin</td><td><span class="d d1">🔴</span></td><td>the netlist pass parked C106–C108 near U3 — they are U16's, bring them back</td></tr>
<tr><td>C110</td><td>4.7 µF</td><td>U16 VDD bulk</td><td><span class="d d2">🟠</span></td><td>local reservoir</td></tr>
<tr><td>C104</td><td>100 nF</td><td>U16 NRST pin</td><td><span class="d d1">🔴</span></td><td>the P6 jack just routes to it</td></tr>
<tr><td>Y3 C113 C114</td><td>25 MHz · 15 pF</td><td>U16 OSC pins</td><td><span class="d d1">🔴</span></td><td>tight triangle, local ground</td></tr>
<tr><td>Y4 C115 C116</td><td>32.768 kHz · 12 pF</td><td>U16 OSC32 pins</td><td><span class="d d1">🔴</span></td><td>tighter still — high-impedance osc</td></tr>
<tr><td>R5 R6 C5</td><td>10k ×2 · 100 nF</td><td>U16 BAT_SENSE ADC pin</td><td><span class="d d2">🟠</span></td><td>divider + filter at the pin</td></tr>
<tr><td>R7 R8 C7</td><td>10k ×2 · 100 nF</td><td>U16 5V_SENSE ADC pin</td><td><span class="d d2">🟠</span></td><td>divider + filter at the pin</td></tr>
<tr><td>Rig2 Rigb1 C9 D5</td><td>22k · 3.3k · 100 nF · BAT54</td><td>U16 IGN_SENSE ADC pin</td><td><span class="d d2">🟠</span></td><td>divider + filter + clamp at the pin</td></tr>
<tr><td>R42 C24</td><td>10k 1% · 100 nF</td><td>U16 NTC1 ADC pin — P7 is just the jack</td><td><span class="d d2">🟠</span></td><td>the probe wire filters at the pin</td></tr>
<tr><td>R126 C157</td><td>10k 1% · 100 nF</td><td>U16 NTC2 ADC pin (PC4) — P8 is just the jack</td><td><span class="d d2">🟠</span></td><td>same rule</td></tr>
<tr><td>R98 R99</td><td>10k ×2</td><td>U16 BOOT straps</td><td><span class="d d3">🔵</span></td><td>anywhere in the block</td></tr>
<tr><td>Rdfu1</td><td>22k</td><td>U16 USART1_RX</td><td><span class="d d3">🔵</span></td><td>series element</td></tr>
<tr><td>TP3 TP4 TP5</td><td>SWDIO · SWCLK · NRST</td><td>U16 side / P6 side</td><td><span class="d d3">🔵</span></td><td>probe access</td></tr>
<tr><td>R1 R40 R56</td><td>1k · 1k · 100k</td><td>control lines U16 → power blocks</td><td><span class="d d3">🔵</span></td><td>anywhere along the route</td></tr>
<tr><td>D17</td><td>LED (blue)</td><td>U16 PC13 vicinity, visible</td><td><span class="d d3">🔵</span></td><td>heartbeat LED</td></tr>
<tr><td>Q4 Rled1</td><td>AO3400A · 10k</td><td>near the P9/P10 edge</td><td><span class="d d3">🔵</span></td><td>external-LED driver</td></tr>
<tr><td>D13</td><td>SS34</td><td>J11 VBUS</td><td><span class="d d2">🟠</span></td><td>VBUS ORing</td></tr>
<tr><td>D14 D15 D16</td><td>PESD5V0S1BA</td><td>J11 pads (DP/DM/VBUS)</td><td><span class="d d1">🔴</span></td><td>ESD at the jack — never mid-route</td></tr>
<tr><td>R100 R101</td><td>5.1k</td><td>J11 CC pads</td><td><span class="d d1">🔴</span></td><td>USB-C sink ID</td></tr>
<tr><td>Rcc1 Rcc2</td><td>5.1k</td><td>J9 CC pads</td><td><span class="d d1">🔴</span></td><td>USB-C sink ID</td></tr>

<tr class="own"><td colspan="5">U11 — W5500 Ethernet (+U12 buck · Y1 · J10)</td></tr>
<tr><td>C90</td><td>10 µF</td><td>U11 TOCAP pin</td><td><span class="d d1">🔴</span></td><td>internal-regulator cap</td></tr>
<tr><td>C91</td><td>4.7 µF</td><td>U11 1V2 pin</td><td><span class="d d1">🔴</span></td><td>core rail</td></tr>
<tr><td>C92 C93 C98</td><td>100 nF ×3</td><td>U11 VCC pins, one each</td><td><span class="d d1">🔴</span></td><td>per-pin decouplers</td></tr>
<tr><td>C94 C102</td><td>10 µF · 22 µF</td><td>U11 supply entry</td><td><span class="d d2">🟠</span></td><td>local bulk</td></tr>
<tr><td>Y1 C95 C96</td><td>25 MHz · 18 pF</td><td>U11 XI/XO pins</td><td><span class="d d1">🔴</span></td><td>tight triangle</td></tr>
<tr><td>R83</td><td>12.4k 1%</td><td>U11 RSET pin</td><td><span class="d d1">🔴</span></td><td>precision bias — short, clean ground</td></tr>
<tr><td>R84</td><td>10k</td><td>U11 PMODE</td><td><span class="d d3">🔵</span></td><td>strap</td></tr>
<tr><td>R92 R93</td><td>49.9R 1%</td><td>U11 TX pins → J10</td><td><span class="d d1">🔴</span></td><td>line terminations</td></tr>
<tr><td>R94 R95 C97</td><td>49.9R ×2 · 6.8 nF</td><td>J10 center taps</td><td><span class="d d1">🔴</span></td><td>Bob Smith / RCT network at the magjack</td></tr>
<tr><td>C103</td><td>100 µF/6.3 V</td><td>J10 3V3 feed</td><td><span class="d d2">🟠</span></td><td>magnetics supply bulk</td></tr>
<tr><td>R96 R97</td><td>330R</td><td>J10 LED pins</td><td><span class="d d3">🔵</span></td><td>link/act LEDs</td></tr>
<tr><td>D11</td><td>SS34</td><td>U12 SW + input ground</td><td><span class="d d1">🔴</span></td><td>ETH buck catch diode</td></tr>
<tr><td>C100</td><td>10 nF</td><td>U12 BOOT</td><td><span class="d d1">🔴</span></td><td>boot flyer</td></tr>
<tr><td>L8</td><td>10 µH/2 A</td><td>U12 SW</td><td><span class="d d2">🟠</span></td><td>minimal SW copper</td></tr>
<tr><td>R85 R86 R87 R88</td><td>FREQ · COMP · FB</td><td>U12 pins</td><td><span class="d d2">🟠</span></td><td>housekeeping at the IC</td></tr>

<tr class="own"><td colspan="5">U17 — AMS1117 3V3 LDO</td></tr>
<tr><td>C117</td><td>10 µF</td><td>U17 IN pin</td><td><span class="d d1">🔴</span></td><td>LDO input</td></tr>
<tr><td>C118</td><td>22 µF/16 V</td><td>U17 OUT pin</td><td><span class="d d1">🔴</span></td><td>LDO output / 3V3 bulk</td></tr>
<tr><td>D12</td><td>SS34</td><td>U17 input feed</td><td><span class="d d2">🟠</span></td><td>feed ORing</td></tr>

<tr class="own"><td colspan="5">Serial block — U15 RS232 · U10 UART · U14 RS485 · U13 expander</td></tr>
<tr><td>C85 C86 C87 C88</td><td>100 nF ×4</td><td>U15 pump pins, hard against the IC</td><td><span class="d d1">🔴</span></td><td>flying caps carry the pump current</td></tr>
<tr><td>C84</td><td>100 nF</td><td>U15 VCC pin</td><td><span class="d d1">🔴</span></td><td>supply</td></tr>
<tr><td>Y2 C82 C83</td><td>1.8432 MHz · 22 pF</td><td>U10 XTAL pins</td><td><span class="d d1">🔴</span></td><td>tight triangle</td></tr>
<tr><td>R30 R31</td><td>4.7k</td><td>U10 side of the I2C bus</td><td><span class="d d3">🔵</span></td><td>bus pull-ups</td></tr>
<tr><td>R80 R81</td><td>10k</td><td>U10 RST/IRQ</td><td><span class="d d3">🔵</span></td><td>pulls</td></tr>
<tr><td>C81 C89</td><td>100 nF ×2</td><td>U14 VCC (one is spare)</td><td><span class="d d1">🔴</span></td><td>supply</td></tr>
<tr><td>R82 JP5</td><td>120R · strap</td><td>P11 RS485 jack</td><td><span class="d d2">🟠</span></td><td>termination lives at the connector</td></tr>
<tr><td>C80</td><td>100 nF</td><td>U13 VCC pin</td><td><span class="d d1">🔴</span></td><td>supply</td></tr>
<tr><td>RB1 RB2 RB3 RB4<br>DB1 DB2 DB3 DB4</td><td>120R + LED ×4</td><td>U13 outputs → LEDs at the visible edge</td><td><span class="d d3">🔵</span></td><td>the netlist pass parked DB1–DB4 at U25 — they belong with U13</td></tr>

<tr class="own"><td colspan="5">U26 — SC7A20 accelerometer (at MH6)</td></tr>
<tr><td>C158 C159</td><td>100 nF ×2</td><td>U26 VDD/VDDIO pins</td><td><span class="d d1">🔴</span></td><td>one per supply pin</td></tr>
<tr><td>C160</td><td>10 µF</td><td>U26 bulk</td><td><span class="d d2">🟠</span></td><td>local reservoir; U26 itself ≤10 mm from MH6</td></tr>

<tr class="own"><td colspan="5">Panel · sensors · leftovers</td></tr>
<tr><td>Cu3</td><td>100 nF</td><td>U3 SHT40 VDD pin</td><td><span class="d d1">🔴</span></td><td>sensor supply</td></tr>
<tr><td>Cu4</td><td>100 nF</td><td>— spare (ex-TMP102)</td><td><span class="d d3">🔵</span></td><td>reassign to any bare VDD pin or delete</td></tr>
<tr><td>C99</td><td>2.2 nF</td><td>U17/U12 area rail bypass</td><td><span class="d d3">🔵</span></td><td>verify its role in the sch before final spot</td></tr>
<tr><td>R41</td><td>10k</td><td>U3/U16 I2C area</td><td><span class="d d3">🔵</span></td><td>pull-up strap</td></tr>
<tr><td>R3 D1</td><td>120R · LED</td><td>P9 pins</td><td><span class="d d3">🔵</span></td><td>R3 at the jack</td></tr>
<tr><td>R89 R90 R91</td><td>120R ×3</td><td>P10 pins</td><td><span class="d d2">🟠</span></td><td>series at the jack — the wire radiates otherwise</td></tr>
<tr><td>D18 R102 R103</td><td>LED (green) · 1k ×2</td><td>3V3 rail, visible spot</td><td><span class="d d3">🔵</span></td><td>power LED</td></tr>
<tr><td>TP6 TP7</td><td>GND · 3V3</td><td>anywhere reachable</td><td><span class="d d3">🔵</span></td><td>probe access</td></tr>
</table></div>
<div class="note"><b>Rail 100 nF rule, restated:</b> every plain 100 nF above pairs with exactly one IC power pin and moves with that IC forever. If you relocate an IC during fine-tuning, its 🔴 rows move in the same drag.</div>

<h2><span class="no">§9</span>Separation rules</h2>
<div class="tblwrap"><table>
<tr><th>Keep apart</th><th>Min</th><th>Why</th></tr>
<tr><td>GNSS island ↔ any switcher L / SW node</td><td>25 mm</td><td>−167 dBm receiver vs. dV/dt fields</td></tr>
<tr><td>GNSS RF run ↔ LTE RF run</td><td>opposite ends</td><td>desense is risk #1; antennas ≥ 20 cm at the enclosure</td></tr>
<tr><td>Any crystal ↔ any inductor</td><td>10 mm</td><td>magnetic pickup into the oscillator</td></tr>
<tr><td>ADC sense traces ↔ SW nodes</td><td>5 mm + ground between</td><td>tntc/vbat readings ride on µV</td></tr>
<tr><td>USB pairs (J9/J11) ↔ switchers</td><td>route as 90 Ω pairs, short</td><td>eye + radiated emissions</td></tr>
<tr><td>U26 accel ↔ mounting hole</td><td>≤ 10 mm (close!)</td><td>chassis coupling, not board flex</td></tr>
</table></div>

<h2><span class="no">§10</span>Order of work from here</h2>
<ol class="steps">
<li><b>Update PCB from Schematic</b> (NTC2 re-net), then fine-tune inside the §1 regions. Field wiring now enters mostly along the north edge + P1 at the SE corner — keep each connector beside its block, and its TVS/filter parts right at the jack, so cable common-mode currents stay off the board core.</li>
<li><b>Say the word and I re-add the four zones</b> — F.Cu GND pour, In1 GND (unbroken, especially under both RF runs and the crystals), In2 3V3, B.Cu GND — plus a stitching-via plan: 5 mm grid around RF, via fence along the board edge.</li>
<li><b>Route in this order:</b> ① both 50 Ω RF runs (CPWG on F.Cu over In1, JLC7628 ≈ 0.35/0.25 mm — confirm in the JLC calculator and order controlled impedance) · ② the two hot loops and VBAT ≥ 3 mm · ③ /SW_BAT ≥ 2 mm + /BAT_PLUS ≥ 1.5 mm with via farms · ④ USB and ETH pairs · ⑤ sense lines · ⑥ everything else.</li>
<li><b>Refill zones, full DRC</b>, then the G2 external review checkpoint before ordering.</li>
<li><b>Bench items carried forward:</b> measure U21's 3V3_GNSS rise (F9P ramp window), verify U25's EP against the TI DDA drawing, and the DzG1 jumper check on the fabbed v5.5 boards.</li>
</ol>

<p class="sub" style="margin-top:36px">EinarBoard HBOX v6 · Helgen · updated 04-Sep-2026: master proximity table (§8) from the live netlist; sch↔pcb designators verified in sync (P1–P12, 0 mismatches).</p>
</div>