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c81b2202ac
Drogheda/03-Architecture-Hardware
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Claude (Cowork) c81b2202ac v6 T3 CLOSED: Leo's Update-PCB-from-Schematic - Block N on the board; -04B pin table verified 
PCB (Leo, KiCad GUI 14:44): U18 + U21 + C119-C124 + R105 placed in the GNSS island
(U18 at 76.8, 101.4 r90 - freed MOD1 area, bottom-left). All nets verified on the board:
/3V3_GNSS 9 pads, U18 GND = 56 pads (8 + the 48-pad ground array), MCU side confirmed
(ANT_DETECT U16.9, ANT_SHORT_N U16.10, RTK_STAT U16.11, TIMEPULSE U16.23, RESET_N U16.53).
The sync also deleted MH7/MH9/MH10 - exactly the shield-bolt holes the delta doc retired;
MH4/5/6 (enclosure) and MH11 (heatsink clamp) survive. Footprints 224 -> 230.

Schematic diff vs previous commit: none (243 symbols / 666 labels / 125 no-connects
identical) - KiCad format normalization only.

-04B PIN CHECK CLOSED: the ZED-F9P-04B datasheet (UBX-21044850) pin table matches the
-15B transcription EXACTLY, all 54 pins. Spec refinement: VCC ramp is a WINDOW,
20-8000 us/V (3.3 V in 66 us .. 26.4 ms) - a normal LDO soft-start sits comfortably
inside it. Keep the bench measurement, drop the alarm.

NEXT: T4 LTE island. Needs the vendor part first:
  easyeda2kicad --full --lcsc_id=C18548276 --output <kicad>/Drogheda-v6
Standing: v6 zone fills still stale (GUI refill pending); DRC not meaningful until then.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-08-25 14:49:16 +00:00
..
CAD-Files auto-sync 2026-07-13 18:00 2026-07-13 18:00:15 -06:00
circuitikz-wiring auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
EinarBoard-Manual sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
Guia-Conexion-Protoboard auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
Informe-Tecnico-V3-V4 auto-sync 2026-08-11 18:00 2026-08-11 18:00:15 -06:00
kicad v6 T3 CLOSED: Leo's Update-PCB-from-Schematic - Block N on the board; -04B pin table verified 2026-08-25 14:49:16 +00:00
Manual-Instalacion-Operacion Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
4G-USB-Reset-LED-addition.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
0007-1000_Assembly_Guide.pdf auto-sync 2026-07-11 18:00 2026-07-11 18:00:15 -06:00
2026-07-06_Drogheda_EinarBoard-1.0-PreFab-Audit_v1.0.md sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
2026-07-08_Drogheda_4G-Modem-Alternatives_v1.0.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
2026-07-24_Drogheda_EinarBoard-1.1_Design-Brief_v1.0.md EinarBoard 1.1 design brief: locked decisions (RS-485+RS-232 via SC16IS752, on-board W5500 Ethernet, RGB status LED, board growth) + execution phases 2026-07-29 01:58:39 +00:00
2026-08-08_Drogheda_Firmware-v3.1_ModoB-PHLG_Design-Brief_v1.0.md auto-sync 2026-08-08 18:00 2026-08-08 18:00:15 -06:00
2026-08-12_Drogheda_EinarBoard-3.0_MCU-Integration_Design-Brief_v1.0.md auto-sync 2026-08-12 18:00 2026-08-12 18:00:16 -06:00
2026-08-14_Drogheda_EinarBoard-3.0_Capacitor-Placement-Map_v1.0.md auto-sync 2026-08-14 18:00 2026-08-14 18:00:14 -06:00
2026-08-20_Drogheda_EinarBoard-v5_Fixes-Applied_v1.0.md auto-sync 2026-08-20 18:00 2026-08-20 18:00:15 -06:00
2026-08-20_Drogheda_EinarBoard-v5_Pre-Audit-Checks_v1.0.md checkpoint: v5.5 as saved by Leo before Claude fixes (pre-audit report included) 2026-08-20 16:37:33 +00:00
Assembly-BOM-Split.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
BOM-master.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
bom.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
cabinet-electrical-bom.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.png 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.svg 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_EinarBoard-1.0_Tabla-Conexiones-Externas_v1.0.pdf auto-sync 2026-07-23 18:00 2026-07-23 18:00:14 -06:00
Drogheda_Guia-Cableado-Proto-Watchdog-v3_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v2.2.pdf auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.0.pdf auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.1.pdf auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
Drogheda-BOM-Maestro.xlsx Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda-Manual-Instalacion-Operacion.pdf Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-v3-pinned-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
firmware-review-v2.3-EinarBoard.md Firmware review: v2.3 as EinarBoard 1.0 production candidate (2026-07-24) 2026-07-24 01:27:20 +00:00
firmware-review.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
hardware-respec-and-pcb-brief.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
harness-connector-pinout.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
hbox-watchdog-v5-schematic.pdf auto-sync 2026-08-12 18:00 2026-08-12 18:00:16 -06:00
JLCPCB-Order-Guide.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
LCSC-search-list.md auto-sync 2026-07-07 18:00 2026-07-07 18:00:12 -06:00
Socket-Pinout-Silkscreen.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
watchdog-connections-rationale.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-connections.xlsx 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-electrical-design-state.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
watchdog-health-telemetry.md add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-LISTA-DE-COMPRAS-ES.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-pcb-v3-blockdiagram.svg auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-bom.xlsx add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-pcb-v3-design.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-pcb-v3-kicad-guide.md auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-routing-status.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
watchdog-production-schematic-delta.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-proto-bench-bringup-v3.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-protoboard-BOM-3boards.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-protoboard-bringup.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-schematic.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00