1.1 Phase C10: production footprint corrections + LCSC + silk rev (PRE-FAB GATE)
CRITICAL FIXES - parts only exist in these packages:
- U11 W5500: QFN-48-1EP -> LQFP-48_7x7mm_P0.5mm (ring 3.4375->4.1625, EP+paste
deleted, courtyard 10.3mm sq, 48 track retargets, RXN/RXP/RSET/GND(3,23,38-48)/
3V3_ETH(15,17,28)/1V2(22)/XI/PMODE/ACTLED/LINKLED reworked under+around body)
- U13 PCF8574: SOIC-16 narrow -> SOIC-16W_7.5x10.3mm (pads +-4.65, SW_BAT neck,
FAN_PWM/SCL/LED_A rework)
- U12 MP1584: stays plain SOIC-8 (EP addition attempted, reverted: SYS5V+COMP
route through EP zone; belly-over-mask accepted at 150mA load - flagged)
- LCSC fields (board+sch): W5500 C32843, SC16IS752 C57156, MP1584 C15051,
PCF8574T C7605, SP3485 C8963, MAX3232 C15846, HR911105A C12074, SS34 C8678 x2
- sch footprint fields synced (U11/U13); silk rev 'HBOX v4 - 2026-07';
toolkit ARCHIVE_NAME HBOX_v4_PROD
- verify: seg/via clearance 0 hits <0.125; SMD pad-aware 0 hits <0.09;
census 0 opens (GND pads U11.9/U11.29 pour-served by design)
Leopoldo Rodríguez
e06387d6a7