EinarBoard v6 Copper Plan

Placement companion for the 140 × 100 re-layout — every capacitor's owner, what clusters together, and the EMC order of work. Cap ownership below is computed from the board netlist, not from memory.

Connector renumber (03-Sep, commit b007c7c): P-refs now follow function order — P1 24V · P2 5V bench · P3 battery (was P4) · P4 fan (was P6) · P5 cutoff (was P11) · P6 reset (was P10) · P7 NTC probe 1 (was P12) · P8 NTC probe 2 (was P18) · P9 panel LED (was P8) · P10 RGB (was P14) · P11 RS485 (was P15) · P12 RS232 (was P16). ⚠ v5 field docs say "P12 = NTC" — in v6 that name is the RS232 port; update harness docs. The NTC2 net fix is applied and synced.

Known leftovers from the auto-clustering: ~54 small courtyard overlaps, nearly all against the legacy V5 regulator families that kept their old spots — L2/D2 (under U19's new outline), L6/DB2/DB3/Q2/Dbk1 near U25, C40, R40/R41 at Y3. Drag those few aside first and the board is clean.

§0Three laws that decide EMC at placement time

Loop area is the antenna

Emission scales with the area of each switching current loop. A hot loop closed in 1 cm² is ~20 dB quieter than the same loop at 10 cm². Placement fixes this; routing can't rescue a bad placement.

Smallest cap closest

A capacitor filters up to the frequency its trace inductance allows. Order banks by descending value toward the pin: bulk → 10 µF → 100 nF → pF, with the pF parts within 2–3 mm.

Aggressors far from victims

Four switchers, one LTE transmitter, one −167 dBm GNSS receiver on one board. Distance and an unbroken In1 ground plane are the only broadband shields you get for free.

§1Floorplan as clustered (NW ETH · NE LTE · SW GNSS · SE power)

The clustered state after commit c7d2552 — your anchors kept (J10, P1, U18, U16, U6, U15, K1, connectors), 160 support parts packed by family. Fine-tune freely inside each region; keep the diagonal.

§2Vehicle power entry — U25 TPS54360B hot loop

Chain order along the copper, left to right from P1: F2 → Q23 (with R119, D33 beside its gate) → D32 SMCJ33A → input caps → U25 → D34/L22 → output caps. D10 stays glued to P1 pin 1.

Loudest loop on the board: C149/C150 (+) → U25 VIN ⟶ U25 SW → D34 cathode ⟶ D34 anode → C149/C150 (−). This is a non-synchronous buck, so the input loop carries the full di/dt. Put C149/C150 within 2–3 mm of U25 pins 2/7, D34 directly across from them, and close the loop over solid ground. Under 1 cm² or do it again.

Ref	Value	Belongs to	Placement
C149 C150	2.2 µF/100 V	U25 VIN	2–3 mm from pins 2/7; the hot loop
C151	100 µF/50 V	U25 input bulk	right behind C149/C150
C152	100 nF	U25 BOOT	directly across pins 1–8
C153 C154	47 µF/16 V	U25 5 V output	at L22 output; FB tap (R121) here, not at the inductor
D34	B560C	U25 catch diode	anode ground ties straight into C149/C150 ground
D32	SMCJ33A	U25 input surge clamp	between Q23 and the input caps, short fat ties
R120 · R123 C155 C156 · R121 R122 · R124 R125	RT · COMP · FB · UVLO (DNP)	U25 analog side	cluster at pins 3–6, opposite the SW node; keep FB thin and away from L22

24 V rail housekeeping: C10/C22 bulk near Q10, C11 100 nF at the load side. Keep the whole entry block in one corner so the dirty 24 V copper never crosses the board.

§3Battery backup — U6 LTC4040 kelvin

Ref	Value	Belongs to	Placement
C30 C31 C78	10 µF · 2.2 µF · 220 µF	U6 VEH5V input	at U6 input pins, after RS1
C32 C33 C34	47 µF ×2 · 10 µF	U6 MAIN5V output	at U6/Q7 output side
C35	22 µF	U6 BAT pin → P3	near P3; `/SW_BAT` ≥ 2 mm polygon, `/BAT_PLUS` ≥ 1.5 mm — the blackout path, a hard v6 requirement

RS1 (10 mΩ) is a Kelvin part: the LTC4040 sense pins must tap the pad faces themselves, not the power trace. Place RS1 immediately at U6 with L22's output feeding it directly.

§4LTE island — U20 buck + U19 A7670SA hot loop

Second hot loop: C127/C128 → U20 VIN/GND. Synchronous buck, so the input loop is the loud one — C127 10 µF within 2–3 mm of U20 pin 2, C128 1 µF even closer. C129 boot across BOOT–SW, L20 right at SW with a minimal SW pour.

The VBAT bank is a one-direction gradient into pins 55/56/57 — largest farthest, smallest touching the module:

Ref	Value	Order	Placement
C130 C131	220 µF/10 V ×2	U19 VBAT · far end	the ≥300 µF droop reservoir (2.8 A bursts, ≤300 mV sag)
C132 → C133 → C134	22 µF → 1 µF → 100 nF	U19 VBAT · middle	stepping toward the module
C135 C136	33 pF · 10 pF	U19 pins 55/56/57	within 2–3 mm — these keep TX harmonics off VBAT
D22	SMAJ5.0A	U19 VBAT bank	across VBAT near C130/C131

VBAT copper ≥ 3 mm wide the whole way. Around the module: C125 at pin 15 (1V8 out); U22 SIM within 5 mm of pins 30–33 with C126 at its VCC pad and D23–D25 PESD at the SIM pads; U23/U24 level shifters between U19 and the MCU side, each with its supply pair (C137/C139 on 1V8, C138/C140 on 3V3) at the pins; Q20–Q22 near the control pins they drive. J13 U.FL at the board edge; the DNP pi network C146/C147 (+ its series element) sits inline in the 50 Ω run right at the connector, D28 ESD at the connector ground side.

§5GNSS island — U18 ZED-F9P + U21 LDO quiet

Ref	Value	Belongs to	Placement
C119	10 µF	U21 input (SW_5V)	at the LDO input pin
C120 C124	10 µF ×2	U21 out → U18 VCC	one at U21 output, one at U18's main VCC entry
C121 C122	100 nF ×2	U18 VCC pins 33/34	one per supply pin, at the pin
C123	100 nF	U21 VOUT, beside C120	U18 has only two VCC pins — C123 is the rail-entry third
Cu4	100 nF	U18 pin 36 V_BCKP (/3V3!)	V_BCKP rides the always-on 3V3, not 3V3_GNSS — that is deliberate (RTC + ephemeris survive when U21 is switched off). It needs its own /3V3 cap at the pin; C120–C124 are all on /3V3_GNSS and cannot serve it. Repurpose the spare Cu4.
C144 C145	100 nF · 100 pF	U18 VCC_RF · L21 bias tee	at L21's feed side — the antenna supply injection
C143	100 nF RF	J12 RF line (DC block)	inline in the 50 Ω run between L21 tap and J12
D27	ESD9L (≤0.5 pF)	J12	at the connector, stub-less tap on the RF line

This corner is the victim: no switcher, no inductor, no fast digital within ~25 mm (U25 sits ~95 mm away in the SE, the fan buck ~130 mm NE — keep it that way); nothing but solid In1 ground under the module and the RF run. TIMEPULSE to the MCU is the one digital line that leaves — route it away from the RF path.

§6MCU core — U16 analog care

Ref	Value	Belongs to	Placement
C111	4.7 µF	U16 VCAP1	≤ 3 mm from the pin — the core regulator, non-negotiable
C109 C112	100 nF · 1 µF	U16 VDDA	at the VDDA pin, on the quiet side, away from the switchers
C105–C108 + C110	100 nF ×4 + 4.7 µF	U16 VDD pins	one 100 nF per VDD pin, bulk nearby
C104	100 nF	U16 NRST	at the pin, with the P6 reset jack routed clean
Y3 + C113 C114	HSE + 15 pF	U16 OSC pins	tight triangle at the pins, local ground, ≥10 mm from any inductor
Y4 + C115 C116	LSE 32 kHz + 12 pF	U16 OSC32 pins	even tighter — high-impedance oscillator, guard with ground
C5 C7 C9 C24 C157	100 nF ×5	U16 ADC pins	with their dividers (R42, R126…) at the MCU pins, not at the jacks — the wire filters at the pin

§7The rest of the families

Ethernet (U11/U12, Y1, C90–C103): one block, U11 close to J10 (magnetics are inside the HR911105A), crystal + 18 pF at the pins, the 3V3_ETH locals (C92–C94, C98, C102, C103) around U11. Keep the RJ45 pair region free of other routes.
RS232 (U15): C85–C88 are charge-pump flying caps — they carry the pump current, so they sit hard against U15; C84 100 nF at its supply pin. P12 (RS232 jack) at the edge.
UART bridge (U10, Y2, C82/C83): crystal caps at the pins, block near the MCU.
Fan buck (U2, Cbst1, Ccomp1, C23): a third switcher — treat like §4's loop, and park it in the noisy quarter near the power entry, away from GNSS.
Accelerometer (U26, C158/C159 at VDD/VDDIO, C160 bulk): ≤ 10 mm from a mounting hole, on stiff board — it should feel the chassis, not board flex.
Rail sprinkles (Cu3 Cu4 C80 C81 C89 C105+…): every 100 nF on 3V3 pairs with one IC's power pin — when you move an IC, its 100 nF moves with it. C118 22 µF is the 3V3 bulk at the regulator.
NTC channels: pullup + filter (R42+C24 → P7, R126+C157 → P8) at the MCU; P7/P8 jacks at the harness edge.

§8Master proximity table — every discrete, its owner designator, and how close

Computed from the current board netlist (post-rename, all 300 footprints), then hand-corrected where the netlist heuristic picked a connected-but-wrong owner (ESD parts belong at connectors, ADC filters at the MCU, comp caps at their regulator). Distance classes:

🔴 GLUED ≤3 mm loop-critical — same pad ground, no via between 🟠 CLOSE ≤5 mm at the pin, short direct trace 🔵 BLOCK ≤15 mm same cluster, routing order free

Ref	Value	Glue to		Why
P1 — 24 V entry (SE corner)
D10	SMBJ33A	P1 pin 1 (24V_IN)	🔴	surge clamp at the jack, before anything else
Rig1	22k	P1 ignition pin	🔴	series element right at the jack
F2	2 A slow 1812	P1 → Q23	🔵	first element in the chain
Q23	IRFR5305	F2 output	🔵	reverse-polarity FET, chain order
R119 D33	100k · BZX84C15	Q23 G–S pads	🔴	gate bias + 15 V clamp across the FET itself
D32	SMCJ33A	between Q23 and C149/C150	🟠	clamps the line before the buck sees it
Q10	IRFR5305	P1 24 V branch	🔵	legacy 24 V rail FET (feeds U2 + K1)
Rrp1 DzG1	10k · BZX84C15	Q10 G–S pads	🔴	gate network — the part behind the v5.5 jumper check
C10 C22	47 µF/50 V · 22 µF/50 V	Q10 load side (/24V)	🔵	24 V rail bulk
U25 — TPS54360B vehicle buck
C149 C150	2.2 µF/100 V	U25 pins 2/7 (VIN–GND)	🔴	THE hot loop of the board
D34	B560C	U25 SW + C149 ground	🔴	closes the hot loop
C151	100 µF/50 V	behind C149/C150	🟠	input bulk
C152	100 nF	U25 BOOT (pins 1–8)	🔴	boot flyer
L22	10 µH SRP1265A	U25 SW pin	🟠	minimal SW copper
C153 C154	47 µF/16 V	L22 output pad	🟠	VEH5V output caps; FB taps here
R121 R122	53.6k · 10.2k	U25 FB pin, tap at C153	🟠	thin trace, away from L22's field
R123 C155 C156	13k · 6.8 nF · 39 pF	U25 COMP pin	🟠	compensation — quiet side, short ground
R120	162k	U25 RT pin	🟠	frequency-set, short ground
R124 R125	UVLO (DNP)	U25 EN pin	🟠	divider lands here if fitted
U6 — LTC4040 battery backup (+P3)
RS1	10 mΩ 1%	U6 sense pins	🔴	Kelvin — sense routes from the pad faces
L6	2.2 µH/8 A	U6 SW pins	🔴	charger/boost loop tight
C30 C31 C78	10 µF · 2.2 µF · 220 µF	U6 VIN, after RS1	🟠	VEH5V bank at the input pins
C32 C33 C34	47 µF ×2 · 10 µF	U6 MAIN5V output / Q7	🟠	output bank
C35	22 µF	U6 BAT pin → P3	🟠	on the wide /BAT_PLUS copper
Q7	AO4406A	U6 gate/PowerPath side	🟠	the blackout switch
R50	825R 1%	U6 PROG pin	🔴	precision current-program R
R51 R52	270k · 100k	U6 PFI pin	🟠	power-fail divider
R53 R54	499k · 100k	U6 FB pin	🟠	boost feedback
R55	10k 1%	U6 NTC pin	🟠	pack-thermistor divider (probe enters at P3)
JP2 JP3 JP4	F-straps	U6 F0/F1/F2 pins	🔵	logic straps
R56 R57 R58	100k ×3	U6 ↔ U16 route	🔵	status/enable pulls, anywhere on the line
TP1 TP2	CLPROG · PFO	U6 block edge	🔵	probe access
U2 — MP1584 fan buck (+P4)
C11	100 nF	U2 VIN pin	🔴	non-sync input loop (C10/C22 bulk behind)
Dbk1	SS34	U2 SW + input ground	🔴	catch diode — same loop
Cbst1	10 nF	U2 BOOT–SW	🔴	boot flyer
L2	10 µH	U2 SW	🟠	minimal SW copper
C23	22 µF/16 V	L2 output → P4	🟠	5V_FAN output cap
R20 R21	100k · 19.1k	U2 FB, tap at C23	🟠	feedback divider
Rcomp1 Ccomp1	40.2k · 2.2 nF	U2 COMP pin	🟠	compensation
Rfreq1	100k	U2 FREQ pin	🟠	frequency-set
Ren1 Ren2	100k · 20k	U2 EN pin	🔵	enable divider
D2	SS34	P4 pins	🔴	flyback right at the fan jack
Q2 Rgs1	AO3400A · 100k	P4 return · Rgs1 on Q2 G–S	🟠	low-side switch at the jack, G–S resistor glued
Q5 Rg1	MMBT3904 · 100R	Q2 gate	🔵	gate driver stage
JP1	0R	P4 5V_FAN link	🔵	current-measure link
U20 — AP64350 modem buck
C127 C128	10 µF · 1 µF	U20 VIN pin 2	🔴	sync input loop — 1 µF closest of all
C129	100 nF	U20 BOOT–SW	🔴	boot flyer
L20	4.7 µH/5 A	U20 SW	🟠	minimal SW copper
D21	PMEG3050EP	U20 VIN feed	🟠	input ORing
D20	SS34	24 V → U20 input branch	🔵	feed diode
R110 R111	75k · 20k	U20 FB pin	🟠	feedback divider
R116 C141 C142	14k · 3.3 nF · 47 pF	U20 COMP pin	🟠	compensation
R117	200k 1%	U20 RT pin	🟠	frequency-set
R113	100k	U20 EN pin	🔵	enable pull
U19 — A7670SA modem (+U22 SIM · U23/U24 · K1 · J13)
C135 C136	33 pF · 10 pF	U19 pins 55/56/57	🔴	TX-harmonic filters — the closest of the bank
C134 C133 C132	100 nF → 1 µF → 22 µF	stepping back from those pins	🟠	the gradient
C130 C131	220 µF/10 V ×2	far end of U19's VBAT bank	🔵	≥300 µF burst reservoir
D22	SMAJ5.0A	at C130/C131	🟠	VBAT clamp
R112	1k	U19 VBAT side	🔵	bleed/monitor
C125	2.2 µF	U19 pin 15 (1V8 out)	🔴	LDO output cap
U22	SIM (fp TBD)	U19 pins 30–33, ≤5 mm	🟠	unshielded SIM bus
C126	100 nF	U22 VCC pad	🔴	SIM supply
D23 D24 D25	PESD5V0S1BA	U22 SIM pads	🔴	ESD at the socket, not mid-route
U23 U24	74LVC2T45	between U19 and U16	🔵	level shifters sit on the path
C137 C139	100 nF	U23/U24 1V8 pins	🔴	supply pair, one each
C138 C140	100 nF	U23/U24 3V3 pins	🔴	supply pair, one each
Q20 R114	2N7002 · 100k	U19 PWRKEY side	🔵	open-drain driver
Q21 R115	2N7002 · 100k	U19 RESET side	🔵	open-drain driver
R109 Q22 Rmled1 D4G1	NETLIGHT chain	U19 netlight pin → LED at a visible spot	🔵	status LED driver
R106 R107 R108	100R · 0R ×2	U23/U24 line ends	🔵	UART series elements
TP8	USB_BOOT	U19 BOOT pin	🔵	probe access
R118 C146 C147	0R · DNP pi	inline in the 50 Ω run, U19 RF pad → J13	🔴	matching seats — zero stubs
D28	ESD9L	J13	🔴	at the connector, stub-less
D6	1N4148W	K1 coil pins	🔴	flyback across the coil
Q6 R2 C101	MMBT3904 · 10k · 22 µF	K1 coil side	🟠	relay driver + coil supply cap
U18 — ZED-F9P GNSS (+U21 LDO · J12)
C121 C122	100 nF ×2	U18 VCC pins 33/34, one each	🔴	per-pin decouplers
C123	100 nF	U21 VOUT beside C120	🟠	third 100 nF — rail entry, not a third VCC pin
Cu4	100 nF	U18 pin 36 V_BCKP — on /3V3	🔴	only /3V3 cap in the corner; backup rail stays alive when U21 is off
C120 C124	10 µF ×2	U21 output · U18 VCC entry	🔴	LDO stability + local bulk
C119	10 µF	U21 input pin	🔴	LDO input
C3 C40	47 µF · 22 µF	SW_5V feed near U21	🟠	upstream bulk
Q1	AO3401A	upstream of U21 on SW_5V	🔵	rail switch
R105	10k	U18 pull-up	🔵	strap
L21 C144 C145	68 nH · 100 nF · 100 pF	bias-tee tap on the 50 Ω run	🔴	antenna supply injection
C143	100 nF RF	inline, L21 tap → J12	🔴	DC block
D27	ESD9L ≤0.5 pF	J12	🔴	at the connector, stub-less
U16 — STM32 MCU (+Y3/Y4 · J11/J9 USB · sense jacks)
C111	4.7 µF	U16 VCAP1 pin	🔴	core regulator — non-negotiable
R104	10R	U16 VDDA feed	🔴	analog supply filter element
C109 C112	100 nF · 1 µF	U16 VDDA pin, behind R104	🔴	analog decoupling
C105 C106 C107 C108	100 nF ×4	one per U16 VDD pin	🔴	the netlist pass parked C106–C108 near U3 — they are U16's, bring them back
C110	4.7 µF	U16 VDD bulk	🟠	local reservoir
C104	100 nF	U16 NRST pin	🔴	the P6 jack just routes to it
Y3 C113 C114	25 MHz · 15 pF	U16 OSC pins	🔴	tight triangle, local ground
Y4 C115 C116	32.768 kHz · 12 pF	U16 OSC32 pins	🔴	tighter still — high-impedance osc
R5 R6 C5	10k ×2 · 100 nF	U16 BAT_SENSE ADC pin	🟠	divider + filter at the pin
R7 R8 C7	10k ×2 · 100 nF	U16 5V_SENSE ADC pin	🟠	divider + filter at the pin
Rig2 Rigb1 C9 D5	22k · 3.3k · 100 nF · BAT54	U16 IGN_SENSE ADC pin	🟠	divider + filter + clamp at the pin
R42 C24	10k 1% · 100 nF	U16 NTC1 ADC pin — P7 is just the jack	🟠	the probe wire filters at the pin
R126 C157	10k 1% · 100 nF	U16 NTC2 ADC pin (PC4) — P8 is just the jack	🟠	same rule
R98 R99	10k ×2	U16 BOOT straps	🔵	anywhere in the block
Rdfu1	22k	U16 USART1_RX	🔵	series element
TP3 TP4 TP5	SWDIO · SWCLK · NRST	U16 side / P6 side	🔵	probe access
R1 R40 R56	1k · 1k · 100k	control lines U16 → power blocks	🔵	anywhere along the route
D17	LED (blue)	U16 PC13 vicinity, visible	🔵	heartbeat LED
Q4 Rled1	AO3400A · 10k	near the P9/P10 edge	🔵	external-LED driver
D13	SS34	J11 VBUS	🟠	VBUS ORing
D14 D15 D16	PESD5V0S1BA	J11 pads (DP/DM/VBUS)	🔴	ESD at the jack — never mid-route
R100 R101	5.1k	J11 CC pads	🔴	USB-C sink ID
Rcc1 Rcc2	5.1k	J9 CC pads	🔴	USB-C sink ID
U11 — W5500 Ethernet (+U12 buck · Y1 · J10)
C90	10 µF	U11 TOCAP pin	🔴	internal-regulator cap
C91	4.7 µF	U11 1V2 pin	🔴	core rail
C92 C93 C98	100 nF ×3	U11 VCC pins, one each	🔴	per-pin decouplers
C94 C102	10 µF · 22 µF	U11 supply entry	🟠	local bulk
Y1 C95 C96	25 MHz · 18 pF	U11 XI/XO pins	🔴	tight triangle
R83	12.4k 1%	U11 RSET pin	🔴	precision bias — short, clean ground
R84	10k	U11 PMODE	🔵	strap
R92 R93	49.9R 1%	U11 TX pins → J10	🔴	line terminations
R94 R95 C97	49.9R ×2 · 6.8 nF	J10 center taps	🔴	Bob Smith / RCT network at the magjack
C103	100 µF/6.3 V	J10 3V3 feed	🟠	magnetics supply bulk
R96 R97	330R	J10 LED pins	🔵	link/act LEDs
D11	SS34	U12 SW + input ground	🔴	ETH buck catch diode
C100	10 nF	U12 BOOT	🔴	boot flyer
L8	10 µH/2 A	U12 SW	🟠	minimal SW copper
R85 R86 R87 R88	FREQ · COMP · FB	U12 pins	🟠	housekeeping at the IC
U17 — AMS1117 3V3 LDO
C117	10 µF	U17 IN pin	🔴	LDO input
C118	22 µF/16 V	U17 OUT pin	🔴	LDO output / 3V3 bulk
D12	SS34	U17 input feed	🟠	feed ORing
Serial block — U15 RS232 · U10 UART · U14 RS485 · U13 expander
C85 C86 C87 C88	100 nF ×4	U15 pump pins, hard against the IC	🔴	flying caps carry the pump current
C84	100 nF	U15 VCC pin	🔴	supply
Y2 C82 C83	1.8432 MHz · 22 pF	U10 XTAL pins	🔴	tight triangle
R30 R31	4.7k	U10 side of the I2C bus	🔵	bus pull-ups
R80 R81	10k	U10 RST/IRQ	🔵	pulls
C81 C89	100 nF ×2	U14 VCC (one is spare)	🔴	supply
R82 JP5	120R · strap	P11 RS485 jack	🟠	termination lives at the connector
C80	100 nF	U13 VCC pin	🔴	supply
RB1 RB2 RB3 RB4 DB1 DB2 DB3 DB4	120R + LED ×4	U13 outputs → LEDs at the visible edge	🔵	the netlist pass parked DB1–DB4 at U25 — they belong with U13
U26 — SC7A20 accelerometer (at MH6)
C158 C159	100 nF ×2	U26 VDD/VDDIO pins	🔴	one per supply pin
C160	10 µF	U26 bulk	🟠	local reservoir; U26 itself ≤10 mm from MH6
Panel · sensors · leftovers
Cu3	100 nF	U3 SHT40 VDD pin	🔴	sensor supply
Cu4	100 nF	reassigned → U18 pin 36 V_BCKP	🔴	see the GNSS group — it is already on /3V3–GND, so a board move is all it takes
C99	2.2 nF	U17/U12 area rail bypass	🔵	verify its role in the sch before final spot
R41	10k	U3/U16 I2C area	🔵	pull-up strap
R3 D1	120R · LED	P9 pins	🔵	R3 at the jack
R89 R90 R91	120R ×3	P10 pins	🟠	series at the jack — the wire radiates otherwise
D18 R102 R103	LED (green) · 1k ×2	3V3 rail, visible spot	🔵	power LED
TP6 TP7	GND · 3V3	anywhere reachable	🔵	probe access

Rail 100 nF rule, restated: every plain 100 nF above pairs with exactly one IC power pin and moves with that IC forever. If you relocate an IC during fine-tuning, its 🔴 rows move in the same drag.

§9Separation rules

Keep apart	Min	Why
GNSS island ↔ any switcher L / SW node	25 mm	−167 dBm receiver vs. dV/dt fields
GNSS RF run ↔ LTE RF run	opposite ends	desense is risk #1; antennas ≥ 20 cm at the enclosure
Any crystal ↔ any inductor	10 mm	magnetic pickup into the oscillator
ADC sense traces ↔ SW nodes	5 mm + ground between	tntc/vbat readings ride on µV
USB pairs (J9/J11) ↔ switchers	route as 90 Ω pairs, short	eye + radiated emissions
U26 accel ↔ mounting hole	≤ 10 mm (close!)	chassis coupling, not board flex

§10Order of work from here

Update PCB from Schematic (NTC2 re-net), then fine-tune inside the §1 regions. Field wiring now enters mostly along the north edge + P1 at the SE corner — keep each connector beside its block, and its TVS/filter parts right at the jack, so cable common-mode currents stay off the board core.
Say the word and I re-add the four zones — F.Cu GND pour, In1 GND (unbroken, especially under both RF runs and the crystals), In2 3V3, B.Cu GND — plus a stitching-via plan: 5 mm grid around RF, via fence along the board edge.
Route in this order: ① both 50 Ω RF runs (CPWG on F.Cu over In1, JLC7628 ≈ 0.35/0.25 mm — confirm in the JLC calculator and order controlled impedance) · ② the two hot loops and VBAT ≥ 3 mm · ③ /SW_BAT ≥ 2 mm + /BAT_PLUS ≥ 1.5 mm with via farms · ④ USB and ETH pairs · ⑤ sense lines · ⑥ everything else.
Refill zones, full DRC, then the G2 external review checkpoint before ordering.
Bench items carried forward: measure U21's 3V3_GNSS rise (F9P ramp window), verify U25's EP against the TI DDA drawing, and the DzG1 jumper check on the fabbed v5.5 boards.

EinarBoard HBOX v6 · Helgen · updated 05-Sep-2026: U18 V_BCKP (pin 36, /3V3) gets Cu4; C123 clarified as U21-output cap; §8 rows corrected.