EinarBoard 1.1 design brief: locked decisions (RS-485+RS-232 via SC16IS752, on-board W5500 Ethernet, RGB status LED, board growth) + execution phases
Keystone: gauge moves to PCF8574 on I2C1 -> frees SPI2 for W5500; SC16IS752 dual-UART bridge on I2C gives RS-485 (Modbus RTU) + RS-232/TTL with zero MCU pins. New 3V3_ETH rail from SYS5V (survives stack power-cycles). Carry-over errata state + depop list + phases A-E. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
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title: EinarBoard 1.1 — Design Brief & Execution Prompt
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tags: [project-drogheda, hardware, einarboard, respin, ethernet, rs485, design-brief, prompt]
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project: Project Drogheda
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author: Helgen CTO + Claude (decisions locked 2026-07-24)
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date: 2026-07-24
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status: Active — THE prompt for the 1.1 design sessions. Read this first, then execute the phases in §9.
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authority: supplements [[watchdog-electrical-design-state]] (canonical) + [[watchdog-production-schematic-delta]]; where they conflict on 1.1 scope, THIS file wins.
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---
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# EinarBoard 1.1 — Design Brief ("the prompt")
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> **How to use this doc.** This is the self-contained instruction set for turning
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> `hbox-watchdog-v3-PROD` (EinarBoard 1.0, as-fabbed, errata E-J1/E-CLR/E-PFI) into
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> **EinarBoard 1.1**. A design session (human or Claude) should be able to start from this
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> file alone. Standing rules: **file-level KiCad edits only** (the KiCad MCP backend
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> corrupted disk state on 2026-07-24 — see [[drogheda-respin-status]]); git checkpoint
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> after every phase; verify every structural edit with an independent parse; bench gates
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> unchanged (nothing fabs without the LTC4040 backup + charge-cutoff validation).
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## 0. Decisions locked 2026-07-24 (Leo)
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| Topic | Decision |
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|---|---|
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| Customer external comms | **RS-485/Modbus RTU AND RS-232/TTL** — one SC16IS752 dual-UART bridge serves both |
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| Ethernet | **On-board W5500 + MagJack**, hardware TCP/IP, SPI2 |
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| External indicators | **1 RGB status LED** (color-coded states), expander-driven |
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| Board outline | **Grow as needed**; ASA case/plate reprinted around the new outline |
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Bench context driving this: board 1.0 is alive on the bench via the external J1 inverter
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adapter; battery-gauge LEDs dark = **firmware** (v2.3 never drives PB12–15 — review F3),
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fan off on a cool bench = **correct** (curve starts 45–48 °C). Neither is a 1.0 hardware bug.
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## 1. The keystone architectural move (read this before touching anything)
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The F411 has no third USART, no CAN, no Ethernet MAC, and as-built the board has ~6 free
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GPIO. Everything new hangs off two buses we already have:
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**Move the battery gauge (PB12–15) to an I²C GPIO expander → SPI2 is freed → W5500
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Ethernet rides SPI2 → customer serial rides the I²C bus via SC16IS752 → RGB LED rides the
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expander.** Net result: all features land AND the free-pin count *increases*.
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Pin plan after 1.1:
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| Pin | 1.0 use | 1.1 use |
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|---|---|---|
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| PB12 | BATLED1 | **W5500 SPI2 CS** |
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| PB13/14/15 | BATLED2–4 | **W5500 SPI2 SCK/MISO/MOSI** |
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| PA15 (free) | — | **W5500 RSTn** |
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| PB2 (free) | — | **W5500 INTn** (BOOT1: irrelevant with BOOT0=0; do not strap) |
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| PB8 (free) | — | **SC16IS752 IRQn** |
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| PA7, PB9, PB10, PC14, PC15 | free/DNP | still free (reserve; PB10 keeps DNP tach provision) |
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| BATLED1–4, RGB | PB12–15 / n/a | **PCF8574 P0–P3 (gauge), P4–P6 (RGB), P7 spare** |
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I²C1 (PB6/PB7, 4.7 k pull-ups) roster: SHT40 **0x44**, TMP102 **0x48**, PCF8574 **0x20**,
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SC16IS752 **strap A1/A0 AWAY from 0x48 — e.g. 0x4C/0x4D** (its address range 0x48–0x57
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collides with the TMP102; this WILL bite if left at default). 4 devices @100 kHz is fine;
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drop pull-ups to 2.2 k only if rise-time says so on the bench.
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## 2. Carry-over fixes from 1.0 (state as of git `19c15e2`)
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- **E-J1 (socket mirrored)** — pads renumbered end-for-end at file level, verified twice
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(module landing map 20/20; backend pad read). Footprint id deliberately renamed
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`Drogheda:PinSocket_1x20_P2.54mm_Vertical_RevNum_EJ1` (library-update can't revert;
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"not found in library" warning is expected — save it into a project `.pretty` in Phase A).
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**Pending:** re-route the 11 ripped signal nets (channel between the socket rows);
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**regenerate the J1 silkscreen net-name labels** — the current text row describes the OLD
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mapping (this is why the fix "looks not flipped" in the editor — trust pad numbers, not silk).
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- **E-CLR (24 V clearance, 23-Jul dead unit)** — netclass `HV24` (0.5 mm) assigned to
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`/24V_IN, 24V, IGN_IN, Q10_GATE`. **Pending:** DRC → re-route the flagged 24 V spots,
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prefer outer layers for 24 V copper. **Decision needed:** pre-existing `PWR_HI/PWR_MID`
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netclass patterns lack the `/` prefix and likely never matched (5 V nets have been on
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Default rules all along — plausibly related to how 1.0 shipped with 0.2 mm gaps). Fix the
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patterns in Phase A and absorb the new DRC flags, or consciously leave them.
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- **E-PFI** — R51 287k→270k DONE (trip 4.40 V falling; bench-proven need). Source 270k 1% 0603.
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- **Pending small:** 220 µF/10 V elco on VEH5V near P2/RS (modem-inrush bulk);
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silkscreen sweep (USB→ arrow + pin-1 dots on J1/J2, P11 `1=MAIN5V IN / 2=SYS5V OUT`,
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P2 `5V VEH IN`, J1 label row regenerated); P11 ships with jumper plug.
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- **Field/bench rules (no board change):** bench modem work at 5.2–5.4 V in or with pack
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connected; install SOP trims SD-15B-05 to ~5.2 V.
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## 3. NEW Block M — customer serial (SC16IS752 + RS-485 + RS-232)
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- **U10 SC16IS752** (I²C mode, addr per §1; XTAL 1.8432 MHz + 2×22 pF → standard bauds to
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115200; IRQn → PB8, 10 k pull-up).
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- **Channel A → RS-485 half-duplex:** SP3485/MAX3485-class transceiver, **auto-direction via
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the SC16IS752's RS-485 RTS mode** (no GPIO). A/B/GND on a 3-pos Phoenix; 120 Ω termination
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behind a jumper (DNP default); optional bias resistors (DNP). Add an **isolated-transceiver
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DNP alternative** (ISO3082-class footprint overlay) — decide once the customer says how far
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off-cabinet the bus runs.
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- **Channel B → RS-232:** MAX3232 + caps, TX/RX/GND on a 3-pos Phoenix; a 4-pin 2.54 mm TTL
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header (3V3 levels) in parallel behind solder jumpers — covers the "plain TTL UART" ask.
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- Firmware (v3.1): SC16IS752 driver + **Modbus RTU slave** exposing the telemetry registers
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(state, link, fix, sats, vbat, v5v, temps, charge status, fault flags, uptime, fw version —
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formal register map to be agreed with the customer, draft it in Phase A notes) + optional
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NMEA-out mode on either channel.
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## 4. NEW Block N — Ethernet (W5500 + MagJack)
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- **U11 W5500** (QFN48): SPI2 @ ≤25 MHz (PB13 SCK / PB14 MISO / PB15 MOSI / PB12 CS),
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RSTn → PA15, INTn → PB2. 25 MHz crystal + load caps, per-datasheet decoupling, 12.4 k RSET.
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- **J10 MagJack** HR911105A-class (integrated magnetics + LEDs) on a case-reachable edge.
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**Layout rules:** no copper pour under the magnetics area; keep the TX/RX pairs short,
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matched-ish, away from the switchers; W5500 + jack in their own corner, far from P3/GNSS RF
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and the SW nodes (existing §8 RF rule stands).
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- **Power: NEW 3V3_ETH rail** — reuse the proven Block-K MP1584 recipe (U12, FB 100k/31.6k),
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fed from **SYS5V** — explicitly NOT `3V3_MODEM` (Ethernet must survive stack power-cycles:
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it is the watchdog's reporting path during recovery) and NOT the Blackpill LDO (W5500
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~132 mA would cook the module regulator's budget). Budget 500 mA.
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- Firmware (v3.2): W5500 socket driver (8 hw sockets); transports in priority order —
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(1) $PHLG/telemetry + STREAM mirror to the htracker backend over TCP, (2) tracker-feed
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mirror using the existing Modo-B PA10 tap, (3) **NTRIP-over-Ethernet client** (fixed
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LAN-connected sites run RTK with NO 4G — a real product unlock for warehouse/port installs),
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(4) Modbus TCP for the customer if they land on Ethernet later.
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- Power/current sanity: +132 mA (W5500) +5 mA (M/O blocks) on 5 V side ≈ +0.1 A at SYS5V —
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SD-15B-05 (3 A) and LTC4040 SYSLIM (3.1 A) both have headroom; battery backup runtime with
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Ethernet up ≈ 12 Ah / ~0.5 A ≈ 24 h — still ample.
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## 5. NEW Block O — expander + indicators
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- **U13 PCF8574 @0x20** on I²C1. LEDs wired **common-anode to 3V3, expander SINKS through
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resistors** (PCF8574 sinks 25 mA/pin, sources almost nothing — active-LOW outputs).
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- P0–P3 → BATLED1–4 (existing on-board gauge LEDs, rewired from PB12–15).
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- P4–P6 → **RGB status LED** on a 4-pos JST (**P14**, replaces/absorbs single-LED P8 — decide
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in Phase A whether P8 stays for backward compatibility): common-anode RGB, one enclosure
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hole. State map (v3.1 firmware): GREEN solid RTK-OK · GREEN blink searching/SPS ·
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YELLOW solid low-battery · YELLOW blink degraded/limp · RED solid fault
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(CHRG_FAULT/thermal/fan) · RED blink recovery cycling · BLUE boot. Exact table goes in the
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operator manual (es-MX) when firmware lands.
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- P7 spare output (future buzzer/4th LED).
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- Existing PB0 EXT_LED path stays as the hardwired fallback indicator (works even if I²C dies).
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- Firmware: gauge refresh ≤1 Hz over I²C is trivial; **power-on self-test walks gauge + RGB +
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spins the fan 2 s** (assembly-line visual check; kills the "is the fan dead?" ambiguity).
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## 6. Depopulation / cleanup (1.1)
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REMOVE outright: P3, P13, H3 (harness alternatives obsoleted by the carrier + Modo-B),
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stale J1 label row. KEEP: J7 USB path (modem config access), PB10 tach DNP provision,
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P10 external reset, P11 (with jumper plug), P12 NTC. DECIDE in Phase A: H1 SWD DNP 4-pad
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(add it this time — it costs nothing and 1.0 bring-up would have used it), P8 vs P14.
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## 7. Sourcing adds (LCSC pass in Phase E)
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W5500 · HR911105A MagJack · 25 MHz + 1.8432 MHz crystals · SC16IS752IPW · SP3485EN ·
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MAX3232 · PCF8574T · RGB LED (plus JST 4-pos) · MP1584EN #3 + FB/L/C set (Block-K clone) ·
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220 µF/10 V elco · 270k 1% 0603 (E-PFI) · isolated-RS485 DNP footprint part TBD.
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Availability check is part of Phase E, not assumed.
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## 8. Risks / open items
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- SC16IS752 vs TMP102 **address collision if left at default** (§1) — strap check is a
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Phase-D ERC-notes item.
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- Magjack footprint + keepout correctness (first Ethernet on a Helgen board) — copy a proven
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reference layout; DRC can't catch magnetics mistakes.
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- Modbus register map needs customer sign-off before v3.1 firmware freezes.
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- Flash/RAM: F411 (512 K/128 K) comfortably fits W5500 driver + Modbus + existing v2.3;
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revisit only if an RTOS enters the picture.
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- Case redesign (RJ45 + RGB + serial glands) rides the outline growth — coordinate with the
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ASA reprint; connector edge placement must be agreed BEFORE routing (Phase B gate).
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- Existing 1.0 boards: bench/pilot use via Leo's J1 inverter adapter (consider panelizing it
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as a rework PCB); 1.1 is the production article.
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## 9. Execution phases (each ends with git commit + parse-verify + snapshot)
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- **A. Schematic** — blocks M/N/O; gauge nets moved to expander; bulk cap; depop §6;
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PWR_* pattern decision; save the RevNum_EJ1 footprint into a project `.pretty`;
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ERC = 0. *(file-level edits + `kicad-cli sch erc` if available, else parse checks)*
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- **B. Outline & placement** — grow the board (target set by connector-edge plan + case),
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move/place new blocks (Ethernet corner rule §4), mounting holes, keepouts. **Gate: Leo
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approves the connector-edge plan before routing.**
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- **C. Routing** — J1 11-net re-route (inter-socket channel) · 24 V re-clear per HV24 ·
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new blocks · zones refill.
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- **D. Verify** — DRC/ERC clean (courtyard-cosmetics excepted), silkscreen sweep done,
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strap/address notes, visual SVG/PDF review pack for Leo.
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- **E. Outputs & sync** — gerbers/drill/pos/BOM, LCSC pass, delta-doc §-updates, PINOUT.md
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rewrite, errata page (E-J1/E-CLR/E-PFI closed in 1.1), firmware v3.0/3.1/3.2 tickets into
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the Notion tracker.
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*Firmware reminder (independent of the board): v3.0 scope in
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[[drogheda-firmware-v23-review]] §4 is unchanged and still blocks fleet flashing — the
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rollover fix and fan-tach fix don't wait for 1.1 silicon.*
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