v6 T4c: ERC fixes - RF_IN retyped passive, PF18 PWR_FLAG on SIM_VDD

Leo's ERC flagged exactly two errors after the T4 sync:
 1. U18 pin 2 RF_IN [Input] undriven - my hand-built ZED-F9P symbol typed the RF port as a
    logic input. RF ports are conventionally passive; retyped in Drogheda-sym AND the
    schematic's lib_symbols cache (1 substitution each, asserted). Its real connection
    arrives with the Block S bias tee in T6.
 2. U22 pin 1 VCC [Power input] undriven - SIM_VDD is fed by the modem's USIM1_VDD, whose
    EasyEDA pin type is not a power output. Idiomatic fix: PF18 PWR_FLAG on SIM_VDD,
    consistent with PF1-PF17.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt

03-Architecture-Hardware/kicad/Drogheda-sym.kicad_sym

@@ -1048,7 +1048,7 @@
           (effects (font (size 1.27 1.27)))
         )
       )
-      (pin input line
+      (pin passive line
         (at -33.02 7.62 0)
         (length 5.08)
         (name "RF_IN"