4b8bdf4916
Leo's ERC flagged exactly two errors after the T4 sync:
1. U18 pin 2 RF_IN [Input] undriven - my hand-built ZED-F9P symbol typed the RF port as a
logic input. RF ports are conventionally passive; retyped in Drogheda-sym AND the
schematic's lib_symbols cache (1 substitution each, asserted). Its real connection
arrives with the Block S bias tee in T6.
2. U22 pin 1 VCC [Power input] undriven - SIM_VDD is fed by the modem's USIM1_VDD, whose
EasyEDA pin type is not a power output. Idiomatic fix: PF18 PWR_FLAG on SIM_VDD,
consistent with PF1-PF17.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2235 lines
52 KiB
Plaintext
2235 lines
52 KiB
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(effects (font (size 1.27 1.27)))
|
|
)
|
|
)
|
|
(pin passive line
|
|
(at 12.7 0 180)
|
|
(length 5.08)
|
|
(name "NC8"
|
|
(effects (font (size 1.27 1.27)))
|
|
)
|
|
(number "8"
|
|
(effects (font (size 1.27 1.27)))
|
|
)
|
|
)
|
|
)
|
|
)
|
|
)
|