Leo's post-C12 DRC run left exactly one error:
[unconnected_items] Zone 'GND_POUR_FCU' [GND] on F.Cu <-> Zone 'GND_POUR_FCU' [GND] on F.Cu
KiCad prints only the zone anchor (60.1917, 40.3231) for both endpoints, so the
report cannot localise the stranded island. Located it analytically instead.
Root cause: U11 pad 9 [GND] @ (91.1275, 55.7600). It is the only GND item on the
board whose item-only connectivity cluster never reaches the In2.Cu GND plane
(two independent fill-independent proofs agree: layer-reach and In2-anchor). An
island survives KiCad's isolated-island removal only if some item props it up,
so pad 9 was propping up a GND_POUR_FCU island that touches nothing else.
island_removal_mode cannot fix that - it needs copper.
Pad 9 is fenced on all four sides (LQFP-48 lead ring, pad 8's westward /3V3_ETH
escape, pad 10's eastward /ETH_RSET escape, the /ETH_RXP chain under the body).
A 0.05mm grid router reached only 227 of 20883 legal cells and found no way to
touch existing GND copper without a via, so a through via is mandatory. A
0.005mm sweep of every legal via site in that pocket picked the best one on the
board's existing drill inventory - no third drill size added.
+ F.Cu GND track w0.3 (91.1275,55.7600) -> (90.1000,55.7600) -> (89.9950,55.8900)
+ F.Cu-B.Cu GND via 0.6/0.3 @ (89.9950,55.8900)
* U11 pad 9 -> (zone_connect 2)
Both track legs hold +0.2000mm clearance - the structural ceiling for a 0.3mm
track between 0.3mm leads on 0.5mm pitch. The via holds +0.1758mm copper and
+2.9705mm hole. The site sits inside GND_POUR_FCU, GND_POUR_BCU, P3V3_PLANE_IN1
and GND_PLANE_IN2 and outside MAGJACK_NO_POUR, with the nearest In2 signal
copper 1.10mm away, so the barrel lands on solid In2 GND plane.
zone_connect 2 mirrors the landed C12 treatment of pad 29: pads 8 and 10 each
knock 0.5mm of pour out around themselves, covering the whole pad-9 lane
(0.10mm tall < min_thickness 0.25), so the pour cannot reach pad 9 in any
connect mode. Solid mode removes the pad from the minimum-spoke test rather
than leaving a starved thermal behind.
Verified on the output file:
drc_c12.py 0 hard clearance violations, same 49 sub-epsilon marginals as C12
proof_c13.py 0 GND clusters without an In2 GND-plane anchor (was 1)
fcu_only.py 0 F.Cu-only GND clusters (was 1 = pad 9)
24V / /24V_IN / IGN_IN copper byte-identical (45 segments)
segments 1984->1986 vias 351->352 zones 5->5 footprints 189->189
Backup: .mcp-backups/hbox-watchdog-v4.kicad_pcb.pre-C13 (md5 042efd5d)
Pushed: md5 94d36711d60985eef109913fcee36b09, 3502885 bytes
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
E1 clearance 0.1433 < 0.15 (/LED_A via vs /I2C_SCL via, 4 raw reports)
Relocated the /LED_A via 202c8cb4 from (147.15,85.85) to (147.25,86.22),
dead centre of the U13.1/U13.2 gap. uuid preserved; both attached segment
endpoints carried (In1.Cu 375e8fa7, B.Cu dee4fa4e). Worst gap now +0.2405.
E2 unconnected_items x2 + starved_thermal x1 -- ONE root cause.
The F.Cu GND pour pocket around U11 pad 29 was an island: it touched the
pad with a single thermal spoke but was fenced in by the LQFP-48 lead ring
and the escape routing, so it reached nothing else. Gave pad 29 a real
copper escape west to a new GND via that punches through to the In2 GND
plane, and set the pad to solid zone connection so the 2-spoke thermal
rule stops applying to a pad the pour can only reach from one side.
seg F.Cu w0.3 GND (99.4525,55.26)->(98.65,55.26) margin +0.2000
seg F.Cu w0.3 GND (98.65,55.26)->(97.55,54.45) margin +0.2000
via 0.6/0.3 F.Cu-B.Cu GND @(97.55,54.45) copper +0.2718
U11 pad 29 -> (zone_connect 2)
+0.2000 is the structural ceiling for a 0.5mm-pitch lead escape with a
0.3 track, and matches the neighbouring /3V3_ETH and /ETH_XI escapes.
E3 via_dangling /3V3_ETH via 3b0bb378 @(87.18,55.23) connected on F.Cu only.
Deleted. Touch test: 4 touching F.Cu segments, zero on In1/In2/B.Cu. The
F.Cu run at x=87.18 is collinear and continuous without it.
Verified: static DRC 0 hard violations (49 pre-existing marginals inside
KiCad's 0.0005 epsilon, unchanged). Per-net islands unchanged at 1 for
/LED_A /3V3_ETH /I2C_SCL /ETH_XI /ETH_RSET. New via lands inside
GND_PLANE_IN2 + GND_POUR_BCU, outside MAGJACK_NO_POUR. U11 is a plain
LQFP-48 with no exposed pad, so the under-body via is clear. Leo's 24V-class
copper (24V /24V_IN IGN_IN, 45 segments) byte-identical.
Backup: .mcp-backups/hbox-watchdog-v4.kicad_pcb.pre-C12 (md5 7c2202cb)
New: md5 042efd5dd0cf99fdcfd27974b7bcb3c1 3502425 bytes
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Static-DRC battery (true pad geometry: circle/oval/roundrect/rect, NPTH as
hole-only) over 693 pads / 351 vias / 1982 segments -> 0 violations at the
project rule of 0.15mm min clearance, 0.25mm hole-to-hole.
Fixed:
[1] hole-to-hole -0.300 duplicate GND stitching via coincident at
(94.79,60.30) -- JLCPCB would have drilled the same hole twice. Removed.
[2] U11.13 (NC) +0.100 GND pad14 stub zigzag -> one straight lane x93.01
[3] U13.3 (GND) +0.130 I2C_SCL y=87.6 excursion -> single lane y=87.5277;
the GND stitcher the zigzag was dodging moved 0.138 north onto U13.2
pad copper (same uuid/net, still bonded to its track)
[4] ETH_LINKLED +0.130 3V3_ETH under-body via/rung -> y=57.455, the exact
centre of the only legal B.Cu window (RSET@56.89 / LINKLED@58.07);
165000nm both ways
[5] U11.17 +0.140 GND pad16 lane x94.14/94.15 -> single lane x94.10
[6][7] U11.46/47 +0.150 ETH_PMODE north lane y=49.31 -> 49.24
[8] stranded 1.5x1.5mm rule area (tracks/vias/pour not_allowed) nested in
U3's footprint but stranded ~22mm east of it with zero copper within
3mm -- a phantom no-route trap. Removed.
[9] stranded /3V3_ETH web on In2.Cu (the GND inner plane): orphaned remains
of the pad17 via removed in C10e, connected to nothing, punching a
clearance void in the GND plane. Removed.
Verified: paren balance 0; 188/188 footprints intact (only U3 shrinks, by the
nested rule area); top-level block census unchanged but segment 1992->1982 and
via 352->351; every touched net resolves to exactly ONE copper island
(/3V3_ETH went 2 -> 1); 24V-class hand-routed copper byte-identical
(24V 23 segs, /24V_IN 12 segs, IGN_IN 10 segs).
Pre-C11 board preserved at .mcp-backups/hbox-watchdog-v4.kicad_pcb.pre-C11
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- 54 of 90 free GND stitching vias aligned into rows/columns (axis equalize +
even spacing, move cap 2.0mm, largest 1.3mm); 8 track-connected free vias frozen
- every move clearance-validated (>=0.15mm to other-net copper, keepout excluded)
- +1 GND via at (92.25,59.8): W5500 AGND cluster (C93/C94/U11.14/16) was
pour-served only — now hard-bonded to the In2 plane
- silkscreen re-audit under new via field: 164 refs re-derived by the uniform
0.15mm-gap rule, 8 re-placed, 0 left unplaced
- verify: census 0 open nets, clearance-lite 0 hits <0.125mm
- NOTE: zone fills stale around moved vias — refill (B) in pcbnew
- C3: 22 detected component lines evened (edge-gap distribution between line
endpoints), 58 parts nudged; everything touched by the hand-routed 24V/IGN
tracks frozen (P1,Q10,D10,DzG1,C10,C11,C22,Rig1,Ren1,U2)
- C4: finer pass — pairs included (33 lines total, 17 more parts), 8 R/C
rotations normalized 180->0 / 270->90 (unpolarized only, pad angles kept
consistent), TOL 1.0mm
- IGN divider: Rigb1 10k -> 3.3k in sch+board (24V ign -> 3.13V at PA5, FT-pin
safe incl. 35V transients; was 7.5V, out of spec). Fleet rework note: same
swap recommended on the 10 EinarBoard 1.0 units
- Leo's 46 track segments byte-identical through both passes; 0 courtyard
conflicts; parens balanced
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- Column A (R94,R95,C97,C98,C95): x=83.9, even pitch 3.575 (y 54.2-68.5)
- Column B (R92,C92,C93,C94,R96): x=87.5, even pitch 3.175 (y 50.3-63.0;
top pulled below MH1 which R92 would have hit at Leo's y46.4)
- C102/C90/C91 row: even x pitch (92.2 / 95.85 / 99.5 at y63.9)
- Serial column (C82,C83,R82,JP5): x=72.5, even pitch 4.4; Y2 centered on
the U10/U15 column (x=72); C85-C87 even pitch 2.4
- C96 kept at Leo's spot (Y1-centerline slot blocked by Y1/Rig1 courtyards)
- Verified: 0 pairwise courtyard conflicts
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- All footprint origins snapped to 0.1mm; 37 near-aligned row/column members
equalized (same-prefix groups within 0.35mm)
- ALL tracks erased for the clean re-route: 1100 segments + 237 vias removed;
zones kept (GND pour definitions + MAGJACK_NO_POUR rule area)
- Verified on Leo's B6 placement: 0 courtyard conflicts, nothing outside the
outline, parens balanced
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- MOD1 shifted +25mm east of B4: its silkscreen outline (module body incl.
USB/SMA overhangs, 24.16mm west of the pad hull) now lands 0.8mm inside the
left board edge — connectors overhang the front as intended; pad hull
x85.5-131.8. U10 no longer displaced (module clears its Phase B spot)
- SW4G1 (4G NTRIP reset) moved beside the XBee sockets J7/J8 at (188,98.8),
2 stale stubs ripped; frees the bottom-edge strip x143-153
- P15/P16 dropped 0.7mm (origin y133.1) so their bodies clear the module's
bottom pad row; entry faces overhang the edge 1.3mm
- C103 clear of the module top pad row at (88,75.4)
- Verified: 0 pairwise courtyard conflicts; module's 32 pad holes clear of
all courtyards/pads; silk min-x 61.03 vs edge 60.19
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
J1/J2 are the STM32 Blackpill sockets, not the GNSS module; B2/B3 moved the
wrong part. This rebuilds from the Phase B baseline (0af0373):
- Blackpill J1/J2 back at original position/rotation with v3 routing intact
- MOD1 (ArduSimple simpleRTK2B Pro, the 10/8/6/8 socket pattern) moved 44.8mm
left: hull now x60.5-106.8, west edge 0.3mm from the board edge; 18 stale
pad stubs ripped for re-route
- P15/P16 into the bottom-edge window MOD1 vacated; U10 tucked between the
module rows (1.2mm TSSOP under ~8.5mm standoff); C103 clear of the top row
- ANT_CORRIDOR keepout retired (module owns the front-left; antenna exits there)
- 3D model vars repointed KICAD6/7 -> KICAD10 (58 refs)
- Verified: 0 pairwise courtyard conflicts; MOD1's 32 pad holes individually
checked clear of all courtyards and pads
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- J1/J2 rotated to vertical rows: J2 (outer) x63.77, J1 (inner) x78.77,
y52.8-101.1 — module hugs the front edge full-length, USB end (J1 pad20
/SYS5V) at the top-front corner; antenna exits directly at the front
- Front edge cleared: P15 (RS-485) -> top edge between MH5/MH1, P16 (RS-232)
-> bottom edge west of the modem pad row, H4 TTL -> top strip next to P5
- RJ45 kept at the bottom-left of the front edge (no other edge window fits
a 19x22.3mm magjack) with the no-pour zone moved under it
- Serial cluster re-laid east of the module; W5500 satellites auto-placed
by greedy collision-free placer; 0 pairwise courtyard conflicts (190 fp)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- J1/J2 socket pair translated -43.43mm: rows now x62.0-113.8, USB end
(J1 pad20 /SYS5V) at the left board edge; 49 stale J1/J2 pad stubs ripped
- Ethernet corner rebuilt lower-left: RJ45 J10 on left edge y106-125 inside
relocated MAGJACK_NO_POUR zone, W5500+25MHz+terminations below the serial
stack, clear of the existing R5/R6/R7/D1/C5/C7 LED cluster
- ANT_CORRIDOR_KEEPOUT retired (antenna now exits at the module end itself)
- Rig1 nudged below Rigb1 (was inside J2's new courtyard band), stub ripped
- 3D models: 58 legacy KICAD6/KICAD7 3DMODEL_DIR refs repointed at
KICAD10_3DMODEL_DIR so new parts render in the 3D viewer
- Verified: 190 footprints, 0 pairwise courtyard conflicts, parens balanced
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- Outline left edge 80.19->60.19; MH5/MH6 mounting holes cloned to new corners
- Antenna corridor keepout front-left (notched around MH6) + magjack no-pour/no-via zone
- RJ45 J10 + RS-485 P15 + RS-232 P16 on new left edge behind antenna corridor
- W5500 U11 + 25MHz + terminations between jack and P5; 3V3_ETH buck U12/L8/D11
in the freed P13/H3 gap under the module (low-profile), bulk caps at load
- SC16IS752 U10 serial cluster behind P15/P16; MAX3232 U15, SP3485 U14
- PCF8574 U13 clear of MOD1 pad ring; RGB JST P14 on right edge (freed P3 slot)
- H4 TTL header moved to front edge (was under module, on D5)
- 24V entry block relocated beside P1 (Q10/C10 in P12 lane, D10/DzG1/Rrp1 pocket);
old cross-board 24V routing ripped for HV24 re-route
- P3/P13/H3 depopulated; J1/J2/DB pad nets updated (ETH SPI, SER_IRQ, LED flip)
- Fix Phase A miss: SC16IS752 pins 13/14 (I2C SCL/SDA) now wired in sch + board
- Placement verified: 190 footprints, 0 courtyard conflicts, 0 corridor intrusions,
all new nets 2-ended (verify_phase_b.py)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
v4 = the live 1.1/Phase-A design (J1 renumbered, blocks M/N/O, HV24, PFI 4.40V). v3-PROD trio = exact as-fabbed state from 9892279 (mirrored J1 as the bench/fleet boards physically are) - do not edit. dru/prl carried to v4. Off-grid warning backlog stays visible-but-muted; real geometry sweep slated for Phase D.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
