Commit Graph

2 Commits

Author SHA1 Message Date
Claude (Cowork)
8be9f41473 v6 T3a: ZED-F9P + generic SOT-23-5 LDO symbols added to Drogheda-sym
ZED-F9P: all 54 pins, numbers 1-54 complete and unique, transcribed from the u-blox
datasheet Table 11 (ZED-F9P-15B_DataSheet_UBX-23009090). Left column = power/RF/antenna
(17), right = interfaces/control/status (16), bottom = the 21 reserved pins. Body 55.88 x
50.8 mm. LCSC C5120257 carried as a property.

FINDING that changes Block N: the ZED-F9P HAS hardware status outputs - RTK_STAT (pin 20)
and GEOFENCE_STAT (pin 19). RTK_STAT: 0 = RTK fixed, blinking = receiving and using
corrections, 1 = no corrections. That is a HARDWARE answer to the question the June and
10-Ago RCAs could not answer. Wire RTK_STAT to PC3. (Earlier note implying only the UM980
had such pins was wrong.) ANT_OFF (pin 5) also exists.

LDO_SOT23-5: generic AP2112K / TPS7A20 pinout (1=VIN 2=GND 3=EN 4=NC/NR 5=VOUT) so U21
can be any SOT-23-5 low-noise LDO without a symbol change.

OPEN - blocks the PCB side of T3, not the schematic:
 * No ZED-F9P FOOTPRINT exists. Not in the project libs, not derivable from the datasheet
   (no land pattern) and the integration manual's drawings do not survive PDF text
   extraction. EasyEDA/LCSC is blocked by the egress allowlist from here.
   Fix: run locally -> pip install easyeda2kicad && easyeda2kicad --full --lcsc_id=C5120257
 * PRE-FAB CHECK: confirm the -04B datasheet carries the SAME pin assignment as the -15B.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-08-24 23:12:28 +00:00
2c3dffa232 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger
Electrical/PCB:
- LTC4040 Block B sized to the 12 Ah 1S4P pack (RPROG 825R -> 2.42 A ~ C/5,
  RS 8 mR -> 3.1 A input limit, PFI 4.60 V, backup 4.79 V, charge 4.00 V Li-ion
  via VSYS-referenced straps) + Block E cutoff (P11) + Block F PA4->VEH5V re-tap
  + Block H fail-safe Modo-B bypass (K1 normally-closed relay) + Block I NTC->PB1.
- CARRIER-BOARD conversion: simpleRTK2B Pro on UNO-pattern female headers (MOD1;
  D0/D1=UART1, D2=RX2, D8=TX2, IOREF=3V3, 5V=SW_5V) + 4G NTRIP Master on on-board
  XBee socket (J7/J8; VCC=3V3_MODEM via new Block K MP1584 buck off SW_5V - the
  HP XBee socket is 3.3 V not 5 V). Board 120x100, placement + GND pour + DRC
  baselines. Custom symbols: LTC4040EUFD, AO4406A, SimpleRTK2B_Pro_Socket.
- Fixed duplicated U2, stale no-connects, A4->A3 sheet; ERC 0 errors.

Docs:
- Canonical electrical-design-state + production delta (Block B values table,
  5b/5c/5d/5e) + design/rationale/connections/BOM swept to the Jul-2 assumptions
  ledger (Conexiones-por-Bloque xlsx).
- Guia de Conexion Protoboard: LaTeX source now maintained in-repo -> v2.1 PDF.
- CircuiTikZ sheet + wiring Beamer: block 11 (NTC->PB1) + guinda ignition legend.
- Client decks: Avance v1.1 (overclaims fixed) + RCA v1.1 (2-jul addendum).

Repo hygiene:
- .gitignore: live rtk-config (SIM/APN/NTRIP creds) now ignored and REMOVED from
  tracking (NOTE: rotate those credentials - they exist in prior commits);
  KiCad .bak/snapshots/.history, LaTeX intermediates, Office locks ignored+purged.
- Removed rogue .history gitlinks that broke git status.
2026-07-02 22:18:56 -06:00