61 lines
3.8 KiB
Markdown
61 lines
3.8 KiB
Markdown
# EinarBoard 3.0 — Capacitor Placement Map (v1.0, 2026-08-14)
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> Generated from the v5 netlist + v4 ownership. Rule: **every 100 nF lives ≤2 mm from the pin
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> it serves, same side of the board.** Crystal caps ≤2 mm of crystal AND chip. Bulk (≥1 µF)
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> gets 5–10 mm of slack. Place each cluster as a unit around its owner, then align/distribute.
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## U16 — STM32F411 (the big cluster)
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| Cap | Value | Where |
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|---|---|---|
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| C105, C106, C107, C108 | 100 nF | one per **VDD pin** — four corners of the chip, ≤2 mm |
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| C111 | 4.7 µF | **VCAP1 (pin 30)** — ≤2 mm, short fat trace. Not decoupling; mandatory core cap |
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| C109 + C112 | 100 nF + 1 µF | **VDDA pin** — ≤3 mm, next to R104 (10R) |
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| C104 | 100 nF | **NRST pin** — ≤3 mm |
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| C110 | 4.7 µF | bulk — anywhere ≤5 mm from the chip |
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## Y3 / Y4 — MCU crystals (tight sub-clusters beside U16)
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- **Y3 (25 MHz) + C113 + C114 (15 pF)** — crystal ≤5 mm from PH0/PH1 pins, caps ≤2 mm of the crystal, caps' GND short.
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- **Y4 (32.768 kHz) + C115 + C116 (12 pF)** — same treatment at PC14/PC15.
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## U17 — AMS1117 LDO
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- **C117 (10 µF)** at the input pin, **C118 (22 µF) at the output — stability cap, the LDO oscillates without it.** Both ≤3 mm. D12/D13 (OR diodes) complete this cluster on the input side.
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## U11 — W5500 (second-biggest cluster)
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| Cap | Value | Where |
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|---|---|---|
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| C92, C93, C98 | 100 nF | one per **VDD pin**, ≤2 mm (C98 belongs here — it only *sat* near Y1 in v4) |
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| C91 | 10 nF | **1V2O pin** — ≤2 mm |
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| C90 | 4.7 µF | **TOCAP pin** — ≤2 mm |
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| C95, C96 | 18 pF | **Y1 crystal caps** — with Y1, ≤2 mm |
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| C94 + C102 | 10 µF + 22 µF | rail bulk — ≤10 mm |
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- **Y1 (25 MHz)** itself: ≤5 mm from the W5500's XI/XO pins — this is the crystal that must NOT live far from U11.
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- **C97 (6.8 nF)** — MagJack RCT termination: between U11 and J10, near the magnetics side.
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## Y2 — SC16IS752 crystal (with U10)
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- **Y2 (1.8432 MHz) + C82 + C83 (22 pF)** — ≤5 mm from U10's XTAL pins, caps ≤2 mm of Y2.
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## U10 / U14 / U15 — serial bridge cluster
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- **C81, C84, C89 (100 nF)** — one each hugging U10, U14, U15 power pins.
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- **C85, C86, C87, C88 (100 nF)** — the **MAX3232 charge-pump caps**: functional, not decoupling — all four ≤3 mm around U15 exactly as its datasheet drawing shows.
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- **C30 (10 µF)** — cluster bulk, ≤10 mm.
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## Sensors & expander
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- **Cu3 (100 nF)** → U3 SHT40. **Cu4 (100 nF)** → U4 TMP102. Each at its chip.
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- **C80 (100 nF)** → U13 PCF8574.
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- **C34 (10 µF), C35/C40 (22 µF), C103 (100 µF), C43 (100 µF)** — area bulk (sensor/modem/expander rails) — flexible, ≤10 mm of their load clusters.
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## Bucks (each is a self-contained island — keep each group TIGHT)
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- **U2 fan buck:** Cbst1 (BST pin), Ccomp1 (COMP pin), C22 (output bulk), + its L/diode. The switch-node loop must be small.
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- **U7 modem buck:** Cbst2, C41, + L/diode — same rule.
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- **U12 ETH buck (if it survives the L8 decision):** C100 (SW snubber/BST), C99 + Ccomp2 (COMP network), C101 (output bulk), L8 — one tight island.
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## ADC input filters (belong with their DIVIDERS, not the MCU)
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- **C5** → BAT_SENSE divider resistors · **C7** → 5V_SENSE divider · **C9** → IGN_SENSE (with Rig/D5 clamp) · **C24** → NTC divider (R42) — each cap sits with its resistor pair; the filtered node then runs to U16.
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## Power entry / rail bulk (flexible placement, near the entry connectors)
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- **C10 (47 µF/50 V)** → 24 V input at Q10. **C3, C78 (220 µF!), C23, C31, C32, C33 (47 µF ×2)** → MAIN5V/VEH5V/SYS5V/LTC4040 rail bulk — near P2/P11/U6 power path; C78 is the modem-inrush bulk near P2/RS per the 1.1 fix.
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- **C11 (100 nF)** → K1 relay coil area.
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## USB ports
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- J11 (DFU): R100/R101 + D14–D16 TVS right at the connector. J9 (modem): Rcc1/Rcc2 likewise.
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