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Drogheda/03-Architecture-Hardware/2026-09-28_v6-audit-attachments/FHJ_layout_bom_ercdrc.md

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F (Layout/EMC) + H (BOM/JLC) + J (ERC/DRC) — v6 audit findings

!!! warning "Designators from before 22-Oct (T43)" This document keeps the designators the board had on its date. Since 22-Oct (T43) the V5.6, V5.7 and v6 carry new ones, and several old names now belong to another part: on the v6, U6 is now the A7670SA modem (was U19) and the LTC4040 is U17 (was U6). To read it against today's board, use the old → new table (in Spanish); parts already gone by 22-Oct are not in it. Snapshot: sch ecee9fed… / pcb 6ddec80d… (evidence pack 2026-09-28)

Sources read

  • Brief: findings/_COMMON_BRIEF.md; master brief §3–§5, §4-F/H/J; INDEX.md; evidence/MANIFEST.md; prior review docs/2026-09-28_…Review-vs-V5.5-Lessons_v1.0.md (§1–§4); pre-fab audit docs/project/claude__2026-09-25_HBox-v6_Pre-Fab-Audit_EN.md; ECO docs/2026-09-27_…V5.6_ECO_ES_v1.0.md (§0, §E, §G); Copper Plan docs/2026-09-02_…v6-Copper-Plan_Placement-EMC-Guide.html (§2–§9).
  • Memory: drogheda-einarboard-short-incident, drogheda-einarboard-v5-audit (V5.5 EMC list; 165 GND vias), drogheda-v6-lte-island (RF/PWR_MODEM netclasses once existed; ESD9L on RF), drogheda-v6-resync-protocol (02-Sep copper wipe → hand layout; GUI saves wipe netclasses), preferences.
  • Evidence: stackup.md, zones.csv, clearance_24v.md/.csv, net_routing_summary.csv, pcb_footprints/pads/tracks.csv, vias.csv, drc_summary.md, drc_items.csv, erc_summary.md, erc_full.json, sch_pcb_sync.md, bom.csv, components.csv, cpl.csv, ref_versions/v56_components.csv, mcp/courtyard_overlaps_mcp.json, outline_and_holes.md, dangling_track_ends.csv, v6-pcb-layers.pdf (viewed).
  • Other block files read to avoid double counting: findings/A_power.md (A-01, A-02, A-06, A-09, A-14, A-15), findings/DG_mcu_connectors.md (D-02, D-03, D-06, D-11, D-16, G-02, G-03, G-05).
  • Own computation (shapely, parsed from src/hbox-watchdog-v6.kicad_pcb with scripts/parse_pcb.py; scratch in work/FHJ/): plane.py/voids.py/crossings2.py (plane coverage under every track), hv24.py (0.5 mm re-check with corrected classes → work/FHJ/hv24_violations_corrected_rule.csv), bucks.py/geodesic.py/islands.py (loops, EP vias, F.Cu GND pieces), stitch.py, xtal.py, esd.py, crt.py, classify.py, bomcheck.py. Renders: work/FHJ/in1_full.png, rf_lte.png, rf_gnss.png, u20.png, u25.png, fcu_gnd_pieces.png.
  • JLC: get_jlcpcb_part on all 121 BOM LCSC numbers + 10 alternates (local DB snapshot, 2026-09-28); search_jlcpcb_parts for MAX3232, SC16IS752, 499 k, PMEG6030EP. Web: KiCad forum (rule precedence, dev JeffYoung: "custom rules are appended after [netclass rules] so have higher priority"); JLCPCB capabilities page (4-layer: 0.09/0.09 mm track/space, via 0.15/0.25 mm, PTH ring ≥ 0.15 (0.20 rec.), hole-hole 0.45 mm, PTH-track 0.28 mm, silk ≥ 0.15 mm line / 1.0 mm text); Sunlord MWSA series spec (alfatec mirror) for MWSA0804S dimensions.

Deliverables alongside this file: findings/bom_check.csv (152 BOM lines), findings/ercdrc_classified.csv (166 ERC + 283 DRC items, each classified).

Findings

F-01 Netclass assignment is broken and one custom rule overrides every clearance: the DRC "0 errors" cannot see any 24 V spacing

  • Severity: Blocker

  • Block / refs: §4-F item 1, §4-J; lesson 23-Jul inner-layer short (drogheda-einarboard-short-incident, action "next rev: 24V-to-LV clearance rule ≥ 0.5–1 mm (netclass)"); drogheda-v6-resync-protocol §5 (GUI saves wiped RF/PWR_MODEM classes); pre-fab audit §6.

  • Evidence:

    • .kicad_pro patterns (stackup.md §4.1): HV24 = /24V_IN, 24V, IGN_IN, Q10_GATE. KiCad matches the full name including the leading /, so only /24V_IN resolves (netlist class attribute). /24V, /IGN_IN, /Q10_GATE, /VIN_FUSED, /VIN_PROT, /VIN_MODEM, /Q23_GATE and the five 24 V switch/boot nodes are Default; /SW_FAN is PWR_MID. Dead patterns: 24V, IGN_IN, Q10_GATE, all un-prefixed PWR_* duplicates, /3V3_MODEM, 3V3_MODEM, /SW3_NODE, SW3_NODE (V5 nets). RF and PWR_MODEM classes are missing.
    • .kicad_dru rule "Minimum clearance 1" = 0.15 mm, condition A.NetClass != 'HV24' && B.NetClass != 'HV24', no layer or type qualifier. In KiCad 10 the netclass clearances and the zone "Clearance" field are implicit rules; custom rules are evaluated after them and a matching custom rule wins; only the board minimum (0.0 mm here) is a floor. So this rule overrides Default 0.2 mm, PWR_HI/PWR_MID 0.2 mm, the zone's own 0.3 mm, and would override any future RF class.
    • Proof in the stored fills: in the same GND zones, the gap to /24V_IN (HV24) is 0.5005 mm, and to every other net 0.1505 mm (clearance_24v.md), although each zone's clearance field is 0.3 mm. DRC reports 0 clearance items.
    • With the stale 0.15 mm rule deleted and Default left at 0.2 mm, 471 item pairs (209 net pairs) at 0.15–0.20 mm would fail (F.Cu 400, In1 33, In2 27, B.Cu 11). The layout was drawn to 0.15 mm, so the floor must stay 0.15 mm, set explicitly.

  • Justification of the number (IPC-2221B Table 6-1): the vehicle rail peaks at the D10/D32 clamp, VC = 53.3 V @ 11.3 A (SMBJ33A/SMCJ33A, JLC C224019/C699039), and ISO 16750-2 suppressed load dump for 24 V systems is 58 V. That puts the design in the 51–100 V row: B1 internal 0.10 mm, B4 external with permanent polymer coating (solder mask) 0.13 mm, A6 external uncoated component lead 0.13 mm (B2 bare external 0.6 mm does not apply under mask). So today's 0.15 mm already meets IPC dielectric spacing. The 0.5 mm inner-layer value is a defect/CAF margin, chosen because Leo lost a board to a suspected inner-layer bridge at 0.20–0.25 mm. Inner layers cannot be inspected or cleaned, and they sit under 24 V bias at 45 °C in humid ports. On outer layers under mask, 0.3 mm (2.3× IPC) is enough and fits the SO-8 pin rows.

  • Consequence: DRC cannot flag a repeat of the 23-Jul geometry. F-02 is exactly that, and it passed DRC with 0 errors.

  • Fix (project + rules; no copper change by itself):

    Class Patterns (exact names, one per line) Clearance Track Via Notes
    HV24 /24V_IN /VIN_FUSED /VIN_PROT /24V /VIN_MODEM /IGN_IN /Q10_GATE /Q23_GATE /SW_PWRIN /BOOT_PWRIN /SW_FAN /BST_FAN /SW_MODEM /BST_MODEM 0.5 (inner and outer set by DRU) 1.0 0.8/0.4 /SW_FAN leaves PWR_MID. /EN_FAN and /EN_PWRIN stay Default (≤ 10 V, high-impedance)
    PWR_HI /BAT_PLUS /SW_BAT /MAIN5V /VEH5V /SYS5V /VIN_SW 0.15 1.5 0.8/0.4 delete the un-prefixed duplicates
    PWR_MID /SW_5V /SW_IN /5V_FAN /FAN_RET 0.15 0.6 0.8/0.4 move /3V3_ETH to Default (0.15 A, see J-02)
    PWR_MODEM /VBAT_MODEM 0.15 1.5 0.8/0.4 re-create (was in T6)
    RF /RF_GNSS /RF_ANT_GNSS /RF_LTE /RF_ANT_LTE CPWG gap from F-06 CPWG width from F-06 none re-create
    Default everything else 0.15 0.2 0.6/0.3 set explicitly (today 0.2 in the class, 0.15 via the DRU)

    .kicad_dru (replace "Minimum clearance 1", "HV24 clearance" and "HV24 exception"; later rules win):

    (rule "Floor 0.15 (non-HV24, non-RF)"
  (condition "A.NetClass != 'HV24' && B.NetClass != 'HV24' && A.NetClass != 'RF' && B.NetClass != 'RF'")
  (constraint clearance (min 0.15mm)))
(rule "HV24 outer"
  (layer outer)
  (condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
  (constraint clearance (min 0.3mm)))
(rule "HV24 inner"
  (layer inner)
  (condition "A.NetClass == 'HV24' && B.NetClass != 'HV24'")
  (constraint clearance (min 0.5mm)))
(rule "HV24 IC land patterns"
  (layer outer)
  (condition "A.Type == 'Pad' && B.Type == 'Pad' && ((A.memberOfFootprint('U2') && B.memberOfFootprint('U2')) || (A.memberOfFootprint('U20') && B.memberOfFootprint('U20')) || (A.memberOfFootprint('U25') && B.memberOfFootprint('U25')))")
  (constraint clearance (min 0.15mm)))

    Then refill all zones and re-run DRC. Expected result: the 6 inner and 15 outer spots of F-02/F-15 (full list in work/FHJ/hv24_violations_corrected_rule.csv). The F.Cu pour will recede to 0.3/0.5 mm around 178 HV24 items; afterwards check isolated_copper and the U25/U20 GND islands (F-03/F-07). After every GUI project save, re-check that the classes survived (resync-protocol §5).

  • Effort: both (rules now; the copper they flag is F-02/F-15)

  • Confidence: high on the facts (fill geometry, 0 DRC items, pattern resolution from the netlist). Medium on the internal rule-precedence mechanism, which is confirmed by a KiCad developer's forum statement plus the fill evidence. A KiCad Inspect → Clearance Resolution on one /24V–GND pair would make it high.

F-02 Raw ignition /IGN_IN crosses the board on In2 at 0.22 mm from /VEH5V: the 23-Jul inner-layer geometry repeated

  • Severity: Blocker

  • Block / refs: §4-F item 1; lesson drogheda-einarboard-short-incident (24 V on In2 at 0.20–0.25 mm from 5 V nets → board scrapped); Copper Plan §8 ("Rig1 22 k — 🔴 series element right at the jack"); same net as D-06 (rated Major there; I rate Blocker because it repeats a lesson already paid for).

  • Evidence: /IGN_IN = {P1.3, Rig1.1}. P1.3 is at (177.5, 135.0) and Rig1 at (123.55, 50.68), 100 mm apart. The net runs 4 mm on F.Cu, 106.5 mm on In2 at 0.5 mm width, plus one via. With the corrected HV24 rule it is the only inner-layer violation set. All 6 inner spots are on /IGN_IN:

    layer other net gap at
    In2 /VEH5V 1.0 mm track 0.221 mm (147.34, 67.49)
    In2 GND via 0.250 mm (154.4, 83.15)
    In2 /FAN_PWM track 0.291 mm (152.63, 73.49)
    In2 /5V_FAN via 0.300 mm (157.5, 104.5)
    In1 /NTC2 track (IGN via) 0.305 mm (127.32, 50.47)
    In2 /VEH5V via 0.340 mm (147.4, 67.4)

    Plus zone fills at 0.1505 mm on F/In1/In2/B.Cu (these re-pour automatically). The run is also one of the slots that split In2 (F-05).

  • Consequence: a single inner-layer defect puts 9–36 V (and load-dump pulses) straight onto /VEH5V, which feeds LTC4040 VIN (abs max 6 V class) and the whole 5 V system, or onto the fan gate/5 V fan rail. This is the failure that scrapped the 23-Jul board, and it cannot be seen or reworked.

  • Fix: move Rig1 (22 k, 0603, C88614) to ≤ 3 mm from P1.3, with /IGN_IN ≤ 3 mm long on F.Cu. The 106 mm run then becomes /IGN_SENSE: current-limited to 36 V/22 k = 1.6 mA (2.6 mA at 58 V) and clamped by D5/C9 at the MCU. A bridge to any 5 V net then injects ≤ 2.6 mA, which is harmless. Keep Rig2/Rigb1/C9/D5 at the MCU (Copper Plan §8). Optional (D-06): SMBJ33A (C224019) on /IGN_IN at P1.3; Rig1 in 1206 for pulse rating. Also move the In1 IGN via at (127.3, 50.5) ≥ 0.5 mm from /NTC2, or it disappears with the reroute.

  • Effort: layout (one resistor moves, one net rerouted; no BOM change)

  • Confidence: high (geometry measured on all layers; netlist membership)

F-03 U25 (24 V buck) hot loop: the input capacitors' GND is on a different F.Cu island from U25/D34; the loop closes through vias 10–30 mm away (≈ 3.1 cm²)

  • Severity: Major (same root item as A-06; not double-counted. It keeps pre-fab audit B5 open)

  • Block / refs: §4-F item 5; Copper Plan §2 ("under 1 cm² or do it again"); ECO §E.4; pre-fab audit B5; TPS54360B layout guidance (Cin at VIN/GND pins, PowerPAD to GND with vias).

  • Evidence (pad edge-to-edge unless noted):

    loop element v6 target
    C150.1 → U25.2 VIN 2.88 mm ✅ (C149: 6.37 mm) ≤ 3 mm
    C150.2 GND → U25 EP / pin 7 5.40 / 9.03 mm straight, but on a different copper piece same copper, ≤ 3 mm
    D34.1 → U25.8 PH 4.28 mm ≤ 3 mm
    D34.2 (anode) → C150.2 8.63 mm straight; no F.Cu path same island
    L22.1 → U25.8 13.75 mm (17.0 ctr; was 25.9 on 25-Sep) ≤ 5 mm
    /SW_PWRIN copper 45.8 mm² (tracks 20.9 mm², 20.4 mm × 1.0 mm) minimal
    U25 EP (3.2 × 2.5) 0 vias, nearest GND via 28 mm; pad joins the pour with 4 × 0.5 mm spokes (18 % perimeter contact) via array, solid

    F.Cu GND copper pieces (pour + GND pads + GND tracks, fcu_gnd_pieces.png): C149.2/C150.2/C151.2 sit on the 270 mm² U6 piece (5 GND vias, nearest 10.2 mm from C150.2). D34.2 and U25.9 sit on the 3766 mm² east piece, whose nearest vias to U25 are (145.7, 129.9) and (148.1, 135.3), ≈ 30 mm away. The input loop C150+ → U25 → PowerPAD → F.Cu → via → In1/In2 → via → C150− encloses ≈ 311 mm². With C150.2 tied to the EP island it would be ≈ 51 mm².

  • Consequence: non-synchronous buck, so the input loop carries the full switched current (3 A pulses at ~620 kHz). An estimated 15–25 nH of loop inductance × 3 A/5 ns gives ~9–15 V of ringing on VIN over the D32 clamp level (53.3 V). TPS54360B VIN abs max is 65 V, so margin disappears during a clamped load dump. Also conducted/radiated EMI into the GNSS/LTE receivers, and the IC dissipates through spokes.

  • Fix (layout): (1) Rotate/re-cluster so C149/C150 (2.2 µF/100 V, C153036) sit ≤ 2 mm from pins 2/7 with their GND pads on the same solid F.Cu copper as the PowerPAD and D34 anode (Copper Plan §2 chain order). D34 cathode ≤ 2 mm from pin 8, anode tied to the Cin GND copper. (2) PowerPAD: 6–9 × 0.3/0.6 mm vias (3 × 3 at 1.0 mm pitch fits 3.2 × 2.5) to In1/In2, pad connection solid (F-13). (3) Four GND vias (0.3/0.6) around the Cin/D34 GND node within 2 mm. (4) L22 ≤ 5 mm from pin 8 with a ≤ 25 mm² /SW_PWRIN pour. Keep /SW_PWRIN off any area above In1 signal tracks (today it sits over In1 /MAIN5V, /SW_5V, /VFB_BST: F-10).

  • Effort: layout

  • Confidence: high (island membership, distances). Medium on the ringing amplitude (inductance estimated, not simulated).

F-04 East-half F.Cu GND pour (3766 mm²: U19 modem, U20, U25, U2, J13) is stitched to the inner planes by only 5 vias; modem and F9P have no GND vias under them

  • Severity: Major
  • Block / refs: §4-F item 4; drogheda-einarboard-v5-audit (V5.5: 165 GND vias, 4.6 mm median NN); Copper Plan §5 ("nothing but solid In1 ground under the module"), §10 (5 mm grid around RF); SIMCom/u-blox hardware-design guidance (module GND pads to the main ground with many vias).
  • Evidence:
    • 69 GND vias on the whole board (V5.5: 165). The largest F.Cu GND piece (3766 mm², x 115–200) touches 5 of them: (145.7, 129.9), (148.1, 135.3), (153.5, 77.0), (152.6, 62.5), (198.8, 78.1). The other GND vias in that area land on 2–22 mm² slivers (e.g. (175.2, 58.7) on 7.3 mm², (184.6, 81.8) on 7.9 mm², (192.8, 78.1) on 20.8 mm²).
    • U19 A7670SA: 39 GND pads (109.5 mm², incl. 20 × 2.1 mm centre pads), 1 via under the 24 × 24 mm body, 4 GND vias in a 5 mm ring. The GND pads join the pour through thermal spokes (pad 85: 24 % perimeter contact; pad 71: 18 %). U18 ZED-F9P: 56 GND pads, 0 vias under the body, 5 in the ring, pads on spokes (pad 65: 45 %).
    • J13 (LTE U.FL) GND pads: nearest GND via 28 mm. D28 (LTE ESD) GND: 30 mm. J12 GND: 4.1 mm.
  • Consequence: the modem's return currents (23 dBm LTE, 2 A GSM bursts) and the F.Cu pour of the whole east half reach In1/In2 through 5 vias spread 30–70 mm apart. The pour behaves as a resonant patch (λ/2 at 1–2.7 GHz ≈ 26–75 mm in FR4) instead of a ground. Expect LTE self-desense of the F9P (−167 dBm sensitivity), antenna-port ESD returning through the pour, and poorer heat spreading from U19 (≈ 1–2 W at max TX) into the planes.
  • Fix (layout): (1) Pad connection solid for SMD pads (F-13). (2) U19: one 0.3/0.6 mm via per centre GND pad (20) plus vias between perimeter GND pads (≥ 30 under the module in total, tented/plugged: JLC "epoxy filled & capped" or tented vias off-pad, so the LGA does not wick). (3) U18: ≥ 1 via per 2 centre GND pads (≥ 24 vias), same rule. (4) J13/J12: 2 GND vias per U.FL ground pad ≤ 1 mm from the pad. (5) Global stitching per F-12.
  • Effort: layout
  • Confidence: high (via/piece connectivity measured). Medium on the desense magnitude (needs the G3 bench test).

F-05 In1, the "solid GND reference", carries 1572 mm of tracks from 49 nets and is 19 % void; almost every fast or sensitive interface crosses a slot

  • Severity: Major
  • Block / refs: §4-F item 2; Copper Plan §0 ("an unbroken In1 ground plane"), §10 ("In1 GND unbroken, especially under both RF runs and the crystals"); pre-fab audit §7; ECO §E.6.
  • Evidence:
    • In1 GND fill 11370.5 mm² in 8 islands (5553 / 4338 / 1289 / 94.5 / 37 / 34.6 / 14.5 / 9.7 mm²); void 2630 mm² (19 %). The voids form one connected slot network of 1276 mm² spanning 133 × 92 mm, plus a 605 mm² network in the Ethernet corner. Biggest In1 users: /SW_5V 181 mm, /DOUT_4G 95, /KCOIL 85, /MAIN5V 73, /CHRG_FAULT 72, /CHRG_STAT 69, /USART6_TX 68, /BOOT0 61, /SER_TXB 57, /SER_RXB 52, /MODEM_STATUS 45, /ETH_LINKLED 40 … /24V_IN 27, /RF_LTE 22.
    • In2 GND (1 island) carries 1009 mm from 25 nets (/IGN_IN 106, /PWR_CTRL 98, /SYS5V 98, /GNSS_ANT_* 88 + 86, /USART1_RX 79, /BAT_PLUS 70 …); its voids form an 856 mm² network. B.Cu is the /3V3 pour (1 island, 12610 mm²).
    • Plane gaps under critical nets (reference = In1 for F.Cu tracks, In2 for In1 tracks, In1 for In2 tracks; "slot" = gap made by a foreign inner track; full list work/FHJ/critical_crossings.csv):
    group net slot crossings (worst)
    SPI2 (W5500) ETH_MISO/MOSI/SCK/CS 1–3 each, 0.24–1.37 mm (In1 /ETH_INT, /ETH_RST)
    USART6 (modem) USART6_TX/RX (routed on In1, 68/37 mm) 7 each; RX over In2 /VEH5V 4.61 mm, /MODEM_PWR_EN 3.18 mm
    Modem UART 1V8 DOUT_4G_M 14 crossings (In1 /CHRG_FAULT 2.62 mm, /KCOIL 1.73, /MAIN5V 1.42)
    Modem power VBAT_MODEM over In1 /RF_LTE (175.5, 57.0) and /MAIN5V 1.3 mm
    Modem power VIN_MODEM 7 (In1 /CHRG_FAULT 1.8, /DOUT_4G 1.73)
    Switch nodes SW_PWRIN / SW_BAT over In1 /SW_5V 1.83 mm, /MAIN5V 1.84, /VFB_BST 1.13 / /SW_5V ×5
    Crystals HSE_IN/OUT over In1 /USART6_RX 1.13 mm each (under Y3); ETH_XO over In1 /ETH_RST 6.28 mm parallel
    USB USB_DP/DM (J9) over In1 /24V_IN 2.5 mm, /SW_5V 2.47, /CHRG_FAULT 1.79; pair split In1/In2
    USB DFU_DM over In1 /ETH_ACTLED 5.98 mm parallel
    SIM SIMB_CLK / SIMA_RST over In1 /SW_5V 4.1 / 2.69 mm
    Misc I2C_SDA over In1 /SER_TXB 12.82 mm parallel; NRST over /USART6_RX 6.45 mm
    RF RF_LTE is itself on In1 (F-06); RF_GNSS/RF_ANT_* have 0 slot crossings ✅
  • Consequence: return currents detour around slots (loop area → emissions and susceptibility). Parallel runs directly above/below foreign traces (12.8 mm I2C_SDA over SER_TXB, 6.3 mm ETH_XO over ETH_RST) are broadside crosstalk with no plane between. For the RF receiver this is the "unbroken In1" rule of the copper plan broken by design.
  • Fix (layout): make In1 a plane again. Move all In1 tracks to In2/B.Cu, or to F.Cu where short. Priority: /RF_LTE (F-06), /24V_IN (F-16), /SW_5V, /MAIN5V, /KCOIL, /USART6_TX/RX, /DOUT_4G, /CHRG_*, /SER_TXB/RXB, /ETH_*, /VFB_BST, /IGATE. In2 then carries the signal layer with In1 GND above and the B.Cu 3V3 pour below. If In2 is kept as GND, accept In2 as the only plane and route everything else on B.Cu. Rule of thumb: no inner track under F.Cu fast nets, crystals, the RF runs, switch nodes or U18/U19. Target ≤ 3 In1 islands and no void longer than 5 mm under a critical net.
  • Effort: layout (large)
  • Confidence: high (geometry). Medium on the EMC consequence magnitude.

F-06 RF feeds: LTE routed 22 mm on In1 under the modem power tracks with 2 via transitions and no fence; GNSS bias line runs 16.7 mm alongside the RF line at 0.27 mm; neither line is 50 Ω on either stackup

  • Severity: Major
  • Block / refs: §4-F items 2/4; Copper Plan §4/§5/§10 (① "both 50 Ω RF runs, CPWG on F.Cu over In1 … 0.35/0.25 mm, order controlled impedance"); drogheda-v6-lte-island (RF class 0.35 mm, "never autoroute"); pre-fab audit §7.
  • Evidence:
    • /RF_LTE: U19.60 → 1.75 mm F.Cu → via (174.25, 58.25) → In1 22.1 mm (4.95 + 15.49 + 1.46 + 0.24) → via (194.27, 53.72) → F.Cu → R118 → /RF_ANT_LTE → J13. Over the In1 run on F.Cu: /VBAT_MODEM (1.15 mm² overlap, the PA supply with 2 A bursts), /SYS5V, /SW_IN, /MODEM_LED_A/K; under it on In2: /DIN_4G. F.Cu GND above the run covers only 51 % of it; In2 GND below 85 %. GND vias within 2.5 mm of the whole 26 mm LTE path: 1 → fence pitch ≈ 52 mm.
    • /RF_GNSS 22.7 mm F.Cu 0.5 mm; /VCC_RF_GNSS runs parallel for 9.8 + 3.2 + 3.75 = 16.7 mm at 0.27 mm edge gap (no GND can fill a 0.27 mm gap). GND vias within 2.5 mm: 2 (fence ≈ 22.7 mm). F.Cu GND pour reaches only 24–41 % of a 0.5 mm band around each RF trace.
    • Fence requirement: λ = c/(f·√εr) = 3e8/(2.7e9·√4.5) = 52.4 mm → λ/20 = 2.6 mm (3.0 mm with microstrip εeff ≈ 3.4). Actual 22–52 mm.
    • Impedance, 0.5 mm microstrip (Hammerstad): file stackup (h = 0.48 mm, εr 4.5) → 68.9 Ω. JLC04161H-7628 (L1–L2 prepreg 0.2104 mm, εr 4.4) → 43.9 Ω (≈ 35 Ω with the intermittent 0.15 mm coplanar ground). The In1 LTE stripline with F.Cu at 0.21 mm and In2 at 1.065 mm is ≈ 30 Ω. The board file still carries the generic stackup (copper finish "None").
  • Consequence: LTE: mismatch plus two unshielded via transitions, and the PA supply crossing the RF line (PA noise and burst ripple couple straight into the antenna feed); radiated desense of the adjacent F9P. GNSS: a coupled-line section between the LNA input and a bias line decoupled only at L21 (C144/C145); the line impedance is uncontrolled. The G3 desense bench test is likely to fail.
  • Fix (layout + stackup): (1) Set the real stackup in Board Setup (JLC04161H-7628: 0.035/0.2104/0.035/1.065/0.035/0.2104/0.035, εr 4.4 prepreg / 4.6 core), and order impedance control. (2) Both RF runs on F.Cu only, as CPWG over solid In1: w ≈ 0.30–0.35 mm, gap ≈ 0.20–0.25 mm (verify in the JLC calculator for 50 Ω), RF netclass with clearance = that gap. (3) LTE: reroute U19.60 → R118/C146/C147 → D28 → J13 on F.Cu (rotate J13 or move U19's RF pad side toward it). Nothing crosses above or below; /VBAT_MODEM stays ≥ 3 mm away. (4) Via fence both sides at ≤ 2.5 mm pitch, ≤ 1 mm from the gap edge, and 2 vias per U.FL GND pad. (5) GNSS: route /VCC_RF_GNSS away (≥ 1 mm with a stitched GND strip between, or on In2 after a 100 pF + 100 nF decoupling at U18 pin 7), with L21 tapping the RF line stub-free at J12.
  • Effort: both (stackup setting) / layout
  • Confidence: high on geometry. Medium on impedance (closed-form estimates; the JLC calculator gives the final numbers).

F-07 U20 (modem buck) input loop returns through a 0.25 mm GND track squeezed between pins 1 and 2; EP on thermal spokes, 0 vias

  • Severity: Major (U20 part of A-06; the geometry details are new here)
  • Block / refs: §4-F item 5; Copper Plan §4 ("C128 1 µF even closer … minimal SW pour"); AP64350 datasheet layout (Cin across VIN–GND/EP, EP vias).
  • Evidence: C128.1 → U20.2: 0.72 mm ✅, C127.1: 2.38 mm ✅. Return: C128.2 → the 0.25 mm GND track routed between U20.1 (BST) and U20.2 (VIN) to the EP. The F.Cu path is 3.7 mm through that 0.25 mm neck; C127.2 → EP is 5.4 mm. Gaps: GND track to /SW_MODEM pad U20.8 0.150 mm, to /VIN_MODEM track 0.150 mm, to U20.2 0.195 mm. /VIN_MODEM 0.5 mm track 0.20 mm from the EP and 0.25 mm from U20.3/.4. EP: 0 vias (nearest GND via 3.85 mm), 13 % perimeter contact (spokes). SW node 11.3 mm² (6.6 mm track) ✅; L20 2.24 mm ✅; BST 1.8 mm ✅. U20 VIN caps: 10 µF X5R 0805 50 V (C440198) keeps ≈ 30 % of its value at 24 V DC bias, and 1 µF (C15849).
  • Consequence: the synchronous buck's hot loop includes ~3–4 nH of 0.25 mm neck, which gives SW-node ringing and input noise at the LTE PA supply. The HV24 outer rule (F-01) flags 15 spots here, because the GND neck sits at 0.15 mm from 24 V copper.
  • Fix (layout): delete the GND neck. Put C128 (and a second 10 µF 50 V 1206, or 2 × 22 µF per ECO A if on 5 V only; see A-01 option A) with its GND pad on a solid F.Cu area bonded to the EP via ≥ 6 × 0.3/0.6 vias in the EP (2 × 3). Keep /VIN_MODEM ≥ 0.3 mm from EN/RT/EP pads.
  • Effort: layout
  • Confidence: high

F-08 U2 (fan buck, 24 V) has no input capacitor within 17 mm; ground return 20–44 mm

  • Severity: Major (moot if A-01 option 1, "delete the 24 V fan buck", is adopted)
  • Block / refs: §4-F item 5; ECO §E.4 (U2 → C11 6.3 mm on V5.5; v6 is worse); pre-fab audit B5.
  • Evidence: U2.7 VIN → C11 (100 nF) 20.75 mm, C22 (10 µF actual) 18.32 mm, C10 17.04 mm (edge). F.Cu GND path C22.2 → Dbk1 anode 20.4 mm, C11.2 → Dbk1 44.1 mm. Dbk1 → U2.1 6.51 mm; L2 11.92 mm. EP 0 vias (nearest GND via 23 mm), solid pad connection ✅. FB divider R20/R21 0.67/1.48 mm ✅ (ECO §E.3 fixed). /SW_FAN 25.7 mm².
  • Consequence: a 24 V non-synchronous loop of several cm², with ringing on a part whose VIN abs max is 30 V (A-01), next to /24V, /COMP_FAN (0.29 mm) and /FREQ_FAN (0.375 mm).
  • Fix: preferred per A-01, delete U2 and run the fan from /VEH5V. If kept: a 1 µF + 100 nF 50 V X7R 0603 pair (C15849 / C14663) ≤ 1.5 mm from pins 7/5, Dbk1 anode on the same GND copper, 4 EP vias, L2 ≤ 5 mm.
  • Effort: layout (or schematic DNP)
  • Confidence: high

F-09 U12 (3V3_ETH buck): catch diode 14 mm away on a different F.Cu island; /ETH_FB node 35 mm long, runs under the /ETH_SW node on In1

  • Severity: Major (repeats the V5.5 EMC finding #3 pattern: FB far from the pin and next to SW)
  • Block / refs: §4-F item 5; ECO §E.3/§E.4; drogheda-einarboard-v5-audit #3/#4.
  • Evidence: C101.1 → U12.2 VIN 1.77 mm ✅. D11.1 → U12.1 SW 11.92 mm, L8.1 → U12.1 15.10 mm, /ETH_SW 20.1 mm long / 27.2 mm². C101.2 (on the 224 mm² piece) and D11.2 (on the 178 mm² piece) are different F.Cu GND islands (loop closes through vias). FB divider: R88 (31.6 k) 2.59 mm from U12.4, but R87 (100 k, top) 25.9 mm away, so the high-impedance FB node /ETH_FB is 35 mm long (F.Cu + 28 mm In1), and 1.84 mm² of it lies directly under the /ETH_SW copper (In1). /SYS5V on In2 also passes under /ETH_SW (3.3 mm²).
  • Consequence: switching noise injected into the FB node shows up as 3V3_ETH ripple/jitter at the W5500. Emissions from a 20 mm SW trace next to the RJ45 corner.
  • Fix (layout): R87/R88 both ≤ 3 mm from U12.4, with the top resistor fed by a Kelvin trace from C102/C94. FB net ≤ 5 mm on F.Cu, nothing under /ETH_SW. D11 ≤ 2 mm from pin 1 with its anode on C101's GND copper. L8 ≤ 5 mm.
  • Effort: layout
  • Confidence: high

F-10 Feedback nodes and power rails under 24 V switch nodes; LTC4040 BSTFB divider 21–23 mm from U6

  • Severity: Minor (the U6 BSTFB part is A-14, Minor; noted here for the switch-node overlap)
  • Block / refs: §4-F item 5 ("switch nodes not routed on inner layers under sensitive lines").
  • Evidence: all switch nodes are F.Cu-only ✅ (/SW_PWRIN, /SW_FAN, /SW_MODEM, /SW_BAT, /ETH_SW). Inner copper under them: /SW_PWRIN over In1 /MAIN5V 2.41 mm², /SW_5V 2.91 mm², /VFB_BST 1.14 mm²; /SW_BAT over In1 /SW_5V 1.39 mm²; /ETH_SW over /ETH_FB (F-09). /VFB_BST (U6 RSTFB pin 10/BSTFB pin 18; R53/R54 499 k/100 k → 83 k Thevenin) is 41.2 mm long, 24 mm of it on In1, and R53/R54 sit 21.4/23.3 mm from the pins. Coupling estimate: C = ε0·4.5·1.14 mm²/0.48 mm = 0.095 pF; with dV/dt ≈ 24 V/10 ns that gives ≈ 0.23 mA spikes into an 83 kΩ node.
  • Consequence: backup boost set-point noise (BSTFB), the mode that R1/R3 depend on. Switching noise on the F9P supply /SW_5V.
  • Fix: R53/R54 ≤ 3 mm from U6.18/10 (A-14). Keep In1 under /SW_PWRIN//SW_BAT solid GND (falls out of F-05).
  • Effort: layout
  • Confidence: high (geometry); medium (effect size)

F-11 Crystals 8–14 mm from their pins (Y1, Y3 HC-49); HSE lines cross an In1 slot; battery copper beside Y3

  • Severity: Minor (HSE/LSE load and gm are covered in D-02/D-03; Y1 load in H-08)
  • Block / refs: §4-F item 3; ECO §E.6 ("cristales ≤ 5 mm"); Copper Plan §6/§9 (crystal ≥ 10 mm from inductors; guard with ground).
  • Evidence (pad edge → IC pin; track length):
    crystal part pin 1 → IC pin 2 → IC In1 GND under courtyard foreign copper through courtyard nearest inductor
    Y1 25 MHz (W5500) HC-49SD 13.74 mm (ETH_XI 23.0 mm) 10.79 mm (ETH_XO 22.0 mm) 90 % F.Cu DFU_DP/DM, In1 ETH_ACTLED, In2 SYS5V L8 13.6 mm ✅
    Y2 3.6864 MHz (SC16IS) HC-49SD 5.51 mm 4.64 mm 90 % In1 BOOT0/DOUT_4G/3V3, In2 GNSS_ANT_* L8 21.3 ✅
    Y3 25 MHz (HSE) HC-49SD 8.32 mm (14.5 mm) 11.30 mm (20.7 mm) 94 % In1 USART6_RX (crosses both HSE lines), BAT_PLUS on all 4 layers L20 14.6 ✅
    Y4 32.768 kHz 3215 3.92 mm ✅ 6.32 mm 100 % ✅ F.Cu LED_C13, B.Cu MODEM_RST 25.3 ✅
  • Consequence: V5.5 worked at 12–15 mm with a solid plane under the lines. v6 adds In1 slots under Y3's lines and signals under Y1. Radiated harmonics (25/50/75 MHz) and marginal start-up (D-02).
  • Fix: follow D-02/D-03 part swaps (3225 crystals). Y1 → 3225 25 MHz CL 10–12 pF (same family as D-02's C2901684) ≤ 3 mm from U11.30/31, caps adjacent, 2 GND vias. No inner-layer track under any crystal or its lines.
  • Effort: both
  • Confidence: high

F-12 Via stitching: 69 GND vias (V5.5: 165), 10 of 35 20 mm cells empty, 2 vias along 480 mm of board edge

  • Severity: Major
  • Block / refs: §4-F item 4; drogheda-einarboard-v5-audit ("165 GND vias, 4.6 mm median NN; 8 empty 20 mm cells" was already a finding on V5.5); ECO §E.6; Copper Plan §10.
  • Evidence: GND vias per 20 × 20 mm cell (rows y 40→140, cols x 60→200): [0,5,4,3,0,1,0] [2,3,4,4,4,0,2] [2,1,2,3,0,1,3] [0,2,2,2,0,2,4] [4,5,0,2,2,0,0]: 10 empty cells. Distance from any board point to the nearest GND via: median 7.7 mm, p90 15.7 mm, max 27.8 mm at (197.7, 42.3) (NE corner next to J13). Vias within 3 mm of the edge: 2 (average pitch 240 mm). NN median 5.2 mm, but the vias are clustered around the MCU.
  • Consequence: edge radiation and ESD return paths are uncontrolled. Plane-to-plane resonances between F.Cu/In1/In2 pours are undamped at LTE frequencies. Regresses V5.5 by 96 vias.
  • Fix (layout): a 5 mm stitching grid tying F.Cu GND, In1, In2 (skip where B.Cu 3V3 needs continuity: the vias are GND and pass through the 3V3 pour with antipads). A fence ≤ 5 mm pitch along all four edges, 1 mm inside the 0.5 mm edge clearance, and ≤ 2.5 mm around the RF runs and U.FL connectors (F-06). Expect ≈ 500–600 vias of 0.3/0.6 mm. Let the pour's min_thickness/island removal keep the F.Cu pieces joined.
  • Effort: layout
  • Confidence: high

F-13 Exposed pads and module grounds: 0 thermal vias on U6/U25/U20/U2/U12; U25 and U20 EPs (and every GND pad except 5 EPs) join the pour through 0.5 mm thermal spokes

  • Severity: Major (U6 is also in A-02; U25/U20/U2/U12 EPs in A-06)
  • Block / refs: §4-F item 4; Review §2 "Switcher EP vias"; ECO §D2 ("EP de U6 con ≥ 9 vías").
  • Evidence: zones use connect_pads default = thermal (gap 0.5 / spoke 0.5 mm) for all pads. Pad overrides zone_connect 2 (solid) exist only on U6.25, U2.9, U12.9, U11.9, U11.29, JP1–5. Contact measured at the pad edge: U25 EP 18 %, U20 EP 13 %, D34 anode 18 %, C150 GND 21 %, U19 GND pads 18–24 %. Vias inside EP: U6 0, U25 0, U20 0, U2 0, U12 0.
  • Consequence: junction temperature: TPS54360B/AP64350 θJA figures assume a soldered PowerPAD with vias into planes. Spokes and no vias roughly double the thermal resistance, at 45 °C port ambient. It also adds inductance in the hot-loop returns.
  • Fix: set all copper zones to "Thermal reliefs for PTH only" ((connect_pads thru_hole_only (clearance 0.3))) so SMD pads are solid. EP via arrays of 0.3/0.6 mm: U6 3 × 3 (≥ 9, ECO D2), U25 3 × 3, U20 2 × 3, U2/U12 2 × 3, all to In1+In2. Tented on the bottom side, or plugged (JLC "via in pad, filled and capped" option) under U19/U18.
  • Effort: layout
  • Confidence: high

F-14 DFU ESD (D14/D15/D16) hangs on stubs; D15 is 11 mm of copper from J11; J9 still has no ESD

  • Severity: Minor (J9 = G-02, Major, not counted here)
  • Block / refs: §4-F item 6; ECO §E.5; V5.5 finding (41 mm) fixed in placement.
  • Evidence: DFU_DP/DM have no series resistors (J11 → U16 PA12/PA11 directly), so "ESD before the series R" is n/a. Pad-edge distance to the nearest J11 pad / copper path J11 → ESD / ESD on the signal path?: D14 (DP) 2.53 / 3.3 mm / no (T-stub); D15 (DM) 6.07 / 10.9 mm / no; D16 (VBUS) 2.62 / 3.0 mm / no. ESD GND pad → nearest GND via: 2.6 / 1.8 / 4.9 mm. Conn → MCU path 48–53 mm.
  • Consequence: a stub adds series inductance to the clamp path (≈ 1 nH/mm): the clamp voltage rises at the fast IEC 61000-4-2 edge. D15 at 10.9 mm is not "at the connector".
  • Fix (layout): route J11 D+/D− through the D14/D15 pads (pad-in-line), D15 ≤ 3 mm copper from J11, each ESD GND pad with its own via ≤ 1 mm. Optional: replace the three PESD5V0S1BA by one USBLC6-2SC6 (C7519) at J11 (≈ 3.5 pF/line). J9: add USBLC6-2SC6 per G-02.
  • Effort: layout
  • Confidence: high

F-15 Outer-layer 24 V spacing: 15 spots < 0.3 mm (38 < 0.5 mm), including /VIN_PROT 0.16 mm from /VEH5V

  • Severity: Minor (IPC-compliant under mask; the 24 → 5 V spot is the one to fix first)
  • Block / refs: §4-F item 1; F-01.
  • Evidence (corrected classes, F.Cu, non-zone copper, unique spots): /SW_MODEM U20.8 – GND 0.25 mm track 0.150; /VIN_MODEM – GND track 0.150 / U20.9 0.200 / U20.2 pad–GND track 0.195; /VIN_PROT 1.5 mm – /VEH5V 0.8 mm track 0.162 mm at (176.24, 116.28) and – /VEH5V via 0.193; /SW_MODEM 1.0 mm – GND 0.170; /Q23_GATE Q23.1 and /VIN_PROT Q23.3 – /USB_VBUS 0.225; /BST_MODEM U20.1 – GND 0.225; /VIN_MODEM – U20.3 /MODEM_PWR_EN 0.250 / U20.4 0.250; /SW_PWRIN – GND 1.0 mm track 0.270; /BST_MODEM – GND 0.275; /24V 1.5 mm – /COMP_FAN 0.290 (noise into the fan-buck compensation). The other 23 spots (0.30–0.50 mm) are listed in work/FHJ/hv24_violations_corrected_rule.csv. Same-footprint pad pairs < 0.5 mm: only U2.7/.1/.8 to U2 EP (0.355–0.416 mm), covered by the F-01 exception.
  • Consequence: a solder splash or conductive contamination at (176.2, 116.3) puts 24 V on /VEH5V. The via there is untented (no tenting set), so it is bare copper 0.19 mm from a 24 V trace.
  • Fix: 0.3 mm outer rule (F-01); reroute /VIN_PROT vs /VEH5V near R124/U25 (≥ 0.5 mm here, since it is 24 → 5 V); remove the U20 GND neck (F-07); /USB_VBUS away from Q23; /COMP_FAN ≥ 1 mm from /24V. Tent all vias except test vias.
  • Effort: layout
  • Confidence: high

F-16 /24V_IN (HV24, 1.5 mm) runs 27 mm on In1 through the GND plane, 0.500 mm from /SW_5V over 2.8 mm

  • Severity: Minor
  • Block / refs: short-incident lesson ("keep 24V_IN off inner layers next to LV or reroute along board edge").
  • Evidence: In1 segments (167.5, 128.65) → (160.6, 121.75) → (143.25, 121.75). Minimum gap to /SW_5V (F9P rail, In1 1.0 mm) = 0.500 mm, with 2.8 mm of /SW_5V within 1 mm. It cuts a 25 mm slot in In1 that the modem USB pair crosses (F-05, F-17).
  • Consequence: meets the 0.5 mm rule exactly, with no margin, in the configuration that failed on 23-Jul.
  • Fix: route P1.1 → F2/Q10/D10 on F.Cu along the south edge (the SE corner has room once U25 is re-clustered). If In1 must be used, keep ≥ 1.0 mm to any LV net and nothing crossing above it.
  • Effort: layout
  • Confidence: high

F-17 USB pairs: J9 (modem, HS-capable) pair split across layers and crossing the /24V_IN and /SW_5V slots; DFU pair runs 6 mm over /ETH_ACTLED

  • Severity: Minor
  • Block / refs: §4-F item 2; pre-fab audit §7 (USB pair split); Copper Plan §9 (90 Ω pairs).
  • Evidence: /USB_DP F.Cu 49.9 + In1 9.6 mm; /USB_DM F.Cu 50.0 + In1 8.0 + In2 1.7 mm. They cross In1 /24V_IN (2.5 mm gap) at (157.75, 121.75), /SW_5V 2.47 mm, /5V_FAN, /IGATE, /CHRG_FAULT/STAT. /DFU_DM over In1 /ETH_ACTLED 5.98 mm parallel.
  • Consequence: A7670SA USB is high speed. Service firmware updates through J9 may fail to enumerate at HS or fall back. The DFU (FS) port is tolerant.
  • Fix: both pairs on F.Cu only, over solid In1, coupled (≈ 0.2/0.15 mm on JLC7628 for 90 Ω; verify), ≤ 1 via pair, no slot crossings.
  • Effort: layout
  • Confidence: high (geometry); medium (HS failure)

F-18 Silkscreen: 304 of 312 reference texts are 0.5 mm / 0.1 mm (JLC minimum 1.0 mm / 0.15 mm); 14 DRC silk items

  • Severity: Minor (G-05 also covers labels; not double-counted)
  • Block / refs: §4-F item 8; pre-fab audit §7; JLC capabilities.
  • Evidence: reference fields: 304 × 0.5/0.1 mm visible, 6 × 0.5/0.1 hidden, 2 × 1.0/0.15. Board texts: 6 × 0.5/0.1, 2 × 1.0/0.1, 1 × 2.0/0.5. The .kicad_dru text rule is 0.5/0.1, so DRC stays silent. DRC: 11 silk_overlap (D27, R99/C157, C126/U19, Q21/U19, JP3, U24, U23, Q10/JP5, Q23), 2 silk_over_copper (Rigb1 ref on C9.2; C10 ref on C10.2), 1 silk_edge (P1 outline at the south edge). Polarity marks: all polarized parts use KiCad or easyeda footprints that carry pin-1/cathode marks (D_SMA/SMB/SMC/SOD-123/323/128/923, CP_Elec, LED, SOIC/QFN/LQFP), but D27/D28 (SOD-923) and the Q10 region marks are among the overlap items: check them in the 3D view.
  • Consequence: JLC prints sub-minimum text blurred or drops it. Technicians (Jesús) cannot read refs and test points.
  • Fix: refs ≥ 0.8 mm/0.15 mm (1.0/0.15 where it fits). Set the DRU text rule to (min 0.8mm)/(min 0.15mm). Clear the 14 DRC items.
  • Effort: layout
  • Confidence: high

F-19 Manufacturability vs JLC 4-layer standard: passes, with J9/J11 (USB4085 THT) at the JLC limits

  • Severity: Note
  • Block / refs: §4-F item 9.
  • Evidence:
    parameter used on v6 .kicad_pro/.kicad_dru JLC 4-layer std
    min track 0.20 mm 0.2 0.09 mm ✅
    min spacing 0.15 mm (rule) 0.15 0.09 mm ✅
    via drill/pad 0.30/0.80 mm (all 210) 0.3/0.5 min 0.15/0.25 mm ✅
    via annular ring 0.25 mm 0.1 ✅
    PTH annular ring 0.15 mm (J9/J11 0.7 pad/0.4 drill) — 0.15 abs / 0.20 rec. ⚠
    hole-to-hole 0.45 mm (J9/J11 rows) 0.25 0.45 mm ⚠ (at limit)
    PTH hole → other-net track 0.30 mm (J11) — 0.28 mm ⚠
    via hole → other-net copper 0.40 mm 0.25 0.2 mm ✅
    copper → edge 0.625 mm (tracks), fills 0.50 0.5 0.2 mm ✅
    fiducials none — optional ✅
    outline 140.002 × 100.002 mm, 4 segments, corner gaps ≤ 2.5 µm — ✅
  • Fix (order notes): ENIG (LGA U18/U19); stackup JLC04161H-7628 with impedance control (F-06); X-ray on U18/U19; tent vias; J9/J11 accepted at the limit (GCT USB4085 standard footprint, V5.5 fabbed fine).
  • Effort: none (order notes)
  • Confidence: high

F-20 Courtyard overlaps: all 15 are bounding-box artefacts (0 real overlaps)

  • Severity: Note
  • Block / refs: §4-F item 7.
  • Evidence: real courtyard polygons from each footprint, intersected: 0.000 mm² for all 15 (C10/C11, C10/Rcomp1, C126/R127, C142/R116, C151/C78, C151/R125, C3/C40, C30/C78, D4G1/Q22, D5/Q4, J9/Rcc2, L20/R111, Q22/R109, R50/U6, TP4/TP5). Minimum pad-to-pad gaps 0.46–3.50 mm. No other polygon overlap on the board. KiCad DRC courtyards_overlap (not ignored) also reports 0. Only MH5–MH8 lack courtyards.
  • Fix: none. Watch the H-03 inductors: MWSA0804S bodies are 8.2 × 8.8 mm against an 8.0 × 8.0 courtyard basis.
  • Effort: none
  • Confidence: high

F-21 The one dangling /SW_5V track end is benign

  • Severity: Note
  • Evidence: segment (88.35, 121.881) → (86.35, 121.881), 0.5 mm, F.Cu. Its end is 0.025 mm outside U21.3's pad edge but overlaps the pad by 0.085 mm². Connected per KiCad (no track_dangling in DRC) and per the pack's union-find.
  • Fix: extend 0.3 mm to the pad centre (cosmetic).
  • Effort: layout (trivial)
  • Confidence: high

H-01 U15 MAX3232ESE (narrow SOIC-16) is assigned to a wide SOIC-16W footprint: it cannot be soldered

  • Severity: Blocker
  • Block / refs: §4-H (package/footprint match); memory drogheda-einarboard-v5-audit (U13 is wide, "package truth only from the mfr ordering table").
  • Evidence: U15 LCSC C15846 = MAX3232ESE+T, "SOIC-16" (JLC DB). Maxim "ESE" = 16-pin narrow SO (150 mil). Footprint Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm, pads 2.05 × 0.6 mm, pad rows 9.3 mm apart (x 117.3 / 126.6). Narrow SOIC lead span ≈ 6.0 mm, so the leads end ≈ 1.6 mm short of the pads on each side. The same combination is in V5.5 as fabbed and V5.6. (U13 PCF8574T C7605 is SOIC-16 300 mil = wide ✅.)
  • Consequence: RS-232 (P12) dead on every v6 board. JLC either rejects or places a part that cannot be soldered. V5.5 boards probably have the same defect unless JLC substituted a part.
  • Fix (choose one): (a) keep the layout and use a wide part: C118514 MAX3232EEWE+T (SOIC-16 300 mil, 30 in stock, $5.68) or C1544667 MAX3232ECDW (0–70 °C, 16 in stock). Both are thin stock, so (b) is recommended: change the footprint to Package_SO:SOIC-16_3.9x9.9mm_P1.27mm and keep C15846 (4873 in stock) or use C19268179 MAX3232ID (SOP-16, −40…125 °C, 5709 in stock, $0.45). Re-place C84–C88 hard against it.
  • Effort: both (footprint + local re-route) for (b); schematic-only for (a)
  • Confidence: high (DB package + footprint pad geometry). Worth one look at a V5.5 board's U15 to confirm the V5.5 history.

H-02 Stock: U10 (15 pcs) and R53 (6 pcs) cannot be placed on a 20-board order; C103211, the A7670SA and J14 limit a 100-board order

  • Severity: Blocker (for any order ≥ 16 boards)
  • Block / refs: §4-H.
  • Evidence (JLC DB stock vs need at 20 / 100 boards):
    ref LCSC part stock per board fix
    U10 C729142 SC16IS762IPW 15 1 C57156 SC16IS752IPW,128 (2670, $3.80 vs $7.32; the value field already says 752; register-identical per memory)
    R53 C131054 499 k 1 % YAGEO 6 1 C177479 RCT03499KFLF 499 k 1 % 0603 (26 862)
    R20,R56–58,R85,R87,Ren1,Rfreq1,Rgs1 C103211 100 k 5 % RALEC 702 9 C25803 100 k 1 % (Basic, 10.8 M, already in BOM for R113–R115/R119)
    U19 C18548276 A7670SA-LASC 96 1 pre-order/consign for qty 100
    U18 C5120257 ZED-F9P-04B 104 1 pre-order for qty ≥ 100
    J14 C2977286 JAE SF72S006 10 890 1 category "Pre-ordered Products": pre-order into the JLC account (pre-fab B4)
    L2+L8 / L6 / U13 / P11+P12 C17700171 / C17700165 / C7605 / C5160226 — 470 / 646 / 517 / 512 2 / 1 / 1 / 2 ok at 100 boards (L2+L8 = 200, P11+P12 = 200)
  • Consequence: JLC leaves U10/R53 unplaced (U10 = RS-485/RS-232 bridge; R53 = LTC4040 boost set-point: the backup rail would not regulate).
  • Fix: LCSC swaps above (schematic field only). Re-check stock on order day (the DB is a snapshot).
  • Effort: schematic-only
  • Confidence: high (DB snapshot; stock moves daily)

H-03 Sunlord MWSA0804S inductors (L2, L6, L8, L20) sit on a Bourns SRU8028 land pattern

  • Severity: Major
  • Block / refs: §4-H (Leo's L7 SRU8028 vs MWSA0804S question); pre-fab audit ("check its pads against the SRU8028 land").
  • Evidence: footprint Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm: pads 2.0 × 3.2 mm at ±3.9 mm (inner gap 5.8 mm, outer 9.8 mm). MWSA0804S (Sunlord spec, table 4-1): body A 8.2 ± 0.3 × B 8.8 ± 0.4 × 3.8 mm, electrodes D 1.4 × E 5.0 mm, recommended land I 2.75 / J 4.0 / H 5.5 mm (typ). Electrode inner gap ≈ 8.2 − 2 × 1.4 = 5.4 mm, so an electrode spans 2.7–4.1 mm from centre while the pad spans 2.9–4.9 mm: overlap 1.2 of 1.4 mm length × 3.2 of 5.0 mm width ≈ 55 % of the electrode area wetted. Body 8.8 mm vs the 8.0 mm courtyard basis. The same combination on V5.5 assembled and ran.
  • Consequence: reduced joint area and self-centring on the heaviest SMD parts, in a vibrating vehicle. L6 (backup boost, ~4 A) and L20 (modem buck, 2 A bursts) are exactly where a cracked joint would show up as the V5.5-style "modem dark on battery".
  • Fix: make Drogheda-v6:IND-SMD_MWSA0804S from the Sunlord drawing (pads 2.75 × 4.0 mm, 5.5 mm inner gap → pad centres ±4.125 mm; courtyard 9.4 × 9.8 mm) and assign it to L2/L6/L8/L20 (C17700171/65/67). Or switch to true SRU8028 parts if JLC stocks them. Re-check neighbours for the 0.4 mm body growth.
  • Effort: both (footprint swap; 4 parts re-placed)
  • Confidence: medium (land pattern letters read from a mirrored Sunlord spec; confirm against the LCSC PDF, which is blocked from this sandbox)

H-04 U25 footprint carries LCSC Part = C2071691 (AP64350) next to LCSC = C524806 (TPS54360B)

  • Severity: Major (A-15 rates it Minor. I rate it Major because the AP64350 is pin-compatible (1 BST, 2 VIN, 3 EN, 4 RT, 5 FB, 6 COMP, 7 GND, 8 SW, EP): a board built with it passes the bench and then dies at the first transient above the AP64350's 40 V rating, behind a 53 V clamp)
  • Evidence: sch_pcb_sync.md §2; the only such conflict on the board. Which field a BOM/CPL plugin uses depends on the tool's field-name priority.
  • Fix: delete the LCSC Part property from U25 on the PCB (and in the Drogheda-v6 footprint library if it came from there). Generate BOM/CPL from the schematic LCSC field only.
  • Effort: schematic/board property only
  • Confidence: high (fact); medium (which field JLC tooling picks)

H-05 Voltage ratings on the vehicle rail: D21 (30 V), Dbk1 (40 V), U2 (28 V operating/30 V abs) sit behind a 36.7–53.3 V TVS

  • Severity: Note (duplicate of A-01, Blocker; listed so the BOM table is complete)
  • Evidence: D21 PMEG3050EP C50603: VR 30 V, IR 8 mA @ 30 V. Reverse bias = /VIN_MODEM − /MAIN5V ≈ 36 − 0.45 − 4.79 ≈ 30.8 V at the top of the TVS standoff band (SMBJ33A VBR 36.7–40.6 V), ≈ 48 V at the 53.3 V clamp. Dbk1 SS34 C8678 (40 V) on /SW_FAN swings to /24V. U2 MP1584EN C15051 "4.5–28 V". All ceramics on 24 V nets are rated ≥ 50 V: C22 50 V (2.1× at 24 V, 1.8× at 28.8 V), C127/C128 50 V, C11 50 V, C149/C150 100 V ✅; C10/C151 50 V electrolytics ✅.
  • Fix: per A-01 (DNP U2, feed U20 from MAIN5V). If D21 stays: C53114006 PMEG6030EP (60 V, 3 A, SOD-128 drop-in, 8956 in stock). If Dbk1 stays: 60 V SMA Schottky (SS36 class).
  • Effort: schematic-only
  • Confidence: high

H-06 J10, P11, P12: PCB DNP vs schematic populated; the P11/P12 schematic footprint is Vertical (not in the library) while the ordered part is right-angle

  • Severity: Minor (= G-03; adds the part/footprint fact)
  • Evidence: PCB DNP on J10/P11/P12; schematic dnp empty, so a schematic-exported BOM orders them. P11/P12 LCSC C5160226 = DEGSON 15EDGRC-3.5-03P, right-angle, which matches the PCB …_Horizontal footprint. The schematic's …_Vertical is stale and absent from the library (ERC footprint_link_issues). J10 C12074 HR911105A: schematic lib nickname Connector_RJ45 is not configured (PCB Connector_RJ). Cost at stake per board: J10 $1.20 / $0.92, P11+P12 $0.35 / $0.28 (qty 20 / 100). With J10 DNP the populated W5500 block (U11, U12, Y1, C90–C103; ≈ $2.5) has no connector.
  • Fix: decide intent. Set the schematic footprints to …_Horizontal and Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal, and put the DNP flags in the schematic so Update-PCB and the BOM agree. If Ethernet is not fitted on v6, DNP U11/U12/Y1 and their passives too (A-05 wants U12 gated anyway).
  • Effort: schematic-only
  • Confidence: high

H-07 Crystal load capacitors do not match the crystals' 20 pF CL (Y1 W5500 18 pF → +70…+130 ppm)

  • Severity: Minor (Y3/Y4 detail in D-02/D-03)
  • Evidence: Y1/Y3 C14872 X49SM25MSD2SC: 25 MHz, CL 20 pF, ±20 ppm, −20…+70 °C. Y1 caps C95/C96 18 pF → CL_eff = 9 + ~4 pF stray = 13 pF. Pulling Δf/f = (C1/2)·[1/(C0+13) − 1/(C0+20)] with C0 3–5 pF, C1 8–15 fF gives +69…+129 ppm, against IEEE 802.3 100BASE-TX ±50 ppm. Y2 C2238 3.6864 MHz CL 20 pF with 22 pF caps (+~50 ppm, irrelevant for UART). The −20…+70 °C crystal rating is below a sealed port box's internal temperature.
  • Consequence: Ethernet link margin (most PHYs tolerate ~±100 ppm total, so it probably links, as on V5.5), and frequency drift above 70 °C.
  • Fix: Y1 caps → 33 pF C0G C1663 (Basic): CL_eff = 16.5 + 4 ≈ 20 pF. Better: Y1 → a 3225 CL 10–12 pF −40…+85 °C crystal with 12–15 pF caps (the same family as D-02's Y3 choice), which also fixes F-11.
  • Effort: schematic-only (caps) / both (3225)
  • Confidence: medium (C0/C1 are typical HC-49S values; the YXC PDF is not fetchable here)

H-08 Value-field / BOM mismatches

  • Severity: Minor
  • Evidence: C22 "22uF/50V" but C138687 is 10 µF 50 V X7R 1210 (known since V5; the BOM is master). Y2 "1.8432MHz" but C2238 is 3.6864 MHz (= D-16). U10 "SC16IS752IPW" but C729142 is SC16IS762 (H-02 fixes it). C103 "100uF/6.3V" but C88744 is 35 V (harmless). C130/C131/C78 "220uF/10V" but C2827940 is 16 V, 85 °C/2000 h general-purpose (life/ripple = A-09, Major there).
  • Fix: correct the value fields (C22 → "10uF/50V", or pick a real 22 µF/50 V 1210 if 22 µF was intended; Y2 → "3.6864MHz").
  • Effort: schematic-only
  • Confidence: high

H-09 BOM completeness, DNP list, test points, stale symbols: pass, with details

  • Severity: Note
  • Evidence: every fitted BOM line has an LCSC number except TP1–TP8 (copper test pads, no part, correct) and PF1–PF21 (virtual). DNP in the schematic: C146/C147 (LTE π, no LCSC), R107/R108, R124/R125, R127–R130 (0 R, LCSC present), U22. On the PCB also J10/P11/P12 (H-06). JP1–JP5 are excluded from BOM/CPL. F2 now C206910 (Littelfuse 0154002.DR 2 A/125 V NANO2 + holder, matches Fuseholder_Littelfuse_Nano2_154x). Stale symbols: the 10 "not found" (Q_PMOS_GDS ×2, Q_PMOS_GSD, Q_NMOS_GSD ×4, D_Zener_ANK ×2, PCF8574) and 22 "differs from library" symbols were checked pin → pad → net against the part datasheets on 25 parts. IRFR5305 DPAK 1 = G, 2 = tab = D (/24V_IN, /VIN_FUSED), 3 = S ✅; AO3401A/AO3400A/2N7002 SOT-23 1 G, 2 S, 3 D ✅; BZX84C15 1 A, 3 K (cathode on /24V, /VIN_PROT) ✅; PCF8574T SO-16W 1–3 A0–A2, 8 VSS, 14 SCL, 15 SDA, 16 VDD ✅; TPS54360B 1 BOOT…8 PH ✅; AMS1117 1 GND, 2/tab OUT, 3 IN ✅; diodes D5/D6/D10/D21/D22/D2 K on pin 1 ✅. No hidden pin mismatch. Current-sense/power resistors: RS1 10 mΩ 1 W at 2.5 A → 62.5 mW (6 %) ✅. Rig1 22 k 0603 at 58 V → 0.15 W > 0.1 W (D-06).
  • Fix: none beyond H-01…H-08.
  • Confidence: high

H-10 Cost: ≈ $132 (qty 20) / $124 (qty 100) per board in parts; +$91 vs V5.6, 94 % of it ZED-F9P + A7670SA; 79 Extended parts = $237 setup per order

  • Severity: Note
  • Evidence (DB price breaks at the per-board quantity × board count; bom_check.csv):
    • v6 fitted parts: 284 placements (schematic BOM less DNP, including J10/P11/P12). Qty 20: $131.98/board. Qty 100: $124.40. Modules: ZED-F9P-04B $80.11 (flat) + A7670SA-LASC $6.07 = $86.18. Everything else: $45.80 at qty 20.
    • V5.6 (same method, ref_versions/v56_components.csv, 235 placements): $40.69 (qty 20) / $33.83 (qty 100). Delta +$91.30 / +$90.14 per board. The main additions are F9P $80.11, A7670SA $6.07, F2+holder $1.10, 2 × 74LVC2T45 $0.82, L22 $0.72, U25 $0.56, D21 $0.39, J14 $0.36; removed are 2 × 220 µF polymer, 2 × TMP102, 2 XBee sockets, USBLC6, SW4G1 (−$1.9).
    • The board delta excludes what v6 removes from the unit: the ArduSimple simpleRTK2B (its own ZED-F9P) and the 4G NTRIP Master. The system cost almost certainly drops (Inputs needed).
    • Setup: 79 unique Extended parts × $3 = $237/order ($11.85/board at 20, $2.37 at 100). The DB flags only 351 parts Basic; some here are Basic at JLC in reality (e.g. C1589 10 nF). Cheap consolidations: C14676 → C21190 (1 k 1 % Basic), C14675/C103211 → C25803, C304185 → C21189 (0 R Basic): −4 fees.
    • A7670SA at $6.07 looks low for this module. Treat it as a DB snapshot price and confirm at order.
  • Confidence: medium (DB snapshot prices, excl. PCB/assembly/THT fees)

J-01 DRC "0 errors" is produced by the rule set, not by the copper

  • Severity: Major (process; the rule fix itself is F-01 Blocker)
  • Evidence: DRC ran with "Minimum clearance 1" = 0.15 mm overriding every class (F-01). With the corrected netclasses and DRU: 6 inner-layer errors (all /IGN_IN, F-02) + 15 outer-layer errors at the 0.3 mm rule (38 at 0.5 mm), plus ≈ 178 zone-fill proximities that disappear on refill. If Default = 0.2 mm were enforced without the floor rule: +471 pairs. An RF class added now would also be silently overridden by the 0.15 mm rule.
  • Fix: F-01 rules → refill → DRC. Accept only after the new DRC is clean (the T15 width warnings excepted per J-02).
  • Effort: rules + layout
  • Confidence: high

J-02 track_width warnings: 59 real (power paths under-sized for their current), 124 benign (T15 rule over-strict)

  • Severity: Major (the copper fix for /SW_BAT, /BAT_PLUS, /VEH5V, /VIN_SW is A-02/A-07; the modem nets are block B)
  • Evidence (IPC-2221, 1 oz, 10 °C rise: 0.25 mm ext 0.88 A / int 0.44 A; 0.5 mm ext 1.45 A / int 0.72 A; 0.8 mm ext 2.03 A):
    net DRC hits widths (mm) est. current verdict
    /SW_BAT 6 0.25/0.3/0.5 ~4 A backup boost real (2 hits; 4 are ≤ 1.5 mm pin necks)
    /BAT_PLUS 4 0.25/0.5 2.4 A charge / ~4 A backup real
    /MAIN5V 21 0.3/0.5 2.5 A real (19)
    /VEH5V 15 0.25–0.8 (incl. In1) 3 A real (11)
    /VIN_SW 10 0.25–0.8 (incl. In2) 2.5 A real (8)
    /VIN_MODEM 9 0.3/0.5 1.9 A on battery real (8)
    /VBAT_MODEM 7 0.25/0.5 (incl. In1) 2 A bursts real (7)
    /3V3_ETH 54 0.25–0.5 (In1) 0.15 A benign: move the net to Default
    /5V_FAN, /FAN_RET, /SW_FAN 14/7/8 0.5 ≤ 0.3 A benign
    /SW_5V, /SW_IN 9/7 0.3/0.5 0.2 A benign
    /SYS5V 6 0.5/0.8 ~0.6 A benign
    /VIN_PROT, /VIN_FUSED 5/1 0.5 0.8 A at 24 V benign (current); keep the 0.8 mm rule for pulse/fuse coordination
    Per-item classification in ercdrc_classified.csv.
  • Fix: widen/pour the seven real nets (targets per A-02/A-07 and block B: /SW_BAT ≥ 2 mm pour, /BAT_PLUS ≥ 1.5 mm, /MAIN5V//VEH5V//VIN_SW ≥ 1.5 mm or F.Cu pours, /VBAT_MODEM ≥ 1.5–3 mm, /VIN_MODEM ≥ 0.8 mm). Relax T15 for the benign nets so the warning list becomes a clean gate.
  • Effort: layout
  • Confidence: high (widths); medium (current estimates, stated per net)

J-03 ERC pin-to-pin (104) are pin-type noise; no real driver conflict

  • Severity: Minor
  • Evidence: all 104 involve pins typed unspecified in easyeda-imported symbols (U19, U20, U23, U24, U26, D21, D22, D27, D28, J12, J13): 50 Unspecified–Passive, 46 Unspecified–Unspecified, 5 –Bidirectional, 2 –Power output, 1 –Input. Net-by-net check found no conflict. U23 DIR (pin 5) = GND (B → A: /DIN_4G → /DIN_4G_M), U24 DIR = VCCA (A → B: DOUT_4G_M → DOUT_4G, MODEM_STATUS_M → MODEM_STATUS); unused channel inputs tied (U23.6 B2 = GND); single drivers on every UART/status net; Q20/Q21 open drain.
  • Consequence: 104 standing warnings hide the next real one.
  • Fix: retype pins in Drogheda-v6.kicad_sym (power_in/power_out/input/output/passive). ERC then shows only real items.
  • Effort: schematic-only (library)
  • Confidence: high

J-04 ERC cosmetics: 23 orphan NC flags, 4 NC flags on connected pins, 2 wire stubs, 10 symbols missing from KiCad 10 libs, 22 lib-mismatched symbols

  • Severity: Minor
  • Evidence: orphan NC flags at x = 453.898 (13) and 484.378 mm (10), left from the deleted SimpleRTK2B socket. NC flags on connected pins U16.37/38 (USART6) and U10.13/14 (I2C), with the nets connected in the netlist (= D-11). Wire stubs at P1.4 and R52.2; both pins are GND in the netlist, so these are dangling extra segments (uuid 2b755f7f…, 46f71e27…, 7c1dbfc0…). Lib issues and mismatches: pin maps verified (H-09).
  • Fix: delete flags/stubs. Copy the 10 missing symbols into Drogheda-sym and re-link. Leave the 22 mismatches (do not bulk-update).
  • Effort: schematic-only
  • Confidence: high

J-05 Ignored DRC checks and library-mismatch warnings hide nothing real today

  • Severity: Note
  • Evidence:
    • missing_courtyard: only MH5–MH8 lack one.
    • footprint_type_mismatch: JP1–5 and TP1–8 are attribute "unspecified" with SMD pads. JP1–5 are excluded from BOM/CPL; TP1–8 are in the CPL without LCSC, so JLC ignores them. U19/L22 are now smd ✅ (pre-fab B2).
    • track_not_centered_on_via: 178 track ends inside a via pad but off-centre (up to 0.40 mm), all connected per union-find.
    • footprint_filters_mismatch, tuning_profile: no tuned nets.
    • lib_footprint_mismatch 82: KiCad 10 library revisions. lib_footprint_issues 4: MountingHole nickname not in fp-lib-table.
  • Fix: re-enable footprint_type_mismatch after setting TP1–8 to SMD + "exclude from BOM". Do not run "Update footprints from library" (it would swap P11/P12 and reset pads).
  • Confidence: high

Pass checks

Check Evidence (one line) Result
/24V_IN (only HV24 net) clearance ≥ 0.500 mm to everything on all 4 layers ✅
Switch nodes only on outer layer SW_PWRIN/SW_FAN/SW_MODEM/SW_BAT/ETH_SW F.Cu-only ✅
U20 VIN cap, BST, L20 placement C128 0.72 mm, C129 1.8 mm, L20 2.24 mm ✅
U25 BST cap, FB/COMP/RT C152 1.49 mm; R122 1.0, R121 2.9 mm; FB net 4.1 mm ✅
U2 FB divider (ECO §E.3) R20 0.67 / R21 1.48 mm from U2.4; FB net 4.1 mm ✅
Crystal ↔ inductor ≥ 10 mm nearest 13.6 mm (Y1–L8) ✅
GNSS island ↔ switchers ≥ 25 mm U18 body + RF_GNSS to nearest SW copper: /ETH_SW 27.5 mm, L8 35.3 mm, /SW_FAN 54.1 mm, others ≥ 77 mm ✅
RF_GNSS/RF_ANT_* over a solid plane 0 slot crossings on In1 ✅
DFU ESD at J11 2.5–6.1 mm pad edge (V5.5: 41 mm) ✅ (stubs: F-14)
Courtyard overlaps real 0 of 15 (polygon intersection 0.000 mm²) ✅
Dangling track ends 1, benign (F-21) ✅
Board outline / holes 140 × 100 mm, 4 MH + 2 NPTH, corner gaps ≤ 2.5 µm ✅
Min track/space/drill vs JLC 0.20/0.15/0.30 mm vs 0.09/0.09/0.15 ✅
J9/J11 PTH ring & hole spacing 0.15 mm / 0.45 mm = JLC minimum ⚠
Thermal vias in regulator EPs 0 in U6/U25/U20/U2/U12 ❌ F-13
Module GND vias (U19/U18) 1 / 0 under bodies ❌ F-04
In1 plane integrity 8 islands, 19 % void, 1572 mm tracks ❌ F-05
Via stitching / edge fence 69 GND vias, 2 at the edge ❌ F-12
Netclasses resolve 1 of 14 HV nets in HV24; RF/PWR_MODEM missing ❌ F-01
Every fitted BOM line has LCSC all except TP1–8 (pads) ✅
LCSC parts exist in the JLC DB 121/121 found ✅
Stock for 20 boards U10 15, R53 6 ❌ H-02
Package ↔ footprint 1 hard mismatch (U15), 4 land mismatches (MWSA0804S) ❌ H-01/H-03
Ceramic voltage margin on 24 V all ≥ 50 V (≥ 1.8× at 28.8 V) ✅
Sense resistor rating RS1 62.5 mW of 1 W ✅
Stale symbols hide pin errors 25 parts checked, 0 mismatches ✅
U19/L22 fab attribute both smd ✅
F2 part number C206910 (was TBD) ✅
ERC errors / DRC errors 0 / 0 (DRC not meaningful: J-01) ⚠

Review-vs-Lessons §4 checklist items re-verified

# Item Status now Evidence
1 U6 copper + EP vias + re-cluster ❌ improved placement, copper and vias unchanged L6 → U6.21/22 10.65 mm ctr (was 15.2); EP 0 vias; /SW_BAT 0.25–0.5 mm (DRC 6 hits); C30/C31 7.2/6.2 mm edge (A-02)
2 U25 set-point + re-cluster ❌ placement improved, loop still open L22 17.0 mm ctr (25.9), D34 6.6 (18.2), C150 5.1 / C149 8.5 ctr; Cin GND on a different F.Cu island (F-03); R121 still 53.6 k (A-04)
4 Modem rail layout ❌ /VBAT_MODEM 0.25/0.5 mm (7 real DRC hits), 6.3 mm on In1; /VIN_MODEM 0.3/0.5 (8 real); U20 GND neck (F-07); bulk distances = block B
7 J9 USB ESD ❌ still none nets /USB_DP/DM/VBUS = J9 + U19 only (G-02)
10 F2 part number / F1 size ✅ F2 / ⚠ F1 F2 = C206910 NANO2 2 A in holder; F1 still 3 A PPTC C20627123 (A-block)
§2 Switcher EP vias (U20, U25) ❌ 0 vias in both EPs; both EPs on thermal spokes (13–18 %) (F-13)
Pre-fab B2 U19/L22 attribute ✅ both smd
Pre-fab B3 LCSC on all parts ✅ (except TP pads) 0 fitted lines without LCSC
Pre-fab B4 J14 pre-order ⚠ open C2977286 still in "Pre-ordered Products"
Pre-fab B5 Switcher placement ❌ partly improved U25/U2/U12 loops (F-03, F-08, F-09); U20 ✅ except GND neck
Pre-fab B6 Power widths ❌ 59 real width hits (J-02)
Pre-fab §7 RF_LTE on In1 ❌ unchanged 22.1 mm In1 (F-06)
Pre-fab §7 USB pair on one layer ❌ unchanged DP In1 / DM In1+In2 (F-17)
Pre-fab §7 Silkscreen size ❌ unchanged 304 refs at 0.5/0.1 mm (F-18)
Pre-fab §7 Stubs ✅ 1 benign end (F-21)
ECO §E.1/§E.2 SW_BAT/BAT_PLUS ❌ see #1
ECO §E.3 Fan FB divider at U2.4 ✅ 0.67/1.48 mm, FB net 4.1 mm (but U12 now repeats the pattern: F-09)
ECO §E.4 Cin loops < 3 mm ⚠ U20 0.72 ✅, U25 2.88 (VIN) but GND split ❌, U2 20.8 ❌, U12 1.77 (VIN) / GND island split ❌
ECO §E.5 DFU ESD at J11 / J9 ESD ✅ / ❌ F-14, G-02
ECO §E.6 Crystals ≤ 5 mm; stitching cells ❌ Y1 13.7/10.8, Y3 8.3/11.3 mm; 10 empty 20 mm cells (F-11, F-12)

Requirements input R1–R5

  • R1 (10-min cycle on battery, report): layout input needed. The backup boost feedback routing (F-10/A-14) and the modem power path copper (J-02 /VIN_MODEM, /VBAT_MODEM, /MAIN5V; F-07) must be fixed so the boost holds regulation during a cold modem start. H-02 (R53 out of stock) must be fixed or the boost set-point resistor is missing. H-03 (L6/L20 land) matters for durability.
  • R2 (MCU control of the modem): no layout/BOM item from these blocks.
  • R3 (report on battery): same as R1, plus modem RF/grounding (F-04, F-06) for link quality at the cycle edge.
  • R4 (thermal management): needs change F-13 (EP vias/solid pads on U6, U25, U20) and F-04 (U19 heat into the planes); sensors are the power auditor's (F-51/F-52).
  • R5 (EMC list of the second batch): needs changes F-03, F-05, F-06, F-07, F-08/A-01, F-09, F-11, F-12, F-14 and G-02 (J9 ESD). v6 does not meet ECO §E as laid out.

Firmware implications (things board_v6.h / FW 0.7.x must do)

  • None of F/H/J forces a pin change. Consequences of the choices above:
    • If Y4/Y3 keep their current caps (D-02/D-03/H-07), use LSE high-drive (LSEMOD) and allow for +40…+130 ppm; RTC smooth calibration can trim LSE.
    • If H-01 is not fixed, RS-232 (P12 via U15) is dead. The firmware must not depend on it, and the self-test should report rs232=absent.
    • U10 swap SC16IS762 → SC16IS752 (H-02): register-compatible per memory. Keep XTAL_FREQ = 3686400 (Y2 = 3.6864 MHz, not the 1.8432 MHz label).
    • Bench/G3: log modem TX power vs F9P C/N0 before and after F-04/F-06 to confirm desense is gone.

Inputs needed from Leo

  1. Fab stackup and impedance control: confirm JLC04161H-7628 (assumed for F-06 numbers) and whether controlled impedance is ordered.
  2. Order quantity for v6 (20 vs 100) decides whether U19/U18 must be pre-ordered (H-02).
  3. Is Ethernet (J10) and are RS-485/RS-232 (P11/P12) fitted on v6? (H-06, H-01.)
  4. Do the V5.5 boards have a soldered U15? (MAX3232ESE on the wide footprint.) A continuity check on P12 would settle the history of H-01.
  5. Enclosure internal temperature at 45 °C ambient, for the crystal (−20…+70 °C) and electrolytic ratings (H-07, A-09).
  6. Unit purchase prices of the ArduSimple simpleRTK2B and 4G NTRIP Master (500-unit order), for a system-level cost delta (H-10).
  7. Fan current (assumed ≤ 0.3 A in J-02).