235 lines
11 KiB
Markdown
235 lines
11 KiB
Markdown
---
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tags: [project-drogheda, hardware, pcb, kicad, jlcpcb, guide, how-to]
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project: Project Drogheda
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author: Helgen CTO
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date: 2026-06-21
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status: Active — working guide
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---
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# KiCad → JLCPCB: build & deploy the Watchdog Carrier PCB v3
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> A from-zero, do-this-then-that guide for capturing the
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> [[03-Architecture-Hardware/watchdog-pcb-v3-design|v3 design]] in **KiCad** and getting it
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> **assembled by JLCPCB**. Written for someone who has done PCB work *a long time ago*.
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> The schematic content (every net, part, value) lives in the design doc and the
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> [[03-Architecture-Hardware/watchdog-pcb-v3-bom|BOM]] — this is the *tooling* path.
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---
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## 0. Pick your path (read first)
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You have two realistic routes to a JLC-assembled board. Both end at the same place.
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| Path | Best when | Trade-off |
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|---|---|---|
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| **A — KiCad** (this guide) | you want a proper, version-controllable design you own outright | steeper, but the right long-term tool; offline; git-friendly |
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| **B — EasyEDA (Std/Pro)** | you want the *fastest* first board with least friction | JLC-native: every part already carries its **LCSC number + footprint**, and "Order at JLCPCB" is one button. Less portable. |
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**My recommendation for *this* board, given you're newer to PCB and going JLC-assembly:**
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do **Path A (KiCad)** because you'll iterate this board for the fleet and want to own it —
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but if you feel stuck on footprints/part-matching, **Path B (EasyEDA) is a legitimate
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shortcut** and uses the exact same LCSC parts in our BOM. Don't lose a week to tooling.
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The rest of this doc is Path A.
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---
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## 1. Install KiCad + two plugins
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1. **KiCad 9 or 10** (current 2026) from kicad.org → install the full suite.
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2. Open KiCad → **Plugin and Content Manager** (button on the home screen) and install:
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- **Fabrication Toolkit** (by *bennymeg*) — one-click export of Gerbers + **BOM + CPL**
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already in JLCPCB's format. This is the deploy button.
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- **JLCPCB Tools** (*Bouni / kicad-jlcpcb-tools*) — lets you assign the **LCSC part
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number** to each component from inside KiCad and query JLC stock. This is how the BOM
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parts get matched.
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> Both are free, in the official plugin manager. With these two, you never hand-edit a
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> JLC CSV.
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---
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## 2. The mental model (the whole workflow in one picture)
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```
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Symbols + wires Footprints Place + route One-click export
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(Schematic editor) ──► (per component) ──► (PCB editor) ──► (Fabrication Toolkit)
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│ │ │ │
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ERC ✓ "what each part DRC ✓ Gerbers.zip + bom.csv
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(no missing nets) physically is" (no shorts/ + positions.csv ──► JLCPCB
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clearance) upload + assemble
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```
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You always go **left to right**. Don't start routing until the schematic passes ERC.
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---
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## 3. Create the project
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1. **File → New Project** → name it `hbox-watchdog-v3`. Save it **inside the repo** at
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`03-Architecture-Hardware/` (or a new `kicad/` subfolder) so it's version-controlled.
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2. You get `.kicad_sch` (schematic) and `.kicad_pcb` (board). Open the **Schematic Editor**.
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---
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## 4. Draw the schematic
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Work **one sub-circuit at a time**, matching design-doc §4. Use **net labels**, not long
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wires — it keeps things readable.
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### 4.1 Place the power symbols first
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Add power ports (the "place power symbol" tool): **+24V, +5V (main), +5V_FAN, +3V3, SW_5V,
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GND**. Every supply/return connects to these by name — no need to draw rails across the page.
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### 4.2 The Blackpill (the trick that saves you)
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You are **not** designing the STM32 chip — the Blackpill module plugs into **two 1×20
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headers**. So represent it as **two `Conn_01x20` connector symbols** (or grab a ready
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"WeAct Blackpill" symbol from a community KiCad library — search GitHub for "Blackpill
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KiCad library"). Label each pin with its **net name from design-doc §2** (PA0=BAT_SENSE,
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PA1=PWR_CTRL, PA6=FAN1_PWM, PB6=I2C1_SCL, …). The header footprints become the socket the
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module sits in. This avoids all MCU bring-up.
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### 4.3 Drop in each sub-circuit (design-doc §4)
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For each, place the symbols, wire locally, and tie to power/net labels:
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- **Input + fan buck (§4.1–4.2):** Q10 (AO3401A), D10 TVS, C10/C11; then U2 **MP1584EN** with
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L2, C22, C23, the FB divider R20/R21, and **JP1** (solder-jumper symbol).
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- **Load switch (§4.3):** Q1 AO3401A + Q5 MMBT3904 + R1/R2 + **F1 PPTC** + C3. Net the drain to
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**SW_5V**. (Optional U1 eFuse footprint — leave it **DNP**.)
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- **Fan driver ×1 (§4.4):** Q2 AO3400A, D2 SS34 flyback, Rg/Rgs gate parts, tach
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pull-up + series into **PB10**. PWM gate from **PA6** (PA7/PB12 left as spares).
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- **Sensors (§5):** U3 SHT40 + U4 TMP102 on **PB6/PB7**, 4.7k pull-ups, 100nF each.
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- **Sense + LED (§4.5–4.6):** the three 10k/10k dividers (PA0/PA4/PA5), D5 clamp, Q4 + D1 + R3.
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- **Connectors (§6):** P1–P6 + P8, H1, H3 (DNP), and the two 2×20 sockets.
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### 4.4 Annotate + ERC
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- **Tools → Annotate** (gives refs R1, U2, …).
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- **Inspect → Electrical Rules Check.** Fix every error (usually an unconnected pin or a
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missing power flag). **Schematic is not done until ERC is clean.**
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---
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## 5. Assign footprints
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Open **Tools → Assign Footprints** (or the Footprint Assignment tool). Map each part to a
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JLC-friendly footprint:
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| Part type | Footprint |
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|---|---|
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| Resistors / caps | `Resistor_SMD:R_0603_1608Metric` / `Capacitor_SMD:C_0603_1608Metric` (C3/C22/C10 → 0805/1206/elec) |
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| AO3400A / AO3401A / MMBT3904 | `Package_TO_SOT_SMD:SOT-23` |
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| SS34 | `Diode_SMD:D_SMA` (DO-214AC) |
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| MP1584EN | `Package_SO:SOIC-8-1EP_…` (the EP/thermal-pad variant) |
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| SHT40 | `Sensor:Sensirion_DFN-4-1EP_…` (or import from LCSC — see below) |
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| TMP102 | `Package_SON:SOT-563` (or import from LCSC) |
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| JST-XH | `Connector_JST:JST_XH_B*` (B4B/B2B etc.) |
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| Headers | `Connector_PinHeader_2.54mm:…` (1×4, 1×3, **2×20** for the sockets) |
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**For the odd parts (SHT40, TMP102, MP1584, JST):** the **JLCPCB Tools** plugin can pull the
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**exact LCSC footprint** so it matches the assembler perfectly. Or use the classic trick:
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on **easyeda2kicad** / the JLC part page, grab the EasyEDA footprint and import. Either way,
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**verify pin-1 orientation** against the datasheet.
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---
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## 6. Lay out the PCB
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1. Open the **PCB Editor** → **Update PCB from Schematic** (pulls in all parts + the
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ratsnest of connections).
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2. **Board outline:** draw a rectangle on `Edge.Cuts` (~100 × 80 mm is plenty). Put the
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**mounting holes** so the board can bolt to the cabinet **metal plate** (design-doc §8 —
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that's your conduction path).
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3. **Place by functional block** (keep each §4 sub-circuit together): power-in + buck in one
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corner, load switch near P3, fan driver near P6, sensors near an air edge / P5, the
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Blackpill sockets central, connectors on the edges.
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4. **Stackup:** 2-layer is fine (cheaper); **4-layer** is better for RF/buck noise. Add a
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**ground pour** (filled zone = GND) on the bottom (and an inner layer if 4-layer).
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5. **Route** (design-doc §8 rules): power/5V ≥0.5 mm, **SW_5V ≥0.8 mm** (modem bursts),
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signals 0.25 mm. **Keep the MP1584 switch node + fan-PWM traces away from the GNSS
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antenna pigtail.** Star-ground the pulsed (fan/modem) returns separately from the ADC/
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sensor ground.
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6. **DRC** (**Inspect → Design Rules Checker**). Zero unrouted, zero clearance errors.
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7. Add **silkscreen labels** on every connector (net names) + pin-1 arrows, and a board
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title/rev. (Serviceability requirement.)
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---
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## 7. Tell JLC which physical part goes where (LCSC numbers)
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Open the **JLCPCB Tools** plugin. For each component, set its **LCSC field** to the code in
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the BOM (e.g., AO3400A → `C347222`, SHT40 → `C2909890`, TMP102 → `C99269`). For the
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**yellow "verify" parts** in the BOM, search the plugin's parts DB live and pick an in-stock
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equivalent. Mark **U1 (eFuse)** and **H3 (USART1 reserve)** as **DNP / "Do not place."**
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> This step is what makes assembly "just work" — the assembler places exactly these LCSC
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> parts. The **Blackpill, the 2×20 sockets, and the GX16 wiring you hand-solder yourself**
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> (mark them DNP for JLC, or "PCBA: no").
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---
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## 8. Export (the deploy button)
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Run **Fabrication Toolkit** (Tools/External-plugins menu in the PCB editor). One click
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produces a `production/` folder with:
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- **Gerbers + drill**, zipped — the board.
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- **bom.csv** — Designator, Footprint, Qty, Value, **LCSC** — already JLC-formatted.
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- **positions.csv (CPL)** — Designator, Mid X/Y, Rotation, Layer — already JLC-formatted.
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No hand-editing. (If you ever do it manually: Plot Gerbers with JLC's layer settings, then
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generate BOM + CPL — but the plugin removes that pain.)
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---
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## 9. Order on JLCPCB
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1. **jlcpcb.com → Add gerber file →** upload the Gerber **.zip**. Confirm the preview looks
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like your board.
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2. Set basics: layers (2 or 4), 1.6 mm, HASL or ENIG, qty **5**.
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3. Toggle **PCB Assembly = ON**. Choose **Economic** (cheaper, top-side only is fine here)
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and **assembled qty 2–3**.
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4. Upload **bom.csv** and **positions.csv** when prompted. JLC matches LCSC parts → fix any
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"not found" by picking an in-stock alternative (this is why we kept to Basic parts).
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5. **Review placements** carefully — **the #1 beginner bug is wrong part rotation** on
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SOT-23 / SOIC / connectors. Check each against the datasheet pin-1; rotate in the review
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tool as needed.
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6. Confirm DNP parts (U1, H3) are excluded. Place the order.
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Lead time ~1–2 weeks to Mexico. Hand-solder the Blackpill, the 2×20 sockets, and the GX16
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pigtail when it arrives.
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---
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## 10. First-board gotchas (the stuff that bites beginners)
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- **Rotations**: JLC's 0° reference often differs from KiCad's. Always eyeball the placement
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preview; SOT-23 and electrolytics are the usual offenders.
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- **Polarity**: double-check D10 TVS, C10 electrolytic, D2 Schottky, the LED, and Q10/Q1
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source/drain before ordering.
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- **The buck (U2)** is the only "real" analog block — if you're nervous, **populate JP1
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closed + upsize the 5 V supply** and leave U2 unpopulated for the first spin (design-doc
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§4.2). One board, two options.
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- **Don't let JLC place the Blackpill or the GX16** — those are hand-soldered.
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- **Order 1–2 spare bare boards** for hand-rework experiments.
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- **Conformal-coat** after you've tested it (mask the SHT40 slot + connectors).
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---
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## 11. Pre-order checklist
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- [ ] Schematic **ERC clean**; every Blackpill pin labelled per design-doc §2.
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- [ ] All footprints assigned; SHT40/TMP102/MP1584/JST verified against datasheet pin-1.
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- [ ] PCB **DRC clean**; GND pour stitched; SW_5V wide; buck/fan noise away from GNSS feed.
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- [ ] Mounting holes positioned to bolt to the cabinet metal plate.
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- [ ] LCSC numbers set on all placed parts; **U1 + H3 = DNP**; Blackpill/GX16 = hand-solder.
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- [ ] Fabrication Toolkit exported Gerbers + BOM + CPL.
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- [ ] JLC placement preview rotations checked.
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- [ ] Bench-test plan ready (design-doc §9) — **especially the §0a 5 V-rail sag test** before
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you trust it in a cabinet.
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## Related
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- [[03-Architecture-Hardware/watchdog-pcb-v3-design|v3 design (schematic spec)]] ·
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[[03-Architecture-Hardware/watchdog-pcb-v3-bom|v3 BOM (LCSC parts)]] ·
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[[03-Architecture-Hardware/watchdog-schematic|as-built watchdog]] ·
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[[CLAUDE|Master Index]]
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