Drogheda/03-Architecture-Hardware/watchdog-production-schematic-delta.md

title	tags	project	author	date	status	supersedes
Watchdog v3 — Production Schematic Build Spec (delta from the prototype)	project-drogheda hardware watchdog schematic production delta build-spec	Project Drogheda	Helgen CTO	2026-06-25	Active — build spec for the PRODUCTION schematic (proto file = current; this = what to add/change)	reconciles watchdog-connections.xlsx (Jun23) + watchdog-pcb-v3-bom.xlsx with the Jun-24 canonical state

Watchdog v3 — Production Schematic Build Spec (Δ from prototype)

Why this exists. Decision (2026-06-25): the current kicad/hbox-watchdog-v3.kicad_sch is the PROTOTYPE (module buck, no battery). This doc is the delta to build the PRODUCTION schematic on the copy kicad/hbox-watchdog-v3-PROD.kicad_sch. It is the single reconciled definition — the connection list (Jun 23) and the v3 BOM predate the Jun-24 battery re-add, so they are not on their own a production spec. Authority order: watchdog-electrical-design-state (CANONICAL) > design doc > BOM/connection-list. Build against this file.

Build status (2026-06-25) — Blocks A / C / D BUILT on PROD

Built on kicad/hbox-watchdog-v3-PROD.kicad_sch via the KiCad MCP. ERC = 0 errors; ~20 cosmetic warnings remain (off-grid auto-placement, reserved-pin NC flags now legitimately used, and L/SW_Push/ Q_NPN_BCE symbol-cache mismatches) — all clear during layout positioning + Tools→Update Symbols from Library.

• Block A — discrete buck — DONE. Replaced the 3-pin U2 module with a custom MP1584EN symbol (Drogheda-sym.kicad_sym; datasheet pinout 1=SW 2=EN 3=COMP 4=FB 5=GND 6=FREQ 7=VIN 8=BST, registered in the project sym-lib-table). Wired: VIN←24V, SW→L2→5V_FAN, FB divider R20 100k / R21 19.1k (→5.0 V), C22 22µF in, C23 22µF out, Dbk SS34 freewheel (K→SW, A→GND), Cbst 10nF BST–SW. New support parts added beyond the original BOM (required for the discrete IC): Rfreq 100k (FREQ→GND, sets fsw), Rcomp 40.2k + Ccomp 2.2nF (COMP loop comp), Ren1 100k / Ren2 20k (EN UVLO divider — EN abs-max is 6 V, so it must NOT tie directly to 24 V). ⚠ Bench-tune (typical placeholders): Rfreq (target fsw), Rcomp/Ccomp (loop stability), Ren1/Ren2 (UVLO threshold).
• Block C — reset — DONE. SW1 (Switch:SW_Push) + P10 (2-pin ext) → NRST (J1.5) → GND.
• Block D — 4-LED gauge — DONE. RB1–4 330 Ω + DB1–4 LED on PB12–15 (J2.1–4) → GND.
• Cleanup: deleted 3 labels (24V/GND/5V_FAN) orphaned when the old U2 module was removed.
• Footprints: the new parts carry no footprint yet — assign at layout (same as the existing parts).
• Still deferred: Block B (LTC4040) + E (cutoff) + F (PA4→VEH5V). Pack Ah confirmed = ~12 Ah (2026-06-30) → LTC4040 sizing can proceed.

Build status (2026-07-02) — Blocks B / E / F / H / I capture session

LTC4040 sized to the 12 Ah pack (§4 values table — datasheet 4040fb formulas; internally compensated, no external comp). New Blocks H (K1 NC bypass relay, §5b) and I (NTC→PB1, §5c) specified from the Jul-2 assumptions ledger.

BUILT 2026-07-02 (all of B/E/F/H/I) — ERC = 0 errors, 62 cosmetic warnings (off-grid auto-placement + L/Q_NPN_BCE/SW_Push/AO4406A symbol-cache mismatches → clear during layout positioning + Tools→Update Symbols from Library). Capture notes:

• 37 new components, 107 pins netted; sheet bumped A4→A3; custom symbols LTC4040EUFD + AO4406A added to Drogheda-sym.kicad_sym.
• Rail split done: P2/R7/JP1 → VEH5V · F1/R2/J1-20/J2-18 → SYS5V (P11 cutoff between MAIN5V→SYS5V). JP1's alt rail is now VEH5V (vehicle 5 V, never battery-backed — a fan on the backed-up rail would drain the pack; refine of the old MAIN5V tie).
• P4 → 3-pos (BAT+, BAT−, NTC); legacy P4 GND stub wire cut, stale labels removed.
• Fixed a duplicated U2 (two MP1584 instances stacked at the same position — deleted both, re-placed one). Removed 10 stale no_connect flags on header pins that had gained nets.
• New MCU taps live: CHRG_EN J2/5 · CHRG_STAT J2/11 · CHRG_FAULT J2/12 · BYP_CTRL J2/13 · NTC_TEMP J1/15. §6.2 GNDREF note is stale — no placed GNDREF remains on PROD (verified).
• Footprints assigned at capture for all new parts except L6 (8040 inductor) and K1 (HFD23 relay) — assigned during layout kickoff.

Fab gate: bench validation of the LTC4040 backup transition + temp-qualified charge cutoff (unchanged).

0. What the prototype schematic already has (the shared core — DO NOT re-draw)

49 parts, ERC-clean. Present and correct on both boards: MCU (J1/J2), MAIN5V/3V3 rails, 24 V reverse-polarity (Q10 IRFR5305 + DzG 15 V Zener + Rrp), TVS D10 + C10/C11, RTK-stack high-side load switch (Q1 AO3401A / Q5 MMBT3904 / R1 / R2 / F1 PPTC / C3), the three sense dividers (BAT PA0, 5V PA4, IGN PA5) incl. on-board ignition chain (Rig + D5 BAT54 + C9), fan low-side driver (Q2 AO3400A + Rg + Rgs + D2 SS34), I²C temp/humidity (U3 SHT40 + U4 TMP102 + R30/R31), status LED (Q4 + D1 + R3 + Rled), connectors P1–P8, H3 (DNP).

The production board keeps all of the above unchanged except the two corrections in §6. Everything in §1–§5 below is added on top.

1. Production delta — summary

Block	Action	Status
A. Fan buck U2	Replace the 3-pin module placeholder with the discrete MP1584 circuit	✅ fully specified · BUILT
B. LTC4040 battery backup	Add charger + power-path + NTC; re-route P2→VEH5V→LTC4040→MAIN5V	✅ sized 2026-07-02 (§4 values table) — bench-validate before fab
C. Reset	Add SW1 (on-board) + P10 (external) → NRST	✅ fully specified · BUILT
D. 4-LED battery gauge	Add D_BAT1–4 + 4×330 Ω on PB12–PB15	✅ fully specified · BUILT
E. Power cutoff	Add P11 series switch in the post-merge 5 V (kills vehicle and battery)	✅ node defined (MAIN5V→SYS5V, §5)
F. Corrections	Move PA4 sense tap to vehicle side (VEH5V); finish GND unify	✅ do on both boards
G. H1 SWD	DROP (rely on USB-C flash + USB log); optional DNP 4-pad footprint	✅ decided 2026-06-25
H. Modo-B fail-safe bypass	Add K1 NC signal relay in the uplink (F9P TX2→4G DIN); MCU energizes to insert	✅ specified 2026-07-02 (§5b)
I. NTC→PB1 hot-spot temp	Add P12 NTC connector + 10 k (1 %) divider + 100 nF on PB1 (block 11)	✅ specified 2026-07-02 (§5c)

2. New Blackpill pins consumed (WeAct pinout, design §2a)

Pin	Header	Net	Use
PA8	J2/5	CHRG_EN	LTC4040 CHGOFF — MCU cuts charge when TMP102/PB1 reads cell hot (100 k pull-down = enabled by default)
PB12	J2/1	BATLED1	gauge 25 % (was reserved 2nd-fan-tach spare → reassigned)
PB13	J2/2	BATLED2	gauge 50 %
PB14	J2/3	BATLED3	gauge 75 %
PB15	J2/4	BATLED4	gauge 100 %
NRST	J1/5	NRST	reset (SW1 + P10)
PB1	J1/15	NTC_TEMP	[NEW 2026-07-02] analog hot-spot temp (ADC1_IN9), block 11
PB3	J2/11	CHRG_STAT	[NEW] U6 CHRG open-drain, 100 k↑3V3 (LOW = charging)
PB4	J2/12	CHRG_FAULT	[NEW] U6 FAULT open-drain, 100 k↑3V3 (LOW = NTC/bad-battery fault)
PB5	J2/13	BYP_CTRL	[NEW] K1 relay driver via Q6 (HIGH = MCU in-line on the Modo-B uplink)

No peripheral conflict: PB12–15 plain GPIO; PA8 plain GPIO; NRST is the module reset pin.

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3. Block A — Discrete fan buck (replace U2 module) ✅

Remove: the U2 = Conn_01x03 placeholder ("MP1584 mod"). Add (values from design §4.2 + production BOM):

Ref	Value / MPN	Pkg	LCSC	Note
U2	MP1584EN	SOIC-8-EP	C107226	24→5.0 V buck
L2	10 µH ≥1 A	SMD 4×4	verify	per datasheet
R20	100 k 1%	0603	C25803	FB top
R21	19.1 k 1%	0603	verify	FB bottom → Vout=0.8·(1+R20/R21)≈5.0 V
C22	22 µF / 50 V	1210	verify	buck input cap
C23	22 µF / 16 V	0805	C45783	buck output cap
Dbk	SS34	DO-214AC	C8678	buck freewheel (separate from fan flyback D2)
JP1	0 Ω / open	0603	C21189	rail select — OPEN = use buck

Connections (From → To · Net): (pin functions per MP1584 datasheet — confirm exact pin #s at capture)

U2.IN   → 24V            24V        (protected rail, post-Q10)
U2.EN   → 24V            -          enable (or datasheet EN divider)
C22.1   → 24V            24V        input cap at the IC
C22.2   → GND            GND
U2.SW   → L2.1           SW2_NODE   keep switch-node copper tiny
Dbk.K   → L2.1           SW2_NODE   freewheel cathode to SW node
Dbk.A   → GND            GND
L2.2    → 5V_FAN         5V_FAN
C23.1   → 5V_FAN         5V_FAN     output cap
C23.2   → GND            GND
R20.1   → 5V_FAN         5V_FAN     FB top
R20.2   → U2.FB          FB
R21.1   → U2.FB          FB
R21.2   → GND            GND
JP1.1   → 5V_FAN         5V_FAN     OPEN by default
JP1.2   → MAIN5V         MAIN5V     close ONLY if upsizing SD-15B-05 (never both)

BST/COMP/SS small caps per MP1584 datasheet (e.g. BST ~10 nF) — add at capture. Keep U2 + L2 + the SW node away from the GNSS antenna feed / P3 (RF, design §8). The existing fan flyback D2 (SS34) across the fan stays as-is.

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4. Block B — LTC4040 battery backup ✅ SIZED 2026-07-02 (datasheet 4040fb pass, 12 Ah pack)

Intent (canonical power tree): P2 (vehicle 5 V from SD-15B-05) → VEH5V → RS → U6 power path → VSYS = MAIN5V (the backed-up rail) ; LTC4040 ↔ 1S4P cell on P4 ; NTC on the cell. LTC4040 architecture: single inductor SW↔BAT works as step-down charger (VSYS→BAT) when input is good and 2.5 A step-up backup (BAT→VSYS) when PFI trips. A mandatory external NFET (Q7) between VIN and VSYS (gate = IGATE charge pump) disconnects the dead input during backup. Buck and boost are internally compensated — no external comp network.

Ref	Value / MPN	Formula → result	Note
U6	LTC4040EUFD	—	QFN-24 4×5 mm, EP = GND (stitch)
Q7	NFET 30 V ≥10 A, ≤15 mΩ, SOIC-8 (AO4406A-class)	—	VIN→VSYS disconnect, gate = IGATE
RS	8 mΩ 1 % (1206/2512 sense)	I_SYSLIM = 25 mV/RS → 3.1 A	protects the SD-15B-05 (5 V/3 A); charge sheds first, load prioritized
RPROG	825 Ω 1 %	I_CHG = 2500·(0.8 V/RPROG) = 2000/RPROG → 2.42 A ≈ C/5	≤2.5 A max; PROG servos 0.8 V
RPF1/RPF2	287 k / 100 k 1 % (VEH5V→PFI→GND)	trip = 1.19 V·(1+R1/R2) → 4.60 V falling, ≈4.72 V recover	⚠ bench-tune if the vehicle rail sags in service
RFB1/RFB2	499 k / 100 k 1 % (VSYS→BSTFB=RSTFB→GND)	V_backup = 0.8 V·(1+R1/R2) → 4.79 V; RST threshold −7.5 % ≈ 4.43 V	BSTFB+RSTFB shorted, one divider (datasheet)
L6	2.2 µH, Isat ≥ 8 A, DCR < 20 mΩ (8040 power inductor)	datasheet range 1–2.2 µH; boost NMOS ILIM 5.5–7.5 A	SW↔BAT; tiny SW copper
CVIN	10 µF X5R + 2.2 µF	—	at U6 VIN
CVSYS	≥100 µF low-ESR ceramic (2×47 µF 1210 + 10 µF)	datasheet minimum	backup-transition hold-up
CBAT	22 µF X5R	≥10 µF required	at U6 BAT
RNTB	10 k 1 % low-drift (VEH5V/VIN→NTC)	with RT1 10 k: datasheet default window	B3380 ideal; B3950 acceptable (trip shifts a few °C — note in bring-up)
RT1	10 k NTC on the cell (via P4.3)	—	NTC→GND at U6
P4	JST-XH 3-pos (was 2-pos)	—	1=BAT+, 2=BAT−, 3=NTC
F2/F0 straps	→ VSYS · F1 → GND (solder jumpers JP2/3/4)	table: F2=1,F1=0,F0=1 → 4.00 V Li-ion	strap to VSYS not 3V3 so chemistry survives an absent MCU; 4.00 V ≈ 3× cycle life, kinder to hot cells (RCA #1); LiFePO4 = re-strap F2→GND (3.50 V)
CHGOFF	net CHRG_EN → PA8 + 100 k pull-down	>1.2 V = charge OFF	default = charging enabled, NTC still guards
BSTOFF	tie GND	—	backup always armed; never float
CHRG / FAULT	→ PB3 / PB4, 100 k↑3V3	open-drain	STREAM-log telemetry
PFO	test point + DNP 100 k↑	—	PA4 (VEH5V ÷2) already covers power-fail sensing
RST	leave open	—	Blackpill has its own supervisor
OVSNS	short to VIN	OVP module unused	input is the regulated SD-15B-05 inside the cabinet; 24 V side carries SPD
CLPROG	test point only	I_SYS = V_CLPROG/(32·RS)	unbuffered — do not load

Connections (From → To · Net):

P2.1      → VEH5V           VEH5V    vehicle 5 V in (RENAMED from MAIN5V)
P2.2      → GND             GND
VEH5V     → RS.1            VEH5V    RS = input current sense
RS.2      → U6.CLN + Q7.D   VIN_SNS  (U6.VIN Kelvin at RS.1 side: VIN pin → VEH5V node)
Q7.S      → MAIN5V          MAIN5V   Q7 = VIN→VSYS disconnect NFET, gate → U6.IGATE
U6.VSYS(1,24) → MAIN5V      MAIN5V   backed-up system rail (feeds §5 cutoff merge)
U6.SW(21,22)  → L6.1        SW_BAT   keep copper tiny
L6.2      → U6.BAT + P4.1   BAT_PLUS (+ existing BAT_SENSE divider R5.1 stays on BAT_PLUS)
P4.2      → GND             GND      1S4P −
P4.3      → U6.NTC          NTC      RT1 at the cell; RNTB 10 k VEH5V→NTC on-board
U6.PROG   → RPROG → GND     -
U6.CLPROG → TP              -
U6.PFI    → RPF1/RPF2 node  PFI      divider from VEH5V
U6.BSTFB + U6.RSTFB → RFB1/RFB2 node FB divider from MAIN5V
U6.CHGOFF → PA8             CHRG_EN  + 100 k → GND
U6.BSTOFF → GND             GND
U6.CHRG   → PB3             CHRG_STAT  + 100 k → 3V3
U6.FAULT  → PB4             CHRG_FAULT + 100 k → 3V3
U6.F2/F0  → MAIN5V (VSYS)   -        via JP2/JP4 ; U6.F1 → GND via JP3
U6.OVSNS  → U6.VIN          VEH5V    OVP unused
U6.EP     → GND             GND      thermal/electrical

Checklist (fab gate unchanged):

• Confirm pack Ah → ~12 Ah (corrected 2026-06-30). RPROG sized (2.42 A ≈ C/5).
• Size L6, RS, PFI divider, compensation → table above (internally compensated; no comp parts).
• Jumper-select charge voltage → JP2/3/4 straps to VSYS/GND, default 4.00 V Li-ion.
• Bench-validate the temp-qualified charge cutoff + backup transition before fab.
• ⚠ Safety-timer note: deep-discharge full recharge (12 Ah @ 2.42 A ≈ 5 h) exceeds the internal charge safety timer — firmware restarts the cycle via CHRG_EN when the cell is cool and BAT_SENSE is low (see canonical §7 firmware items).

The proto validates this path with the TP4056 + MT3608 + 1N5819 OR-ing + 10 k NTC stand-in (proto BOM). The PCB uses the LTC4040. Only the temp-qualified cutoff is LTC4040-only → validate that in firmware logic.

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5. Blocks C / D / E — reset, gauge, cutoff ✅ (E node pending B)

C. Reset

Ref	Part	Connections
SW1	SPST momentary (SOT/SMD tact)	NRST → SW1 → GND
P10	JST-XH 2-pos (external reset)	P10.1 → NRST · P10.2 → GND

D. 4-LED battery gauge (firmware-driven from BAT_SENSE, HIGH = lit)

Ref	Part	Connections
R_BL1..4	330 Ω 0603 ×4	PB12→R_BL1, PB13→R_BL2, PB14→R_BL3, PB15→R_BL4
D_BAT1..4	LED 0805 ×4	R_BLn → D_BATn.A ; D_BATn.K → GND

E. Power cutoff (kills vehicle and battery)

• External switch in series in the post-merge 5 V (LTC4040 VSYS/MAIN5V → system loads).
• Define SYS5V = MAIN5V after the cutoff; route the Blackpill 5 V pin + load-switch (Q1 source
  • F1) + the K1 relay coil from SYS5V. Implement as 2-pos connector P11 to an external switch: P11.1 → MAIN5V · P11.2 → SYS5V. Ship with a jumper plug installed (open P11 = dead board). The PA4 divider taps VEH5V (Block F), not SYS5V.
• Merge/cutoff node finalized with the §4 pass: MAIN5V = U6 VSYS output rail.

5b. Block H — Modo-B fail-safe uplink bypass ✅ NEW 2026-07-02

Requirement (ledger): a dead/absent/hung MCU must never cut RTCM3 corrections. In Modo B the watchdog sits in-line on the uplink (F9P TX2 → 4G DIN) to inject $PHLG; the RTCM3 downlink (4G DOUT → F9P RX2) is always direct and never enters the MCU.

Implementation: SPDT signal relay, normally-closed — chosen over an analog mux because a mux dies with the 3V3 rail; relay contacts keep the direct path even with the Blackpill physically removed or the board unpowered.

Ref	Part	Note
K1	SPDT signal relay, 5 V coil (HFD23/005-class)	NC = direct path; coil ~30 mA only while MCU inserted
Q6	MMBT3904 (SOT-23)	low-side coil driver
R40 / R41	1 k (PB5→base) / 10 k (base→GND)	default OFF
D6	1N4148 (SOD-123)	coil flyback
P13	JST-XH 3-pos	1 = F9P_TX2 · 2 = 4G_DIN · 3 = GND

P13.1   → K1.NC + PA10      F9P_TX2   PA10 = passive monitor tap (USART1 RX)
K1.COM  → P13.2             4G_DIN
K1.NO   → PA9               PA9_TX    MCU uplink (USART1 TX, $PHLG injection)
SYS5V   → K1.coil+          SYS5V
K1.coil− → Q6.C ; Q6.E → GND ; PB5 → R40 → Q6.B ; R41 B→GND ; D6 across coil (K→SYS5V)

De-energized (default, MCU dead, board cut off): NC closes F9P TX2 → 4G DIN — corrections and position flow exactly as if the watchdog weren't there.

5d. Block J — CARRIER-BOARD sockets (F9P + 4G on the board) ✅ NEW 2026-07-02 (PM)

Decision (Leo): the PROD board is now the HBOX carrier/motherboard — all three modules ride on female headers: Blackpill (J1/J2, already socketed), simpleRTK2B Pro as an Arduino-UNO-form shield (MOD1), and the 4G NTRIP Master on its own XBee socket (J7/J8). Board grown 100×80 → 120×100 mm (Leo approved; ASA case/plate to be reprinted).

Ref	Part	Note
MOD1	4× UNO female headers (10+8+8+6, 2.54 mm)	footprint Module:Arduino_UNO_R3; custom symbol SimpleRTK2B_Pro_Socket in Drogheda-sym
J7/J8	2× PinSocket 1×10, 2.00 mm	XBee socket, rows 22.35 mm apart (J7 = pins 1–10 row)

MOD1 pin map (pads = KiCad UNO footprint; functions verified against the official pinout-simpleRTK2B_Pro-R00 image + UNO geometry cross-check):

D0 = TX1 (F9P UART1 TX)  → GNSS_RX (PA3)      power hdr: 5V → SW_5V  (Pro's "5V=OUTPUT" sw OFF)
D1 = RX1 (F9P UART1 RX)  → GNSS_TX (PA2)                 IOREF → 3V3 (defines TX/RX levels)
D2 = RX2 (F9P UART2 RX)  → DOUT_4G (RTCM3 in, direct)     GND ×3 → GND
D8 = TX2 (F9P UART2 TX)  → USART1_RX (K1.NC + PA10 tap)   3V3/VIN/RESET/A0–A5/D3–D7/D9–D13/
                                                          AREF/SDA/SCL → NC (per Ardusimple:
                                                          don't connect unused special pins)

XBee socket: J7.1 VCC → 3V3_MODEM (⚠ the Pro's HP socket spec is 3.3 V, 1 A/1.5 A pk — NOT 5 V; the old "socket gives 5 V" note was wrong) · J7.2 DOUT → DOUT_4G → F9P RX2 (RTCM3 direct, never through the MCU) · J7.3 DIN ← K1.COM (DIN_4G) · J7.10 GND. J8 all NC.

Consequences: Modo B is now the permanent uplink architecture with the K1 NC bypass as the hardware fail-safe (dead/absent MCU ⇒ TX2→DIN direct). The F9P's own XBee socket stays EMPTY; its XBEE↔UART switch parks on UART1 so UART2 stays on the rails. P3 / P13 / H3 → DNP (harness alternatives for non-socketed installs).

5e. Block K — 3V3_MODEM buck (U7) ✅ NEW 2026-07-02 (PM)

The modem needs 3.3 V @ ≥1.5 A pk — too much for the Blackpill's LDO, and an LDO from 5 V would burn ~1.7 W. Second MP1584EN (U7, same BOM as Block A) fed from SW_5V so the watchdog's stack power-cycle also reboots the modem (invariant #3): U7: VIN/EN=SW_5V · SW→L7 10 µH→3V3_MODEM · FB R60 100k / R61 31.6k (→3.33 V) · Dbk2 SS34 · Cbst2 10 nF · Rfreq2 100k · Rcomp2 40.2k + Ccomp2 2.2 nF · C40 22 µF in · C41 22 µF + C43 100 µF elco out (LTE bursts).

Build status (2026-07-02 PM) — carrier conversion BUILT

MOD1 + J7/J8 + Block K captured; ERC 0 errors (82 cosmetic). Board 120×100, outline + GND pour resized, holes at (5,5)(115,5)(5,95)(115,95). Placement: shield field center-bottom (courtyard ≈ x22.6–98, y45–99) with only SMD ≤6 mm underneath (LTC4040 block, dividers, I²C, NTC, Rdfu); Blackpill sockets horizontal above it; XBee rows vertical right (module field x≈92–119, y26–44); K1/relay + buck A top-right; all operator/access parts (SW1, gauge, JSTs, P1) outside the shield. DRC: 87 pre-route errors — ~55 are the by-design under-shield courtyard overlaps vs MOD1 + ~29 sub-mm courtyard kisses left for the placement review. ⚠ Review notes: P3 (DNP) sits in the shield's notch corner; J8 is 1.2 mm from the board edge; verify D2/D8 = RX2/TX2 against a physical Pro before routing (positions read from the official pinout image).

5c. Block I — NTC→PB1 hot-spot temperature (block 11) ✅ NEW 2026-07-02

Ref	Part	Note
R42	10 k 1 % (3V3 → PB1 node)	divider top
P12	JST-XH 2-pos	external 10 k NTC (B≈3950), placed at the hot spot (battery/modem)
C24	100 nF (PB1 → GND)	ADC settling

3V3 → R42 → PB1 (+C24) → P12.1 ; P12.2 → GND. ≈1.65 V @ 25 °C; firmware Beta/Steinhart; can drive the CHRG_EN cutoff. This is the proto's temperature path (no SHT40 in hand); the PCB keeps U3/U4 (I²C) and this channel.

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6. Corrections to make on BOTH boards (proto + production) ✅

1. PA4 5V-sense tap → vehicle side (live Finding 3). With the LTC4040 backing MAIN5V, R7.1 must move from MAIN5V to VEH5V (the P2/SD-15B-05 node, before hold-up). On the proto (no LTC4040) MAIN5V == vehicle 5 V so it's harmless there, but make the net VEH5V now so both boards match and production is correct. Without this, v5v never drops below V5V_OFF, vehiclePower never clears, and the cell drains.
2. Finish the GND unify. The file still has 4 power:GNDREF symbols (canonical §4 claimed these were converted to power:GND — not persisted). Convert all 4 to power:GND (or wire them to the GND-label net) and re-run ERC, or ground splits into GND vs GNDREF.

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7. Open decisions / flags

• H1 (SWD header) — DECIDED 2026-06-25: DROP. SWD (PA13/PA14) isn't on the Blackpill 2×20 socket — it's on the module's own separate SWD header — so a carrier H1 buys nothing the USB-C path doesn't already give: flashing via USB DFU (BOOT0), diagnostics via the USB CDC STREAM log. Optional: lay an unpopulated (DNP) 4-pad SWD footprint (3V3 / SWDIO / SWCLK / GND) for bench bring-up; if ever used, jumper SWDIO/SWCLK to the module's SWD header. Remove or mark DNP the H1 rows in watchdog-connections.xlsx and watchdog-pcb-v3-bom.xlsx.
• PB12 reassigned from "2nd-fan-tach spare" to gauge BATLED1 (fans are 2-wire, no tach — canonical open item). PB10 tach stays a DNP provision.
• JP1 stays OPEN (dedicated fan rail). Only close if SD-15B-05 is upsized to 5 V/5 A.

8. Build mechanics

• Production project copy already created: kicad/hbox-watchdog-v3-PROD.kicad_{pro,sch,pcb} (the proto file is untouched — it was open in KiCad).
• I can generate this in KiCad once the KiCad backend is back up and the proto is closed (so there's no file conflict). Suggest also renaming the proto to …-proto once you're out.

Related

• watchdog-electrical-design-state (CANONICAL) · watchdog-pcb-v3-design (§4 sub-circuits) · watchdog-connections-rationale (Finding 3) · watchdog-connections.xlsx · watchdog-pcb-v3-bom.xlsx · kicad/hbox-watchdog-v3-PROD.kicad_sch