153 lines
7.9 KiB
Markdown
153 lines
7.9 KiB
Markdown
---
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title: HBOX v3 — 4G modem USB / Reset / LED / power-pin fix (build spec)
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project: Project Drogheda
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date: 2026-07-05
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status: SCHEMATIC COMPLETE (ERC 0 errors) — board sync + place + route to finish in KiCad GUI
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tags: [project-drogheda, hardware, 4g, usb, revision]
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---
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# 4G NTRIP module — add USB, reset, LED + fix required power pins
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Goal: firmware-update and reset the 4G modem **in place** on the EINARBoard (no more
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swapping it to the simpleRTK), and wire the module's **mandatory** pins that are
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currently floating.
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## Module pin map (XBee-form, per datasheet) → EINARBoard socket
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J7 = module pins 1–10 (row 1), J8 = module pins 11–20 (row 2, numbered 20→11 top-to-bottom).
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| Module pin | Function | Socket pad | Current | Action |
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|---|---|---|---|---|
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| 1 VCC | 3.3–3.6 V, 2 A pk | J7.1 | 3V3_MODEM ✓ | keep |
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| 2 TX | data out | J7.2 | DOUT_4G ✓ | keep |
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| 3 RX | data in | J7.3 | DIN_4G ✓ | keep |
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| 4 GND | ground | J7.4 | **NC** | → GND |
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| 5 RESET | low = reset | J7.5 | **NC** | → reset button → GND |
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| 6 V_USB | 5 V enables USB | J7.6 | **NC** | → USB VBUS (5 V) |
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| 7 USB+ | USB D+ | J7.7 | **NC** | → USB D+ |
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| 8 USB− | USB D− | J7.8 | **NC** | → USB D− |
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| 9 DTR | disabled | J7.9 | NC | leave |
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| 10 GND | ground | J7.10 | GND ✓ | keep |
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| 11 GND | ground | **J8.10** | **NC** | → GND |
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| 12 CTS | disabled | J8.9 | NC | leave |
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| 13 LED | 1.8 V LED drive | **J8.8** | **NC** | → R + LED → GND |
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| 14 VREF | **must = VCC** | **J8.7** | **NC** | → 3V3_MODEM |
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| 15 GND | ground | **J8.6** | **NC** | → GND |
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| 16 RTS | disabled | J8.5 | NC | leave |
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| 20 ON/OFF | **GND = always ON** | **J8.1** | **NC** | → GND |
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> ⚠️ **Must-fix even if we skipped USB:** VREF (J8.7→VCC) and ON/OFF (J8.1→GND). Without
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> ON/OFF tied low the modem may never power on. Confirm J8 pad numbers vs. the Ardusimple
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> footprint before wiring.
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## Parts to add
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| Ref | Part | Notes |
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|---|---|---|
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| J9 | **USB-C receptacle, USB 2.0** (e.g. GCT USB4085 / TYPE-C-31-M-12) | D+/D−, VBUS, GND, 2×CC |
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| R_cc1, R_cc2 | 5.1 kΩ 0402/0603 | CC1, CC2 → GND (device-mode detect, required for Type-C) |
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| R_dp, R_dm | 0 Ω (optional series) | in D+/D− if you want the option; can be DNP |
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| SW_4G | tactile 6 mm (or SMD) | RESET(J7.5) ↔ GND |
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| D_4G | LED 0805 | anode ← R_led ← LED(J8.8); cathode → GND |
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| R_led | ~1 kΩ | LED current limit (pin sources 1.8 V) |
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## New nets
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`USB_VBUS` (→ J7.6 V_USB + USB-C VBUS), `USB_DP` (J7.7 ↔ USB-C D+), `USB_DM` (J7.8 ↔ USB-C D−),
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`MODEM_RST` (J7.5 ↔ SW_4G ↔ GND), `MODEM_LED` (J8.8 ↔ R_led ↔ D_4G ↔ GND).
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Reuse existing `3V3_MODEM` for VREF, `GND` for ON/OFF + spare grounds.
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## Placement
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Open pocket **right of / below the XBee sockets** (board ≈ x200–212, y76–98). USB-C at the
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board edge (mechanical access), button + LED beside it.
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## Routing
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- **USB D+/D−**: keep the pair together and short; USB-2.0 FS/HS firmware speed is forgiving —
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no controlled-impedance needed, just route them side-by-side, similar length, GND nearby.
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- Everything else is low-speed/DC — trivial.
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- Do it by adding to the **schematic first** → re-import → place → FreeRoute the new nets
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(lock existing routing) → DRC → re-export fab.
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---
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## STATUS 2026-07-05 — what's done, what's left
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**DONE (in the schematic `hbox-watchdog-v3-PROD.kicad_sch`, verified ERC 0 errors):**
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- Modem must-fix pins wired: **J8.1→GND (ON/OFF), J8.7→3V3_MODEM (VREF), J8.6/J8.10/J7.4→GND**.
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- New parts added + net-labelled: **J9** USB-C (USB_C_Receptacle_USB2.0_14P, fp GCT_USB4085),
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**Rcc1/Rcc2** 5.1k, **SW4G** reset (CK_PTS636 SMD), **Rmled** 1k, **D4G** LED (0805).
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- All connections: USB_VBUS→J7.6, USB_DP→J7.7, USB_DM→J7.8, MODEM_RST→J7.5+SW4G, MODEM_LED→J8.8
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chain, CC resistors→GND, USB-C VBUS/GND/CC/D±. (Verified on a trial board sync — J7/J8 pads
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took the right nets.)
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- Fixed a reference collision: the schematic already had a `Rled` (10k, live circuit); the new
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LED resistor is **`Rmled`** so the existing part is untouched.
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**LEFT (do in the KiCad GUI — the MCP's board backend left spurious DRC shorts on sync, so the
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board was reverted to its clean pre-USB state; the schematic is the source of truth):**
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1. **Tools → Update PCB from Schematic (F8)** — pulls in J9, Rcc1, Rcc2, SW4G, Rmled, D4G and
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assigns the modem-pin nets. (GUI F8 is clean; don't use the MCP sync.)
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2. **Place** the 6 parts in the pocket right of the XBee (board coords, mm):
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| Ref | x | y | note |
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|---|---|---|---|
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| J9 (USB-C) | 199.5 | 79 | fills pocket; pads clear J8 (left) & P3 (right) |
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| Rcc1 | 198.5 | 75.3 | CC1 5.1k, row above J9 |
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| Rcc2 | 201.2 | 75.3 | CC2 5.1k |
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| Rmled | 203.9 | 75.3 | LED 1k |
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| D4G | 206.4 | 75.3 | LED |
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| SW4G | 202.5 | 90 | reset, in the strip below the y≈87.5 trace |
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Courtyard "kisses" with J8/P3 are OK (pads clear) — same as the board's existing by-design kisses.
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3. **Route 9 nets.** GND pads (J9 grounds+shields, Rcc·2, SW4G·2, D4G·1) drop to the In1 GND plane
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with a via each (THT grounds auto-connect). Signals: USB_VBUS/DP/DM run J7.6/7/8 → J9 (under the
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module is fine); MODEM_RST J7.5→SW4G; MODEM_LED J8.8→Rmled→D4G; CC1/CC2 J9→Rcc. Keep D+/D-
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together. **FreeRouting** the ratsnest is the fast path (as before).
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4. **Fill All Zones (B)** → **DRC** → should be back to the pre-existing cosmetic set (0 shorts).
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5. **Re-export the JLCPCB fab package** (`fab-jlcpcb/`) — the current zip predates all of this.
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Backup of the clean board kept at `kicad/hbox-watchdog-v3-PROD.kicad_pcb.bak-preusb`.
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---
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## STATUS 2026-07-05 (later) — board cleaned, ready to place + route in GUI
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**What happened:** F8 from the (fixed) PROD project pulled in the 6 USB parts **plus 15
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duplicates**, because this project has a **board↔schematic refdes mismatch** (schematic names 18
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parts `Cbst1, Rled1 … D4G1, Rmled1, SW4G1`; the routed board uses the clean names `Cbst, Rled …`).
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KiCad saw the schematic names as "missing" and added copies. Cleaned at the file level:
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- Removed the 15 duplicate footprints from the board; renamed my 3 USB parts to clean names.
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- **Board = 132 parts, no duplicates, all 6 USB parts present with correct nets (J9 verified:
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VBUS×4, GND+shields, CC1/CC2, D+/D− pairs).** Loads clean, electrically sound.
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- Backups: `…kicad_pcb.bak-predupclean`, `…kicad_sch.bak-predupclean`, `…kicad_pro.bak-projfix`.
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**F8 is now SAFE (reconciled 2026-07-05).** The schematic's 18 `…1` names were renamed to the
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board's clean names (`Cbst1→Cbst … D4G1→D4G, Rmled1→Rmled, SW4G1→SW4G`), so schematic and board
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now agree — a future F8 will match by reference and won't duplicate. ERC added **0 new errors**
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(one pre-existing "Pin not connected" remains — unrelated; locate it via Inspect→ERC in the GUI).
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Backup: `…kicad_sch.bak-prereconcile`.
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**Placement:** the board is packed — no clean ~11 mm hole for J9 (USB-C is ~10.5 mm; the J8 pocket
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is ~9 mm, and the lower-right is under U7/C43/Ccomp2). Place J9 where its **pads** clear even if
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courtyards "kiss" a neighbor (the board already has by-design kisses) — do it live in the GUI.
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**Net map for routing (ratsnest targets):**
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| Part · pin | Net | Connects to |
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|---|---|---|
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| J9 A4/A9/B4/B9 | USB_VBUS | **J7 pin 6** |
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| J9 A6/B6 | USB_DP | **J7 pin 7** |
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| J9 A7/B7 | USB_DM | **J7 pin 8** |
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| J9 A5 | USB_CC1 | Rcc1·1 |
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| J9 B5 | USB_CC2 | Rcc2·1 |
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| J9 GND + 4 shields | GND | plane (via) |
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| Rcc1·2, Rcc2·2 | GND | plane |
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| SW4G·1 | MODEM_RST | **J7 pin 5** |
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| SW4G·2 | GND | plane |
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| Rmled·1 | MODEM_LED | **J8 pin 8** |
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| Rmled·2 ↔ D4G·anode | MODEM_LED_A | each other |
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| D4G·cathode | GND | plane |
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So the USB/reset cluster (J9, Rcc1, Rcc2, SW4G) wants to sit near **J7** (left XBee column); the
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LED pair (Rmled, D4G) near **J8 pin 8**. GND pads just drop a via into the In1 plane.
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**Finish:** place the 6 → route (FreeRoute the DSN or hand-route; D+/D− as a pair) → **B** to fill
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zones → DRC (expect 0 shorts) → re-export the JLCPCB package.
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