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tags project author date status
project-drogheda
hardware
pcb
kicad
jlcpcb
guide
how-to
Project Drogheda Helgen CTO 2026-06-21 Active — working guide

KiCad → JLCPCB: build & deploy the Watchdog Carrier PCB v3

A from-zero, do-this-then-that guide for capturing the 03-Architecture-Hardware/watchdog-pcb-v3-design in KiCad and getting it assembled by JLCPCB. Written for someone who has done PCB work a long time ago. The schematic content (every net, part, value) lives in the design doc and the 03-Architecture-Hardware/watchdog-pcb-v3-bom — this is the tooling path.

0. Pick your path (read first)

You have two realistic routes to a JLC-assembled board. Both end at the same place.

Path Best when Trade-off
A — KiCad (this guide) you want a proper, version-controllable design you own outright steeper, but the right long-term tool; offline; git-friendly
B — EasyEDA (Std/Pro) you want the fastest first board with least friction JLC-native: every part already carries its LCSC number + footprint, and "Order at JLCPCB" is one button. Less portable.

My recommendation for this board, given you're newer to PCB and going JLC-assembly: do Path A (KiCad) because you'll iterate this board for the fleet and want to own it — but if you feel stuck on footprints/part-matching, Path B (EasyEDA) is a legitimate shortcut and uses the exact same LCSC parts in our BOM. Don't lose a week to tooling.

The rest of this doc is Path A.

1. Install KiCad + two plugins

  1. KiCad 9 or 10 (current 2026) from kicad.org → install the full suite.
  2. Open KiCad → Plugin and Content Manager (button on the home screen) and install:
    • Fabrication Toolkit (by bennymeg) — one-click export of Gerbers + BOM + CPL already in JLCPCB's format. This is the deploy button.
    • JLCPCB Tools (Bouni / kicad-jlcpcb-tools) — lets you assign the LCSC part number to each component from inside KiCad and query JLC stock. This is how the BOM parts get matched.

Both are free, in the official plugin manager. With these two, you never hand-edit a JLC CSV.

2. The mental model (the whole workflow in one picture)

 Symbols + wires        Footprints           Place + route        One-click export
 (Schematic editor) ──► (per component) ──►  (PCB editor)   ──►   (Fabrication Toolkit)
        │                     │                    │                     │
      ERC ✓             "what each part        DRC ✓            Gerbers.zip + bom.csv
   (no missing nets)     physically is"     (no shorts/      + positions.csv  ──► JLCPCB
                                             clearance)            upload + assemble

You always go left to right. Don't start routing until the schematic passes ERC.

3. Create the project

  1. File → New Project → name it hbox-watchdog-v3. Save it inside the repo at 03-Architecture-Hardware/ (or a new kicad/ subfolder) so it's version-controlled.
  2. You get .kicad_sch (schematic) and .kicad_pcb (board). Open the Schematic Editor.

4. Draw the schematic

Work one sub-circuit at a time, matching design-doc §4. Use net labels, not long wires — it keeps things readable.

4.1 Place the power symbols first

Add power ports (the "place power symbol" tool): +24V, +5V (main), +5V_FAN, +3V3, SW_5V, GND. Every supply/return connects to these by name — no need to draw rails across the page.

4.2 The Blackpill (the trick that saves you)

You are not designing the STM32 chip — the Blackpill module plugs into two 1×20 headers. So represent it as two Conn_01x20 connector symbols (or grab a ready "WeAct Blackpill" symbol from a community KiCad library — search GitHub for "Blackpill KiCad library"). Label each pin with its net name from design-doc §2 (PA0=BAT_SENSE, PA1=PWR_CTRL, PA6=FAN1_PWM, PB6=I2C1_SCL, …). The header footprints become the socket the module sits in. This avoids all MCU bring-up.

4.3 Drop in each sub-circuit (design-doc §4)

For each, place the symbols, wire locally, and tie to power/net labels:

  • Input + fan buck (§4.1–4.2): Q10 (AO3401A), D10 TVS, C10/C11; then U2 MP1584EN with L2, C22, C23, the FB divider R20/R21, and JP1 (solder-jumper symbol).
  • Load switch (§4.3): Q1 AO3401A + Q5 MMBT3904 + R1/R2 + F1 PPTC + C3. Net the drain to SW_5V. (Optional U1 eFuse footprint — leave it DNP.)
  • Fan drivers ×2 (§4.4): Q2/Q3 AO3400A, D2/D3 SS34 flyback, Rg/Rgs gate parts, tach pull-up + series into PB10 / PB12. PWM gates from PA6 / PA7.
  • Sensors (§5): U3 SHT40 + U4 TMP102 on PB6/PB7, 4.7k pull-ups, 100nF each.
  • Sense + LED (§4.5–4.6): the three 10k/10k dividers (PA0/PA4/PA5), D5 clamp, Q4 + D1 + R3.
  • Connectors (§6): P1–P8, H1, H3 (DNP), and the two 2×20 sockets.

4.4 Annotate + ERC

  • Tools → Annotate (gives refs R1, U2, …).
  • Inspect → Electrical Rules Check. Fix every error (usually an unconnected pin or a missing power flag). Schematic is not done until ERC is clean.

5. Assign footprints

Open Tools → Assign Footprints (or the Footprint Assignment tool). Map each part to a JLC-friendly footprint:

Part type Footprint
Resistors / caps Resistor_SMD:R_0603_1608Metric / Capacitor_SMD:C_0603_1608Metric (C3/C22/C10 → 0805/1206/elec)
AO3400A / AO3401A / MMBT3904 Package_TO_SOT_SMD:SOT-23
SS34 Diode_SMD:D_SMA (DO-214AC)
MP1584EN Package_SO:SOIC-8-1EP_… (the EP/thermal-pad variant)
SHT40 Sensor:Sensirion_DFN-4-1EP_… (or import from LCSC — see below)
TMP102 Package_SON:SOT-563 (or import from LCSC)
JST-XH Connector_JST:JST_XH_B* (B4B/B2B etc.)
Headers Connector_PinHeader_2.54mm:… (1×4, 1×3, 2×20 for the sockets)

For the odd parts (SHT40, TMP102, MP1584, JST): the JLCPCB Tools plugin can pull the exact LCSC footprint so it matches the assembler perfectly. Or use the classic trick: on easyeda2kicad / the JLC part page, grab the EasyEDA footprint and import. Either way, verify pin-1 orientation against the datasheet.

6. Lay out the PCB

  1. Open the PCB Editor → Update PCB from Schematic (pulls in all parts + the ratsnest of connections).
  2. Board outline: draw a rectangle on Edge.Cuts (~100 × 80 mm is plenty). Put the mounting holes so the board can bolt to the cabinet metal plate (design-doc §8 — that's your conduction path).
  3. Place by functional block (keep each §4 sub-circuit together): power-in + buck in one corner, load switch near P3, fan drivers near P6/P7, sensors near an air edge / P5, the Blackpill sockets central, connectors on the edges.
  4. Stackup: 2-layer is fine (cheaper); 4-layer is better for RF/buck noise. Add a ground pour (filled zone = GND) on the bottom (and an inner layer if 4-layer).
  5. Route (design-doc §8 rules): power/5V ≥0.5 mm, SW_5V ≥0.8 mm (modem bursts), signals 0.25 mm. Keep the MP1584 switch node + fan-PWM traces away from the GNSS antenna pigtail. Star-ground the pulsed (fan/modem) returns separately from the ADC/ sensor ground.
  6. DRC (Inspect → Design Rules Checker). Zero unrouted, zero clearance errors.
  7. Add silkscreen labels on every connector (net names) + pin-1 arrows, and a board title/rev. (Serviceability requirement.)

7. Tell JLC which physical part goes where (LCSC numbers)

Open the JLCPCB Tools plugin. For each component, set its LCSC field to the code in the BOM (e.g., AO3400A → C347222, SHT40 → C2909890, TMP102 → C99269). For the yellow "verify" parts in the BOM, search the plugin's parts DB live and pick an in-stock equivalent. Mark U1 (eFuse) and H3 (USART1 reserve) as DNP / "Do not place."

This step is what makes assembly "just work" — the assembler places exactly these LCSC parts. The Blackpill, the 2×20 sockets, and the GX16 wiring you hand-solder yourself (mark them DNP for JLC, or "PCBA: no").

8. Export (the deploy button)

Run Fabrication Toolkit (Tools/External-plugins menu in the PCB editor). One click produces a production/ folder with:

  • Gerbers + drill, zipped — the board.
  • bom.csv — Designator, Footprint, Qty, Value, LCSC — already JLC-formatted.
  • positions.csv (CPL) — Designator, Mid X/Y, Rotation, Layer — already JLC-formatted.

No hand-editing. (If you ever do it manually: Plot Gerbers with JLC's layer settings, then generate BOM + CPL — but the plugin removes that pain.)

9. Order on JLCPCB

  1. jlcpcb.com → Add gerber file → upload the Gerber .zip. Confirm the preview looks like your board.
  2. Set basics: layers (2 or 4), 1.6 mm, HASL or ENIG, qty 5.
  3. Toggle PCB Assembly = ON. Choose Economic (cheaper, top-side only is fine here) and assembled qty 2–3.
  4. Upload bom.csv and positions.csv when prompted. JLC matches LCSC parts → fix any "not found" by picking an in-stock alternative (this is why we kept to Basic parts).
  5. Review placements carefully — the #1 beginner bug is wrong part rotation on SOT-23 / SOIC / connectors. Check each against the datasheet pin-1; rotate in the review tool as needed.
  6. Confirm DNP parts (U1, H3) are excluded. Place the order.

Lead time ~1–2 weeks to Mexico. Hand-solder the Blackpill, the 2×20 sockets, and the GX16 pigtail when it arrives.

10. First-board gotchas (the stuff that bites beginners)

  • Rotations: JLC's 0° reference often differs from KiCad's. Always eyeball the placement preview; SOT-23 and electrolytics are the usual offenders.
  • Polarity: double-check D10 TVS, C10 electrolytic, D2/D3 Schottky, the LED, and Q10/Q1 source/drain before ordering.
  • The buck (U2) is the only "real" analog block — if you're nervous, populate JP1 closed + upsize the 5 V supply and leave U2 unpopulated for the first spin (design-doc §4.2). One board, two options.
  • Don't let JLC place the Blackpill or the GX16 — those are hand-soldered.
  • Order 1–2 spare bare boards for hand-rework experiments.
  • Conformal-coat after you've tested it (mask the SHT40 slot + connectors).

11. Pre-order checklist

  • Schematic ERC clean; every Blackpill pin labelled per design-doc §2.
  • All footprints assigned; SHT40/TMP102/MP1584/JST verified against datasheet pin-1.
  • PCB DRC clean; GND pour stitched; SW_5V wide; buck/fan noise away from GNSS feed.
  • Mounting holes positioned to bolt to the cabinet metal plate.
  • LCSC numbers set on all placed parts; U1 + H3 = DNP; Blackpill/GX16 = hand-solder.
  • Fabrication Toolkit exported Gerbers + BOM + CPL.
  • JLC placement preview rotations checked.
  • Bench-test plan ready (design-doc §9) — especially the §0a 5 V-rail sag test before you trust it in a cabinet.

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