Agent brief — Full audit of EinarBoard v6 (with V5.5/V5.6 lessons learned)

Owner: Leo (Helgen Technologies) · Date: 2026-09-28 · For: a fresh Claude session/agent with the Drogheda folder mounted ($HOME/mnt/Projects/Drogheda) and the KiCad MCP tools available on Leo's Mac. Language: write the report in English with a Spanish executive summary (same convention as 2026-09-28_Drogheda_EinarBoard-v6_Review-vs-V5.5-Lessons_v1.0.md).

1. Goal

Audit the EinarBoard v6 design (03-Architecture-Hardware/kicad/hbox-watchdog-v6.kicad_sch + .kicad_pcb, current state on disk) completely, not only against the nine V5.5 lessons: power tree, modem, GNSS, MCU pin map vs. firmware, Ethernet, thermal/EMC, connectors, BOM/JLC, identity/telemetry, DRC/ERC. Output a single ranked report with evidence and concrete fixes so Leo can decide what to change before ordering v6. Read-only by default; apply fixes only on a copy and only if Leo asks (§7).

2. Inputs (read all before starting)

Design files (do not modify in place):

03-Architecture-Hardware/kicad/hbox-watchdog-v6.{kicad_sch,kicad_pcb,kicad_pro} — the target. hbox-watchdog-v6 respaldo.* is an older backup, ignore unless comparing.
03-Architecture-Hardware/kicad/hbox-watchdog-v5.* — V5.5 as fabbed (frozen; never touch). hbox-watchdog-v56.* — V5.6 ECO copy (reference for what was fixed on V5).
Libraries: Drogheda-v6.kicad_sym, Drogheda.pretty in the kicad folder.

Lessons and prior reviews (the audit must cite these):

03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Review-vs-V5.5-Lessons_v1.0.md — lesson-by-lesson review F1–F9 (✅ F1 F2 F3 · ⚠ F4 F6 F8 F9 · ❌ F5 F7). Start from its §4 risk checklist; re-verify every item against the current files (it was written on the 25-Sep state).
03-Architecture-Hardware/2026-09-27_Drogheda_EinarBoard-V5.6_ECO_ES_v1.0.md — the V5.6 ECO: sections A (modem power), B (MCU lines), C (charger RS1/R50), D (temperature), E (EMC list), F (misc), H (firmware 0.7.0 needs), I (validation).
03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-V5.6_Schematic-Change-Report_v1.0.md — how V5.6 was implemented, open items §6.
03-Architecture-Hardware/2026-08-24_Drogheda_EinarBoard-v6_GNSS-4G-Integration_Design-Brief_v1.0.md, ..._Phase-2_Schematic-Delta_v1.0.md, 2026-09-02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html, 2026-08-27_Drogheda_v6-Antenna-Chain_Diagram.html.
Project docs (claude.ai project "Drogheda"): 2026-09-25_HBox-v6_Pre-Fab-Audit_EN.md, 2026-09-26_HBOX-V4-V5_Pinmap-Audit-FW-0.5.4.md, 2026-09-27_HBOX-V5.5-V4_Modem-on-battery_Diagnosis-and-0.5.8-Field-Strategy.md, 2026-09-28_Drogheda_Status-and-Next-Steps.md.
Obsidian vault Second Brain/03 Projects/Helgen/Project-Drogheda/: "EinarBoard — Lecciones aprendidas V5.5 (sep 2026)", "EinarBoard v6 — Revisión contra lecciones V5.5", "Drogheda — Decision Log", "Drogheda — Risk Register".
Test evidence: 06-Testing-Validation/2026-09-28_H0008_charging-overnight-log.md (charger works; average charge current ≈ 1.3 A vs 2.4 A programmed; 8.5 h to full; rail 5.25 V; MODEM watch threshold flapping).
Firmware: 04-Source-Code/firmware/hbox_v5_bringup/hbox_v5_bringup.ino (0.6.0) and CHANGELOG.md — the pin map and every GPIO/ADC/UART/SPI/I²C the firmware expects. v6 will need a new pin map; the audit must produce it.
Memory files in this project (read: drogheda-einarboard-v6-brief, drogheda-v6-zed-f9p-integration, drogheda-v6-lte-island, drogheda-v6-resync-protocol, drogheda-einarboard-v5-audit, drogheda-battery-hightemp, drogheda-backup-lowpower, drogheda-einarboard-harness, drogheda-einarboard-modem-rail, drogheda-einarboard-short-incident, drogheda-mff2-footprint, drogheda-power-cost, preferences).

3. Ground rules (Leo's standing rules — non-negotiable)

Never edit the v6 files in place. Work read-only; if a fix phase is requested, copy to hbox-watchdog-v6-audit.*, keep backups of every intermediate state under kicad/_to_delete/v6-audit-<date>/, preserve UUIDs, and prove every change with a netlist diff (kicad-cli sch export netlist) before and after.
Never run bare numeric regex over KiCad files (values like 0.3, 825 appear everywhere). Parse S-expressions (python sexpdata/kiutils or the KiCad MCP tools) and match by ref/UUID/net.
No git from the mounted folder — give Leo the commands. The mount cannot delete (use _to_delete/).
Hardware bodges on existing boards are rejected — every fix is a design change for the next fab.
Look things up yourself (netlist, datasheets, JLC parts DB via the KiCad MCP search_jlcpcb_parts/get_jlcpcb_part) — do not ask Leo for values you can derive from the files.
Verify with tools, not by reading: kicad-cli sch erc, kicad-cli pcb drc, netlist export, pad→net dump, track width/length per net, courtyard overlaps (check_courtyard_overlaps), clearance (check_clearance).

4. Audit scope — do every block, in this order

A. Power tree (24 V → 5 V → rails), incl. lessons F5/F7/F4

U25 TPS54360B: output set-point (R121/R122) vs. the 0.6.0 charge governor (CHG_RAIL_ON 5.05 / CHG_RAIL_OFF 4.90 V) and LTC4040 PFI (4.44 V on V5). Required: ≥ 5.30 V nominal (R121 57.6k proposal) — confirm with the datasheet formula, check FB divider tolerance, output ripple, Cout, and that the 5 V rail can source F9P + modem peak + 2 A charge with margin. Input protection on 24 V (TVS, reverse, inrush) and the 24V/5V inner-layer clearance lesson from the 23-Jul short incident (drogheda-einarboard-short-incident): report every 24 V-to-other-net clearance < 0.5 mm on inner layers.
LTC4040 U6 block: RS1 (input limit 25 mV/RS vs. what U25 can supply), R50 (825 Ω = 2.42 A → 1.5 k = 1.33 A per ECO C; justify with the H0008 finding), PROG/NTC/RNTB/JP2 chemistry (Li-ion vs LFP-HT — drogheda-battery-hightemp), BSTFB divider (backup V), PFI divider, safety timer, CHRG/FAULT pull-ups to the MCU. Thermal: SW_BAT/BAT_PLUS track widths (target ≥ 2 mm / 1.5 mm), U6 EP thermal vias (≥ 9), L6 distance, copper area, a temperature sensor within 10 mm of U6 (TMP102 or NTC) so the firmware can see charger die heating.
Every buck/LDO on the board: input/output caps location (< 3 mm), BST cap, compensation network vs datasheet application table for the actual Vout/L/Cout, EN pull-downs (default OFF where the firmware expects OFF), UVLO vs the minimum battery voltage in backup (3.5 V boost floor).
Backup path: what runs on battery, what the boost can deliver (VSYS backup 4.79 V on V5) and whether F9P + modem + W5500 cold-start on battery is within the LTC4040 boost limit — this is the root cause of the V5.5 "modem dark on battery" failure (2026-09-27_..._Modem-on-battery_Diagnosis). Produce a worst-case current budget table (per rail, cold start and steady state).

B. Modem (A7670SA) — lessons F1/F2/F3, ECO A/B

U20 AP64350 3.80 V: source (D21/MAIN5V vs D20/24 V), EN = MODEM_PWR_EN (PC10) with 100k pull-down (R113), compensation/frequency network vs datasheet for 3.8 V, Cout, bulk ≥ 220 µF polymer within 10–20 mm of VBAT_MODEM pins, track width ≥ 0.25 mm (2 A bursts), ground return.
Control lines: PWRKEY (PC8), STATUS (PC9), RST (PC11), level shifting to 1.8 V logic where the module requires it, series resistors, pull-ups/downs at power-up (module must not be back-powered through UART/GPIO while its rail is off).
UART USART6 PC6/PC7 with the R106 100 Ω RTCM tap: confirm direction, no contention with the ArduSimple/F9P path, and that the firmware can read RTCM age ($GxGGA field 13) or raw RTCM.
SIM/eSIM (U22 MFF2 footprint — drogheda-mff2-footprint), SIM ESD, antenna path (matching, DC block, ESD), LTE island copper rules (drogheda-v6-lte-island).
Cold-start on battery test case: state explicitly whether v6 can bring the modem up from the LTC4040 boost alone; if not, which sequencing the firmware must enforce (this is requirement R1 of the ECO: "10 minutes off, come back to life, report, while on battery").

C. GNSS (ZED-F9P) — drogheda-v6-zed-f9p-integration

VCC ramp window (20–8000 µs/V), RTK_STAT, TIMEPULSE, SAFEBOOT/RESET_N handling, backup battery/V_BCKP, antenna chain (LNA bias, DC block, ESD, 50 Ω trace geometry on the stack-up), UART/I²C/SPI to MCU, u-center passthrough via J11 (P17 removed).
Confirm no $GPTXT H00xx source exists on v6 → identity must be $PHID from the MCU (lesson F9); check the MCU has a UID-based ID path and the monitor/firmware plan (2026-09-25_HBox-v6_Pre-Fab-Audit_EN.md).

D. MCU pin map vs firmware 0.6.0 (STM32F411RET6)

Build the full table: every net on U16 (or whatever the MCU ref is on v6) → function → firmware macro in hbox_v5_bringup.ino (PIN_*). Flag: pins used by firmware that are unconnected on v6; v6 nets with no firmware counterpart; ADC pins on non-ADC-capable pads; UART/SPI/I²C alternate-function conflicts; PWM (fan) timer availability; 5 V-tolerant requirement on any 5 V signal; BOOT0/BOOT1/DFU trap (drogheda-einarboard-30-mcu-integration); NRST routing (SW1, P10, C104); SWD header; the CHRG_STAT/FAULT/PFO inputs; IGN_SENSE divider (Rig 22k) and its junction (the V5.6 tool bug removed a junction there — check v6 too).
Deliverable: pinmap-v6.md table ready to become #ifdef HBOX_BOARD_V6 in firmware.

E. Ethernet W5500 — lesson F8

SPI2 wiring, CS/INT/RST, RST pull-down (100k), 3V3_ETH source and whether it should be switchable (always-on on V5 wastes battery), magnetics/HR911105A, ESD on J9 (USBLC6-2SC6 or equivalent), no PoE (state it), 25 MHz crystal placement ≤ 5 mm.

F. Thermal and EMC (ECO section E, copper plan) — lesson F5/F6

Fan driver/FB divider location, fan tach, temperature sensors: count and placement (near modem, near U6, board ambient, P12 NTC for the battery pack), and whether the firmware's thermal inhibit (CHG_CELL_HOT 45 °C) has a real cell temperature source.
Crystals ≤ 5 mm; via stitching under the modem; DFU ESD (D14/D15/D16) at J11; return paths across splits; 24 V in inner layers; courtyard overlaps; DRC clean.

G. Connectors and harness — drogheda-einarboard-harness, drogheda-einarboard-j1-mirror

P1/P2 power entry, ignition GND return, JP_CUT across the P11 equivalent, pin-1 marking and mirrored-socket check on every header (the J1 mirror errata), silkscreen names (RESET MÓDEM / RESET MCU / F2), mounting holes and case fit.

H. BOM / JLC manufacturability

Every part with an LCSC property: exists, in stock, Basic vs Extended, footprint matches the JLC part (e.g. the L7 SRU8028 vs MWSA0804S question), polarity marks, DNP list explicit, no TBD. Export BOM + CPL with kicad-cli and check with get_jlcpcb_part. Estimate the unit BOM cost delta vs V5.6.

I. Requirements traceability (from the ECO §0 R1–R5)

R1 10-min off/on on battery with report; R2 modem never left dark (MCU can power-cycle it); R3 report while on battery; R4 temperature management (sensors + fan + charger inhibit); R5 charge at ≥ 1.3 A without thermal cycling. For each: satisfied by v6 as-is / needs change X / needs firmware only.

J. ERC/DRC — run both with kicad-cli; list every error and warning, classify pre-existing vs real.

5. Method and evidence standard

Every finding: ID, severity (Blocker / Major / Minor / Note), block, evidence (ref, net, coordinates, measured width/length/distance, datasheet page), consequence, concrete fix (part value + LCSC, or layout instruction with numbers), effort (schematic-only / layout / both).
"Pass" items need evidence too (one line each) — the report must show what was checked, not only what failed.
Compute, don't eyeball: track widths via pcb parsing, distances from footprint positions, divider outputs from resistor values, current budgets from datasheets.
If a fact is not derivable from the files (e.g. enclosure dimensions), list it under "Inputs needed from Leo" at the end — do not stop the audit for it.

6. Deliverables

03-Architecture-Hardware/2026-MM-DD_Drogheda_EinarBoard-v6_Full-Audit_v1.0.md — sections in the order of §4, then §4-I traceability table, §4-D pin map, a ranked change list (Blockers first) and a "ready to order? YES/NO + conditions" verdict.
03-Architecture-Hardware/pinmap-v6.md (or inside the report) — the MCU pin table.
Same report as a project doc claude/…_EinarBoard-v6_Full-Audit.md (claude.ai project "Drogheda") and a vault note EinarBoard v6 — Auditoría completa (fecha).md in Second Brain/03 Projects/Helgen/Project-Drogheda/, linked from Project Drogheda MOC.md; append decisions to Drogheda — Decision Log.md and new risks to Drogheda — Risk Register.md.
Update 2026-09-28_Drogheda_Status-and-Next-Steps.md (project) with a v6 line.
Git commands for Leo (two-step: kicad submodule first, then the parent gitlink — drogheda-kicad-submodule).

7. Optional phase 2 (only if Leo says "apply")

Apply the Blocker/Major schematic fixes on a copy hbox-watchdog-v6-audit.* following the V5.6 method (2026-09-28_..._Schematic-Change-Report): copy → backups per step → KiCad MCP edits by ref/UUID → ERC → netlist diff = only the intended pins → PDF export → change report. Layout changes are listed for Michelle, not executed, unless explicitly requested.

8. Acceptance

The audit is done when: every §4 block has a pass/fail table with evidence; ERC/DRC outputs are attached; the R1–R5 traceability table is complete; the pin map covers 100 % of MCU pins; every proposed part has an LCSC number; the verdict states what blocks the order and what can follow in v6.1.

14 KiB Raw Blame History Unescape Escape