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19c15e2864
Drogheda/03-Architecture-Hardware
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Leopoldo Rodríguez 19c15e2864 EinarBoard respin WIP: E-J1 pad renumber, PFI 4.40V (R51 270k), HV24 24V clearance class, J1 nets ripped for reroute 
J1 pads renumbered end-for-end (positions/uuids kept, nets follow numbers, lib id renamed Drogheda:..._RevNum_EJ1 so library-update cannot revert); verified pad-by-pad against the module landing map. R51 287k->270k on board+schematic (PFI trip 4.60->4.40V falling, per 24-Jul bench data). HV24 class (0.5mm clearance) assigned to /24V_IN, 24V, IGN_IN, Q10_GATE after the 23-Jul inner-layer bridge incident. 177 segments/vias ripped on the 11 J1 signal nets + 5 power stubs: reroute pending in the inter-socket channel. NOTE: pre-existing PWR_HI/PWR_MID netclass patterns lack the '/' prefix and likely never matched.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
2026-07-25 04:04:12 +00:00
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CAD-Files auto-sync 2026-07-13 18:00 2026-07-13 18:00:15 -06:00
circuitikz-wiring auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
EinarBoard-Manual sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
Guia-Conexion-Protoboard auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
kicad EinarBoard respin WIP: E-J1 pad renumber, PFI 4.40V (R51 270k), HV24 24V clearance class, J1 nets ripped for reroute 2026-07-25 04:04:12 +00:00
Manual-Instalacion-Operacion Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
4G-USB-Reset-LED-addition.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
0007-1000_Assembly_Guide.pdf auto-sync 2026-07-11 18:00 2026-07-11 18:00:15 -06:00
2026-07-06_Drogheda_EinarBoard-1.0-PreFab-Audit_v1.0.md sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
2026-07-08_Drogheda_4G-Modem-Alternatives_v1.0.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
Assembly-BOM-Split.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
BOM-master.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
bom.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
cabinet-electrical-bom.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.png 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.svg 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_EinarBoard-1.0_Tabla-Conexiones-Externas_v1.0.pdf auto-sync 2026-07-23 18:00 2026-07-23 18:00:14 -06:00
Drogheda_Guia-Cableado-Proto-Watchdog-v3_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v2.2.pdf auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.0.pdf auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.1.pdf auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
Drogheda-BOM-Maestro.xlsx Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda-Manual-Instalacion-Operacion.pdf Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-v3-pinned-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
firmware-review-v2.3-EinarBoard.md Firmware review: v2.3 as EinarBoard 1.0 production candidate (2026-07-24) 2026-07-24 01:27:20 +00:00
firmware-review.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
hardware-respec-and-pcb-brief.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
harness-connector-pinout.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
JLCPCB-Order-Guide.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
LCSC-search-list.md auto-sync 2026-07-07 18:00 2026-07-07 18:00:12 -06:00
Socket-Pinout-Silkscreen.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
watchdog-connections-rationale.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-connections.xlsx 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-electrical-design-state.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
watchdog-health-telemetry.md add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-LISTA-DE-COMPRAS-ES.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-pcb-v3-blockdiagram.svg auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-bom.xlsx add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-pcb-v3-design.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-pcb-v3-kicad-guide.md auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-routing-status.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
watchdog-production-schematic-delta.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-proto-bench-bringup-v3.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-protoboard-BOM-3boards.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-protoboard-bringup.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-schematic.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00