J1 pads renumbered end-for-end (positions/uuids kept, nets follow numbers, lib id renamed Drogheda:..._RevNum_EJ1 so library-update cannot revert); verified pad-by-pad against the module landing map. R51 287k->270k on board+schematic (PFI trip 4.60->4.40V falling, per 24-Jul bench data). HV24 class (0.5mm clearance) assigned to /24V_IN, 24V, IGN_IN, Q10_GATE after the 23-Jul inner-layer bridge incident. 177 segments/vias ripped on the 11 J1 signal nets + 5 power stubs: reroute pending in the inter-socket channel. NOTE: pre-existing PWR_HI/PWR_MID netclass patterns lack the '/' prefix and likely never matched.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Leopoldo Rodríguez
19c15e2864