Drogheda/03-Architecture-Hardware
Claude (Cowork) 3494413eaf v6 T3: Block N - ZED-F9P (U18) + low-noise LDO (U21) placed and wired
Leo generated the vendor part with easyeda2kicad (C5120257) -> Drogheda-v6.kicad_sym /
.pretty / .3dshapes, now registered in sym-lib-table and fp-lib-table.

CROSS-CHECK: the EasyEDA/LCSC symbol independently CONFIRMS the datasheet transcription -
pads 1-54 match the u-blox pin assignment function for function, and the 21 Reserved pads
are identical. Pads 55-102 are 48 extra GND pads (the ground array under the module), which
our symbol was missing; T3a2 adds them stacked on the pin-1 coordinate so one GND label
serves all. Symbol is now 102/102 pins, footprint = Drogheda-v6:LCC-LGA-102_L22.0-W17.0_FM660.

Block N as wired (verified by rebuilding connectivity from label-on-pin geometry):
  GNSS_TX      U16.16 + U18.43        GNSS_RX  U16.17 + U18.42
  DOUT_4G      U18.26 (RXD2, RTCM in - modem end lands in T4)
  USART1_RX    U16.43 + Rdfu1.1 + U18.27 (TXD2 uplink; K1.1 also on this net per the PCB)
  GNSS_RESET_N U16.53 (PC12) + U18.49 + R105 10k pull-up to 3V3_GNSS
  GNSS_TIMEPULSE  U16.23 (PA7) + U18.53
  GNSS_ANT_DETECT U16.9 (PC1) + U18.4
  GNSS_ANT_SHORT_N U16.10 (PC2) + U18.6
  GNSS_RTK_STAT   U16.11 (PC3) + U18.20  <- hardware answer to are-corrections-being-used
  3V3_GNSS = U21.5 + U18.33/34 + C120-C124 + R105; U21 fed from SW_5V (stays MCU-gated)
  V_BCKP   = U18.36 on the UNGATED 3V3 so ephemeris survives a power-cycle
  33 no-connects: the 21 reserved pads plus V_USB, USB_DM/DP, ANT_OFF, SDA, SCL, TX_READY,
  D_SEL (open = UART mode), SAFEBOOT_N, EXTINT, GEOFENCE_STAT and the LDO NC/NR pin.

T3c fixes two coordinates the generators emitted as 3.552713679e-15 (i.e. zero); KiCad is
not guaranteed to accept exponent notation. See the script header for the lesson: a first
attempt used a bare numeric regex over the whole file and corrupted 264 UUIDs, because
segments such as 895e-4153 parse as scientific notation. Reverted from backup and redone
scoped to (at ...) forms only, with a UUID-integrity guard. Verified 2298 UUIDs, 0
malformed, 0 exponent coordinates.

STILL OPEN: the PCB has no U18/U21/passive footprints yet - that is a KiCad
Update-PCB-from-Schematic. And confirm the -04B datasheet pin assignment on paper.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-08-24 23:25:44 +00:00
..
CAD-Files auto-sync 2026-07-13 18:00 2026-07-13 18:00:15 -06:00
circuitikz-wiring auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
EinarBoard-Manual sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
Guia-Conexion-Protoboard auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
Informe-Tecnico-V3-V4 auto-sync 2026-08-11 18:00 2026-08-11 18:00:15 -06:00
kicad v6 T3: Block N - ZED-F9P (U18) + low-noise LDO (U21) placed and wired 2026-08-24 23:25:44 +00:00
Manual-Instalacion-Operacion Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
4G-USB-Reset-LED-addition.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
0007-1000_Assembly_Guide.pdf auto-sync 2026-07-11 18:00 2026-07-11 18:00:15 -06:00
2026-07-06_Drogheda_EinarBoard-1.0-PreFab-Audit_v1.0.md sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
2026-07-08_Drogheda_4G-Modem-Alternatives_v1.0.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
2026-07-24_Drogheda_EinarBoard-1.1_Design-Brief_v1.0.md EinarBoard 1.1 design brief: locked decisions (RS-485+RS-232 via SC16IS752, on-board W5500 Ethernet, RGB status LED, board growth) + execution phases 2026-07-29 01:58:39 +00:00
2026-08-08_Drogheda_Firmware-v3.1_ModoB-PHLG_Design-Brief_v1.0.md auto-sync 2026-08-08 18:00 2026-08-08 18:00:15 -06:00
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2026-08-14_Drogheda_EinarBoard-3.0_Capacitor-Placement-Map_v1.0.md auto-sync 2026-08-14 18:00 2026-08-14 18:00:14 -06:00
2026-08-20_Drogheda_EinarBoard-v5_Fixes-Applied_v1.0.md auto-sync 2026-08-20 18:00 2026-08-20 18:00:15 -06:00
2026-08-20_Drogheda_EinarBoard-v5_Pre-Audit-Checks_v1.0.md checkpoint: v5.5 as saved by Leo before Claude fixes (pre-audit report included) 2026-08-20 16:37:33 +00:00
Assembly-BOM-Split.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
BOM-master.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
bom.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
cabinet-electrical-bom.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.png 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.svg 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_EinarBoard-1.0_Tabla-Conexiones-Externas_v1.0.pdf auto-sync 2026-07-23 18:00 2026-07-23 18:00:14 -06:00
Drogheda_Guia-Cableado-Proto-Watchdog-v3_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v2.2.pdf auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.0.pdf auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.1.pdf auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
Drogheda-BOM-Maestro.xlsx Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda-Manual-Instalacion-Operacion.pdf Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-v3-pinned-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
firmware-review-v2.3-EinarBoard.md Firmware review: v2.3 as EinarBoard 1.0 production candidate (2026-07-24) 2026-07-24 01:27:20 +00:00
firmware-review.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
hardware-respec-and-pcb-brief.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
harness-connector-pinout.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
hbox-watchdog-v5-schematic.pdf auto-sync 2026-08-12 18:00 2026-08-12 18:00:16 -06:00
JLCPCB-Order-Guide.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
LCSC-search-list.md auto-sync 2026-07-07 18:00 2026-07-07 18:00:12 -06:00
Socket-Pinout-Silkscreen.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
watchdog-connections-rationale.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-connections.xlsx 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-electrical-design-state.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
watchdog-health-telemetry.md add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-LISTA-DE-COMPRAS-ES.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-pcb-v3-blockdiagram.svg auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-bom.xlsx add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-pcb-v3-design.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-pcb-v3-kicad-guide.md auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-routing-status.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
watchdog-production-schematic-delta.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-proto-bench-bringup-v3.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-protoboard-BOM-3boards.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-protoboard-bringup.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-schematic.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00