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3e37a66ec7
Drogheda/CLAUDE.md
Leopoldo Rodríguez 3e37a66ec7 Auditoria 21-oct, tarde: T32 + T33 aplicados (kicad + hbox-docs) 
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01QCy5VHMVLkAmftYM6swWmx
2026-10-21 14:04:52 -06:00

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tags project author date status
project-drogheda
master-index
gps-rtk
hbox
Project Drogheda Helgen CTO 2026-06-20 Active

Project Drogheda — Master Index (CLAUDE.md)

Source of truth for this workspace. Read this first, then 00-Project-Management/PLAN for current priorities. Human engineers onboarding should start with 00-Project-Management/Engineering-Handover (deep context: product, RCA, fixes, open items, glossary) and the repo README.md. You are acting as the CTO/CSO of Helgen Technologies — principal hardware/software architect for the Drogheda GPS-RTK fleet. Tone: precise, fail-safe first. Keep this index and its directory table current as files change.

Codename: the team / Google Drive / official manual call this project Drogheda (GPS RTK). This local folder was renamed from "Galway" → "Drogheda" on 2026-06-20; all docs now use Drogheda.

0. Where we are (2026-06-20)

Helgen deployed HBOX RTK trackers on heavy port equipment at Hutchison Ports ICAVE (Veracruz). They worked "ish," then failed. We are mid-crisis and hardening the product for scale. Three independent failure fronts, all being fixed in parallel:

  1. Backend (confirmed in code). The production retranslator.py blocks the whole fleet on any upstream slowness, and an anti-jump filter can permanently black-hole a healthy unit → some "dead" units may be backend victims, not dead radios. See 02-Architecture-Software/backend-review.
  2. Thermal (component-level). The ASA HBOX (UV-stable, softens ~95–100 °C — the case is fine) sits sealed inside a sealed ABS IP67 cabinet that also holds the Mean Well supply → nested heat trap that cooks the battery / boost / modem in full sun. See 06-Testing-Validation/RCA-2026-06-field-failures.
  3. Prototype hardware. Dupont, hand-wiring, 18650 + PowerBoost — the client's (ICAVE) own indictment. Fix = ruggedize now + production PCB.

Status of units: all pulled from machines. 4 in hand (3 dead, 1 working-ish), physically in Veracruz; team in Querétaro → remote debug. Units run firmware v1 (no thermal log). Triage: 06-Testing-Validation/remote-diagnostic-protocol.

Commercial reality: productized across ICAVE, TIMSA, EIT, LCT (Hutchison terminals); target 30 units operational by August; hundreds of cabinets planned. The fix must be production-grade and repeatable.

Logs & observability (2026-06-20). Analyzed the first real bench + healthy-baseline log set (u-blox .ubx, 4G-NTRIP console .log, server retranslator tcpdump) + the caster/F9P config. GNSS receivers are healthy but no unit reached RTK — all SPS (corrections not applied: free rtk2go caster + RAM-only F9P config + indoor sky). The 4G-NTRIP console is an unreliable health signal (see §6 — "master-14 fault" retracted; only master 21 confirmed). Built hbox-log-tools (Log Explorer + analyzer + dashboard + manual) and a Blackpill v2.1 logging spec to fix observability. Canonical: 06-Testing-Validation/2026-06-20_Drogheda_GNSS-Findings-Summary.md.

Electrical / PCB (2026-06-24). Watchdog v3 KiCad schematic (03-Architecture-Hardware/kicad/hbox-watchdog-v3.kicad_sch, ERC-clean). DFR1015 folded on-board → GX16 pin 3 now carries RAW machine ignition (12–24 V), not pre-conditioned 5 V. Battery re-added with a proper charger — LTC4040 + NTC temperature-qualified charging on the 1S4P pack; the Blackpill cuts charge when the cell is hot (answers the RCA's #1 failure). Added reset (on-board + external), a 4-LED battery gauge, and a power-cutoff switch; fixed two real schematic bugs (EXT_LED disconnect, panel-LED short). Proto = 3 boards of easy-to-find parts (watchdog-protoboard-BOM-3boards.xlsx + Spanish shop list watchdog-LISTA-DE-COMPRAS-ES.xlsx). Canonical electrical state → 03-Architecture-Hardware/watchdog-electrical-design-state.md — read first for any electrical context.

PROD schematic complete + PCB layout kickoff (2026-07-02). hbox-watchdog-v3-PROD.kicad_sch now carries all blocks — ERC 0 errors: LTC4040 Block B sized to the 12 Ah pack (RPROG 825 Ω → 2.42 A ≈ C/5 · RS 8 mΩ → 3.1 A input limit · PFI trip 4.60 V · backup 4.79 V · charge 4.00 V Li-ion via VSYS-referenced straps), Block E cutoff (P11, MAIN5V→SYS5V), Block F PA4→VEH5V re-tap, Block H fail-safe Modo-B bypass (K1 normally-closed signal relay — corrections survive a dead/absent MCU), Block I NTC→PB1 (block 11). New MCU pins live: PB1 · PB3 · PB4 · PB5 · PA8. Same day (PM): CARRIER-BOARD conversion — the PROD board now sockets all three modules on female headers: Blackpill (J1/J2) + simpleRTK2B Pro as UNO-form shield (MOD1, D0/D1=UART1, D2=RX2, D8=TX2, IOREF=3V3, 5V=SW_5V) + 4G NTRIP Master on an on-board XBee socket (J7/J8 2 mm; VCC = 3V3_MODEM, a second MP1584 buck off SW_5V — the HP XBee socket is 3.3 V not 5 V). Modo B + K1 NC bypass = permanent uplink; RTCM3 downlink direct; P3/P13/H3 DNP. Board 120×100 mm, shield field with SMD-only underneath, XBee field right, access parts outside; ERC 0; carrier DRC baseline saved (…-drc-carrier-baseline.txt; ~29 sub-mm placement kisses + by-design under-shield courtyard overlaps). Next gate: placement review vs HBOX/cabinet mechanicals (+ verify D2/D8=RX2/TX2 on a physical Pro), then routing (5 V ≥0.5 mm, SW_5V ≥0.8 mm per kicad-guide). Fab gate unchanged: bench-validate the LTC4040 backup + hot-cell charge cutoff on the proto first. Latest proto assumptions ledger = Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx (Estado y cambios) + Drogheda_Guia-Conexion-Protoboard_ES_v3.1.pdf (LaTeX source in repo: Guia-Conexion-Protoboard/). Wiring diagrams v2.1 (blocks 1–11) in circuitikz-wiring/; client decks Avance + RCA refreshed to v1.1.

Proto sensor suite realigned to parts in hand (2026-07-03). No SHT40 (long lead) → proto Block 6 = AHT10 (0x38 fija, 3V3 only, alone on I²C1 — Aosong restriction); LM35 → PA7 (last free ADC channel) joins NTC→PB1 → triple temperature (3 technologies, 3 electrical paths); humidity = AHT10 only. SHT40/TMP102 stay PCB-only (PROD schematic untouched). The kit's TP4056 exposes no TEMP pin → charger-NTC unused on proto; new PA8 CHRG_RUN high-side cut of TP4056 IN+ (2N3904+IRF9540N; HIGH = charge, MCU absent = no charge — inverted vs PROD CHRG_EN, firmware flag). Cutoff switch now wired: nodo SYS (OR merge) → SPST → MAIN5V (= Block E/P11, kills vehicle AND battery). Caps in hand 100 nF/10 µF/100 µF; fan confirmed 2-wire. Docs synced: ledger xlsx · Guía v2.2 · circuitikz v2.1 · both proto BOMs · design-state (canonical).

EinarBoard 1.0 Rev 1.1 — audit closed, order-prep pack (2026-07-07). The PROD carrier is officially Helgen EinarBoard 1.0 (title-block EINARBoard HBOX 1.0), 135.1×100.1 mm (grew from 120×100 on Jul-3). Pre-fab audit (03-Architecture-Hardware/2026-07-06_…PreFab-Audit_v1.0.md) CLOSED: H1 Q7 S/D corrected (S=VIN_SW, D=MAIN5V) · H2 Q5/Q6 → Q_NPN_BEC · H3 Rig 22k (+ DFR1015 removed — raw 12–24 V → 22k/10k divider + BAT54 clamp → PA5) · H4 SW_IN → PWR_MID 1.0 mm; ERC 0 / DRC 0; M3 closed on a physical Pro (switchless variants: XBee socket hardwired to UART2 — never plug the Pro's USB-XBee port in service) · M4 HBOX fit verified → bare-board order RELEASED; fleet PCBA still gated by M2 (LTC4040 bench validation) + LCSC re-confirm at upload. Order-prep pack in 03-Architecture-Hardware/EinarBoard-Manual/: einarboard-manual.tex → branded 21-pp PDF (embeds the Rev 1.1 schematic full sheet + F/In1/In2/B layer plots + silk assembly view, exported fresh from the Jul-7 saves into assets/; the Jul-6 …-PROD-schematic.pdf/-blueprints.pdf at 03-AH root are stale — pre-H1/H2) · helgen_einarboard_1.0_production_bom.xlsx (Summary + Internal PCBA w/ verified LCSC + External Integration, live formulas) · tools/generate_production_bom.py + tools/sync_bom.py (Excel→pcba_bom.tex + external_bom.tex — both BOMs in the report; the workbook is the BOM source of truth) · scripts/prep_order_release.sh (safe cleanup + release commit; dry-run default). KiCad sch↔board sync is manual (F8 retired). Vault note: EinarBoard 1.0 — System Overview & Toolchain.

Guía de protoboard v3.0 + 4G alternatives (2026-07-08). Guía rewritten for a low-experience technician: new visual parts catalog (Guia-Conexion-Protoboard/ modulos-pinout.tex) — physical top-views of every IC module (LM2596 · MT3608 · TP4056 · AHT10 · DFR1015), full Blackpill 40-pin physical map (used pins colored, VB/B12 corner check), simpleRTK2B Pro with its real silk names (RX1/TX1/RX2/TX2/IOREF + XBee switch), 4G NTRIP Master + BOB-08276 breakout, TO-92/TO-220 pinouts, diode/LED/cap polarity, resistor color codes, protoboard anatomy + pre-power checklist; per-block «Piezas de este bloque» lines. Bloque 9 reworked around the XBee pitch: the 4G is 2.0 mm (not 1.27 — 10 pins = 18 mm) vs protoboard 2.54 mm → bridge options (★ BOB-08276 + 2× PRT-08272 ≈MX$100, SANDOROBOTICS CDMX, 1–2 days) + soldering steps + modem VCC = 3.3 V from SAL via dedicated buck (mirrors 3V3_MODEM; never 5 V) + bulk cap for LTE bursts. Also fixed: IOREF→3V3 rows added to Blocks 8/9 (missing in v2.2 — Pro UARTs are dead without it), Blackpill USB + 5 V rail never simultaneous warning, and the circuitikz socket label corrected 5 V→3.3 V (wiring-blocks.tex; lámina + Beamer PDFs rebuilt, still content-v2.1). Cheap-4G survey → 2026-07-08_Drogheda_4G-Modem-Alternatives_v1.0.md: bench = keep Ardusimple on breakout; experiment = LILYGO T-A7670SA (~US$33, TinyGSM NTRIP, ~1 day fw); Aug 30-unit run stays Ardusimple (€112 @ ≥50); scale = A7670SA raw (US$9.4, NTRIP-over-AT fw) or Digi XBee 3 LTE Cat 1 (US$76, socket drop-in, MicroPython NTRIP on-module). Avoid -E band variants, SIM7000G (Telcel LTE-M provisioning risk).

Production audit V5.6 / V5.7 / v6 (2026-10-16). None is ready to order. V5.6 (hbox-watchdog-v5, kicad 5a93232) is close: pass 3 of layout (~1 day) + firmware 0.7.0 (board_v56.h, also runs V5.7 — same MCU pins) + a 5-board pilot. V5.7 (hbox-watchdog-v57, a7c0116): V5.6's pass-2 power fixes were not replicated (/BAT_PLUS on In1 at 0.5 mm again), U25 EP has 0 vias, FB divider 22 mm away; input range without the SD-15B = 9–32 V DC (TVS D10 SMBJ33A is the ceiling; recommend SMBJ33CA). v6: PCB never updated from the verified schematic (70 parity diffs incl. JP2 Li-ion, R52 open) and no firmware replaces the 4G NTRIP Master yet. Findings that apply beyond one board: the 7 V5.5 production holes (MH5/MH6/MH4 3.2 mm, MH4 at (185.2, 90.3) — 193.2 is only the old footprint anchor; MH7/MH9/MH10 ArduSimple; MH11 clamp) were lost from V5.6/V5.7 by Update PCB → restore with kicad/tools/t25_mounting_holes_v55.py (board-only footprints); and the LTC4040 input limit is ≈ 1 A instead of 2.5 A on V5.5/V5.6/V5.7 (VIN/CLN sense taps include ~19 mm of copper; fix = Kelvin to RS1 pads). D8 (identify v6 by the SC7A20) no longer works — V5.6/V5.7 have it too. Canonical: 03-Architecture-Hardware/2026-10-16_Drogheda_Auditoria-Produccion_V5.6-V5.7-v6_ES_v1.0.md

  • Michelle's 2026-10-16_Drogheda_Instrucciones-Michelle_V5.6-V5.7-Pasada-3_ES.md (site: hardware/auditoria-produccion-16oct/).

v6 production audit + weekend plan (2026-10-16 PM) → re-audit of all three + T30 (2026-10-19). Audited on HBox_PCB 4f4681f (Michelle's pass 3 + Leo's merge fix). V5.6 (hbox-watchdog-v5, 240e2c3) is almost ready: /BAT_PLUS off the inner layers, /3V3_MODEM 1.0 mm, U7 EP 4 vias, no loose copper, RS1 Kelvin intact; DRC = only the 3 MOD1 NPTH-in-courtyard errors (by design), 0 unconnected. T30 (kicad/tools/t30_v56_v57_mecanicos.py; dry-run by default, .T30bak, aborts on geometry drift, DRC-verified on copies) adds parallel vias at every single-via power layer change, turns the 4 "micro" vias into through vias (/NTC 0.3/0.1 → 0.5/0.3), takes JP/TP/MOD1 out of BOM/CPL (PCB + schematic), sets title block + JLC04161H-7628 stackup; on V5.7 also +11 GND vias at U25 and deletes 12 loose items. After T30, V5.6 needs ~1 h of layout (L7 ≤ 5 mm from U7 + Dbk2, U6 VSYS 0.3 mm escape, 3 single vias, DRC exclusions) → Gerber/BOM/CPL → 5-board pilot. V5.7 (f3f35f4) now replicates V5.6, but /SYS5V runs 10.9 mm on In2 at 0.5 mm under K1 (blocker) and the U25 input loop is 52 mm² (target < 30) → ~half a day. v6 (00a9af4, only +15 GND vias since the audit): NOT READY, the 8 blockers of the 16-oct v6 audit stand (U25 still the AP64350 part code, no mounting holes, 5 V on In1/In2 at 0.5 mm, charger U6, U25 layout, modem RF on In1, GND vias, stackup); T25 --set v6 + T28 (kicad/tools/t28_v6_mecanicos.py) still apply; weekend plan rev 1.1 shifted one week (24–25 Oct, 31 Oct–1 Nov, pilot of 20 ordered Mon 2-Nov, G2 ≈ 22-Nov; JLC pre-orders not shifted). Merge incident (19-oct): 40decf8 wrote git conflict markers into both V5.x PCBs — Michelle's branch from f65c830 vs the Friday 18:00 auto-sync (2889ba2) of KiCad files from Leo's Mac; fixed in 240e2c3 + .gitattributes merge=binary (4f4681f). Rule: one person per board at a time, scripts only with KiCad closed and a clean tree; recommended: keep kicad/ out of the auto-sync (decision D-19-3). Canonical: 03-Architecture-Hardware/2026-10-19_Drogheda_Re-Auditoria_V5.6-V5.7-v6_ES_v1.0.md + 2026-10-19_Drogheda_Instrucciones-Michelle_V5.6-V5.7-Pasada-4_ES.md (Michelle) + 2026-10-16_Drogheda_Auditoria-Produccion_v6_ES_v1.0.md + 2026-10-16_Drogheda_Plan-Fines-de-Semana_v6-Produccion_ES.md (site: hardware/re-auditoria-19oct/). V5.6 triage (2026-10-19 PM, on Leo's 18:59 working copy after T30 7650b96). One critical item, new and inherited from V5.5: U6 (LTC4040) has no capacitor at its VSYS pins 1/24 (nearest C34 10 µF at 11.5 mm, C32/C33 47 µF at 15 mm, all behind vias). The datasheet ranks the VSYS cap above everything else (single hot loop: buck 2.25 MHz / boost 1.125 MHz; VSYS abs max 6 V). Fix = add C129 10 µF 0603 X5R 10 V (LCSC C19702, basic) vertical at ≈ (153.07, 111.95) with a GND via, rerouting /PROG, /CLPROG_TP, /CHRG_EN (U6 pins 2–4); no part moves. The 18:59 save also lost T30's two /MAIN5V vias at (145.15/146.15, 97.6) and put /3V3_MODEM through 2 single vias. L7 (8.8 mm from U7) and the V5.5-inherited converter layouts (L6 11.7 mm, L8 35 mm from U12, Dbk1 18 mm from U2) stay for the pilot and are measured on the bench. Canonical: 03-Architecture-Hardware/2026-10-19_Drogheda_V5.6_Clasificacion-Criticos_ES_v1.0.md (site: hardware/v56-clasificacion-19oct/). T31 — C129 in, Dbk2 out (2026-10-20). kicad/tools/t31_c129_vsys_quitar_dbk2.py (dry-run by default, .T31bak, deterministic UUIDs, aborts on drift, idempotent) applied to both V5.6 and V5.7 schematics: C129 10 µF 0603 X5R 10 V (CL10A106KP8NNNC, C19702) on /MAIN5V–GND next to U6 (the missing VSYS cap); Dbk2 removed (U7 AP64350 is synchronous → D-19-2 resolved; the deleted diagonal wire was U7.8's only link to SW3_NODE, so U7.8 now carries its own SW3_NODE label); V5.6 also loses a stray no-connect flag on U10.14 (SC16IS752 SDA, wired to I2C_SDA — KiCad's ERC reports it only depending on read order). Verified on copies: ERC identical (0 errors), netlist only +C129/−Dbk2, schematic parity = exactly "C129 missing" + "Dbk2 extra". Next: Leo runs F8 on both boards (C129 arrives unplaced); Michelle places it at ≈ (153.07, 111.95) — same spot and same 3 signals to reroute on V5.7 — and deletes the Dbk2 branch (V5.6: 5 F.Cu tracks, 18.6 mm; V5.7: 4 tracks, 18.3 mm). Pasada-4 instructions → v1.1 (§0b, A-1, B-0, B-3); figure img/2026-10-20_Drogheda_T31-C129-y-Dbk2_v1.0.png. Audit of Michelle's pass 4 (2026-10-21; HBox_PCB 85e7602 V5.6, 1416dcb V5.7; T31 + F8 in, parity = only PF).* Both boards: C129 placed at (152.2, 111.8) and tied to U6.1/24 on F.Cu; Dbk2 branch gone; U7 rotated 180° (not in the plan) → L7.1–U7.8 4.0 mm (V5.6) / 0.4 mm (V5.7), SW node 13 → 10 / 6 mm, but U7.2 (VIN) now 5–6.5 mm from C119–C121, fed through ONE via under the IC, COMP node 13 → 23 mm. V5.6 NOT READY: new short /MODEM_EN–GND at R106.2 (R105/R106 moved 1.75 mm, the MODEM_EN track end now sits on R106's GND pad → modem never powers) + /SYS5V B.Cu at 0.09 mm from a U7 EP via (DRC errors). Both: VSYS→/MAIN5V down to ONE via, C129 GND has no via (0.25 mm track only), RS1 entry via moved onto the RS1.1 pad edge and its 2nd via dangling; V5.6 3V3_MODEM still 2 single vias. V5.7: K1 blocker solved (/SYS5V off In2), L22.1 2.3 mm from D34.1, but C149/C150 untouched (U25 input loop 52 mm²) and single vias on the 5 V path ((168.0, 110.6) + (162.85, 113.19) carry all of U25 → RS1; (145.9, 57.6) is only the C78/C30 bulk + NTC/5V_SENSE divider branch — corrected PM, the AM text said all of U25's output); 4 one-layer vias. Lesson: DRC with --refill-zones needs the project .kicad_dru in the copy, else false unconnected items. Decision D-21-1 for Leo: C130 100 nF 0402 (C1525) at U7.2. Canonical: 03-Architecture-Hardware/2026-10-21_Drogheda_Auditoria-Pasada-4_V5.6-V5.7_ES_v1.0.md (site: hardware/v56-v57-auditoria-21oct/). T32 + T33 (2026-10-21 PM; D-21-1 approved by Leo). kicad/tools/t32_c130_vin_u7.py (both schematics; imports T31's helpers, so both stay in tools/): C130 100 nF 0402 X7R 16 V (CL05B104KO5NNNC, C1525) /SYS5V–GND = U7.2 VIN bypass; ERC identical, netlist only +C130. kicad/tools/t33_v56_v57_auditoria_21oct.py (both PCBs; per-board plan embedded as JSON; dry-run default, .T33bak, uuid5, aborts on drift): V5.6 R106 short removed (MODEM_EN track now ends on R105.1) and /SYS5V under U7 narrowed 1.0 → 0.7 mm (0.24 mm to the EP via); both: 2nd VSYS→/MAIN5V via; V5.6 +2 vias at each /3V3_MODEM layer change and at /SYS5V (136.97, 86.96)/(146.37, 86.96) (U12 = MP1584 /3V3_ETH branch); V5.7 +2 at /SYS5V (158.6, 57.925) and (136.97, 86.96), via (163.79, 113.19) joined on B.Cu so (162.85, 113.19) is backed; 5 one-layer vias + a 0.14 mm stub deleted. Verified on Mac copies (DRC with .kicad_dru + refill + parity): only the 3 MOD1 errors, 0 unconnected, 0 dangling; parity = "C130 missing" + PF*. Left for Michelle (pass 5, audit section 3): F8; C130 at U7.2 with its own GND via + 2nd U7.2 feed via (needs EN/FREQ/COMP moved ~0.8 mm); C129 GND via(s) (move PROG/CLPROG_TP/CHRG_EN ~0.5 mm); 2nd RS1 entry via; V5.7 C149/C150 + (168.0, 110.6) (+ (145.9, 57.6) if it fits); MH7/9/10 exclusions; optional Rcomp2/Ccomp2/Rfreq2 closer (COMP 13 → 23 mm after the U7 rotation). The planner found no room for those, nor for V5.7 (146.37, 86.96) (U12 branch, accepted 19-oct). Lessons: deleting a via can leave a sub-mm stub (delete it too); a new via with a long stub can split a GND pour island (1 unconnected) → always re-run DRC with parity on the copy before applying. Figure img/2026-10-21_Drogheda_T33-Arreglos-y-Pendientes_v1.0.png.

1. System architecture (corrected from the BOM, 2026-06-20)

 Machine power+ignition (12/24/48/110/230 V, per equipment)
   │
   ▼  ┌──────────────── Gabinete IP67 (ABS, Yetlebox P3901) ─────────────────┐
 breaker│ Phoenix SPD · fuse holder · DIN rail · SSR/opto (ignition isolation)│
 + SPD ►│ Mean Well DDR-60G-24 ──► regulated 24 Vdc ───┐                       │
        │                                              │  GX16-5 connector     │
        │   ┌────────── HBOX (3D-printed ASA) ─────────┼────┐                  │
        │   │ Mean Well SD-15B-05 (18–36V→5V,3A) ──► 5V rail │                 │
        │   │   ├► PowerBoost 1000C (+18650 Li-ion 1S4P) backup                │
        │   │   ├► STM32F411 Blackpill WATCHDOG ──UART(PA2)──► simpleRTK2B Pro  │
        │   │   │     └ switches RTK 5V via 2N3904→IRF9540N (PA1)              │
        │   │   ├► simpleRTK2B Pro (ZED-F9P) + 4G NTRIP Master (XBee LTE)      │
        │   │   └► ignition 24V ──► DFR1015 buck ──► STM32 PA5 (ign sense)     │
        │   └──────────────────────────────────────────────────────────────┘ │
        └───────────────────────────────────────────────────────────────────┘
            4G/LTE ▲ RTCM3 in (NTRIP)        │ NMEA out (UDP)
   Base station (Ardusimple AS-PRO-CORS) ────┘        ▼
            retranslator.py ─(anti-jump+speed filter)─► Wialon / Traccar ─► VERONICA
  • Power into HBOX = clean 24 V from the cabinet (via GX16-5). Internal Mean Well SD-15B-05 makes 5 V; PowerBoost 1000C + 18650 is battery backup; DFR1015 conditions ignition to the Blackpill. (This diagram is the field as-built; the EinarBoard 1.0 carrier supersedes the battery + ignition path — LTC4040 battery-backup on-board, DFR1015 removed entirely (Rev 1.1): GX16 pin 3 raw ignition → 22k/10k divider + BAT54 clamp → PA5. See 03-Architecture-Hardware/watchdog-electrical-design-state.md + the 2026-07-06 audit.)
  • Corrections arrive over the 4G modem (RTCM3 via NTRIP), not the GNSS — so a GNSS reset can't fix a dead link; recover by power-cycling the stack (v2 does).
  • Watchdog = STM32F411; see 03-Architecture-Hardware/watchdog-schematic.

1b. Canonical invariants (inherits Helgen Project Ethos)

The rules this system must never violate. Check every design/code output against these before presenting; if it breaks one, say so and propose the compliant fix.

  1. Power-off is the safe state. The RTK stack defaults OFF (gate pull-up) until the MCU asserts; loss of confidence → safe state, not best-guess.
  2. Never vanish, never loop. A unit must keep reporting (standalone if needed) rather than go silent, and must never enter an infinite fast-reboot loop.
  3. Corrections ride the 4G modem, not the GNSS — recover the link by power-cycling the stack; a GNSS reset is never a fix for lost NTRIP.
  4. No material that softens below ~80 °C (PLA-class) in the thermal path — the current ASA enclosure complies. Design to the measured cabinet-interior temperature, not spec-sheet ambient.
  5. Backend reads/forwards without head-of-line blocking, and the anti-jump filter must never permanently lock out a healthy unit.
  6. No secrets in the repo — ever. (The committed MSSQL password is a live violation to remediate.)

1c. Hard constraints (non-negotiables)

  • HBOX input is the cabinet's regulated 24 V + isolated ignition; don't re-implement the cabinet's surge/breaker/SSR on the HBOX.
  • IP67 maintained — cooling by conduction only; no IP-breaking vents/fans.
  • Bench-test firmware before any field flash (no STM32 build in the sandbox).
  • Client-facing docs are Spanish, routed through Leo.
  • Use the file tools for file changes; verify the shell mount before bulk moves.

2. Directory (Helgen English NN- standard — keep this table current)

Folder Holds Key files
00-Project-Management plan, ethos, hackathon, financials, handover, client comms, Drive tooling 00-Project-Management/PLAN · 00-Project-Management/Engineering-Handover · ethos.md · hackathon-plan.md · Financials.md · Drive-Upload/ · client-comms/
01-Requirements what we build SRS.md · HBOX-product-spec.md
02-Architecture-Software backend/software analysis, ADRs backend-review.md
03-Architecture-Hardware HBOX/cabinet, wiring, BOM, watchdog PCB v3 hardware-respec-and-pcb-brief.md · cabinet-electrical-bom.md · watchdog-schematic.md · watchdog-health-telemetry.md · firmware-review.md · BOM-master.md (+§5 Block B/E/H/I parts) · watchdog-pcb-v3-design.md (schematic spec) · watchdog-pcb-v3-bom.xlsx · watchdog-pcb-v3-kicad-guide.md (KiCad→JLCPCB) · watchdog-pcb-v3-blockdiagram.svg · watchdog-protoboard-bringup.md + watchdog-proto-bench-bringup-v3.md · watchdog-connections.xlsx (PCB pin/net list; H1 DNP; +B/H/I rows) · watchdog-connections-rationale.md (+§7 additions 2026-07-02) · watchdog-electrical-design-state.md (CANONICAL — read first) · watchdog-production-schematic-delta.md (PROD build spec; LTC4040 §4 values) · kicad/ — hbox-watchdog-v3.kicad_sch (DEV/proto) · hbox-watchdog-v3-PROD.kicad_sch/.kicad_pcb (PRODUCTION: ERC 0, layout started, DRC baseline) · Drogheda-sym.kicad_sym (MP1584EN · LTC4040EUFD · AO4406A) · Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx (proto assumptions ledger) · Guia-Conexion-Protoboard/ (LaTeX source; modulos-pinout.tex = visual parts catalog) → Drogheda_Guia-Conexion-Protoboard_ES_v3.1.pdf · 2026-07-08_Drogheda_4G-Modem-Alternatives_v1.0.md (XBee 2.0 mm bridge + cheap-4G survey) · circuitikz-wiring/ (sheet + Beamer v2.1, blocks 1–11; XBee-socket 3V3 fix 07-08; Drogheda_Diagrama-Unico-Proto = todo-en-una-hoja para verificación rápida, Modo B; v1.1 07-10 agrega XBee 20-pin obligatorios VREF(14)→VCC · ON/OFF(20)→GND · GND×4 + USB config + franja de pinouts para el técnico; HiRes-300dpi.png para TV; v1.2 07-20: letras G/D/S·B/C/E en todos los transistores + bloque 5b Q10+DzG 15V) · Guía v3.1 (5b Q10+Zener · 9c pines obligatorios XBee + USB · disipadores · plano 10×10) · lista de compras reconstruida DESDE CERO (1 tarjeta ≈MX$2,087) · watchdog-protoboard-BOM-3boards.xlsx + watchdog-LISTA-DE-COMPRAS-ES.xlsx (proto BOMs; 07-10: +BOB-08276/PRT-08272, buck «MODEM 3.3V», breakout USB-C+cable, botón/LED módem, straps VREF/ON-OFF, surtido +220R/22k) · 2026-07-06_Drogheda_EinarBoard-1.0-PreFab-Audit_v1.0.md (CLOSED — Rev 1.1 fixes) · Assembly-BOM-Split.md + LCSC-search-list.md (verified LCSC) + JLCPCB-Order-Guide.md (ordering runbook) · harness-connector-pinout.md + Socket-Pinout-Silkscreen.md · EinarBoard-Manual/ (Rev 1.1 order-prep pack: einarboard-manual.tex → branded PDF · helgen_einarboard_1.0_production_bom.xlsx · tools/generate_production_bom.py + tools/sync_bom.py Excel→LaTeX BOM sync) — plus repo-root scripts/prep_order_release.sh (safe cleanup + release commit) · 2026-10-16_Drogheda_Auditoria-Produccion_V5.6-V5.7-v6_ES_v1.0.md (production audit + comparison table) + 2026-10-16_Drogheda_Instrucciones-Michelle_V5.6-V5.7-Pasada-3_ES.md · kicad/tools/t25_mounting_holes_v55.py (restores the 7 V5.5 holes) · kicad/tools/t27_paso1_2_mh11_rs1_kelvin.py (MH11 out + RS1 Kelvin, V5.6/V5.7) · kicad/tools/t28_v6_mecanicos.py (v6: U25 part code, stackup, U6 paste) · kicad/tools/t30_v56_v57_mecanicos.py (V5.6/V5.7 mechanical fixes, 19-oct) · kicad/tools/t31_c129_vsys_quitar_dbk2.py (V5.6/V5.7 schematic: C129 at U6 VSYS + Dbk2 out, 20-oct) · kicad/tools/t32_c130_vin_u7.py (V5.6/V5.7 schematic: C130 at U7 VIN, 21-oct) · kicad/tools/t33_v56_v57_auditoria_21oct.py (V5.6/V5.7 PCB fixes from the 21-oct audit) · 2026-10-16_Drogheda_Auditoria-Produccion_v6_ES_v1.0.md + 2026-10-16_Drogheda_Plan-Fines-de-Semana_v6-Produccion_ES.md (v6 audit + weekend plan, rev 1.1) · 2026-10-19_Drogheda_Re-Auditoria_V5.6-V5.7-v6_ES_v1.0.md (re-audit of all three) + 2026-10-19_Drogheda_Instrucciones-Michelle_V5.6-V5.7-Pasada-4_ES.md · 2026-10-19_Drogheda_V5.6_Clasificacion-Criticos_ES_v1.0.md (V5.6 critical vs. can-stay; C129) · 2026-10-21_Drogheda_Auditoria-Pasada-4_V5.6-V5.7_ES_v1.0.md (audit of pass 4, T32/T33 results + pass-5 list for Michelle)
04-Source-Code firmware + backend repos firmware/ (own git repo hbox-firmware: blackpillrtkcode_v2/ deploy · legacy/ v1 · docs/LOGGING-SPEC.md v2.1) · htracker/ · notifications/ · rtk-config/
05-Analytics-Reports SQL views, dashboards (VERONICA/PowerBI), observability 2026-06-22_Drogheda_Manual-Logs-Grafana_v1.0.pdf (Grafana/Loki log-consultation manual)
06-Testing-Validation RCA, diagnostics, test evidence, log analysis & tooling RCA-2026-06-field-failures.md · remote-diagnostic-protocol.md · 2026-06-20_Drogheda_Bench-Log-Analysis_v1.0.md (rev-3) · 2026-06-20_Drogheda_GNSS-Findings-Summary.md · log-analysis/ (repo hbox-log-tools: log-explorer.html · analyze_logs.py · build_dashboard.py · docs/manual.pdf)
Marketing product-facing collateral (LaTeX→PDF) HBOX-Datasheet/ (industrial spec sheet) · HBOX-Brochure-RTK/ (flyer)
99-Archive superseded raw inputs (read-only) situation_ORIGINAL.md
.claude/skills/ vendored project skill project-drogheda/

Structure follows the Helgen Project Template (English NN-). The Google Drive mirror keeps the legacy Spanish 00_…99_ scheme (Drive manual); finalized deliverables export there. Naming: AAAA-MM-DD_Drogheda_Descripción_vX.X — no loose files in root except this index. Empty legacy Spanish dirs remain (the mount can't delete them) — remove locally: rmdir 0?_* 99_Archivo docs hardware …

3. HBOX BOM (per unit, 24 V variant — see 03-Architecture-Hardware/BOM-master)

simpleRTK2B Pro (AS-RTK2B-PROF9P-L1L2-NH-00) · 4G NTRIP Master (AS-XBEE-4G-NA-UFL-00) · Blackpill STM32F411 · U-blox multiband antenna (AS-ANT2B-ANN-L1L2-50SMA) + 2× LTE antennas (AR1582) · Mean Well SD-15B-05 (24→5 V) · PowerBoost 1000C + 18650 1S4P · DFR1015 (ignition) · 2N3904 + IRF9540N + 2N7000 watchdog · GX16-5 HBOX↔cabinet · ASA case/top/ brackets · Telcel micro-SIM.

4. Deployment & people

BUs / terminals: ICAVE (stress lab, live), TIMSA, EIT, LCT. ICAVE machine voltages: RTG 24 V, Reach Stacker 24 V, Empty Handler 24 V, Tractoplana 12 V, Montacargas 12 V. Target: 30 units by August.

Name Email Role
Leo Rodriguez leo@helgen.tech / ceo@helgen.tech Helgen — founder/CEO
Adriana Del Angel adriana@helgen.tech Helgen — implementation/plan
Paola Rodriguez paola@helgen.tech Helgen
Angel Daniel Martinez daniel@helgen.tech Helgen
Gibran Ortega gibran@helgen.tech Helgen — GPS/telemetry
Agustín Alfonseca alfonseca.agustin@icave.com.mx Client — ICAVE Tech Research Supervisor
Leon David Piña pina.david@hutchisonports.com.mx Hutchison Ports

5. Where things live (off this workspace)

  • Google Drive (team source of truth): Drogheda (GPS RTK) — official numbered structure 00–99 + manual LEEME_Drogheda_Estructura_y_Uso. Mirror this workspace's structure to it for finalized deliverables.
  • Second Brain vault (~/Documents/Second Brain/03 Projects/Helgen/): only polished, evergreen notes (decisions, lessons, contacts) — see Project-Drogheda/ once synced.
  • Backend repo: ssh://git.helgen.dev:6611/htracker (retranslator + monitor), cloned at 04-Source-Code/htracker (branch feature/test500unidades).
  • Observability (logs): backend logs ship off-box to Grafana Loki (free tier, 50 GB/mo, 14-day) via Vector (default) or Grafana Alloy reading journald (capped 200 MB) — 04-Source-Code/htracker/log-shipping/ (README.md runbook · setup-logging.sh · vector.toml). Read in Grafana → Explore → Loki: {job="htracker"} (Vector) or {unit="htracker.service"} (Alloy). Consultation manual (PDF): 05-Analytics-Reports/2026-06-22_Drogheda_Manual-Logs-Grafana_v1.0.pdf. Creds in /etc/vector/htracker.env (server) — never in the repo.
  • Firmware repo: ssh://git.helgen.dev:6611/hbox-firmware (STM32F411 watchdog), lives at 04-Source-Code/firmware (branch main) — its own git repo with README, docs/PINOUT.md, redacted RTK-config template, CHANGELOG. Push instructions in its README. v2.1 logging spec at docs/LOGGING-SPEC.md (structured/parseable Blackpill log; not yet flashed).
  • Log-tools repo: ssh://git.helgen.dev:6611/hbox-log-tools (HBOX log analysis — in-browser Log Explorer + batch analyzer + dashboard + Spanish LaTeX manual), lives at 06-Testing-Validation/log-analysis/. Raw logs + config files git-ignored (credentials). Built 2026-06-20.
  • Project tracker: Notion — HBOX Unit Status — Bench Triage board under Project Drogheda — GPS RTK (corrected to rev-3, 2026-06-20) + Mattermost (team chat).

6. Hard facts — don't relearn these

  • NMEA GGA quality ≥4 = healthy (4 = RTK-fixed, 5 = RTK-float).
  • ZED-F9P rated −40…+85 °C — heat casualties are the 18650/PowerBoost and the 4G modem, not the GNSS or the case.
  • The case is ASA (UV-stable, softens ~95–100 °C) — adequate for the nested ABS IP67 cabinet interior; the enclosure is not the liability. A bare fan inside a sealed box does not cool it — conduct heat out, or use a ducted fan (v3.0). See hardware brief §2b.
  • Corrections come over 4G → recover by power-cycling the stack (v2), not a GNSS reset. Backend can take healthy units off Wialon (HOL block + anti-jump lockout).
  • HBOX input = 24 V from the cabinet; design the redesign around that.
  • Firmware: edit 04-Source-Code/firmware/blackpillrtkcode_v2/blackpillrtkcode_v2.ino (own git repo hbox-firmware); bench-test before field flash (sandbox can't build STM32).
  • 20 Jun logs — receivers are fine; RTK is not being achieved. Every board emits valid NMEA (good sats/HDOP) but every epoch is SPS (1), zero RTK (4/5). Corrections aren't applied: free public rtk2go caster (no SLA), F9P config dumped from RAM only (verify saved to FLASH; check the Pro's XBEE↔UART2 switch), plus indoor sky. F9P message config is correct (GGA on UART2 @1 Hz).
  • The 4G-NTRIP-Master console does NOT prove forwarding — a healthy unit logs the same sparse console ("registered", no State main/UDP Bytes sent) as a failed-looking one. Confirm health only from a .ubx (fix), the Blackpill, or a server delivery capture. → "master-14 ingest fault" RETRACTED; only master 21 (modem 0xFFFFF + 511 AT errors) is a confirmed fault.
  • Healthy GNSS baseline = RTK14NTRIP14_440 (server-verified 1 Hz delivery, 12 sats, HDOP 0.75, but SPS not RTK). Raise the bar to an open-sky fix-≥4 capture.
  • Heat is NOT implicated by the bench logs (faults reproduce cold; v1 has no thermal channel). Field thermal hypothesis still needs a thermocouple cabinet soak.
  • dashboard.html predates the rev-3 retraction (still marks the no-forward captures "Failed"); the canonical corrected record is the GNSS summary + the rev-3 findings doc.

7. Working notes

  • Use the file tools (Read/Write/Edit) for file changes; the shell mount can go stale — verify before bulk shell moves. Six empty legacy dirs (docs, firmware, …) remain from the restructure; delete them manually.
  • Client-facing docs are Spanish and route through Leo.

Objectivity — partner, not sycophant

I want an objective partner, not a sycophant. On every task:

  • Genuine take first. Lead with your real assessment. Don't mirror my tone or sentiment, and don't open by validating me.
  • Disagree when you disagree. Say so plainly and explain why — and pair the criticism with a concrete better option (direct and constructive).
  • Self-check. If a reply is about to start with something semantically like "You're right" / "Good point" / "Great question," stop and first answer: "Is this true?"