4f6e1bb347
Block O (modem): U19 A7670SA-LASC (C18548276, LGA-124) - 19 signal nets + 39 GND + 66 NC, all 124 pads accounted for. UART via 1.8V-side nets (_M suffix); USB joins J9 directly (VBUS A4/A9/B4/B9 + DP/DM); USB_BOOT -> TP8; VDD_EXT -> 1V8_MODEM (shifter reference only); NETLIGHT (1.8V) -> R109 4.7k -> Q22 MMBT3904 low-side, reusing the existing Rmled1+D4G1 LED string re-driven: MODEM_LED label -> 3V3, D4G1 cathode GND label -> MODEM_LED_K. Block P (3.8V rail): 24V -> D20 SS34 || MAIN5V -> D21 PMEG3050EP (C50603) -> VIN_MODEM -> U20 AP64350SP-13 (C2071691, 40V/3.5A) -> L20 4.7uH -> VBAT_MODEM. Values from datasheet DS41976: FB 0.8V (R110 75k / R111 20k = 3.8V), RT R117 200k = 500kHz (pin must not float), COMP R116 14k + C141 3.3nF + C142 47pF, BST C129 100nF, EP -> GND. EN = MODEM_PWR_EN (PC10) with R113 100k pull-down: rail DEFAULTS OFF (invariant #1); EN low >= 2s = HARD_CYCLE (invariant #3). Bulk: 2x 220uF/10V (C2827940) + 22uF/1uF/100nF/33pF/10pF + R112 1k bleed + D22 SMAJ5.0A TVS (C113952). VERIFY at layout: D22 pad-1-is-cathode against the fp marker. Block Q (SIM): U22 MFF2_SIM symbol (new in Drogheda-sym; FOOTPRINT TBD "Drogheda:MFF2_5x6_TBD" - build from the chosen carrier chip datasheet; PCB sync will flag it, expected). SIM_VDD 100nF + PESD5V0S1BA on DATA/CLK/RST (D23-25, C2827694, orientation cloned from D14). Block R (level shift): 2x 74LVC2T45DC (C730237, direction-fixed). U23 DIR=GND: 3V3 DIN_4G -> 1.8V DIN_4G_M. U24 DIR=1V8: DOUT_4G_M -> DOUT_4G (also feeds U18 RXD2) and MODEM_STATUS_M -> MODEM_STATUS (PC9). R106 100R taps DOUT_4G -> USART6_RX (PC7). DNP 0R bypasses R107/R108 across the RTCM path. Q20/Q21 2N7002 open-drain on PWRKEY/RESET with 100k pull-downs - MCU absent leaves the modem free (invariant #1). PWRKEY timing: SIMCom >=50ms on / >=2.5s off. CORRECTIONS this pass: (1) the schematic has 382 WIRE SEGMENTS - the earlier "zero wires" finding was a regex artifact (multi-line xy); label-on-pin work was unaffected (all verified against the PCB), but the LED relabel needed a wire-graph trace, now in the script. (2) 9 stale no_connect markers removed from MCU pins that now carry labels (PC1-PC3, PA7, PC8-PC12). (3) A7670SA is a 124-pad LGA, not the 88 claimed in the modem survey. NEXT: Leo runs ERC + Update PCB from Schematic (U22 will complain - footprint TBD, skip it), then T5 = LTC4040 input-limit errata fix + U7/L7 disposition, T6 = RF Block S + netclasses. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
32 lines
1.9 KiB
Plaintext
32 lines
1.9 KiB
Plaintext
(module easyeda2kicad:SOD-128_L3.7-W2.5-LS4.7-RD (layer F.Cu) (tedit 5DC5F6A4)
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(attr smd)
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(fp_text reference REF** (at 0.000 -4.000) (layer F.SilkS)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value SOD-128_L3.7-W2.5-LS4.7-RD (at 0.000 4.000) (layer F.Fab)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text user %R (at 0 0) (layer F.Fab)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(property "LCSC Part" "C50603")
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(fp_line (start -1.98 -1.30) (end 1.98 -1.30) (layer F.SilkS) (width 0.15))
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(fp_line (start 1.98 -1.30) (end 1.98 -1.11) (layer F.SilkS) (width 0.15))
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(fp_line (start -1.98 1.30) (end 1.98 1.30) (layer F.SilkS) (width 0.15))
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(fp_line (start 1.98 1.30) (end 1.98 1.11) (layer F.SilkS) (width 0.15))
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(fp_line (start -1.47 -1.30) (end -1.47 1.30) (layer F.SilkS) (width 0.15))
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(pad 2 smd rect (at 2.20 0.00 180.00) (size 1.250 1.700) (layers F.Cu F.Paste F.Mask))
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(pad 1 smd rect (at -2.20 0.00 180.00) (size 1.250 1.700) (layers F.Cu F.Paste F.Mask))
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(fp_circle (center -2.35 1.23) (end -2.32 1.23) (layer F.SilkS) (width 0.06))
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(fp_line (start -1.90 1.22) (end -1.90 -1.22) (layer F.CrtYd) (width 0.05))
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(fp_line (start -1.90 -1.22) (end 1.90 -1.22) (layer F.CrtYd) (width 0.05))
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(fp_line (start 1.90 -1.22) (end 1.90 1.22) (layer F.CrtYd) (width 0.05))
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(fp_line (start 1.90 1.22) (end -1.90 1.22) (layer F.CrtYd) (width 0.05))
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(fp_poly (pts (xy -1.899996 -1.377391) (xy -1.899996 -0.999998) (xy -2.204796 -0.999998) (xy -2.204796 -1.377391) (xy -1.899996 -1.377391)) (stroke (width 0) (type solid)) (fill solid) (layer "F.SilkS"))
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(fp_poly (pts (xy -1.899996 1.377391) (xy -1.899996 0.999998) (xy -2.204796 0.999998) (xy -2.204796 1.377391) (xy -1.899996 1.377391)) (stroke (width 0) (type solid)) (fill solid) (layer "F.SilkS"))
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(model "Drogheda-v6.3dshapes/SOD-128_L3.7-W2.5-LS4.7-RD-1.wrl"
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(offset (xyz 0.000 0.000 0.000))
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 0))
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)
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) |