Helgen-Services/Drogheda
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
83 Commits 1 Branch 0 Tags 358 MiB
TeX 40.6%
HTML 35.6%
Python 19.8%
Shell 3.3%
C++ 0.7%
4f6e1bb347
Go to file
Claude (Cowork) 4f6e1bb347 v6 T4: Blocks O+P+Q+R - A7670SA LTE island complete in the schematic (33/33 net checks pass) 
Block O (modem): U19 A7670SA-LASC (C18548276, LGA-124) - 19 signal nets + 39 GND + 66 NC,
all 124 pads accounted for. UART via 1.8V-side nets (_M suffix); USB joins J9 directly
(VBUS A4/A9/B4/B9 + DP/DM); USB_BOOT -> TP8; VDD_EXT -> 1V8_MODEM (shifter reference only);
NETLIGHT (1.8V) -> R109 4.7k -> Q22 MMBT3904 low-side, reusing the existing Rmled1+D4G1 LED
string re-driven: MODEM_LED label -> 3V3, D4G1 cathode GND label -> MODEM_LED_K.

Block P (3.8V rail): 24V -> D20 SS34 || MAIN5V -> D21 PMEG3050EP (C50603) -> VIN_MODEM ->
U20 AP64350SP-13 (C2071691, 40V/3.5A) -> L20 4.7uH -> VBAT_MODEM. Values from datasheet
DS41976: FB 0.8V (R110 75k / R111 20k = 3.8V), RT R117 200k = 500kHz (pin must not float),
COMP R116 14k + C141 3.3nF + C142 47pF, BST C129 100nF, EP -> GND. EN = MODEM_PWR_EN (PC10)
with R113 100k pull-down: rail DEFAULTS OFF (invariant #1); EN low >= 2s = HARD_CYCLE
(invariant #3). Bulk: 2x 220uF/10V (C2827940) + 22uF/1uF/100nF/33pF/10pF + R112 1k bleed +
D22 SMAJ5.0A TVS (C113952). VERIFY at layout: D22 pad-1-is-cathode against the fp marker.

Block Q (SIM): U22 MFF2_SIM symbol (new in Drogheda-sym; FOOTPRINT TBD "Drogheda:MFF2_5x6_TBD"
- build from the chosen carrier chip datasheet; PCB sync will flag it, expected). SIM_VDD
100nF + PESD5V0S1BA on DATA/CLK/RST (D23-25, C2827694, orientation cloned from D14).

Block R (level shift): 2x 74LVC2T45DC (C730237, direction-fixed). U23 DIR=GND: 3V3 DIN_4G ->
1.8V DIN_4G_M. U24 DIR=1V8: DOUT_4G_M -> DOUT_4G (also feeds U18 RXD2) and MODEM_STATUS_M ->
MODEM_STATUS (PC9). R106 100R taps DOUT_4G -> USART6_RX (PC7). DNP 0R bypasses R107/R108
across the RTCM path. Q20/Q21 2N7002 open-drain on PWRKEY/RESET with 100k pull-downs -
MCU absent leaves the modem free (invariant #1). PWRKEY timing: SIMCom >=50ms on / >=2.5s off.

CORRECTIONS this pass: (1) the schematic has 382 WIRE SEGMENTS - the earlier "zero wires"
finding was a regex artifact (multi-line xy); label-on-pin work was unaffected (all verified
against the PCB), but the LED relabel needed a wire-graph trace, now in the script.
(2) 9 stale no_connect markers removed from MCU pins that now carry labels (PC1-PC3, PA7,
PC8-PC12). (3) A7670SA is a 124-pad LGA, not the 88 claimed in the modem survey.

NEXT: Leo runs ERC + Update PCB from Schematic (U22 will complain - footprint TBD, skip it),
then T5 = LTC4040 input-limit errata fix + U7/L7 disposition, T6 = RF Block S + netclasses.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-08-25 22:20:39 +00:00
_brand Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
.claude/skills/project-drogheda Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
00-Project-Management auto-sync 2026-07-10 18:00 2026-07-10 18:00:15 -06:00
01-Requirements Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
02-Architecture-Software auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
03-Architecture-Hardware v6 T4: Blocks O+P+Q+R - A7670SA LTE island complete in the schematic (33/33 net checks pass) 2026-08-25 22:20:39 +00:00
04-Source-Code auto-sync 2026-08-20 18:00 2026-08-20 18:00:15 -06:00
05-Analytics-Reports auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
06-Testing-Validation auto-sync 2026-08-18 18:00 2026-08-18 18:00:14 -06:00
99-Archive auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
Marketing auto-sync 2026-07-10 18:00 2026-07-10 18:00:15 -06:00
mcpmarket-me auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
scripts v6 T4: Blocks O+P+Q+R - A7670SA LTE island complete in the schematic (33/33 net checks pass) 2026-08-25 22:20:39 +00:00
.gitignore v4 production package for JLCPCB: gerbers, BOM, CPL + audit 2026-08-01 06:57:17 +00:00
.gitmodules Wire firmware/htracker/log-analysis as proper submodules 2026-06-22 00:03:31 -06:00
CLAUDE.md auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
mcpmarket-plugin-me.zip auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
README.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00

README.md

Project Drogheda (GPS RTK)

Helgen Technologies' HBOX RTK GPS tracker fleet for Hutchison Ports heavy equipment (ICAVE / TIMSA / EIT / LCT) — centimetre-class position over 4G, streamed to the Helgen backend (retranslator → Wialon/Traccar → VERONICA), built to survive a hot, salty, high-vibration port environment.

New here? Read 00-Project-Management/Engineering-Handover.md first. It is the deep context: product, failure analysis, fixes, repo map, open items, glossary. This README is the 2-minute orientation; CLAUDE.md is the terse machine index.

Where we are (2026-06-20 · updated 2026-07-02)

2026-07-02: backend deployed + stable; thermal chamber run done; 3-board protoboard campaign in flight (units to ICAVE 7-jul). Watchdog v3 PROD schematic is complete (ERC 0) — LTC4040 battery-backup sized to the 12 Ah pack, fail-safe Modo-B relay bypass — and the PCB is now a 120×100 carrier board: Blackpill + simpleRTK2B Pro (UNO-shield sockets) + 4G NTRIP Master (on-board XBee socket) all on female headers. Layout in placement review; fab gate = proto bench validation. Canonical: 03-Architecture-Hardware/watchdog-electrical-design-state.md.

We deployed a first batch of HBOX trackers on ICAVE machines in Veracruz. They worked "ish," then failed. We are mid-crisis, hardening for scale — target 30 units by August. The failure is three independent fronts, fixed in parallel:

  1. Backend (confirmed in code) — retranslator.py head-of-line blocks the whole fleet on slow upstream, and an anti-jump filter can permanently black-hole a healthy unit.
  2. Thermal — an ASA case (UV-stable, ~95–100 °C — adequate) sealed in a sealed IP67 cabinet that also holds the heat-generating Mean Well PSU, in full sun → nested heat trap for the battery / boost / modem (not the case).
  3. Prototype hardware — Dupont + hand-wiring + 18650/PowerBoost; fragile under vibration.

Units: all pulled — 4 in hand (3 dead, 1 working-ish) in Veracruz; team in Querétaro → remote debug. Field firmware is v1 (no thermal log).

Free triage: a unit ONLINE in htracker but OFFLINE in Wialon is a backend victim, not dead hardware. Check that before condemning a radio.

The product in one breath

Rover (HBOX) on the machine + Base Station (Ardusimple AS-PRO-CORS, 110/230 V) publishing RTCM3 corrections over NTRIP. The rover gets corrections over the 4G modem, not the GNSS → recover a dead link by power-cycling the 4G stack, never a GNSS reset. HBOX core: simpleRTK2B Pro (ZED-F9P) · 4G NTRIP Master · STM32F411 watchdog · Mean Well SD-15B-05 (24→5 V) · PowerBoost + 18650 · GX16-5 to the cabinet. 24 V is the production variant.

Invariants (never violate)

  1. Power-off is the safe state. 2. Never vanish, never loop. 3. Corrections ride the 4G modem, not the GNSS. 4. No material that softens below ~80 °C (PLA-class) in the thermal path — the ASA enclosure complies; design to measured cabinet temperature. 5. Backend forwards without head-of-line blocking; anti-jump never locks out a healthy unit. 6. No secrets in the repo (the committed MSSQL password is a live violation to rotate).

Repo layout

00-Project-Management (plan, ethos, financials, handover, Drive tooling) · 01-Requirements (SRS, product spec, tracker) · 02-Architecture-Software (backend review) · 03-Architecture-Hardware (cabinet/HBOX, BOM, PCB brief, watchdog, manual) · 04-Source-Code (firmware/ · htracker/ · notifications/) · 05-Analytics-Reports (SQL views — placeholder) · 06-Testing-Validation (RCA, diagnostics) · Marketing (datasheet, brochure) · _brand (LaTeX style) · 99-Archive (raw inputs).

Quick start

# Branded docs (XeLaTeX; League Spartan + MADE Evolve Sans):
cd 01-Requirements/HBOX-Ficha-Tecnica && latexmk -xelatex main.tex

# Firmware (own repo 'hbox-firmware', at 04-Source-Code/firmware):
#   open blackpillrtkcode_v2/blackpillrtkcode_v2.ino in the STM32duino toolchain.
#   ⚠ Bench-test before any field flash — the sandbox cannot build STM32.

# Backend: 04-Source-Code/htracker  (ssh://git.helgen.dev:6611/htracker, feature/test500unidades)

Storage model (one home per artifact)

This repo = working source of truth (editable .md/.tex, code). Google Drive Drogheda (GPS RTK) = finalized exports (branded PDFs, native Docs/Sheets). Second Brain vault = distilled decisions/lessons. Author in repo → export final to Drive → distill to vault. Drive upload how-to + mapping: 00-Project-Management/Drive-Upload/README.md. Never change Drive sharing — that's Leo's call.

Go deeper