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Drogheda/03-Architecture-Hardware
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Claude (Cowork) 4f6e1bb347 v6 T4: Blocks O+P+Q+R - A7670SA LTE island complete in the schematic (33/33 net checks pass) 
Block O (modem): U19 A7670SA-LASC (C18548276, LGA-124) - 19 signal nets + 39 GND + 66 NC,
all 124 pads accounted for. UART via 1.8V-side nets (_M suffix); USB joins J9 directly
(VBUS A4/A9/B4/B9 + DP/DM); USB_BOOT -> TP8; VDD_EXT -> 1V8_MODEM (shifter reference only);
NETLIGHT (1.8V) -> R109 4.7k -> Q22 MMBT3904 low-side, reusing the existing Rmled1+D4G1 LED
string re-driven: MODEM_LED label -> 3V3, D4G1 cathode GND label -> MODEM_LED_K.

Block P (3.8V rail): 24V -> D20 SS34 || MAIN5V -> D21 PMEG3050EP (C50603) -> VIN_MODEM ->
U20 AP64350SP-13 (C2071691, 40V/3.5A) -> L20 4.7uH -> VBAT_MODEM. Values from datasheet
DS41976: FB 0.8V (R110 75k / R111 20k = 3.8V), RT R117 200k = 500kHz (pin must not float),
COMP R116 14k + C141 3.3nF + C142 47pF, BST C129 100nF, EP -> GND. EN = MODEM_PWR_EN (PC10)
with R113 100k pull-down: rail DEFAULTS OFF (invariant #1); EN low >= 2s = HARD_CYCLE
(invariant #3). Bulk: 2x 220uF/10V (C2827940) + 22uF/1uF/100nF/33pF/10pF + R112 1k bleed +
D22 SMAJ5.0A TVS (C113952). VERIFY at layout: D22 pad-1-is-cathode against the fp marker.

Block Q (SIM): U22 MFF2_SIM symbol (new in Drogheda-sym; FOOTPRINT TBD "Drogheda:MFF2_5x6_TBD"
- build from the chosen carrier chip datasheet; PCB sync will flag it, expected). SIM_VDD
100nF + PESD5V0S1BA on DATA/CLK/RST (D23-25, C2827694, orientation cloned from D14).

Block R (level shift): 2x 74LVC2T45DC (C730237, direction-fixed). U23 DIR=GND: 3V3 DIN_4G ->
1.8V DIN_4G_M. U24 DIR=1V8: DOUT_4G_M -> DOUT_4G (also feeds U18 RXD2) and MODEM_STATUS_M ->
MODEM_STATUS (PC9). R106 100R taps DOUT_4G -> USART6_RX (PC7). DNP 0R bypasses R107/R108
across the RTCM path. Q20/Q21 2N7002 open-drain on PWRKEY/RESET with 100k pull-downs -
MCU absent leaves the modem free (invariant #1). PWRKEY timing: SIMCom >=50ms on / >=2.5s off.

CORRECTIONS this pass: (1) the schematic has 382 WIRE SEGMENTS - the earlier "zero wires"
finding was a regex artifact (multi-line xy); label-on-pin work was unaffected (all verified
against the PCB), but the LED relabel needed a wire-graph trace, now in the script.
(2) 9 stale no_connect markers removed from MCU pins that now carry labels (PC1-PC3, PA7,
PC8-PC12). (3) A7670SA is a 124-pad LGA, not the 88 claimed in the modem survey.

NEXT: Leo runs ERC + Update PCB from Schematic (U22 will complain - footprint TBD, skip it),
then T5 = LTC4040 input-limit errata fix + U7/L7 disposition, T6 = RF Block S + netclasses.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-08-25 22:20:39 +00:00
..
CAD-Files auto-sync 2026-07-13 18:00 2026-07-13 18:00:15 -06:00
circuitikz-wiring auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
EinarBoard-Manual sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
Guia-Conexion-Protoboard auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
Informe-Tecnico-V3-V4 auto-sync 2026-08-11 18:00 2026-08-11 18:00:15 -06:00
kicad v6 T4: Blocks O+P+Q+R - A7670SA LTE island complete in the schematic (33/33 net checks pass) 2026-08-25 22:20:39 +00:00
Manual-Instalacion-Operacion Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
4G-USB-Reset-LED-addition.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
0007-1000_Assembly_Guide.pdf auto-sync 2026-07-11 18:00 2026-07-11 18:00:15 -06:00
2026-07-06_Drogheda_EinarBoard-1.0-PreFab-Audit_v1.0.md sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
2026-07-08_Drogheda_4G-Modem-Alternatives_v1.0.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
2026-07-24_Drogheda_EinarBoard-1.1_Design-Brief_v1.0.md EinarBoard 1.1 design brief: locked decisions (RS-485+RS-232 via SC16IS752, on-board W5500 Ethernet, RGB status LED, board growth) + execution phases 2026-07-29 01:58:39 +00:00
2026-08-08_Drogheda_Firmware-v3.1_ModoB-PHLG_Design-Brief_v1.0.md auto-sync 2026-08-08 18:00 2026-08-08 18:00:15 -06:00
2026-08-12_Drogheda_EinarBoard-3.0_MCU-Integration_Design-Brief_v1.0.md auto-sync 2026-08-12 18:00 2026-08-12 18:00:16 -06:00
2026-08-14_Drogheda_EinarBoard-3.0_Capacitor-Placement-Map_v1.0.md auto-sync 2026-08-14 18:00 2026-08-14 18:00:14 -06:00
2026-08-20_Drogheda_EinarBoard-v5_Fixes-Applied_v1.0.md auto-sync 2026-08-20 18:00 2026-08-20 18:00:15 -06:00
2026-08-20_Drogheda_EinarBoard-v5_Pre-Audit-Checks_v1.0.md checkpoint: v5.5 as saved by Leo before Claude fixes (pre-audit report included) 2026-08-20 16:37:33 +00:00
Assembly-BOM-Split.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
BOM-master.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
bom.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
cabinet-electrical-bom.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.png 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.svg 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_EinarBoard-1.0_Tabla-Conexiones-Externas_v1.0.pdf auto-sync 2026-07-23 18:00 2026-07-23 18:00:14 -06:00
Drogheda_Guia-Cableado-Proto-Watchdog-v3_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v2.2.pdf auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.0.pdf auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.1.pdf auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
Drogheda-BOM-Maestro.xlsx Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda-Manual-Instalacion-Operacion.pdf Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-v3-pinned-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
firmware-review-v2.3-EinarBoard.md Firmware review: v2.3 as EinarBoard 1.0 production candidate (2026-07-24) 2026-07-24 01:27:20 +00:00
firmware-review.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
hardware-respec-and-pcb-brief.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
harness-connector-pinout.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
hbox-watchdog-v5-schematic.pdf auto-sync 2026-08-12 18:00 2026-08-12 18:00:16 -06:00
JLCPCB-Order-Guide.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
LCSC-search-list.md auto-sync 2026-07-07 18:00 2026-07-07 18:00:12 -06:00
Socket-Pinout-Silkscreen.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
watchdog-connections-rationale.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-connections.xlsx 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-electrical-design-state.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
watchdog-health-telemetry.md add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-LISTA-DE-COMPRAS-ES.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-pcb-v3-blockdiagram.svg auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-bom.xlsx add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-pcb-v3-design.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-pcb-v3-kicad-guide.md auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-routing-status.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
watchdog-production-schematic-delta.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-proto-bench-bringup-v3.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-protoboard-BOM-3boards.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-protoboard-bringup.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-schematic.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00