Drogheda/03-Architecture-Hardware/2026-10-13_Drogheda_EinarBoard-V5.6_Audit-Michelle-Pass_NOT-READY_EN.md

# EinarBoard HBOX V5.6 — Purchase-readiness audit of Michelle's pass (kicad `d71098d`, 13-Oct-2026)

**Verdict: NOT READY — one more layout pass.** Independent review agent (59 checks, files only: PCB d71098d vs b508a2c, schematic, KiCad XML netlist, kicad-cli DRC JSON). Cross-checked by Claude's own pad-level parity run (0 differences). Michelle's correction list (ES): `2026-10-13_Drogheda_Instrucciones-Michelle_V5.6-Pasada-2_ES.md`.

---


Reviewer: independent (files only, no prior knowledge of the board). Date: 2026-10-13.
Inputs: `hbox-watchdog-v5.kicad_pcb` (after layout pass, 13-Oct), `pcb_pre_michelle_b508a2c.kicad_pcb` (12-Oct, before the pass), `hbox-watchdog-v5.kicad_sch`, `v56-netlist-1013.xml`, `v56-drc-1013-nofill.json`. Analysis with Python 3 stdlib on the s-expression trees (pad positions = footprint `at` + rotated pad `at`; connectivity by true copper-shape overlap incl. zone fills; IPC-2221 with k=0.048 external / 0.024 internal, 1 oz outer = 35 µm, 0.5 oz inner = 17.5 µm as specified for the JLCPCB 4-layer stackup).

## 1. Verdict

**NOT READY.** Do not order this revision. The layout pass introduced a battery-path regression that would act as a fuse (0.5 mm trace on the In1 GND-plane layer carrying up to 2–4 A), moved six edge connectors and 12 other parts that were explicitly frozen, failed to do items 4 and 5 of the brief, and placed U26 and its decoupling away from the requested location/distances. Independently of this pass, the pre-existing board carries three more power paths through undersized inner-layer traces (MAIN5V, SYS5V, U7 switch node) that must also be corrected before any order. Pad-level schematic parity, zone fills, and DRC clearance are otherwise clean.

## 2. Findings, ranked

### BLOCKER

**B1. `/BAT_PLUS` from P4.1 now runs 10.7 mm on In1.Cu at 0.5 mm width, then through a single 0.3 mm-drill via — in series with the whole battery current.**
Path P4.1 (165.10, 44.88) → In1.Cu 0.5 mm: (165.10,44.88)→(165.10,52.70)→(165.85,53.45)→(165.85,55.25) [10.69 mm] → via 0.8/0.3 at (165.85,55.25) → B.Cu 1.0 mm, 52.9 mm → via (180.12,100.81) → In2 1.5 mm 9.6 mm → via (179.96,109.61) → F.Cu 1.0 mm → L6.2. Every element listed is a single-point series element (removing it disconnects P4 from L6/U6/C35; there is no zone or parallel copper on this net).
IPC-2221, 0.5 mm × 17.5 µm internal: **0.44 A at ΔT=10 °C, 0.59 A at 20 °C, 0.71 A at 30 °C**. At the 1.4 A charge current the formula extrapolates to ≈140 °C rise; at 2 A ≈300 °C; 4 A peaks are not survivable — the trace is a buried fuse under the connector row, and it also slots the GND plane right where P4.2 returns the same current. Even if JLCPCB inner copper were 1 oz, capacity is only 0.72 A at 10 °C.
Before the pass: P4.1 (190.2,44.64) → B.Cu 1.5 mm for 63.8 mm → via (180.12,100.81) → In2 1.5 mm 9.6 mm → via → F.Cu 1.0 → L6.2; narrowest element 1.5 mm/B.Cu = 3.21 A @10 °C (the pre-existing In2 1.5 mm/0.5 oz stretch = 0.97 A @10 °C, see M3). Trunk resistance ≈27 mΩ before vs ≈53 mΩ now (In1 0.5 mm alone ≈21 mΩ → 0.34 W at 4 A).
Fix: route P4.1 → U6/L6 entirely on outer copper at ≥1.5 mm (2.0 mm preferred for 4 A peaks), no inner-layer segments, ≥2 vias (0.5 mm drill) wherever a layer change is unavoidable. Instruction 7 ("do not change track widths") was also violated: the trunk went 1.5 → 1.0 mm on B.Cu.

**B2. Six edge connectors and 12 other components were moved although instruction 7 froze everything except the U26 block.**
P4 (battery) −25.1 mm in x (190.2 → 165.1), P6 −17.7, P8 −17.4, P2 −12.6, P11 −12.1, P10 −11.1 mm, all along the top edge; plus F1, JP1, D1, D6, R3, Q2, Rgs1, Rigb1, Rled1, R112, TP6, TP7 (table §4.3). The whole top connector row was compacted leftwards to make room for U26/C126–C128/TP6/TP7 at x≈88–101. Any enclosure cut-outs, panel labels, harness lengths or test fixtures referenced to the previous connector positions are now wrong. The move is also what forced the BAT_PLUS re-route (B1) and the NTC/LED/FAN/SYS5V/MAIN5V/VEH5V re-routes (457 segments and 85 vias changed in total). Fix: revert all 18 non-U26 footprints and their routing to b508a2c unless Leo explicitly approves the new connector positions.

### MUST-FIX-BEFORE-ORDER

**M1 (pre-existing). `/MAIN5V`: U6.1/24 (VSYS, boost output up to 2.5 A in backup) leaves the IC through a 0.3 mm × 1.05 mm F.Cu neck → one 0.3 mm via (153.19,110.88) → In1.Cu 1.0 mm, 15.1 mm (153.20,110.89)→(160.79,110.89)→(166.09,116.19) → one 0.3 mm via → F.Cu.** All series for every MAIN5V load (P11, JP6, Q7). In1 1.0 mm/0.5 oz = 0.72 A @10 °C; 2.5 A → ≈170 °C rise (≈55 °C even at 1 oz inner). Present identically in b508a2c — not introduced by the pass, but it is the backup-power path and must be fixed: bring VSYS out on F.Cu/B.Cu ≥1.5 mm with 2+ vias, no In1 segment.

**M2 (pre-existing). `/SYS5V`: the only path from P11.2/JP6.2 to U7.2 (modem buck VIN, ≈1.4–2 A) and U12.2 is K1.2 → B.Cu 1.0 → via 0.6/0.3 (158.60,57.92) → In2.Cu 0.5 mm, 9.1 mm (158.64,57.95)→(156.47,57.95)→(154.19,60.23)→(154.19,63.06)→(153.57,63.69) → via 0.8/0.3 → F.Cu 0.75/0.5 mm.** In2 0.5 mm/0.5 oz = 0.44 A @10 °C; 1.5 A → ≈160 °C rise. Also 31 mm of 0.5 mm F.Cu (1.45 A @10 °C) in series on the way to U7. Fix: 1.0–1.5 mm outer-layer route P11 → U7/U12 input caps, 2 vias per transition.

**M3 (pre-existing). Inner-layer 1.5 mm segments in the battery trunk and BAT pin path at 0.5 oz:** In2 1.5 mm, 9.6 mm (178.77,102.17)→(179.94,109.59) in series to L6.2 (0.97 A @10 °C; 2 A → ≈52 °C), and In1 1.5 mm, 21.7 mm (156.18,99.89)→(172.75,106.28) to U6.23/C35. Two 0.3 mm-drill vias in series carry the full battery current (≈1.8 A @10 °C each by annular-ring area). Fix together with B1: outer layers only, 2× vias ≥0.5 mm drill.

**M4 (pre-existing). `/SW3_NODE` (U7 pin 8 switch node → L7.1) runs 12.85 mm on In1.Cu at 0.5 mm through two 0.3 mm vias** ((136.0,105.0)→(142.68,111.68)→(142.68,115.08)). 0.44 A @10 °C for a node carrying the full inductor current (2 A peaks), and a high-dv/dt switching node slotted into the GND reference plane under the modem supply. Fix: SW node on F.Cu only, short and wide (≥1.0 mm), L7 adjacent to U7.

**M5. Instruction 5 not done: title blocks still read Rev "3.0".** PCB title block: date 2026-08-12, rev 3.0 (unchanged pre→cur). Schematic: date 2026-07-07, rev 3.0. Silkscreen "HBOX v5.6 - 2026-10" / "EINARBoard 5.6" is present (it already was in b508a2c). Fabrication drawings/Gerber job file will carry the wrong revision.

**M6. Instruction 4 not done, and reversed: In1 (GND plane) gained 90 mm of new signal routing.** The two `/NTC_CELL` In1 segments (114.4,52.2)→(119.2,52.2)→(123.0,56.0) are still on In1.Cu (ADC input to U16 pin 25). New on In1: `/I2C_SDA` 30.7 mm, `/I2C_SCL` 28.9 mm, `/ACC_INT1` 29.6 mm, all 0.25 mm, running x≈109–125, y≈51–75, i.e. straight under the MCU (In1 signal copper inside the U16 13×13 mm courtyard went 45.4 → 56.0 mm). Plus the `/BAT_PLUS` 0.5 mm slot (B1). In1 totals: 917 → 985 mm of non-GND tracks, 27 → 28 nets.

**M7. U26 block placed away from the request and decoupling out of spec.** U26 at (93.2, 44.68) instead of (124.5, 84.5) — 3.4 mm from the top board edge, 30 mm from U16. C126.1 → U26.7 (VDD) = 3.43 mm, C127.1 → U26.3 (VDDIO) = 3.06 mm (spec ≤2 mm); both caps sit on the left of the part while VDD/VDDIO pins are on the right. C128 (10 µF) courtyard is 0.50 mm from the board edge (pad edge ≈0.85 mm) — below JLCPCB's ≥1 mm component-to-edge guidance. An 0.8 mm GND via sits dead-centre under the LGA body at (93.2,44.6) (tented per `(tenting (front yes))`, acceptable but unnecessary). Pad nets are correct (1 GND/SDO, 2 SDA, 3 VDDIO, 5 INT1→U16.62 PB9, 7 VDD, 8/9 GND, 10 CS→3V3, 12 SCL; 4/6/11 unconnected), pin-1 marker coincides with pad 1 (bottom-left, CCW numbering, LGA top view). Routing to U16: ACC_INT1 19.3 mm F.Cu + 29.6 mm In1; SDA/SCL ≈19–22 mm F.Cu + ≈30 mm In1 each (see M6).

**M8. BOM hygiene for SMT order.** 14 non-DNP symbols carry no LCSC code and are not marked exclude-from-BOM: JP1–JP6 (solder jumpers), TP1–TP7 (test points), MOD1 (header outline) — JLCPCB's BOM import will flag them; set `exclude_from_bom`/DNP or add codes. LCSC C5126709 (U26 SC7A20TR) showed "out of stock" on LCSC at review time and is an Extended part — confirm stock before ordering. 10 nF 0603 uses two different codes (C57112 and C1589) — consolidate. DNP: Dbk2 (SS34), R109 (10k). No empty footprints. 20 through-hole footprints (connectors, K1, SW1/SW2, H4, MOD1) are hand-assembly or JLC TH-assembly items.

### SHOULD-FIX

**S1. Dangling copper (DRC warnings, all in the changed area):** `/BAT_PLUS` B.Cu 1.5 mm stub (181.53,100.79)→(180.13,100.79), 1.40 mm — remnant of the old right-edge trunk; `/3V3_ETH` In2 spur (105.16,47.89)→(104.72,48.32), 0.61 mm; `/24V` via at (181.04,64.075) connected on F.Cu only — the "stray via" at (182.92,60.325) from instruction 2 was removed but a new dangling one was created when the C22 stub was re-drawn.
**S2. Silkscreen regressions from the moves:** Rig1 reference text over Rigb1 pad 2 (GND) at (131.6,50.6); Rled1 reference text over D5 pad 1 (/3V3) at (121.6,50.7); silk-overlap pairs U7/Cbst2 (pre-existing), Rig1/Rigb1, D5/Rled1.
**S3 (pre-existing). `/SW_IN` (F1 PPTC 4 A → Q1 → MOD1 5 V) runs 85.3 mm on In2.Cu at 1.0 mm** (0.72 A @10 °C), lengthened from 74.6 mm by the pass. Either the PPTC rating or the trace is wrong; move to outer layer ≥1.5 mm or document the real MOD1 current.
**S4 (pre-existing). `/3V3_MODEM` L7.2 → J7.1: 54 mm of 0.5 mm F.Cu in series** (1.45 A @10 °C; ≈54 mΩ → ≈110 mV drop at 2 A modem peaks). Widen to ≥1.0 mm.
**S5 (pre-existing). U6 EP DFM:** 6 paste windows 0.95×0.85 mm = 4.84 mm² of 9.67 mm² EP (50 %) and 3 GND vias 0.6/0.3 in the EP — as per the standing rule — but two of the vias ((155.74,111.92) and (157.13,111.88)) are centred inside paste windows (155.79,111.9)/(157.11,111.9): paste printed over an open via barrel wicks solder and is a known cause of EP voids/solder balls. Recommend shifting those two vias into the gaps between windows (or specify plugged vias) while keeping the 50 % rule. U6 footprint is byte-identical pre→cur (rule respected by the pass).
**S6 (pre-existing). `/VEH5V` trunk P2.1 → RS1.1 is 122.8 mm of 1.0 mm B.Cu** (2.39 A @10 °C; ≈61 mΩ → ≈150 mV at 2.5 A) — marginal for the 2.5 A rating; 1.5 mm recommended. Lengthened by 11.8 mm by the connector move.
**S7 (pre-existing). No mounting holes anywhere on the 140×100 mm board** (no MH*/NPTH footprints, no Edge.Cuts circles). Confirm the enclosure retains the board by other means before ordering.
**S8. Stackup declared in KiCad does not match the JLCPCB order:** all four copper layers are 0.035 mm in `(stackup)`, dielectrics 0.48/0.48/0.48 mm. JLCPCB 4-layer uses 0.5 oz inner copper (and ≈0.21/1.06/0.21 mm dielectrics). This is probably why inner traces were sized as if they were 1 oz; fix the stackup so the current-capacity tooling tells the truth.

### NOTE

N1. Pad-level parity is clean: 813/835 netlist nodes match exactly; 9 differ only by the `/`→`{slash}` encoding of unconnected pin names on U10; 13 are PWR_FLAG PF* nodes (no footprint, expected). No footprint without a symbol, no footprint-name or value mismatch.
N2. DRC: 0 errors, 0 unconnected, 13 parity items (all PF* missing footprints), 97 warnings = 85 `lib_footprint_mismatch` (library drift, noise), 2 `silk_edge_clearance` (MOD1 outline past the left edge, noise), 5 `silk_overlap`, 2 `silk_over_copper` (S2), 2 `track_dangling` + 1 `via_dangling` (S1). Ignored checks: missing_courtyard, track_not_centered_on_via, tuning_profile, footprint_filters, footprint_type.
N3. Zones: all 4 copper zones carry `filled_polygon`s and the fills are fresh (no foreign copper inside any fill; the pre-pass file had U26 pads inside the F.Cu pour, so the refill was done). `P3V3_PLANE_IN2`: 1 polygon, 11 563 mm² (one piece ✓). `GND_PLANE_IN1`: 4 polygons — main 11 796 mm² (84 % of board area) + islands 28.1, 11.3, 0.8 mm²; the plane is not fragmented into islands but it is heavily slotted (see M6; largest In1 signal runs: /IGN_IN 116 mm @1.0 mm, /MODEM_LED_MCU 89 mm, /I2C_SDA 76 mm, /RTCM_TAP 74 mm, /MODEM_RST_MCU 69 mm, /I2C_SCL 66 mm, 4× /BATLED 44–61 mm). `MAGJACK_NO_POUR` is a keep-out (no fill, correct).
N4. `/24V` Q10.3 → U2.7 runs 47 mm on In2 at 1.0 mm (0.72 A @10 °C) for ≈0.7 A — acceptable (~10 °C). `/3V3_ETH` 27.9 mm on In2 at 1.0 mm (different 3.3 V rail cutting the 3V3 plane) — acceptable.
N5. U26 pin 4 is left unconnected; the SC7A20 datasheet names it NC but its connection table lists GND in all modes — harmless to tie to GND in the next schematic touch. I²C pull-ups R30/R31 present; address 0x18 (SDO=GND) and CS=3V3 (I²C mode) are correct. Footprint pad arrangement (4-2-4-2, CCW from pad 1 bottom-left) matches the "BL" LCSC-style footprint convention but could not be checked against the datasheet figure from text — verify against the JLCPCB/EasyEDA footprint for C5126709 before first build.
N6. Courtyards: 4 overlaps, all pre-existing (C35/U6, C3/C123, C3/JP5, C32/D19); none introduced. No copper within 0.5 mm of the board edge (closest: /3V3_ETH 1.0 mm tracks at y=41.40, 0.58 mm). No acute (<45°) track junctions; 2 exact duplicate segments (GND F.Cu at (125.33,75.86), /CHRG_EN at (148.0,108.0), pre-existing).
N7. `/SW_BAT` (L6.1 → U6.21/22) is 11 mm at 1.0 mm plus a 0.75 mm neck on F.Cu (1.94 A @10 °C neck) — acceptable for short peaks, but 1.5 mm would match the BAT trunk.
N8. C35 (the only BAT_PLUS capacitor) is 20 mm from L6.2 and reached through two vias and the In1 1.5 mm run (M3); the charger's output ripple loop is long. Consider a second 22 µF at L6.2.
N9. Items of instruction 2 that were done: the old `/24V` via at (182.92,60.325) is gone; no P12/R42/C24 copper remains near (181,45) (nothing dangles there). K1 only had the uuid of its reference text regenerated (harmless).

## 3. Instruction-by-instruction status

| # | Instruction | Status | Evidence |
|---|---|---|---|
| 1 | Update PCB from schematic (add U26, C126–C128; remove P12, R42, C24) | Already done in b508a2c (pre-pass board has all four, none of the three) — nothing further required; parity clean | §4.1 |
| 2 | Remove P12/R42/C24 leftovers near (181,45) and stray /24V via (182.9,60.3) | Partly: old via removed, no leftovers near (181,45); but a new dangling /24V via at (181.04,64.08) and a dangling /BAT_PLUS stub at (181.5,100.8) were left | S1 |
| 3 | Place U26 near (124.5,84.5); C126/C127 ≤2 mm from pins 7/3; route SDA/SCL/3V3/GND/INT1→PB9; 4/6/11 NC | Done differently: U26 at (93.2,44.68); caps 3.43 / 3.06 mm; nets and connectivity correct; INT1→U16.62 ✓ | M7 |
| 4 | Move /NTC_CELL In1 segments to B.Cu so In1 has no tracks under the MCU | Not done; /NTC_CELL still on In1 and 90 mm of new In1 signal tracks added under/near U16 | M6 |
| 5 | Silkscreen v5.6 texts; title block Rev 5.6 + date on PCB and schematic | Silk texts present (pre-existing); title blocks NOT updated (PCB rev 3.0 / 2026-08-12, SCH rev 3.0 / 2026-07-07) | M5 |
| 6 | Refill zones; DRC: 0 unconnected, 0 parity, 0 dangling; In2 plane one piece | Zones refilled ✓; 0 unconnected ✓; parity = 13 PF* only ✓; 3 dangling items ✗; In2 plane 1 polygon ✓ | N2, N3, S1 |
| 7 | Do not move other parts, change widths, touch U6 paste, use bottom side | Violated: 18 non-U26 footprints moved (6 connectors), BAT_PLUS trunk 1.5→1.0 mm plus a 0.5 mm In1 run; U6 untouched ✓; no bottom-side components added ✓ (B.Cu tracks were already in use) | B1, B2, §4.3 |

## 4. Raw tables

### 4.1 Parity (netlist `v56-netlist-1013.xml` vs current PCB)

| Quantity | Value |
|---|---|
| Netlist components | 253 (incl. 13 PWR_FLAG PF*, 2 DNP: Dbk2, R109) |
| PCB footprints | 240 (pre-pass also 240) |
| In netlist, no footprint | 13 — PF1, PF2, PF4–PF14 (PWR_FLAG, expected) |
| On PCB, not in netlist | 0 (no MH* exist) |
| Footprint-name mismatches / value mismatches | 0 / 0 |
| Netlist (ref,pin) nodes | 835 |
| Exact net match on PCB pad | 813 |
| Name-encoding-only differences | 9 (U10 pins 12,18–21,25–28: `/` vs `{slash}` in unconnected-net names) |
| PWR_FLAG nodes (no pad) | 13 |
| Real mismatches / missing pads / extra-net pads | 0 / 0 / 0 |
| Pads on `unconnected-*` nets | 76 (77 no-connects in schematic) |
| Track/via nets not in netlist | 0 |

### 4.2 DRC classification (`v56-drc-1013-nofill.json`, KiCad 10.0.4, severities error/warning/exclusion)

| Type | Count | Class |
|---|---|---|
| errors (any) | 0 | — |
| unconnected_items | 0 | — |
| schematic_parity: missing_footprint PF1…PF14 | 13 | expected noise (PWR_FLAG) |
| lib_footprint_mismatch | 85 | library drift, noise (C80–C118, R80–R97, D14–D18, U3/U6/U10–U17, Y1–Y4, P1/P4/P8/P10/P14–16, JP5, H4, MOD1) |
| silk_edge_clearance (MOD1 outline at x=56–62) | 2 | expected noise |
| silk_overlap | 5 | 2 pre-existing (U7/Cbst2), 3 new (Rig1/Rigb1, D5/Rled1 ×2) |
| silk_over_copper | 2 | new (Rig1 ref on Rigb1 pad; Rled1 ref on D5 pad) |
| track_dangling | 2 | /3V3_ETH In2 (105.155,47.89) 0.61 mm; /BAT_PLUS B.Cu (181.525,100.79) 1.40 mm |
| via_dangling | 1 | /24V via (181.04,64.075), F.Cu only |

### 4.3 Footprints moved in the pass (22 of 240; none added/removed; no footprint-name/value/pad-net changes)

| Ref | Value | Before (x,y,rot) | After (x,y,rot) | Shift mm | Classification |
|---|---|---|---|---|---|
| C126 | 100nF | (116.62,95.105,0) | (89.8,44.4,180) | 57.4 | required (U26 block) |
| C127 | 100nF | (116.62,97.615,0) | (89.8,46.6,180) | 57.6 | required (U26 block) |
| C128 | 10uF | (116.84,92.345,0) | (89.6,41.8,180) | 57.4 | required (U26 block) |
| U26 | SC7A20TR | (120.445,95.54,0) | (93.2,44.68,0) | 57.7 | required (but not at requested 124.5,84.5) |
| D1 | LED | (176.37,43.645,90) | (159.8,43.6,90) | 16.6 | NOT requested (instr. 7) |
| D6 | 1N4148W | (152.24,48.2675,90) | (152.2,52.6,90) | 4.3 | NOT requested (instr. 7) |
| F1 | PPTC 4A/8A 12V 1812 | (147.2,43.91,180) | (132.4,43.8,180) | 14.8 | NOT requested (instr. 7) |
| JP1 | 0R | (154.26,44.05,180) | (137.6,44.4,180) | 16.7 | NOT requested (instr. 7) |
| P10 | RESET-EXT | (116.655,44.655,0) | (105.55,44.6,0) | 11.1 | NOT requested (instr. 7) - connector |
| P11 | CUTOFF-SW | (135.8,44.755,0) | (123.7,44.6,0) | 12.1 | NOT requested (instr. 7) - connector |
| P2 | 5V-IN-SD15B05 | (127.2,44.795,0) | (114.6,44.6,0) | 12.6 | NOT requested (instr. 7) - connector |
| P4 | BATT-1S4P+NTC | (190.2,44.64,0) | (165.1,44.875,0) | 25.1 | NOT requested (instr. 7) - connector |
| P6 | FAN 2-pin | (160.41,44.755,0) | (142.7,44.755,0) | 17.7 | NOT requested (instr. 7) - connector |
| P8 | PANEL_LED | (169.3,44.755,0) | (151.9,44.8,0) | 17.4 | NOT requested (instr. 7) - connector |
| Q2 | AO3400A | (145.8,49.0,0) | (149.0,50.4,0) | 3.5 | NOT requested (instr. 7) |
| R112 | 4.7k | (98.2,48.4,0) | (101.8,50.4,0) | 4.1 | NOT requested (instr. 7) |
| R3 | 120R | (170.25,50.47,0) | (159.2,46.4,180) | 11.8 | NOT requested (instr. 7) |
| Rgs1 | 100k | (142.8,48.8,-90) | (146.0,50.4,-90) | 3.6 | NOT requested (instr. 7) |
| Rigb1 | 3.3k | (128.585,49.575,0) | (130.6,50.4,0) | 2.2 | NOT requested (instr. 7) |
| Rled1 | 10k | (123.145,45.65,90) | (121.4,52.625,90) | 7.2 | NOT requested (instr. 7) |
| TP6 | GND | (107.38,42.14,0) | (97.8,42.6,0) | 9.6 | NOT requested (instr. 7) |
| TP7 | 3V3 | (110.465,42.23,0) | (100.6,42.6,0) | 9.9 | NOT requested (instr. 7) |

Pass totals: segments 2102 → 2139 (210 removed, 247 added), vias 343 → 352 (38 removed, 47 added), zones 5 → 5 (refilled), gr_text unchanged (21). Nets with changed routing (bbox of change): /24V, /3V3, /3V3_ETH, /5V_FAN, /ACC_INT1 (new), /BASE_LS, /BAT_PLUS, /BOOT0, /BYP_CTRL, /ETH_ACT_A, /ETH_LNK_A, /ETH_PMODE, /ETH_RST, /EXT_LED, /FAN_GATE, /FAN_RET, /I2C_SCL, /I2C_SDA, /IGN_SENSE, /KCOIL, /LED_A, /LED_K, /MAIN5V, /MODEM_EN, /NRST, /NTC, /SWCLK, /SW_IN, /SYS5V, /USART1_RX, /VEH5V, GND.

### 4.4 IPC-2221 reference (A, ΔT = 10 / 20 / 30 °C)

| Width | F/B.Cu 1 oz (35 µm) | In1/In2 0.5 oz (17.5 µm) | inner if 1 oz |
|---|---|---|---|
| 0.25 mm | 0.88 / 1.19 / 1.42 | 0.26 / 0.36 / 0.43 | 0.44 / 0.59 / 0.71 |
| 0.3 mm | 1.00 / 1.36 / 1.62 | 0.30 / 0.41 / 0.49 | 0.50 / 0.68 / 0.81 |
| 0.5 mm | 1.45 / 1.96 / 2.35 | 0.44 / 0.59 / 0.71 | 0.72 / 0.98 / 1.17 |
| 0.75 mm | 1.94 / 2.63 / 3.15 | — | — |
| 1.0 mm | 2.39 / 3.24 / 3.88 | 0.72 / 0.98 / 1.17 | 1.20 / 1.62 / 1.94 |
| 1.5 mm | 3.21 / 4.35 / 5.20 | 0.97 / 1.32 / 1.57 | 1.60 / 2.18 / 2.60 |
| 2.0 mm | 3.95 / 5.36 / 6.41 | 1.20 / 1.62 / 1.94 | 1.98 / 2.68 / 3.21 |
| via 0.3 drill, 25 µm plating | 1.80 / 2.44 / 2.91 | | |
| via 0.4 drill | 2.21 / 3.00 / 3.59 | | |

Temperature rise at rated current, worst series element: BAT_PLUS In1 0.5 mm @0.5 oz: 1.4 A → ≈140 °C, 2 A → ≈316 °C, 4 A → off-scale; In1 0.5 mm even at 1 oz: 2 A → ≈100 °C. B.Cu 1.0 mm: 2 A → 7 °C, 4 A → 32 °C (was 3 / 17 °C at 1.5 mm). Inner 1.5 mm @0.5 oz: 2 A → 52 °C. MAIN5V In1 1.0 mm: 2.5 A → ≈170 °C. SYS5V In2 0.5 mm: 1.5 A → ≈160 °C.

### 4.5 High-current nets — total copper by layer/width and series-path analysis (pre vs cur)

| Net | Board | Segments | Vias | Length by layer/width (mm) |
|---|---|---|---|---|
| /BAT_PLUS | pre | 40 | 6 | B.Cu/0.3: 0.2, B.Cu/0.5: 33.2, B.Cu/1.5: 72.3, F.Cu/0.3: 1.5, F.Cu/0.5: 17.6, F.Cu/1.0: 2.5, F.Cu/1.5: 11.4, In1.Cu/1.5: 21.7, In2.Cu/0.5: 16.1, In2.Cu/1.0: 0.0, In2.Cu/1.5: 9.6 |
| /BAT_PLUS | cur | 35 | 6 | B.Cu/0.3: 0.2, B.Cu/0.5: 16.6, B.Cu/1.0: 52.9, B.Cu/1.5: 10.0, F.Cu/0.3: 1.5, F.Cu/0.5: 17.6, F.Cu/1.0: 2.5, F.Cu/1.5: 11.4, In1.Cu/0.5: 10.7, In1.Cu/1.5: 21.7, In2.Cu/1.0: 0.0, In2.Cu/1.5: 9.6 |
| /SW_BAT | pre | 6 | 0 | F.Cu/0.75: 3.1, F.Cu/1.0: 12.0 |
| /SW_BAT | cur | 6 | 0 | F.Cu/0.75: 3.1, F.Cu/1.0: 12.0 |
| /VEH5V | pre | 46 | 4 | B.Cu/0.5: 32.9, B.Cu/1.0: 111.0, F.Cu/0.25: 5.9, F.Cu/0.5: 7.6, F.Cu/1.0: 36.3 |
| /VEH5V | cur | 46 | 4 | B.Cu/0.5: 27.6, B.Cu/1.0: 122.8, F.Cu/0.25: 5.9, F.Cu/0.5: 8.0, F.Cu/1.0: 48.9 |
| /MAIN5V | pre | 39 | 2 | B.Cu/1.0: 95.3, F.Cu/0.25: 1.6, F.Cu/0.3: 1.6, F.Cu/1.0: 15.8, F.Cu/1.5: 25.7, In1.Cu/1.0: 15.1 |
| /MAIN5V | cur | 40 | 2 | B.Cu/1.0: 102.5, F.Cu/0.25: 1.6, F.Cu/0.3: 1.6, F.Cu/1.0: 25.8, F.Cu/1.5: 25.7, In1.Cu/1.0: 15.1 |
| /SYS5V | pre | 72 | 5 | B.Cu/0.75: 9.4, B.Cu/1.0: 4.6, F.Cu/0.5: 37.8, F.Cu/0.75: 79.7, F.Cu/1.0: 44.8, F.Cu/1.5: 28.4, In2.Cu/0.5: 9.1, In2.Cu/1.5: 20.2 |
| /SYS5V | cur | 69 | 5 | B.Cu/0.75: 9.4, B.Cu/1.0: 4.6, F.Cu/0.5: 37.8, F.Cu/0.75: 79.7, F.Cu/1.0: 43.8, F.Cu/1.5: 28.1, In2.Cu/0.5: 9.1, In2.Cu/1.5: 20.2 |
| /24V | pre | 34 | 5 | B.Cu/1.0: 13.9, F.Cu/0.5: 2.3, F.Cu/1.0: 47.6, In2.Cu/0.5: 5.3, In2.Cu/1.0: 47.2 |
| /24V | cur | 30 | 5 | B.Cu/1.0: 13.9, F.Cu/0.5: 2.3, F.Cu/1.0: 44.0, In2.Cu/0.5: 5.3, In2.Cu/1.0: 47.2 |
| /24V_IN | pre | 11 | 1 | B.Cu/1.0: 34.2, F.Cu/1.0: 15.3 |
| /24V_IN | cur | 11 | 1 | B.Cu/1.0: 34.2, F.Cu/1.0: 15.3 |
| /SW_IN | pre | 14 | 2 | F.Cu/1.0: 3.9, In2.Cu/1.0: 75.0 |
| /SW_IN | cur | 13 | 2 | F.Cu/1.0: 3.2, In2.Cu/1.0: 86.0 |
| /SW_5V | pre | 13 | 0 | F.Cu/1.0: 229.0 |
| /SW_5V | cur | 13 | 0 | F.Cu/1.0: 229.0 |
| /3V3_MODEM | pre | 21 | 0 | F.Cu/0.5: 93.7 |
| /3V3_MODEM | cur | 21 | 0 | F.Cu/0.5: 93.7 |
| /SW3_NODE | pre | 10 | 2 | F.Cu/0.5: 17.6, F.Cu/1.0: 0.5, In1.Cu/0.5: 12.8 |
| /SW3_NODE | cur | 10 | 2 | F.Cu/0.5: 17.6, F.Cu/1.0: 0.5, In1.Cu/0.5: 12.8 |
| /5V_FAN | pre | 11 | 0 | F.Cu/0.5: 5.7, F.Cu/1.0: 43.8 |
| /5V_FAN | cur | 12 | 0 | F.Cu/1.0: 65.2 |
| /VIN_SW | pre | 5 | 0 | F.Cu/0.25: 6.1, F.Cu/1.0: 8.5 |
| /VIN_SW | cur | 5 | 0 | F.Cu/0.25: 6.1, F.Cu/1.0: 8.5 |

| Net | Path | Board | Series min width (layer) | IPC-2221 I @ΔT=10 °C (A) | Series length by layer/width (mm) | Series vias (drill) |
|---|---|---|---|---|---|---|
| /BAT_PLUS | P4.1→L6.2 | pre | 1.5 mm (In2.Cu, 9.57 mm) | 0.97 | B.Cu/1.5: 63.8, F.Cu/1.0: 2.5, In2.Cu/1.5: 9.6 | 2: 0.3, 0.3 |
| /BAT_PLUS | P4.1→L6.2 | cur | 0.5 mm (In1.Cu, 10.69 mm) | 0.44 | B.Cu/1.0: 52.9, F.Cu/1.0: 2.5, In1.Cu/0.5: 10.7, In2.Cu/1.5: 9.6 | 3: 0.3, 0.3, 0.3 |
| /BAT_PLUS | P4.1→U6.23 | pre | 1.5 mm (In1.Cu, 21.69 mm) | 0.97 | B.Cu/1.5: 72.3, F.Cu/0.3: 1.5, F.Cu/1.5: 11.4, In1.Cu/1.5: 21.7, In2.Cu/1.5: 9.6 | 4: 0.3, 0.4, 0.3, 0.3 |
| /BAT_PLUS | P4.1→U6.23 | cur | 0.5 mm (In1.Cu, 10.69 mm) | 0.44 | B.Cu/1.0: 52.9, B.Cu/1.5: 8.6, F.Cu/0.3: 1.5, F.Cu/1.5: 11.4, In1.Cu/0.5: 10.7, In1.Cu/1.5: 21.7, In2.Cu/1.5: 9.6 | 5: 0.3, 0.3, 0.4, 0.3, 0.3 |
| /SW_BAT | L6.1→U6.21 | pre | 0.75 mm (F.Cu, 2.35 mm) | 1.94 | F.Cu/0.75: 2.3, F.Cu/1.0: 11.1 | 0:  |
| /SW_BAT | L6.1→U6.21 | cur | 0.75 mm (F.Cu, 2.35 mm) | 1.94 | F.Cu/0.75: 2.3, F.Cu/1.0: 11.1 | 0:  |
| /VEH5V | P2.1→U6.6 | pre | 0.25 mm (F.Cu, 3.94 mm) | 0.88 | B.Cu/1.0: 111.0, F.Cu/0.25: 3.9 | 1: 0.3 |
| /VEH5V | P2.1→U6.6 | cur | 0.25 mm (F.Cu, 3.94 mm) | 0.88 | B.Cu/1.0: 122.8, F.Cu/0.25: 3.9 | 1: 0.3 |
| /VEH5V | P2.1→JP1.2 | pre | 0.5 mm (F.Cu, 1.88 mm) | 1.45 | B.Cu/0.5: 27.2, F.Cu/0.5: 1.9 | 1: 0.4 |
| /VEH5V | P2.1→JP1.2 | cur | 0.5 mm (F.Cu, 2.25 mm) | 1.45 | B.Cu/0.5: 22.9, F.Cu/0.5: 2.3 | 1: 0.3 |
| /MAIN5V | U6.1→P11.1 | pre | 1.0 mm (In1.Cu, 15.09 mm) | 0.72 | B.Cu/1.0: 93.8, F.Cu/0.3: 1.0, In1.Cu/1.0: 15.1 | 2: 0.3, 0.3 |
| /MAIN5V | U6.1→P11.1 | cur | 1.0 mm (In1.Cu, 15.09 mm) | 0.72 | B.Cu/1.0: 102.5, F.Cu/0.3: 1.0, In1.Cu/1.0: 15.1 | 2: 0.3, 0.3 |
| /MAIN5V | U6.1→JP6.1 | pre | 1.0 mm (In1.Cu, 15.09 mm) | 0.72 | B.Cu/1.0: 93.8, F.Cu/0.3: 1.0, F.Cu/1.0: 5.9, In1.Cu/1.0: 15.1 | 2: 0.3, 0.3 |
| /MAIN5V | U6.1→JP6.1 | cur | 1.0 mm (In1.Cu, 15.09 mm) | 0.72 | B.Cu/1.0: 102.5, F.Cu/0.3: 1.0, F.Cu/1.0: 15.9, In1.Cu/1.0: 15.1 | 2: 0.3, 0.3 |
| /MAIN5V | U6.1→Q7.5 | pre | 1.0 mm (In1.Cu, 15.09 mm) | 0.72 | F.Cu/0.3: 1.0, F.Cu/1.0: 3.7, F.Cu/1.5: 5.2, In1.Cu/1.0: 15.1 | 2: 0.3, 0.3 |
| /MAIN5V | U6.1→Q7.5 | cur | 1.0 mm (In1.Cu, 15.09 mm) | 0.72 | F.Cu/0.3: 1.0, F.Cu/1.0: 3.7, F.Cu/1.5: 5.2, In1.Cu/1.0: 15.1 | 2: 0.3, 0.3 |
| /SYS5V | P11.2→U7.2 | pre | 0.5 mm (In2.Cu, 9.11 mm) | 0.44 | B.Cu/1.0: 4.1, F.Cu/0.5: 31.0, F.Cu/0.75: 30.9, F.Cu/1.0: 27.9, In2.Cu/0.5: 9.1 | 2: 0.3, 0.3 |
| /SYS5V | P11.2→U7.2 | cur | 0.5 mm (In2.Cu, 9.11 mm) | 0.44 | B.Cu/1.0: 4.1, F.Cu/0.5: 31.0, F.Cu/0.75: 30.9, F.Cu/1.0: 32.2, In2.Cu/0.5: 9.1 | 2: 0.3, 0.3 |
| /SYS5V | P11.2→F1.1 | pre | 1.0 mm (F.Cu, 12.35 mm) | 2.39 | F.Cu/1.0: 12.4 | 0:  |
| /SYS5V | P11.2→F1.1 | cur | 1.0 mm (F.Cu, 11.66 mm) | 2.39 | F.Cu/1.0: 11.7 | 0:  |
| /SYS5V | P11.2→U12.2 | pre | 0.5 mm (In2.Cu, 9.11 mm) | 0.44 | B.Cu/0.75: 9.4, B.Cu/1.0: 4.1, F.Cu/0.75: 36.7, F.Cu/1.0: 27.9, In2.Cu/0.5: 9.1 | 4: 0.3, 0.3, 0.3, 0.3 |
| /SYS5V | P11.2→U12.2 | cur | 0.5 mm (In2.Cu, 9.11 mm) | 0.44 | B.Cu/0.75: 9.4, B.Cu/1.0: 4.1, F.Cu/0.75: 36.7, F.Cu/1.0: 32.2, In2.Cu/0.5: 9.1 | 4: 0.3, 0.3, 0.3, 0.3 |
| /SYS5V | JP6.2→U7.2 | pre | 0.5 mm (In2.Cu, 9.11 mm) | 0.44 | B.Cu/1.0: 4.1, F.Cu/0.5: 31.0, F.Cu/0.75: 30.9, F.Cu/1.0: 32.8, In2.Cu/0.5: 9.1 | 2: 0.3, 0.3 |
| /SYS5V | JP6.2→U7.2 | cur | 0.5 mm (In2.Cu, 9.11 mm) | 0.44 | B.Cu/1.0: 4.1, F.Cu/0.5: 31.0, F.Cu/0.75: 30.9, F.Cu/1.0: 17.8, In2.Cu/0.5: 9.1 | 2: 0.3, 0.3 |
| /24V | Q10.3→U2.7 | pre | 1.0 mm (In2.Cu, 47.2 mm) | 0.72 | B.Cu/1.0: 13.9, F.Cu/1.0: 9.4, In2.Cu/1.0: 47.2 | 3: 0.3, 0.3, 0.3 |
| /24V | Q10.3→U2.7 | cur | 1.0 mm (In2.Cu, 47.2 mm) | 0.72 | B.Cu/1.0: 13.9, F.Cu/1.0: 9.4, In2.Cu/1.0: 47.2 | 3: 0.3, 0.3, 0.3 |
| /24V_IN | P1.1→Q10.2 | pre | 1.0 mm (B.Cu, 33.33 mm) | 2.39 | B.Cu/1.0: 33.3 | 1: 0.4 |
| /24V_IN | P1.1→Q10.2 | cur | 1.0 mm (B.Cu, 33.33 mm) | 2.39 | B.Cu/1.0: 33.3 | 1: 0.4 |
| /SW_IN | F1.2→Q1.2 | pre | 1.0 mm (In2.Cu, 74.6 mm) | 0.72 | F.Cu/1.0: 1.3, In2.Cu/1.0: 74.6 | 2: 0.4, 0.3 |
| /SW_IN | F1.2→Q1.2 | cur | 1.0 mm (In2.Cu, 85.31 mm) | 0.72 | F.Cu/1.0: 1.7, In2.Cu/1.0: 85.3 | 2: 0.4, 0.3 |
| /SW_5V | Q1.3→MOD1.5 | pre | 1.0 mm (F.Cu, 178.55 mm) | 2.39 | F.Cu/1.0: 178.5 | 0:  |
| /SW_5V | Q1.3→MOD1.5 | cur | 1.0 mm (F.Cu, 178.55 mm) | 2.39 | F.Cu/1.0: 178.5 | 0:  |
| /3V3_MODEM | L7.2→J7.1 | pre | 0.5 mm (F.Cu, 54.15 mm) | 1.45 | F.Cu/0.5: 54.1 | 0:  |
| /3V3_MODEM | L7.2→J7.1 | cur | 0.5 mm (F.Cu, 54.15 mm) | 1.45 | F.Cu/0.5: 54.1 | 0:  |
| /SW3_NODE | U7.8→L7.1 | pre | 0.5 mm (In1.Cu, 12.85 mm) | 0.44 | F.Cu/0.5: 4.4, In1.Cu/0.5: 12.8 | 2: 0.3, 0.3 |
| /SW3_NODE | U7.8→L7.1 | cur | 0.5 mm (In1.Cu, 12.85 mm) | 0.44 | F.Cu/0.5: 4.4, In1.Cu/0.5: 12.8 | 2: 0.3, 0.3 |
| /5V_FAN | JP1.1→P6.1 | pre | 0.5 mm (F.Cu, 5.69 mm) | 1.45 | F.Cu/0.5: 5.7 | 0:  |
| /5V_FAN | JP1.1→P6.1 | cur | 1.0 mm (F.Cu, 4.09 mm) | 2.39 | F.Cu/1.0: 4.1 | 0:  |
| /VIN_SW | Q7.1→U6.7 | pre | 1.0 mm (F.Cu, 8.47 mm) | 2.39 | F.Cu/1.0: 8.5 | 0:  |
| /VIN_SW | Q7.1→U6.7 | cur | 1.0 mm (F.Cu, 8.47 mm) | 2.39 | F.Cu/1.0: 8.5 | 0:  |

Reading the series table: "series" elements are those whose removal disconnects the two pads (no parallel copper exists); the worst element is the one with the lowest IPC-2221 capacity. Branches to sense dividers (R5 on BAT_PLUS, R51/R55/R7 on VEH5V, U6.6 VIN pin neck 0.25 mm, U6.16 OVSNS) are 0.25–0.5 mm and are fine; they are listed only where a pair was explicitly requested.

### 4.6 Inner-layer signal routing (non-plane nets)

| Layer | Board | Nets | Segments | Total length | Largest |
|---|---|---|---|---|---|
| In1.Cu (GND plane) | pre | 27 | 143 | 917 mm | /IGN_IN 116, /MODEM_LED_MCU 89, /RTCM_TAP 74, /MODEM_RST_MCU 69, /BATLED4 61 |
| In1.Cu (GND plane) | cur | 28 | 157 | 985 mm | + /I2C_SDA 76 (was 46), /I2C_SCL 66 (was 37), /ACC_INT1 30 (new), /BAT_PLUS 32 (was 22) |
| In2.Cu (3V3 plane) | pre | 28 | 198 | 1293 mm | /SER_TXB 150, /SER_RXB 133, /NTC 99, /CHRG_FAULT 94, /CHRG_STAT 89, /SW_IN 75 |
| In2.Cu (3V3 plane) | cur | 28 | 199 | 1258 mm | /SW_IN 86 (+11), /NTC 80 (−19), /BAT_PLUS 9.6 (−16, R5 branch moved) |
| In1 non-GND copper inside U16 13×13 mm courtyard | pre / cur | | | 45.4 / 56.0 mm | cur adds /ACC_INT1 10.1 mm, /I2C_SDA 0.5 mm; /NTC_CELL 10.2 mm sits just above the courtyard (y 52.2–56.0) on In1 in both |

### 4.7 BOM / LCSC gaps (netlist fields; 238 active parts, 224 with `LCSC`)

| Ref | Value | Footprint | Issue |
|---|---|---|---|
| JP1, JP2, JP3, JP4, JP5, JP6 | solder jumpers | Jumper:SolderJumper-* / Drogheda:SolderJumper-3 | no LCSC, not excluded from BOM |
| TP1–TP7 | test points | TestPoint:TestPoint_Pad_D1.5mm | no LCSC, not excluded from BOM |
| MOD1 | simpleRTK2B-Pro on UNO headers | Module:Arduino_UNO_R3 (B.Cu, TH, net-connected pads) | no LCSC, not excluded from BOM/POS |
| C? (10 nF 0603) | 10nF | C_0603 | two codes in use: C57112, C1589 |
| U26 | SC7A20TR | LGA-12 2×2 | C5126709 Extended; LCSC page showed out of stock at review time |
| Dbk2, R109 | SS34, 10k | — | DNP (correct) |
| C86817 (22uF vs 22uF/16V), C25803 (100k vs 100k/1%), C17700171 (10uH vs 10uH/2A), C158012 (5× JST XH 2p), C2925557, C7095263, C5160226, C83205 | | | same code, cosmetic value-string differences only |

### 4.8 Title blocks / silkscreen

| Item | Value |
|---|---|
| PCB title block (pre and cur) | title "EINARBoard HBOX", date 2026-08-12, rev 3.0, company "Helgen Servicios Especializados", comment "Last Review: Dr. Leopoldo Rodriguez Salazar" |
| Schematic title block | title "EINARBoard HBox", date 2026-07-07, rev 3.0 (A1 sheet, KiCad 10.0 format 20260306) |
| PCB silkscreen | "EINARBoard 5.6" at (115.7,134.5); "HBOX v5.6 - 2026-10" at (112.8,136.6); "www.helgen.tech" at (112.8,138.3) — identical pre/cur |
| Schematic revision notes | texts "V5.6 ECO (2026-09-28)…", "V5.6 add (2026-10-08): U26 SC7A20TR … INT1 -> PB9 EXTI9. C126/C127 100nF at VDD/VDDIO, C128 10 µF" present |

### 4.9 U6 (LTC4040) DFM snapshot (identical pre/cur)

EP pad 25: 2.65 × 3.65 mm, layers F.Cu + F.Mask only (no paste), net GND. Paste: 6 unnumbered F.Paste-only pads 0.95 × 0.85 mm at x = 155.79 / 157.11, y = 111.90 / 113.12 / 114.34 → 4.84 mm² = 50.1 % of EP. Vias in EP: 3 × 0.6/0.3 GND at (155.74,111.92), (156.45,112.50), (157.13,111.88); the first and third are centred in paste windows (S5). No other thermal vias within 4 mm of U6. 24 signal pads 0.85 × 0.25 mm with F.Paste. No footprint- or pad-level paste margin overrides.