Helgen-Services/Drogheda
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
52c530d201
Drogheda/03-Architecture-Hardware/2026-09-28_Drogheda_EinarBoard-v6_Ports-and-No-Respin_v1.0.md

43 KiB
Raw Blame History

title tags project author date version status audience
EinarBoard v6 — Puertos y sin nueva versión (pasada 2, inglés)
project-drogheda
hardware
hbox
v6
esquematico
ports
Project Drogheda Helgen Technologies 2026-09-28 1.0 FINAL — pass 2 of 3 (ports / no new version) Michelle (layout), Leo, ingenieros

EinarBoard v6: ports end to end and the no-v6.1 close-out (v1.0)

!!! warning "Designators from before 22-Oct (T43)" This document keeps the designators the board had on its date. Since 22-Oct (T43) the V5.6, V5.7 and v6 carry new ones, and several old names now belong to another part: on the v6, U6 is now the A7670SA modem (was U19) and the LTC4040 is U17 (was U6). To read it against today's board, use the old → new table (in Spanish); parts already gone by 22-Oct are not in it.

!!! warning "EinarBoard v6 (hbox-watchdog-v6): en diseño, no se pide" Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. No es la V5.6 que se manda a fabricar esta semana (hbox-watchdog-v5, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios.

!!! info "Pass 2 of 3 — ports and no new version" Spanish summary, final state per block and the combined layout delta: EinarBoard v6 — Cambios de esquemático: resumen de las 3 pasadas. The final independent check (pass 3) passed this pass 26 / 27. The one FAIL was the IND-SMD_MWSA0804S land in §4.3 and in L-53: the correct land is pads 2.75 × 5.5 mm at ±3.375 mm (gap 4.0 mm), courtyard 10.0 × 9.0 mm (L-63). The schematic hash f73f41a8…27ee below was superseded by 2b394ef9…5f33 (C176 added).

Date: 2026-09-28 · Board: kicad/hbox-watchdog-v6.* (HBOX RTK, Helgen Technologies) · Input state: the schematic after the apply pass (sha256 d54e330d…, netlist apply/netlists/05-final.xml; a fresh export was identical) · Author: Claude (ports and no-respin pass) · Rules: edited in place, span-scoped S-expression splices with a UUID guard, .kicad_pcb not touched, no git, backups in kicad/_to_delete/v6-ports-20260928/.

Resumen (ES)

Se revisó cada puerto de la v6 corregida, de extremo a extremo (conector → protección → pasivos → transceptor/PHY → pin de MCU o módem → periférico de firmware), contra hojas de datos. Todos los puertos funcionan como están dibujados después de este pase. Se encontraron y corrigieron en el esquemático seis defectos que habrían dejado un puerto débil o fallando:

  1. RS-485: el SP3485 sólo tiene ±2 kV HBM y fail-safe con entradas abiertas; además, con DE/RE̅ atados a RTS̅ del SC16IS752 (que queda en ALTO tras el reset), el transceptor transmitía y bloqueaba el bus durante el reset, en DFU o sin firmware. Se cambió U14 por THVD1410DR (mismo pinout, ±18 kV IEC, fail-safe con bus abierto, en corto o inactivo). Se añadió U32 (inversor 74LVC1G04), así que el transceptor arranca en recepción. También se añadió D39 SM712 en P11 y la opción de polarización R145/R146 (DNP).
  2. RS-232: el MAX3232 (sin especificación ESD) pasa a TRS3232EIDR (mismo pinout, ±8 kV IEC contacto).
  3. Header TTL H4: estaba en paralelo directo con la salida R1OUT del transceptor. Se añadió R147 1 k, así que un dispositivo TTL puede manejar RXB sin contienda.
  4. Ethernet J10: el LED amarillo (ACT) estaba invertido (pines 11/12), así que nunca encendía. El pin 8 (retorno del capacitor Bob-Smith de 1000 pF) estaba sin conectar; ahora va a GND.
  5. SC16IS752: las entradas CTSA̅/CTSB̅ estaban flotando; ahora van a GND.
  6. Módem USB (J9): se añadió TP12 (1V8) junto a TP8, para forzar el modo de descarga USB.

USB-C (J9 y J11) ya estaba correcto: CC1/CC2 tenían 5.1 kΩ a GND, D+/D− iban en ambas filas y VBUS no retro-alimenta. No hubo cambios.

Mapa I²C: sin colisiones. En el bus: SC7A20 0x18, PCF8574 0x20, SHT40 0x44, TMP102 0x48 y 0x49, SC16IS752 0x4D. Las direcciones posibles de los TMP102 (0x48–0x4B) no incluyen 0x4D.

Cierre de «no v6.1»: H-03 hecho (nueva huella IND-SMD_MWSA0804S con la tierra recomendada por Sunlord, usada en L2/L6/L8/L20) y B-13 hecho (K1 DNP; enlace directo PC6 → DIN_4G con R148 0 Ω). TP1–TP8 salen del BOM y del CPL. Se añaden 14 puntos a la lista de Michelle (L-49…L-62) y se aceptan 20 ítems permanentemente, cada uno con su razón. El único riesgo aceptado a conciencia en la ruta de potencia es A-10: no hay protección de sobretensión en VEH5V. La opción OVP del LTC4040 mueve el divisor PFI y cambia la recuperación del modo respaldo, y no puede validarse sin banco. Cada grupo se probó con diff de netlist: lo esperado coincide exactamente con lo obtenido. ERC: 0 errores (134 warnings, igual que antes). SHA-256 final del esquemático: f73f41a8…27ee.

0. Summary

Item Result
Ports traced 24 (every J/P/H/SW/TP ref plus the internal modem, GNSS and I²C interfaces)
Port verdicts 17 ✅ as drawn · 7 🔧 fixed now (RS-485, RS-232, H4, SC16IS752 CTS, Ethernet LEDs + Bob-Smith, modem USB boot pad, modem UART B-13) · 📐 layout items on 11 ports · ⚙ firmware items on 14 ports
USB-C CC J9 and J11 both correct: Rcc1/Rcc2 and R100/R101 = 5.1 kΩ 1 % (C23186) CC→GND; D+ A6/B6 and D− A7/B7 tied; no VBUS back-feed
I²C collisions None (map in §3)
Schematic groups P1 ports · N1 no-respin · C1 cleanup: 8 parts added, 0 removed, 41 field changes, 8 pin-net changes, 0 net-class changes. Each group: expected == actual; composed = total, 0 differences
ERC (kicad-cli 10 via KiCad MCP) 0 errors after every group; warnings 134 → 134
Overlaps / wire crossings 30 → 30 / 9 → 9 (all pre-existing; none involve a new part)
BOM all 298 fitted real parts have an LCSC number (TP1–TP12 and JP1–JP6 are now out of the BOM/CPL; the PF* power flags are virtual)
New library file Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod (sha256 dbf53557…)
Untouched .kicad_pcb 6ddec80d…, .kicad_pro d577aa43…, .kicad_dru 31ce0f4f…
Michelle's list +14: L-49 … L-62 (§5)
Accepted permanently 20 items (§7); done now: 17 (§8)

1. Port-by-port verification

Legend: ✅ works as drawn · 🔧 fixed now (schematic) · 📐 layout item added (L-nn) · ⚙ firmware item (§6). Datasheets used: TI THVD1410, TI SN65HVD72, MaxLinear SP3485, ADI/Maxim MAX3222-MAX3241, TI TRS3232E, NXP SC16IS752/762, WIZnet W5500 v1.1.0, the KiCad Connector:RJ45_Hanrun_HR911105A_Horizontal symbol (drawn from the Hanrun HR911105A sheet; see §1.6), Semtech/Littelfuse SM712, ADI LTC4040 Rev B, Sunlord MWSA-S series spec, and AOS AO4264E. Pin and net evidence comes from ports/netlists/final.xml (= 03-cleanup.xml).

# Port Chain (final) Checks Verdict Evidence
1 RS-485 (P11) P11.1 /RS485_A, P11.2 /RS485_B, P11.3 GND → D39 SM712 (A/B → GND) · R82 120 Ω + JP5 (open) termination · R145/R146 390 Ω bias (DNP) → U14 THVD1410DR (6 A, 7 B, 8 VCC /3V3 + C84, 5 GND) → 1 RO /SER_RXA → U10.4 RXA · 4 DI ← /SER_TXA U10.3 TXA · 2 RE̅ + 3 DE ← /RS485_DE ← U32 74LVC1G04 ← /SER_DEA ← U10.1 RTSA̅ A/B polarity: P11.1 = A = U14.6 ✅ · Pinout of THVD1410 D pkg = SP3485 (R, RE̅, DE, D, GND, A, B, VCC) ✅ · RTSA̅ is HIGH after reset (NXP DS). With the old direct tie, DE = 1 during reset, DFU and unflashed boards, so the node drove the bus (bus hog). U32 inverts it: receive at reset; auto-RS-485 with EFCR RTSCON=1, RTSINVER=0 ✅ · Fail-safe: SP3485 = open inputs only; THVD1410 = open, short and idle bus ✅ · ESD: SP3485 ±2 kV HBM only → THVD1410 ±18 kV IEC contact, ±30 kV HBM, EFT ±4 kV; surge by SM712 (−7/+12 V, 400 W 8/20 µs); THVD1410 bus abs max ±18 V ✅ · Termination by solder jumper (bus ends only) ✅ · 3.3 V supply, logic 3.3 V ✅ · Speed: THVD1410 500 kbps > SC16IS752 max 230.4 kBd at 3.6864 MHz ✅ 🔧 📐 L-49/L-50/L-59 · ⚙ 01-ports.xml: /RS485_DE = {U14.2, U14.3, U32.4}; /SER_DEA = {U10.1, U32.2}; /RS485_A = {P11.1, U14.6, R82.1, D39.1, R145.2}
2 RS-232 (P12) P12.1 /RS232_TX ← U15.14 T1OUT · P12.2 /RS232_RX → U15.13 R1IN · P12.3 GND · U15 TRS3232EIDR: C85 C1± (1/3), C86 C2± (4/5), C87 V+ (2)→GND, C88 V− (6)→GND, all 100 nF; C89 100 nF VCC (16) /3V3; T1IN (11) ← /SER_TXB U10.23 TXB; R1OUT (12) → /RS232_R1OUT → R147 1 k → /SER_RXB U10.24 RXB; T2IN/R2IN → GND, T2OUT/R2OUT NC Pinout identical to MAX3232 (1 C1+ … 16 VCC) ✅ · Pump caps 0.1 µF at 3.0–3.6 V per both datasheets ✅ · V+ cap to GND allowed ✅ · Unused TX input tied, RX input tied (5 kΩ internal) ✅ · Channel B of U10 ✅ · Direction: board TX on pin 1 (DTE-style, cross to the far end's RX) ✅ · ESD: MAX3232 (non-E) has no ESD rating → TRS3232E ±15 kV HBM, ±8 kV IEC contact, ±15 kV air ✅ 🔧 📐 L-51/L-59 · ⚙ /RS232_R1OUT = {U15.12, R147.1}
3 TTL UART B (H4) H4.1 3V3, H4.2 /SER_TXB (U10.23 + U15.11), H4.3 /SER_RXB (U10.24 + R147.2), H4.4 GND Before: H4.3 was hard-wired to U15 R1OUT, so an external TTL TX fought a CMOS output (R1OUT idles HIGH when R1IN is open). With R147: an external driver wins (≤ 3.3 mA, VIL ≈ 0.16 V with a 50 Ω driver); normal RS-232 RX delay 1 k × ~10 pF ≈ 10 ns ✅ · Use H4 or P12, not both at once 🔧 · ⚙ /SER_RXB = {U10.24, H4.3, R147.2}
4 SC16IS752 bridge (U10) I2C/SPI̅ (9) = /3V3 → I²C mode · A0 (10), A1 (11) = GND → 0x9A = 7-bit 0x4D · Y2 3.6864 MHz (C2238) + C82/C83 22 pF on XTAL1/2 (6/7) · IRQ̅ (15) open-drain → R81 10 k → /3V3, → U16.61 PB8 · RESET̅ (5) → R80 10 k → /3V3 (POR inside; no MCU control) · VDD (8) /3V3 + C81 · ch A = RS-485, ch B = RS-232/H4 · CTSA̅ (2), CTSB̅ (16) → GND (were floating) · GPIO0–7 NC Address table verified (A1=VSS, A0=VSS → 0x9A) ✅ · Crystal: divisors exact for 9600…230400 ✅ · IRQ̅ is open-drain and needs the pull-up; NXP quotes 1 k for fast edges, but 10 k only slows the de-assert edge (≈ 0.2 µs), which is fine for a level-read EXTI ✅ · POR exists, so R80 is enough; firmware issues IOControl.SRESET after every MCU reset ✅ · I²C max 400 kHz (the bus runs at 100 kHz, see #5) ✅ · Floating CTS inputs removed; GPIOs set to outputs in firmware ✅ 🔧 (CTS) · 📐 L-57 · ⚙ 03-cleanup.xml: U10.2, U10.16 → GND
5 I²C1 bus PB6 SCL (U16.58) / PB7 SDA (U16.59), AF4; R30/R31 4.7 k to /3V3; U3, U10, U13, U26, U29, U31 Map in §3: no collision ✅ · PCF8574T (C7605) is a 100 kHz device, so the whole bus runs at 100 kHz · tr ≈ 0.85 × 4.7 k × ~80 pF ≈ 0.32 µs < 1 µs ✅ · sink 0.7 mA < 3 mA ✅ · ZED-F9P DDC (0x42) not wired (U18.44/45 NC), A7670 CI2C NC ✅ ✅ · ⚙ nets /I2C_SCL, /I2C_SDA
6 Ethernet (J10 + U11) U11 TXP/TXN (2/1) → J10.1 TD+ / J10.2 TD−, each 49.9 Ω (R92/R93) to /3V3_ETH, J10.4 TCT = /3V3_ETH · RXP/RXN (6/5) → J10.3 RD+ / J10.6 RD−, R94/R95 49.9 Ω to /ETH_RCT = J10.5 RCT + C97 6.8 nF → GND · J10.9 green A ← R96 330 Ω ← /3V3_ETH, J10.10 green K → U11.25 LINKLED · J10.12 yellow A ← R97 330 Ω, J10.11 yellow K → U11.27 ACTLED · J10.8 → GND · J10.7 NC · SH → GND · Y1 25 MHz HC-49 + C95/C96 33 pF · EXRES1 12.4 k 1 % · TOCAP 4.7 µF · 1V2O 10 nF · AVDD 100 nF ×6 + 10 µF/22 µF/100 µF · PMODE[2:0] = 111 via R84 (auto-neg) · RSVD23 → GND, RSVD38–42 NC · SPI2: CS̅ PB12, SCK PB13, MISO PB14, MOSI PB15 (AF5) · INT̅ PC0 · RST̅ PA15 + R140 4.7 k PD · 3V3_ETH from U12 MP1584EN, EN = /ETH_PWR_EN PD2 + R139 100 k PD Terminations and centre taps = W5500 reference topology ✅ · LED polarity: the HR911105A symbol draws the yellow LED anode on pin 12 and cathode on pin 11; v6 had 11 = anode supply and 12 = W5500 ACTLED, so ACT never lit → swapped 🔧 · Pin 8 is the Bob-Smith 1000 pF return (symbol pin type power_in); it was NC with a flag, so the unused-pair termination floated (EMI/ESD) → GND 🔧 · Y1 load ≈ 19–20 pF for the CL 20 pF part ✅ · W5500 pin table: TOCAP 4.7 µF, 1V2O 10 nF, EXRES1 12.4 k, RSVD23 → GND, 38–42 NC ✅ · RSTn internal pull-up 62–112 k + PA15 JTDI pull-up vs 4.7 k → ≤ 0.66 V < VIL 0.8 V ✅ · MP1584 EN: 1 µA internal pull-up, 100 k → 0.1 V = off; PD2 3.3 V > 1.5 V = on ✅ · W5500 I/O 5 V-tolerant (no back-power through SPI/RST when 3V3_ETH is off) ✅ · J10 footprint Connector_RJ:RJ45_Hanrun_HR911105A_Horizontal = part C12074 ✅ 🔧 📐 L-52 · ⚙ 01-ports.xml: J10.8 GND; /ETH_ACTLED = {J10.11, U11.27}; /ETH_ACT_A = {J10.12, R97.1}
7 USB-C DFU (J11) GCT USB4085-GF-A (C7095263, USB 2.0 Type-C) · CC1 A5 → R100 5.1 k → GND, CC2 B5 → R101 5.1 k → GND · D+ A6+B6 /DFU_DP → D14 → U16.45 PA12 · D− A7+B7 /DFU_DM → D15 → U16.44 PA11 · VBUS A4/A9/B4/B9 /DFU_VBUS → D16 · → D13 SS34 → /LDO_IN (U17), OR-ed with D12 from SYS5V · SH → GND · BOOT0 = SW2 to 3V3 + R98 10 k PD; PB2 = R99 10 k PD; HSE Y3 25 MHz Sink Rd on both CC ✅ · flip support ✅ · PA11/PA12 = OTG_FS DM/DP ✅ · VBUS back-feed: D12 blocks VBUS → SYS5V, D13 blocks the board → host; USB powers only the 3V3 domain ✅ · VBUS sensing is not needed (PA9 is TP9): ROM DFU on F411 runs without it; firmware disables it ✅ · PA10 idles high in DFU via Rdfu1 100 k (so the ROM USART1 detector sees no noise) ✅ · ESD D14–D16 PESD5V0S1BA (full speed tolerates their capacitance; V5.5 proven; routing fixed by L-42) ✅ ✅ · 📐 L-42 (existing), L-58/L-59 · ⚙ nets /DFU_*
8 USB-C modem (J9) USB4085 · CC1 A5 → Rcc1 5.1 k, CC2 B5 → Rcc2 5.1 k → GND · D+ A6+B6 /USB_DP → U30.3/4 → U19.27 · D− A7+B7 /USB_DM → U30.1/6 → U19.28 · VBUS → U30.5 + U19.24 (detect only; feeds no rail) · SH → GND · U19.6 USB_BOOT → TP8, TP12 = /1V8_MODEM beside it Rd on both CC ✅ · both D rows tied ✅ · USBLC6-2SC6 (~3.5 pF) suits high speed ✅ · no back-feed path (VBUS only reaches the modem detect pin and the USBLC6 rail pin) ✅ · J9 works only while firmware keeps the modem powered ⚙ · forced download needs VDD_EXT on USB_BOOT at power-on: there was no 1.8 V pad beside TP8 → TP12 🔧 ✅ 🔧 (TP12) · 📐 L-41/L-43 (existing), L-55/L-58/L-59 · ⚙ /1V8_MODEM gains TP12
9 P1 24 V + ignition DIBO DB128V-5.0-5P (C424683, 5.0 mm, 16 A) on TerminalBlock_Phoenix_MKDS-1,5-5…Horizontal · 1 /24V_IN → F2 3 A → /VIN_FUSED (D10, Q23) · 2 GND · 3 /IGN_IN → D35 SMBJ33A + Rig1 22 k → /IGN_SENSE (PA5 ADC, ratio 0.0833) · 4 GND · 5 NC Apply-pass fixes V1-01/A-01/F-02 in place ✅ · pin numbering 1–5 = land 1–5 ✅ · 5.0 mm land fits a KF128-class block; confirm hole/pin and wire-entry side (L-62) ✅ · 📐 L-62 /IGN_IN = {P1.3, Rig1.1, D35.1}
10 P2 bench 5 V XH-2 (C158012) · 1 /VEH5V, 2 GND Bench-only input; no reverse or over-voltage protection (A-10 and A-20c accepted, §7; silk per L-46) ✅ (bench use) —
11 P3 battery XH-3 (C144394) · 1 /BAT_PLUS (L6, U6.23), 2 GND, 3 /NTC (R55 10 k to VIN; U6.17; R137 tap → PC5) 3 A/contact vs 1.4 A charge (R50 1.43 k), backup average 0.6–1 A, LTE-only peaks ≈ 2 A (D9) ✅ ✅ (G-07 accepted) —
12 P4 fan XH-2 · 1 /5V_FAN (= VEH5V via JP1 bridged), 2 /FAN_RET → Q2 AO3400A (PA6) + D2 flyback ✅ ✅ · ⚙ —
13 P5 cut-off + JP6 XH-2 · /MAIN5V–/SYS5V; JP6 open bypass ✅ ✅ —
14 P6 external reset XH-2 · 1 /NRST (D36 PESD5V0S1BA, C104 100 nF, SW1, TP5, U16.7), 2 GND ✅ (renumber hazard handled by silk, L-46) ✅ —
15 P7/P8 NTC probes XH-2 · /NTC_TEMP (R42 10 k to 3V3, C24, D37, PB1 ADC IN9) · /NTC2 (R126, C157, D38, PC4 IN14) ✅ ✅ · ⚙ —
16 P9 panel LED XH-2 · 1 /LED_A (R3 120 Ω from 3V3), 2 /LED_K → Q4 (PB0); on-board D1 in parallel Works with a panel LED of Vf ≤ 2.2 V (it shares ≈ 11 mA with D1) ✅ (usage rule) —
17 P10 external RGB XH-4 · 1 3V3 (common anode), 2–4 cathodes via R89–R91 120 Ω → PCF8574 P4–P6 (sink) Red about 11 mA; blue/green (Vf about 2.8–3.0 V at 3.3 V) run at a few mA, so they are dimmer. Functional ✅ —
18 J12 GNSS antenna U.FL (C88374) → /RF_ANT_GNSS: D27, C143 DC block → U18.2; bias L21 68 nH ← /ANT_BIAS ← U28 TPS2552 (75 mA limit, EN̅ = F9P ANT_OFF, FAULT̅ → PC2) Apply-pass C-01 in place ✅ ✅ · 📐 L-30/L-33 (existing) · ⚙ —
19 J13 LTE antenna U.FL → /RF_ANT_LTE: D28 PESD0402-240, R118 0 Ω, C146/C147 DNP π → U19.60 Apply-pass B-03 in place ✅ ✅ · 📐 L-31 (existing) —
20 J14 nano-SIM / U22 eSIM J14 (C2977286, pre-order) C1 /SIMB_VDD (C171) via R131 0 Ω; C2/C3/C7 via R132–R134 22 Ω; ESD D23–D25 on the modem side; U22 + R127–R130 DNP ✅ (B-09 applied; ESD move per L-38) · SIM detect unused (USIM1_DET NC) ✅ · ⚙ —
21 SWD / test pads TP3 SWDIO (PA13), TP4 SWCLK (PA14), TP5 NRST, TP6 GND, TP7 3V3, TP9 PA9 TX Complete SWD set, no connector (D-12) → pads grouped in one row (L-56) ✅ · 📐 L-56 —
22 SW1 reset / SW2 BOOT0 SW1 NRST→GND; SW2 3V3→BOOT0 (R98 PD) ✅ ✅ —
23 Modem UART (internal) PC6 USART6_TX → R148 0 Ω → /DIN_4G (R143 100 k PU) → U23 → modem RXD; modem TXD → U24 → /DOUT_4G → R106 1 k → PC7 and U27 → F9P RXD2 K1 relay path removed (B-13, §4) 🔧 🔧 · 📐 L-54 · ⚙ /DIN_4G ∋ R148.2; /USART6_TX = {U16.37, R148.1, K1.10 (DNP)}
24 GNSS UARTs (internal) USART2 PA2/PA3 ↔ F9P UART1; F9P TXD2 → PA10 (RX-only) + Rdfu1 PU ✅ (unchanged; /USART1_RX no longer reaches K1's contact in practice, since K1 is DNP) ✅ · ⚙ —

1.6 Note on the HR911105A LED pin evidence

The Hanrun PDF could not be read here (image-only on every mirror). The pin mapping comes from KiCad's official symbol Connector:RJ45_Hanrun_HR911105A_Horizontal, whose datasheet link points to the LCSC copy of the Hanrun drawing, and from the copy already embedded in the v6 sheet. Both draw the yellow LED with its anode on pin 12 and cathode on pin 11, and the green LED with its anode on pin 9 and cathode on pin 10. They also both type pin 8 as the power_in return of the 1000 pF Bob-Smith capacitor. The v6 wiring contradicted its own symbol drawing. The original designer's note said "G+/G−/Y+/Y− – VERIFY". Bench check on the first board: both LEDs light with the link up.

2. Datasheet facts that decided the fixes

Part Fact Consequence
SP3485 (MaxLinear) Fail-safe only for open inputs; ESD ±2 kV HBM; no IEC rating Too weak for a cabled port on port machinery → THVD1410DR
THVD1410 (TI) SOIC-8 = R, RE̅, DE, D, GND, A, B, VCC; fail-safe open/short/idle; IEC contact ±18 kV, air ±25 kV, HBM ±30 kV; EFT ±4 kV; bus abs max ±18 V; 3–5.5 V; 500 kbps; DE 2 MΩ PD, RE̅ 2 MΩ PU; 100 nF decoupling Drop-in on U14's land; C84 is its 100 nF
SN74LVC1G04 DBV 1 NC, 2 A, 3 GND, 4 Y, 5 VCC U32 on SOT-23-5
SC16IS752 (NXP) A1=VSS, A0=VSS → 0x9A (0x4D) · RTSA̅/RTSB̅ = logic 1 after reset · EFCR[4] RTSCON, EFCR[5] RTSINVER · POR plus RESET̅ · IRQ̅ open-drain · I²C ≤ 400 kbit/s · GPIO inputs after reset Inverter needed for receive-by-default; firmware SRESET and GPIO direction
MAX3232 (non-E) No ESD rating; 0.1 µF pump caps at 3.0–3.6 V → TRS3232E
TRS3232E (TI) Same 16-pin order as MAX3232; ±15 kV HBM, ±8 kV IEC contact, ±15 kV air; 0.1 µF at 3.3 V Drop-in on U15's narrow SOIC-16 land (H-01 fixed it in the apply pass)
SM712 2 I/O pins + common pin 3; −7/+12 V standoff, 400 W 8/20 µs (Semtech SM712.TCT) Standard RS-485 surge clamp; matches the THVD1410's ±18 V bus rating
W5500 v1.1.0 TOCAP 4.7 µF, 1V2O 10 nF, EXRES1 12.4 k 1 %; RSVD23 → GND, RSVD38–42 NC (internal pull-down); RSTn low ≥ 500 µs, internal pull-up; SCSn internal pull-up; 5 V-tolerant I/O; SPI guaranteed ≥ 33.3 MHz Confirms the apply-pass values and the firmware sequence
LTC4040 Rev B OVP = MN1 in series VPWR→VIN with IGATE shared with MN2; 6.2 k to OVSNS; 6.1/6.4/6.7 V trip; IGATE pulled to GND in backup; recovery starts when the PFI comparator sees input power; PFI abs max = max(VIN, VBAT, VSYS) + 0.3 V Why A-10 was not applied blind (§7)
Sunlord MWSA-S spec Table 4-1 MWSA0804S: A 8.2±0.3, B 8.8±0.4, C 3.8±0.2, D 1.4±0.3 (electrode width), E 5.0±0.3 (electrode length); recommended land I 2.75, J 4.0, H 5.5 (typ) New footprint (§4)

3. I²C address map (I²C1, PB6/PB7, 4.7 k pull-ups to /3V3, run at 100 kHz)

7-bit address Device Ref Strap Range the part can take
0x18 SC7A20 accelerometer (INT1 → PB9) U26 SDO/SA0 = GND, CS = VDD (I²C) 0x18–0x19
0x20 PCF8574T I/O expander (battery gauge LEDs, RGB) U13 A0–A2 = GND (NXP PCF8574T/3, not the "A" version) 0x20–0x27
0x44 SHT40-AD1B humidity/temperature U3 fixed 0x44
0x48 TMP102 charger sensor U29 ADD0 = GND 0x48–0x4B
0x49 TMP102 modem-area sensor U31 ADD0 = V+ 0x48–0x4B
0x4D SC16IS752 dual UART U10 A1 = A0 = GND 0x48–0x57
(0x42) ZED-F9P DDC U18 not connected (pins 44/45 NC) —

No collisions. Only the SC16IS752 range (0x48–0x57) overlaps the TMP102 range (0x48–0x4B). It sits at 0x4D, outside the four TMP102 values, so no TMP102 strap change can reach it. No strap change needed. Bus speed limit: PCF8574 = 100 kHz, so the bus runs at 100 kHz. At that speed the SC16IS752 moves about 10 kB/s in total, which is enough for Modbus RTU at ≤ 38.4 kBd on RS-485 plus RS-232 at ≤ 57.6 kBd (FIFO + IRQ).

4. Schematic fixes applied, with proof

Method: the apply-pass editor (apply/tools/ops.py: span-scoped splices on the original text, a UUID multiset guard, canonical KiCad node layout). Each group was written as its own script (ports/tools/gP_ports.py, gN_norespin.py, gC_cosmetic.py), with the expected change set written before commit. After each commit to the Mac (unique staged path each time, sha256 checked on the Mac afterwards) the netlist was exported with the KiCad MCP (kicad-cli), diffed semantically with ndiff.py and asserted; ERC and the overlap and wire-crossing checks ran after each group.

4.1 Hashes

State hbox-watchdog-v6.kicad_sch sha256 Backup
Pre (apply-pass final) d54e330d189910afd58e18fc7cd498bdb3e6e5b7b3c4472b6cae7f95650b34c4 _to_delete/v6-ports-20260928/00-pre/ (+ pro, dru, pretty, old PDF), 01-ports/…pre
After P1 ports 26f50aaa7dc7795dcc5aec12b1ed8d8c1a762c09c8d63b0190e36d1078679a0e 01-ports/…post, 02-norespin/…pre
After N1 no-respin 3aceff28ac2d91624c37216e2cb83a53f37503452288a86bd52331e211d413c1 02-norespin/…post, 03-cleanup/…pre
Final (after C1 cleanup) f73f41a878655896211b429c6f30d82f13d6e0b7eba78468a6bb0473de8a27ee 03-cleanup/…post; container ports/hbox-watchdog-v6.kicad_sch.final
Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod (new) dbf535570b133bcb05e6ee7861f06e62cb54d554520488650e0b3c5429d5a71f new file (nothing overwritten)
Schematic PDF 03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf a2c94a49… → 41241140201f8f19098b1e1c37d3b256b1b6d83df7d338e6204c0fdf0e7191b0 old copy in 00-pre/; new copy ports/hbox-watchdog-v6-schematic.pdf

4.2 Netlist proof (expected written before commit, asserted after)

Group Netlists Expected (added / removed / field / pin-net / class) Actual Result
P1 ports 00-baseline → 01-ports 7 / 0 / 11 / 6 / 0 7 / 0 / 11 / 6 / 0 MATCH
N1 no-respin 01-ports → 02-norespin 1 / 0 / 30 / 0 / 0 1 / 0 / 30 / 0 / 0 MATCH
C1 cleanup 02-norespin → 03-cleanup 0 / 0 / 2 / 2 / 0 0 / 0 / 2 / 2 / 0 MATCH
Total 00-baseline → 03-cleanup composition of P1+N1+C1 8 / 0 / 41 / 8 / 0 0 differences (ports/netlist_diff_total.md)

The 8 pin-net changes: U14.2 and U14.3 /SER_DEA → /RS485_DE; U15.12 /SER_RXB → /RS232_R1OUT; J10.8 NC → GND; J10.11 /ETH_ACT_A → /ETH_ACTLED; J10.12 /ETH_ACTLED → /ETH_ACT_A; U10.2 and U10.16 NC → GND. No existing symbol changed its UUID (asserted per group). Netlists are in kicad/_to_delete/v6-ports-20260928/netlists/ and ports/netlists/ (final.xml = 03-cleanup.xml, sha256 a5555894…b5b3).

4.3 What changed

ID Ref Change LCSC (verified: stock / package)
P-1 U14 SP3485EN (C8963) → THVD1410DR, TI; symbol Interface_UART:SP3485EN kept (identical pinout); value text THVD1410 C2671345 (8 006 / SOIC-8; JLC "pre-ordered chips")
P-1 U14.2, U14.3 /SER_DEA → new /RS485_DE —
P-1 U32 (new) SN74LVC1G04DBVR, 74xGxx:74LVC1G04, Package_TO_SOT_SMD:SOT-23-5: 2 /SER_DEA, 4 /RS485_DE, 5 /3V3, 3 GND, 1 NC C7827 (163 327 / SOT-23-5)
P-1 C175 (new) 100 nF 0603 at U32 C14663 (Basic)
P-1 D39 (new) SM712.TCT, Diode:SM712_SOT23, SOT-23: 1 /RS485_A, 2 /RS485_B, 3 GND C12067 (49 238 / SOT-23)
P-4 R145, R146 (new, DNP) 390 Ω 0603: /3V3–/RS485_A, /RS485_B–GND (bias option) C23151 (Basic, 311 280)
P-2 U15 MAX3232ESE+T (C15846) → TRS3232EIDR, TI; symbol Interface_UART:MAX3232 kept; value text TRS3232E C308878 (3 564 / SOIC-16 narrow)
P-2 U15.12 /SER_RXB → new /RS232_R1OUT —
P-2 R147 (new) 1 kΩ 0603: /RS232_R1OUT → /SER_RXB C21190 (Basic, 39.8 M)
P-3 J10.11 / J10.12 labels swapped: 11 = /ETH_ACTLED (yellow K), 12 = /ETH_ACT_A (yellow A) —
P-3 J10.8 NC flag → wire + GND label (Bob-Smith return) —
P-5 TP12 (new) TestPoint_Pad_D1.5mm on /1V8_MODEM, excluded from BOM and CPL no part
C U10.2, U10.16 CTSA̅/CTSB̅ NC flags → GND —
H-03 L2 (DNP), L6, L8, L20 footprint Inductor_SMD:L_Bourns-SRU8028_8.0x8.0mm → Drogheda-v6:IND-SMD_MWSA0804S (parts unchanged: C17700171 / C17700165 / C17700171 / C17700167) —
B-13 K1, Q6, D6, R40, R41 → DNP (relay and its driver) —
B-13 R148 (new) 0 Ω 0603: /USART6_TX → /DIN_4G (never together with K1) C21189 (Basic, 13.9 M)
J-05 TP1–TP8 in_bom no, in_pos_files no (copper pads, not parts) —
C text notes BLOCK M note (RS-485 direction and EFCR, H4 rule) and BLOCK P note (K1 DNP) updated —

New footprint IND-SMD_MWSA0804S (KiCad 9/10 format, Drogheda-v6.pretty): two SMD round-rect pads 2.75 × 4.0 mm (rratio 0.1) at x = ±4.125 mm (inner gap 5.5 mm, outer extent ±5.5 mm); F.Fab body 8.2 × 8.8 mm; F.CrtYd 11.5 × 9.7 mm; silk lines at y = ±4.6 mm between the pads. The pad axis is the body's 8.2 mm A dimension, where the 1.4 mm electrodes sit (the inter-electrode gap of 8.2 − 2 × 1.4 = 5.4 mm matches H = 5.5). Each pad covers 1.35 of the 1.4 mm electrode depth, plus a 1.4 mm toe beyond the body, and 4.0 of the 5.0 mm electrode length. The electrode is now ≈ 77 % wetted plus a toe fillet, against 55–64 % on the SRU8028 land. The audit's courtyard estimate (9.4 × 9.8 mm) left out the pad overhang; the true courtyard is 11.5 × 9.7 mm (L-53). The KiCad MCP cannot list project-local libraries, but the ERC footprint-link check passed with the new footprint (no footprint_link_issues).

4.4 ERC (kicad-cli 10 via KiCad MCP)

0 errors before and after every group; 134 warnings before and after (the same pin-type, library-mismatch and not-in-library families listed in the change report §5). The new symbols (74LVC1G04, SM712_SOT23) are embedded fresh from the KiCad 10 libraries; Device:R and TestPoint are existing cached symbols. Overlaps 30 → 30 and wire crossings 9 → 9: all pre-existing, none involving a new part. I checked the new clusters in the rendered PDF (crops of U10/U14/U32/D39, U15/R147/R145–146, J10, K1/R148, TP12).

5. Additions to Michelle's layout list (continue after L-48)

49. RS-485 direction (P-1): U32 (SOT-23-5) + C175 within 5 mm of U14 pins 2/3; C175 ≤ 2 mm from U32.5; /RS485_DE ≤ 10 mm; /SER_DEA U10.1 → U32.2. C84 ≤ 2 mm from U14.8.

50. RS-485 protection at P11 (P-1/P-4): D39 SM712 ≤ 5 mm of copper from P11.1/P11.2, A/B routed flow-through (P11 → D39 pads → U14), D39.3 to GND with 2 vias ≤ 1 mm; R82 + JP5 beside P11 (termination at the bus end); R145/R146 (DNP 0603) beside P11. Route A/B as a pair (0.3 mm, gap ≤ 0.3 mm), ≥ 0.5 mm from other nets, nothing crossing on the adjacent layer.

51. RS-232 / H4 (P-2): R147 ≤ 3 mm from U15.12; H4.3 connects on the U10 side (/SER_RXB), not at U15. U15's pump caps C85–C88 ≤ 3 mm and its decoupler C89 ≤ 2 mm from U15.16. Correction to L-37: C84 is U14's decoupler, not U15's.

52. J10 (P-3): pin 8 → GND with a ≥ 0.5 mm track to 2 GND vias placed outside the MAGJACK_NO_POUR keep-out (no pour under the magnetics). Re-route pins 11/12: J10.12 = /ETH_ACT_A (from R97), J10.11 = /ETH_ACTLED (to U11.27).

53. MWSA0804S land on L2/L6/L8/L20 (H-03): the footprint swaps to Drogheda-v6:IND-SMD_MWSA0804S on Update PCB from Schematic. Pads go from 2.0 × 3.2 mm at ±3.9 mm to 2.75 × 4.0 mm at ±4.125 mm; the courtyard is 11.5 × 9.7 mm (+0.6 mm per side on the pad axis, +0.4–0.6 mm across). Re-check neighbours and keep L-11/L-21/L-22/L-23 distances measured to the new pads. Update only through the schematic sync, never with a global "update footprints from library" (L-45).

54. B-13: place R148 (0603) on the shortest path U16.37 (PC6) → U23.7 (/DIN_4G). K1, Q6, D6, R40, R41 are DNP; keep their footprints, with no copper change other than R148's two connections. Silk "K1 XOR R148".

55. TP12 beside TP8 (2.54 mm centre spacing) so tweezers can bridge them; both reachable with the lid open.

56. Debug pad row (D-12): TP3 SWDIO, TP4 SWCLK, TP5 NRST, TP6 GND, TP7 3V3, TP9 PA9-TX in one straight row at 2.54 mm pitch, ≤ 30 mm of track from U16, silk labels. A 1×6 pogo clip or header can then be pressed on; no connector part needed.

57. SC16IS752 (U10): Y2 + C82/C83 ≤ 5 mm from U10.6/7, no inner-layer track under them (extends L-39 to Y2); C81 ≤ 2 mm from U10.8.

58. USB-C CC resistors: Rcc1/Rcc2 ≤ 5 mm from J9.A5/B5; R100/R101 ≤ 5 mm from J11.A5/B5.

59. Port silkscreen (extends L-46): P11 "RS-485 A+ B− GND"; P12 "RS-232 TX RX GND"; JP5 "TERM"; R145/R146 "BIAS DNP"; H4 "UART-B TTL 3V3 TX RX GND"; J9 "MODEM USB"; J11 "DFU"; TP8/TP12 "USB_BOOT / 1V8"; P2 "5 V ONLY, BENCH".

60. Footprint attributes (J-05): TP1–TP12 and JP1–JP6 set to SMD and "exclude from BOM/position files" on the board (matches the schematic now); then re-enable the DRC check footprint_type_mismatch.

61. Fiducials: three global fiducials (1.0 mm copper, 2.0 mm mask opening) on F.Cu at three corners (LGA U18/U19 and 0.5 mm-pitch parts). The audit listed them as "optional"; no v6.1 means fit them now.

62. P1 check: confirm that the DIBO DB128V-5.0-5P (C424683) pins fit the MKDS-1,5 land's holes (5.0 mm pitch) and that its wire entry faces the harness side of the enclosure. This is a check only; no change is expected.

Order notes for the same pass: pre-order THVD1410DR C2671345 (JLC pre-order category, like U21 C2862740 and J14 C2977286). P11 and P12 are pluggable headers (DEGSON 15EDGRC-3.5-03P): buy the mating plugs (15EDGK-3.5-03P, 2 per board) with the harness, since they are not in the board BOM.

6. Firmware notes per port (FW 0.7.x, board_v6.h)

  1. SC16IS752 (U10, I²C1 0x4D, 100 kHz): BOARD_SER_XTAL_HZ 3686400; divisor = 3 686 400/(16·baud): 9600 → 24, 19 200 → 12, 38 400 → 6, 57 600 → 4, 115 200 → 2. After every MCU reset write IOControl.SRESET (bit 3), because RESET̅ has no MCU line. Enable the FIFOs. IODir = 0xFF, IOState = 0x00 (GPIO0–7 as outputs, driven low: no floating inputs). IRQ̅ on PB8 (EXTI8, falling, no internal pull; R81 is external): service RHR/THR/LSR until IIR says no interrupt pending. CTSA̅/CTSB̅ are tied low, so leave auto-CTS (EFR[7]) off.
  2. RS-485 (channel A): EFCR = 0x10 (RTSCON = 1, RTSINVER = 0). RTSA̅ goes LOW while transmitting, and U32 turns that into DE = 1; idle and reset leave the transceiver in receive. Never set RTSINVER (with U32 fitted it would invert the logic). Modbus RTU: time the 3.5-character gaps on the MCU; line turnaround is automatic after the last stop bit. Termination (JP5) and bias (R145/R146, DNP) are hardware options only.
  3. RS-232 (channel B) and H4: plain 8N1, no flow control. H4 and P12 share channel B: use one at a time. H4 pin 3 can be driven by a TTL device (R147).
  4. Ethernet (U11, SPI2 PB13/PB14/PB15 AF5, CS̅ PB12 GPIO, INT̅ PC0, RST̅ PA15, power PD2): at boot drive PA15 LOW and PD2 LOW before anything else. Power-up: SPI pins low → PD2 HIGH → wait ≥ 2 ms for 3V3_ETH → keep RST̅ LOW ≥ 500 µs → release → wait 1 ms (PLL) → SPI mode 0 at ≤ 21 MHz → check VERSIONR = 0x04 → PHYCFGR link. PC0 needs no pull; enable EXTI0 only while PD2 is HIGH. Off / battery: RST̅ LOW, SPI pins LOW or analog, PD2 LOW. LEDs are driven by the PHY (no firmware).
  5. USB DFU (J11): ROM DFU (BOOT0 button + NRST) needs HSE 25 MHz (Y3). In the application's USB CDC (u-center passthrough) on OTG_FS PA11/PA12, disable VBUS sensing (PA9 is the debug-TX pad, not VBUS).
  6. Modem USB (J9): J9 enumerates only while the modem is powered (PC10 MODEM_PWR_EN + PWRKEY sequence). Add a service command that holds the modem on for FOTA/debug. Forced download: short TP8–TP12 at modem power-on (hardware procedure, no firmware).
  7. Modem UART: USART6 PC6 TX now reaches the modem directly through R148 (no K1): drop every BYP_CTRL/Mode-B relay step and keep PB5 LOW (driver DNP). PC7 RX via R106 1 k; 115 200 Bd. PC9 STATUS has a hardware pull-down.
  8. I²C sensors: 0x18 SC7A20 (INT1 → PB9, EXTI9); 0x20 PCF8574 (P0–P3 battery-gauge LEDs, P4–P6 RGB cathodes on P10, active LOW); 0x44 SHT40; 0x48 TMP102 charger (tchg); 0x49 TMP102 modem (tmodem). Keep I²C1 at 100 kHz (PCF8574 limit). The SC7A20 WHO_AM_I read at 0x18 also serves as the v6 board identity check before any v6-only pin is driven (D-08, §7).
  9. ADC ports: PB1 IN9 (P7 NTC), PC4 IN14 (P8 NTC2), PC5 IN15 (pack NTC tap), PA5 IN5 ignition (ratio 0.0833), PA4 IN4 5 V sense; compute VDDA from VREFINT.
  10. Other ports: P4 fan on PA6 as GPIO on/off (TIM3 stays free for PPS); P9 panel LED on PB0 (Q4); P6 is a hardware reset (no firmware). SIM: no detect line (USIM1_DET NC), so keep SIM hot-swap detection disabled in the modem.

7. Accepted permanently

# ID Item Reason it is safe for the product's life
1 A-10 No over-voltage protection on VEH5V (TPS54360B high-side short, or > 6 V into P2) It takes a component failure or bench misuse. The field input is the cabinet's regulated, current-limited 24 V (DDR-60G-24, D1), and F2 3 A caps the energy. The datasheet OVP option (MN1 + 6.2 k, sharing IGATE with Q7) also moves the PFI divider to the raw side and changes how backup mode recovers. A mistake there would break normal operation on every board, which is worse than the rare fault it guards against, and it cannot be validated without a bench cycle. P2 gets a "5 V ONLY, BENCH" silk label (L-59).
2 D-08 Board-ID strap Decision D8: firmware-only. The v6 is identified at boot by the SC7A20 WHO_AM_I at 0x18 (v6-only part) and the F9P answering on USART2, before any v6-only pin is driven. Binary names carry the board (memory rule). PD2 is taken by ETH_PWR_EN and PA9 by the debug pad.
3 E-06 (option) Low-capacitance ESD array between the magjack and U11 The HR911105A magnetics isolate the cable (1500 Vrms), the WIZnet reference design has no array, and the cabling stays inside the cabinet. J10.8 (Bob-Smith return) is fixed now.
4 E-07 PoE Not a requirement (Leo: ports must work; no PoE mentioned). The recorded decision is an external splitter.
5 A-20a U12 MP1584EN → AP64350 U12 is now PD2-gated (E-01), runs only on vehicle power and is proven on V5.5. A swap would need a new compensation/RT design and a different land, which adds risk for no functional gain.
6 G-07 P3 XH-3 → XH-5/VH 3 A per contact vs 1.4 A charge (R50 1.43 k), 0.6–1 A backup average, and ≈ 2 A LTE-only peaks (D9). XH-3 keeps the fielded 1S4P packs compatible.
7 G-06 P2-only power back-feeds VEH5V → U25 body diode → P1.1 (≈ 4 V) Benign; with A-01 the Q10/U2 branch is DNP, so nothing on /24V is powered. Documented for the bench procedure.
8 F-14 (option) One USBLC6 at J11 instead of D14–D16 Full-speed USB tolerates the PESD5V0S1BA capacitance (proven on V5.5). The stub problem is solved by routing (L-42).
9 G-08 (option) 100 Ω series on NRST D36 (PESD5V0S1BA) plus C104 100 nF already clamp and filter the P6 cable; a series R would split /NRST for no measurable gain.
10 J-03 Retype unspecified library pins Cosmetic. The warnings were checked net by net (single drivers, no conflicts), pin types do not reach the netlist, BOM or PCB, and the 134-warning baseline is recorded, so a new warning is found by diffing against it.
11 J-04 (re-link) 10 "not found" symbols (+ TPS2552) not copied into a library Cosmetic. The embedded copies make the schematic self-contained, and pin → pad → net was checked on 25 parts (H-09). Re-linking would change 11 lib_ids for zero electrical effect.
12 B-09 (option) ESD on /SIM_VDD (array) The SIM is inserted once at installation inside the enclosure. Data, CLK and RST have D23–D25 (moved next to J14 by L-38), and VDD has C171 100 nF at J14.
13 A-16 Populate R124/R125 (U25 UVLO) The board always sees the cabinet's regulated 24 V (D1), so the 4.3–5.8 V input dropout band is never reached in service.
14 A-18 (+ R123 option) U25 compensation The datasheet example with ≥ 60° phase margin (audit estimate) needs no change; the 0.3 → 2.5 A step is part of bring-up.
15 A-19 ISO 16750-2 load dump The cabinet DC-DC isolates the board from the alternator bus. SMCJ33A/SMBJ33A survive 36 V/60 min and ISO 7637 fast pulses; F2 opens behind them if a TVS ever shorts.
16 A-20b F1 3 A PPTC now protects only the F9P LDO branch Harmless and not needed for protection; keeping it avoids a footprint change.
17 C-05 (option) C143 100 nF → 47 pF C0G DC block 100 nF X7R 0402 is ESL-dominated at L1/L2 (≈ 3–4 Ω); insertion loss < 0.01 dB after a ≥ 25 dB antenna LNA.
18 D-06 (option) D5 BAT54 → BAT54S verify_2: optional once the SMBJ33A (D35) sits at P1.3 (applied).
19 A-03/A-04 (option) R121/R122 at 0.1 % 5.18–5.46 V at 1 % meets the LTC4040 VIN ≤ 5.5 V and the governor thresholds; no 0.1 % LCSC parts in the DB.
20 A-13 (option) CLPROG → ADC No ADC pin is left (PC5 went to the pack NTC). CLPROG stays on TP1 for bench current measurement.

8. Done now

# ID What Where
1 P-1 (new) RS-485 transceiver → THVD1410DR (IEC ESD, fail-safe on open/short/idle bus) Schematic (U14)
2 P-1 (new) Receive-by-default direction: U32 inverter + C175 Schematic + L-49
3 P-1 (new) RS-485 surge TVS D39 SM712 at P11 Schematic + L-50
4 P-4 (new) RS-485 bias option R145/R146 (DNP) Schematic + L-50
5 P-2 (new) RS-232 transceiver → TRS3232EIDR (IEC ESD) Schematic (U15)
6 P-2 (new) H4 contention fixed: R147 1 k R1OUT → SER_RXB Schematic + L-51
7 P-3 (new) J10 yellow LED polarity (pins 11/12) Schematic + L-52
8 P-3 / E-06 J10.8 Bob-Smith return → GND Schematic + L-52
9 P-5 (new) TP12 1V8 pad for modem USB forced download Schematic + L-55
10 C (new) SC16IS752 CTSA̅/CTSB̅ tied to GND Schematic
11 H-03 MWSA0804S footprint per the Sunlord land; L2/L6/L8/L20 re-pointed Library + schematic + L-53
12 B-13 K1 relay path removed: K1/Q6/D6/R40/R41 DNP, R148 0 Ω PC6 → DIN_4G Schematic + L-54
13 J-05 / H-09 TP1–TP8 out of the BOM and CPL Schematic + L-60
14 D-12 (option) SWD/debug access as one 2.54 mm pad row L-56
15 FHJ note Fiducials L-61
16 L-37 (correction) U15 decoupler is C89 (not C84) L-51
17 C Block notes and value texts updated (no overlap on U14/U15) Schematic

Already closed by the apply pass and so not repeated here: every §7.1/§7.2 item, the D19 Minors, F-52 (modem TMP102 0x49), B-15, G-03, G-04, G-08 diodes, and J-04's flag and stub cleanup. Layout-only Minors and Notes (A-14, B-08, E-06 routing, F-14, F-17, F-18, G-05, J-02, C-09, D-15, F-21, A-20c silk) are in Michelle's L-1…L-48 list. Firmware-only Notes (B-14, B-16, C-08, D-13) are in the audit §8 and §6 above.

9. Anything that would still stop a port from working

None found in the schematic after this pass. Conditions that remain:

  • Layout: L-49…L-62, plus the existing L-30/31/33 (RF), L-41/42/43 (USB) and L-44 (Ethernet pairs), must be done. In particular, the new MWSA land (L-53) must be placed before routing the switchers.
  • Order logistics: pre-order THVD1410DR, U21 and J14; buy the P11/P12 mating plugs.
  • Bench confirmation on the first board: J10 LINK (green) and ACT (yellow) both light; RS-485 idles in receive during MCU reset and in DFU (DE low); an RS-485 loopback at 9 600 and 115 200 Bd with EFCR = 0x10; RS-232 loopback; an H4 TTL adapter drives RXB with RS-232 idle; J9 enumerates with the modem on, and download mode works with TP8–TP12 shorted.

10. Files

  • This report: /home/claude/v6audit/ports/2026-09-28_Drogheda_EinarBoard-v6_Ports-and-No-Respin_v1.0.md
  • Final schematic copy: ports/hbox-watchdog-v6.kicad_sch.final (sha256 f73f41a8…27ee); PDF: ports/hbox-watchdog-v6-schematic.pdf and on the Mac 03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf (sha256 41241140…91b0)
  • Final netlist: ports/netlists/final.xml (= 03-cleanup.xml); per-group diffs: ports/out/{P1-ports,N1-norespin,C1-cleanup}/netlist_diff.md; total: ports/netlist_diff_total.md
  • BOM: ports/bom_final_ungrouped.csv (also in _to_delete/v6-ports-20260928/)
  • Scripts: ports/tools/ (gP_ports.py, gN_norespin.py, gC_cosmetic.py, pcommon.py, q.py); footprint source ports/work/IND-SMD_MWSA0804S.kicad_mod
  • Mac backups: kicad/_to_delete/v6-ports-20260928/ (00-pre/, 01-ports/, 02-norespin/, 03-cleanup/, netlists/, scratch/)
  • Git (for Leo; nothing was run here): in the kicad submodule commit hbox-watchdog-v6.kicad_sch and Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod, push to Gitea HBox_PCB, then bump the parent gitlink (git -c diff.ignoreSubmodules=none commit …). If KiCad is open on v6, close it without saving before Update PCB.