Leopoldo Rodríguez
538b62b72c
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
212 lines
21 KiB
HTML
212 lines
21 KiB
HTML
<title>EinarBoard v6 Copper Plan</title>
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<div class="wrap">
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<h1>EinarBoard v6 Copper Plan</h1>
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<p class="sub">Placement companion for the 140 × 100 re-layout — every capacitor's owner, what clusters together, and the EMC order of work. Cap ownership below is computed from the board netlist, not from memory.</p>
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<div class="note"><b>Connector renumber (03-Sep, commit <code>b007c7c</code>):</b> P-refs now follow function order — <code>P1</code> 24V · <code>P2</code> 5V bench · <code>P3</code> battery (was P4) · <code>P4</code> fan (was P6) · <code>P5</code> cutoff (was P11) · <code>P6</code> reset (was P10) · <code>P7</code> NTC probe 1 (was P12) · <code>P8</code> NTC probe 2 (was P18) · <code>P9</code> panel LED (was P8) · <code>P10</code> RGB (was P14) · <code>P11</code> RS485 (was P15) · <code>P12</code> RS232 (was P16). ⚠ v5 field docs say "P12 = NTC" — in v6 that name is the RS232 port; update harness docs. The NTC2 net fix is applied and synced.</div>
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<div class="note"><b>Known leftovers from the auto-clustering:</b> ~54 small courtyard overlaps, nearly all against the legacy V5 regulator families that kept their old spots — <code>L2</code>/<code>D2</code> (under U19's new outline), <code>L6</code>/<code>DB2</code>/<code>DB3</code>/<code>Q2</code>/<code>Dbk1</code> near U25, <code>C40</code>, <code>R40</code>/<code>R41</code> at Y3. Drag those few aside first and the board is clean.</div>
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<h2><span class="no">§0</span>Three laws that decide EMC at placement time</h2>
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<div class="laws">
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<div class="law"><b>Loop area is the antenna</b><p>Emission scales with the area of each switching current loop. A hot loop closed in 1 cm² is ~20 dB quieter than the same loop at 10 cm². Placement fixes this; routing can't rescue a bad placement.</p></div>
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<div class="law"><b>Smallest cap closest</b><p>A capacitor filters up to the frequency its trace inductance allows. Order banks by descending value <i>toward</i> the pin: bulk → 10 µF → 100 nF → pF, with the pF parts within 2–3 mm.</p></div>
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<div class="law"><b>Aggressors far from victims</b><p>Four switchers, one LTE transmitter, one −167 dBm GNSS receiver on one board. Distance and an unbroken In1 ground plane are the only broadband shields you get for free.</p></div>
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</div>
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<h2><span class="no">§1</span>Floorplan as clustered (NW ETH · NE LTE · SW GNSS · SE power)</h2>
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<figure>
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<svg viewBox="0 0 700 500" style="max-width:100%;height:auto" role="img" aria-label="Current floorplan of the 140 by 100 mm board">
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<rect x="30" y="40" width="630" height="450" fill="none" stroke="var(--ink)" stroke-width="2"/>
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<text x="30" y="28" font-size="12" fill="var(--ink2)">140 × 100 mm · as clustered on 03-Sep (commit c7d2552) · N = top of the KiCad screen</text>
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<!-- NW ETH -->
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<rect x="32" y="42" width="200" height="130" fill="var(--plane-soft)"/>
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<text x="42" y="64" font-size="13" fill="var(--plane)">NW — ETHERNET</text>
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<text x="42" y="81" font-size="11" fill="var(--ink2)">J10 RJ45 · U11/U12 · Y1</text>
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<text x="42" y="96" font-size="11" fill="var(--ink2)">C90–C103 · J11 USB-DFU</text>
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<!-- NE LTE -->
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<rect x="440" y="42" width="218" height="200" fill="var(--copper-soft)"/>
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<text x="452" y="64" font-size="13" fill="var(--copper)">NE — LTE ISLAND</text>
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<text x="452" y="81" font-size="11" fill="var(--ink2)">U20 buck+L20 · VBAT bank</text>
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<text x="452" y="96" font-size="11" fill="var(--ink2)">U19 A7670SA · K1 · shifters</text>
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<text x="452" y="111" font-size="11" fill="var(--ink2)">J13 U.FL → NE corner</text>
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<!-- MCU -->
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<rect x="250" y="90" width="170" height="150" fill="none" stroke="var(--line)" stroke-dasharray="5 4"/>
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<text x="335" y="115" font-size="13" text-anchor="middle" fill="var(--ink)">MCU U16</text>
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<text x="335" y="132" font-size="11" text-anchor="middle" fill="var(--ink2)">crystals · VCAP · VDDA</text>
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<text x="335" y="147" font-size="11" text-anchor="middle" fill="var(--ink2)">sense RCs · U10/Y2 below</text>
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<!-- SW GNSS -->
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<rect x="32" y="255" width="200" height="233" fill="var(--plane-soft)"/>
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<text x="42" y="277" font-size="13" fill="var(--plane)">SW — GNSS ISLAND</text>
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<text x="42" y="294" font-size="11" fill="var(--ink2)">U21 LDO · C119–C124</text>
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<text x="42" y="309" font-size="11" fill="var(--ink2)">U18 F9P · L21 bias tee</text>
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<text x="42" y="324" font-size="11" fill="var(--ink2)">C143/144/145 · D27 · J12 → W edge</text>
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<text x="42" y="345" font-size="11" fill="var(--ink2)">U26 accel at MH6 (SW hole)</text>
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<text x="42" y="366" font-size="11" fill="var(--crit)">quiet corner — no switchers</text>
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<!-- SE power -->
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<rect x="440" y="290" width="218" height="198" fill="var(--copper-soft)"/>
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<text x="452" y="312" font-size="13" fill="var(--copper)">SE — POWER ENTRY</text>
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<text x="452" y="329" font-size="11" fill="var(--ink2)">P1 24V · F2 Q23 D32 · 24V parts</text>
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<text x="452" y="344" font-size="11" fill="var(--ink2)">U25 + L22 + C149–C154</text>
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<text x="452" y="359" font-size="11" fill="var(--ink2)">U6 LTC4040 + RS1 · fan U2 above</text>
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<text x="452" y="374" font-size="11" fill="var(--ink2)">J9 USB · RS232 U15 just west</text>
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<!-- diagonal separation -->
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<line x1="235" y1="370" x2="500" y2="130" stroke="var(--crit)" stroke-dasharray="6 5"/>
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<text x="368" y="262" font-size="11" text-anchor="middle" fill="var(--crit)" transform="rotate(-42 368 262)">GNSS ↔ LTE on the diagonal · antennas ≥ 20 cm at the enclosure</text>
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</svg>
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<figcaption>The clustered state after commit <code>c7d2552</code> — your anchors kept (J10, P1, U18, U16, U6, U15, K1, connectors), 160 support parts packed by family. Fine-tune freely inside each region; keep the diagonal.</figcaption>
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</figure>
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<h2><span class="no">§2</span>Vehicle power entry — U25 TPS54360B <span class="tag">hot loop</span></h2>
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<p>Chain order along the copper, left to right from P1: <code>F2</code> → <code>Q23</code> (with <code>R119</code>, <code>D33</code> beside its gate) → <code>D32</code> SMCJ33A → input caps → <code>U25</code> → <code>D34</code>/<code>L22</code> → output caps. <code>D10</code> stays glued to P1 pin 1.</p>
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<div class="loop"><b>Loudest loop on the board:</b> C149/C150 (+) → U25 VIN ⟶ U25 SW → D34 cathode ⟶ D34 anode → C149/C150 (−). This is a non-synchronous buck, so the input loop carries the full di/dt. Put <code>C149</code>/<code>C150</code> within 2–3 mm of U25 pins 2/7, D34 directly across from them, and close the loop over solid ground. Under 1 cm² or do it again.</div>
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<div class="tblwrap"><table>
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<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
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<tr><td>C149 C150</td><td>2.2 µF/100 V</td><td>U25 VIN</td><td>2–3 mm from pins 2/7; the hot loop</td></tr>
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<tr><td>C151</td><td>100 µF/50 V</td><td>input bulk</td><td>right behind C149/C150</td></tr>
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<tr><td>C152</td><td>100 nF</td><td>U25 BOOT</td><td>directly across pins 1–8</td></tr>
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<tr><td>C153 C154</td><td>47 µF/16 V</td><td>5 V output</td><td>at L22 output; FB tap (R121) here, not at the inductor</td></tr>
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<tr><td>D34</td><td>B560C</td><td>catch diode</td><td>anode ground ties straight into C149/C150 ground</td></tr>
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<tr><td>D32</td><td>SMCJ33A</td><td>surge clamp</td><td>between Q23 and the input caps, short fat ties</td></tr>
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<tr><td>R120 · R123 C155 C156 · R121 R122 · R124 R125</td><td>RT · COMP · FB · UVLO (DNP)</td><td>U25 analog side</td><td>cluster at pins 3–6, opposite the SW node; keep FB thin and away from L22</td></tr>
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</table></div>
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<p>24 V rail housekeeping: <code>C10</code>/<code>C22</code> bulk near Q10, <code>C11</code> 100 nF at the load side. Keep the whole entry block in one corner so the dirty 24 V copper never crosses the board.</p>
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<h2><span class="no">§3</span>Battery backup — U6 LTC4040 <span class="tag q">kelvin</span></h2>
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<div class="tblwrap"><table>
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<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
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<tr><td>C30 C31 C78</td><td>10 µF · 2.2 µF · 220 µF</td><td>VEH5V input</td><td>at U6 input pins, after RS1</td></tr>
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<tr><td>C32 C33 C34</td><td>47 µF ×2 · 10 µF</td><td>MAIN5V output</td><td>at U6/Q7 output side</td></tr>
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<tr><td>C35</td><td>22 µF</td><td>BAT_PLUS</td><td>near P3; <code>/SW_BAT</code> ≥ 2 mm polygon, <code>/BAT_PLUS</code> ≥ 1.5 mm — the blackout path, a hard v6 requirement</td></tr>
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</table></div>
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<div class="note"><b>RS1 (10 mΩ) is a Kelvin part:</b> the LTC4040 sense pins must tap the pad faces themselves, not the power trace. Place RS1 immediately at U6 with L22's output feeding it directly.</div>
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<h2><span class="no">§4</span>LTE island — U20 buck + U19 A7670SA <span class="tag">hot loop</span></h2>
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<div class="loop"><b>Second hot loop:</b> C127/C128 → U20 VIN/GND. Synchronous buck, so the input loop is the loud one — C127 10 µF within 2–3 mm of U20 pin 2, C128 1 µF even closer. C129 boot across BOOT–SW, L20 right at SW with a minimal SW pour.</div>
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<p>The VBAT bank is a one-direction gradient into pins 55/56/57 — largest farthest, smallest touching the module:</p>
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<div class="tblwrap"><table>
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<tr><th>Ref</th><th>Value</th><th>Order</th><th>Placement</th></tr>
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<tr><td>C130 C131</td><td>220 µF/10 V ×2</td><td>far end</td><td>the ≥300 µF droop reservoir (2.8 A bursts, ≤300 mV sag)</td></tr>
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<tr><td>C132 → C133 → C134</td><td>22 µF → 1 µF → 100 nF</td><td>middle</td><td>stepping toward the module</td></tr>
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<tr><td>C135 C136</td><td>33 pF · 10 pF</td><td>at the pins</td><td>within 2–3 mm of pins 55/56/57 — these keep TX harmonics off VBAT</td></tr>
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<tr><td>D22</td><td>SMAJ5.0A</td><td>at the bank</td><td>across VBAT near C130/C131</td></tr>
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</table></div>
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<p>VBAT copper ≥ 3 mm wide the whole way. Around the module: <code>C125</code> at pin 15 (1V8 out); <code>U22</code> SIM within 5 mm of pins 30–33 with <code>C126</code> at its VCC pad and <code>D23–D25</code> PESD at the SIM pads; <code>U23</code>/<code>U24</code> level shifters between U19 and the MCU side, each with its supply pair (<code>C137</code>/<code>C139</code> on 1V8, <code>C138</code>/<code>C140</code> on 3V3) at the pins; <code>Q20–Q22</code> near the control pins they drive. <code>J13</code> U.FL at the board edge; the DNP pi network <code>C146</code>/<code>C147</code> (+ its series element) sits inline in the 50 Ω run right at the connector, <code>D28</code> ESD at the connector ground side.</p>
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<h2><span class="no">§5</span>GNSS island — U18 ZED-F9P + U21 LDO <span class="tag q">quiet</span></h2>
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<div class="tblwrap"><table>
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<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
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<tr><td>C119</td><td>10 µF</td><td>U21 input (SW_5V)</td><td>at the LDO input pin</td></tr>
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<tr><td>C120 C124</td><td>10 µF ×2</td><td>3V3_GNSS</td><td>one at U21 output, one at U18's main VCC entry</td></tr>
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<tr><td>C121 C122 C123</td><td>100 nF ×3</td><td>U18 VCC pins</td><td>one per supply pin, at the pin</td></tr>
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<tr><td>C144 C145</td><td>100 nF · 100 pF</td><td>VCC_RF / bias tee</td><td>at L21's feed side — the antenna supply injection</td></tr>
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<tr><td>C143</td><td>100 nF RF</td><td>DC block</td><td>inline in the 50 Ω run between L21 tap and J12</td></tr>
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<tr><td>D27</td><td>ESD9L (≤0.5 pF)</td><td>J12</td><td>at the connector, stub-less tap on the RF line</td></tr>
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</table></div>
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<p>This corner is the victim: no switcher, no inductor, no fast digital within ~25 mm (U25 sits ~95 mm away in the SE, the fan buck ~130 mm NE — keep it that way); nothing but solid In1 ground under the module and the RF run. <code>TIMEPULSE</code> to the MCU is the one digital line that leaves — route it away from the RF path.</p>
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<h2><span class="no">§6</span>MCU core — U16 <span class="tag q">analog care</span></h2>
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<div class="tblwrap"><table>
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<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
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<tr><td>C111</td><td>4.7 µF</td><td>VCAP1</td><td>≤ 3 mm from the pin — the core regulator, non-negotiable</td></tr>
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<tr><td>C109 C112</td><td>100 nF · 1 µF</td><td>VDDA</td><td>at the VDDA pin, on the quiet side, away from the switchers</td></tr>
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<tr><td>C105–C108 + C110</td><td>100 nF ×4 + 4.7 µF</td><td>VDD pins</td><td>one 100 nF per VDD pin, bulk nearby</td></tr>
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<tr><td>C104</td><td>100 nF</td><td>NRST</td><td>at the pin, with P10 reset routed clean</td></tr>
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<tr><td>Y3 + C113 C114</td><td>HSE + 15 pF</td><td>crystal</td><td>tight triangle at the pins, local ground, ≥10 mm from any inductor</td></tr>
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<tr><td>Y4 + C115 C116</td><td>LSE 32 kHz + 12 pF</td><td>crystal</td><td>even tighter — high-impedance oscillator, guard with ground</td></tr>
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<tr><td>C5 C7 C9 C24 C157</td><td>100 nF ×5</td><td>ADC sense filters</td><td>with their dividers (R42, R126…) at the MCU pins, not at the jacks — the wire filters at the pin</td></tr>
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</table></div>
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<h2><span class="no">§7</span>The rest of the families</h2>
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<ul>
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<li><b>Ethernet</b> (<code>U11</code>/<code>U12</code>, <code>Y1</code>, <code>C90–C103</code>): one block, U11 close to J10 (magnetics are inside the HR911105A), crystal + 18 pF at the pins, the 3V3_ETH locals (<code>C92–C94</code>, <code>C98</code>, <code>C102</code>, <code>C103</code>) around U11. Keep the RJ45 pair region free of other routes.</li>
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<li><b>RS232</b> (<code>U15</code>): <code>C85–C88</code> are charge-pump flying caps — they carry the pump current, so they sit hard against U15; <code>C84</code> 100 nF at its supply pin. P12 (RS232 jack) at the edge.</li>
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||
<li><b>UART bridge</b> (<code>U10</code>, <code>Y2</code>, <code>C82</code>/<code>C83</code>): crystal caps at the pins, block near the MCU.</li>
|
||
<li><b>Fan buck</b> (<code>U2</code>, <code>Cbst1</code>, <code>Ccomp1</code>, <code>C23</code>): a third switcher — treat like §4's loop, and park it in the noisy quarter near the power entry, away from GNSS.</li>
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||
<li><b>Accelerometer</b> (<code>U26</code>, <code>C158</code>/<code>C159</code> at VDD/VDDIO, <code>C160</code> bulk): ≤ 10 mm from a mounting hole, on stiff board — it should feel the chassis, not board flex.</li>
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||
<li><b>Rail sprinkles</b> (<code>Cu3</code> <code>Cu4</code> <code>C80</code> <code>C81</code> <code>C89</code> <code>C105+</code>…): every 100 nF on 3V3 pairs with one IC's power pin — when you move an IC, its 100 nF moves with it. <code>C118</code> 22 µF is the 3V3 bulk at the regulator.</li>
|
||
<li><b>NTC channels</b>: pullup + filter (<code>R42</code>+<code>C24</code> → P7, <code>R126</code>+<code>C157</code> → P8) at the MCU; <code>P7</code>/<code>P8</code> jacks at the harness edge.</li>
|
||
</ul>
|
||
|
||
<h2><span class="no">§8</span>Separation rules</h2>
|
||
<div class="tblwrap"><table>
|
||
<tr><th>Keep apart</th><th>Min</th><th>Why</th></tr>
|
||
<tr><td>GNSS island ↔ any switcher L / SW node</td><td>25 mm</td><td>−167 dBm receiver vs. dV/dt fields</td></tr>
|
||
<tr><td>GNSS RF run ↔ LTE RF run</td><td>opposite ends</td><td>desense is risk #1; antennas ≥ 20 cm at the enclosure</td></tr>
|
||
<tr><td>Any crystal ↔ any inductor</td><td>10 mm</td><td>magnetic pickup into the oscillator</td></tr>
|
||
<tr><td>ADC sense traces ↔ SW nodes</td><td>5 mm + ground between</td><td>tntc/vbat readings ride on µV</td></tr>
|
||
<tr><td>USB pairs (J9/J11) ↔ switchers</td><td>route as 90 Ω pairs, short</td><td>eye + radiated emissions</td></tr>
|
||
<tr><td>U26 accel ↔ mounting hole</td><td>≤ 10 mm (close!)</td><td>chassis coupling, not board flex</td></tr>
|
||
</table></div>
|
||
|
||
<h2><span class="no">§9</span>Order of work from here</h2>
|
||
<ol class="steps">
|
||
<li><b>Update PCB from Schematic</b> (NTC2 re-net), then fine-tune inside the §1 regions. Field wiring now enters mostly along the north edge + P1 at the SE corner — keep each connector beside its block, and its TVS/filter parts right at the jack, so cable common-mode currents stay off the board core.</li>
|
||
<li><b>Say the word and I re-add the four zones</b> — F.Cu GND pour, In1 GND (unbroken, especially under both RF runs and the crystals), In2 3V3, B.Cu GND — plus a stitching-via plan: 5 mm grid around RF, via fence along the board edge.</li>
|
||
<li><b>Route in this order:</b> ① both 50 Ω RF runs (CPWG on F.Cu over In1, JLC7628 ≈ 0.35/0.25 mm — confirm in the JLC calculator and order controlled impedance) · ② the two hot loops and VBAT ≥ 3 mm · ③ /SW_BAT ≥ 2 mm + /BAT_PLUS ≥ 1.5 mm with via farms · ④ USB and ETH pairs · ⑤ sense lines · ⑥ everything else.</li>
|
||
<li><b>Refill zones, full DRC</b>, then the G2 external review checkpoint before ordering.</li>
|
||
<li><b>Bench items carried forward:</b> measure U21's 3V3_GNSS rise (F9P ramp window), verify U25's EP against the TI DDA drawing, and the DzG1 jumper check on the fabbed v5.5 boards.</li>
|
||
</ol>
|
||
|
||
<p class="sub" style="margin-top:36px">EinarBoard HBOX v6 · Helgen · updated 03-Sep-2026: clustered layout + connector renumber (<code>c7d2552</code> · <code>43a967b</code> · <code>b007c7c</code>).</p>
|
||
</div>
|